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EVAL-ADM1069LQEB [ADI]

SUPER SEQUENCER-TM WITH MARGINING CONTROL AND AUXILIARY ADC INPUTS; 超音序器TM与保证金控制和辅助ADC输入
EVAL-ADM1069LQEB
型号： EVAL-ADM1069LQEB
厂家： ADI    ADI
描述：

SUPER SEQUENCER-TM WITH MARGINING CONTROL AND AUXILIARY ADC INPUTS
超音序器TM与保证金控制和辅助ADC输入

输入元件
文件： 总32页 (文件大小：3070K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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REFIN REFOUT REFGND  
VREF  
SDA SCL A1  
A0  
ADM1069  
SMBus  
INTERFACE  
12-BIT  
SAR ADC  
EEPROM  
CLOSED-LOOP  
MARGINING SYSTEM  
CONFIGURABLE  
OUTPUT  
DRIVERS  
PDO1  
PDO2  
PDO3  
PDO4  
PDO5  
PDO6  
DUAL-  
FUNCTION  
INPUTS  
VX1  
VX2  
VX3  
(HV CAPABLE  
OF DRIVING  
GATES OF  
(LOGIC INPUTS  
OR  
SFDs)  
VX4  
N-CHANNEL FET)  
SEQUENCING  
ENGINE  
VP1  
VP2  
VP3  
VH  
CONFIGURABLE  
OUTPUT  
DRIVERS  
PROGRAMMABLE  
RESET  
GENERATORS  
PDO7  
PDO8  
(LV CAPABLE  
OF DRIVING  
(SFDs)  
LOGIC SIGNALS)  
AGND  
PDOGND  
VDDCAP  
VDD  
ARBITRATOR  
V
V
V
V
OUT  
DAC  
OUT  
DAC  
OUT  
DAC  
OUT  
DAC  
DAC1 DAC2 DAC3 DAC4  
GND  
10  
F
REFIN  
REFOUT  
REFGND SDA SCL A1  
A0  
SMBus  
INTERFACE  
VREF  
ADM1069  
OSC  
12-BIT  
SAR ADC  
DEVICE  
CONTROLLER  
EEPROM  
GPI SIGNAL  
CONDITIONING  
CONFIGURABLE  
O/P DRIVER  
(HV)  
PDO1  
VX1  
VX2  
VX3  
VX4  
SFD  
PDO2  
PDO3  
PDO4  
PDO5  
GPI SIGNAL  
CONDITIONING  
CONFIGURABLE  
O/P DRIVER  
(HV)  
PDO6  
SEQUENCING  
ENGINE  
SFD  
SFD  
SELECTABLE  
ATTENUATOR  
VP1  
VP2  
VP3  
CONFIGURABLE  
O/P DRIVER  
(LV)  
PDO7  
CONFIGURABLE  
O/P DRIVER  
(LV)  
SELECTABLE  
ATTENUATOR  
VH  
SFD  
PDO8  
AGND  
PDOGND  
REG 5.25V  
CHARGE PUMP  
V
V
OUT  
DAC  
OUT  
DAC  
VDDCAP  
VDD  
ARBITRATOR  
10  
F
GND  
VCCP  
10 F  
DAC1 DAC2 DAC3 DAC4  
25  
32  
1
24  
VX1  
VX2  
VX3  
VX4  
VP1  
VP2  
VP3  
VH  
PDO1  
PDO2  
PDO3  
PDO4  
PDO5  
PDO6  
PDO7  
PDO8  
PIN 1  
INDICATOR  
ADM1069  
TOP VIEW  
(Not to Scale)  
8
17  
9
16  
6
5
4
3
2
1
0
180  
160  
140  
120  
100  
80  
60  
40  
20  
0
0
0
0
1
2
3
4
5
6
16  
6
0
0
0
1
2
3
4
5
6
16  
6
V
(V)  
(V)  
(V)  
V
(V)  
(V)  
(V)  
VP1  
VP1  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
6
5
4
3
2
1
0
2
4
6
8
10  
12  
14  
2
4
6
8
10  
12  
14  
V
V
VH  
VH  
350  
300  
250  
200  
150  
100  
50  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
0
1
2
3
4
5
1
2
3
4
5
V
V
VP1  
VH  
14  
12  
10  
8
1.0  
0.8  
0.6  
0.4  
0.2  
0
6
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
4
2
0
0
2.5  
5.0  
I
7.5  
10.0  
12.5  
15.0  
0
1000  
2000  
3000  
4000  
CURRENT ( A)  
CODE  
LOAD  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1.0  
0.8  
0.6  
0.4  
0.2  
VP1 = 5V  
0
VP1 = 3V  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
0
1
2
3
4
5
6
0
1000  
2000  
3000  
4000  
I
(mA)  
CODE  
LOAD  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
12000  
10000  
8000  
6000  
4000  
2000  
0
9894  
VP1 = 5V  
VP1 = 3V  
25  
2047  
81  
0
10  
20  
30  
40  
50  
60  
2048  
2049  
I
(
A)  
CODE  
LOAD  
1.005  
1.004  
1.003  
1.002  
1.001  
1.000  
0.999  
0.998  
0.997  
0.996  
0.995  
VP1 = 3.0V  
VP1 = 4.75V  
DAC  
BUFFER  
OUTPUT  
20k  
47pF  
PROBE  
POINT  
1
–40  
–20  
0
20  
40  
60  
80  
100  
CH1 200mV  
M1.00  
s
CH1  
756mV  
TEMPERATURE ( C)  
2.058  
2.053  
2.048  
2.043  
2.038  
VP1 = 3.0V  
DAC  
100k  
VP1 = 4.75V  
BUFFER  
OUTPUT  
1V  
PROBE  
POINT  
1
–40  
–20  
0
20  
40  
60  
80  
100  
CH1 200mV  
M1.00  
s
CH1  
944mV  
TEMPERATURE ( C)  
VDDCAP  
VP1  
VP2  
VP3  
VH  
IN  
OUT  
OUT  
OUT  
OUT  
4.75V  
LDO  
EN  
IN  
4.75V  
LDO  
EN  
IN  
4.75V  
LDO  
EN  
IN  
INTERNAL  
DEVICE  
SUPPLY  
4.75V  
LDO  
EN  
SUPPLY  
COMPARATOR  
RANGE  
SELECT  
ULTRA  
LOW  
OV  
COMPARATOR  
+
VPn  
–
GLITCH  
FILTER  
FAULT  
OUTPUT  
VREF  
+
LOW  
MID  
–
UV  
FAULT TYPE  
SELECT  
COMPARATOR  
INPUT PULSE SHORTER  
THAN GLITCH FILTER TIMEOUT  
INPUT PULSE LONGER  
THAN GLITCH FILTER TIMEOUT  
PROGRAMMED  
TIMEOUT  
PROGRAMMED  
TIMEOUT  
INPUT  
INPUT  
T
0
T
GF  
T
0
T
GF  
OUTPUT  
OUTPUT  
T
0
T
GF  
T
0
T
GF  
VXn  
+
(DIGITAL INPUT)  
TO  
GLITCH  
FILTER  
SEQUENCING  
ENGINE  
DETECTOR  
–
VREF = 1.4V  
VFET (PDO1-6 ONLY)  
V
DD  
VP4  
VP1  
SEL  
CFG4 CFG5 CFG6  
SE DATA  
SMBus DATA  
CLK DATA  
PDO  
MONITOR  
FAULT  
STATE  
TIMEOUT  
SEQUENCE  
SEQUENCE  
STATES  
IDLE1  
VX1 = 0  
IDLE2  
VP1 = 1  
MONITOR FAULT  
STATES  
TIMEOUT  
STATES  
EN3V3  
10ms  
VP1 = 0  
VP2 = 1  
EN2V5  
DIS3V3  
20ms  
(VP1 + VP2) = 0  
VX1 = 1  
VP3 = 1  
PWRGD  
DIS2V5  
VP2 = 0  
(VP1 + VP2 + VP3) = 0  
VX1 = 1  
VX1 = 1  
FSEL1  
(VP1 +  
VP2) = 0  
VP3 = 0  
FSEL2  
VP1 = 0  
VP2 = 0  
MONITORING FAULT  
DETECTOR  
1-BIT FAULT  
DETECTOR  
FAULT  
SUPPLY FAULT  
DETECTION  
VP1  
MASK  
SENSE  
1-BIT FAULT  
DETECTOR  
FAULT  
LOGIC INPUT CHANGE  
OR FAULT DETECTION  
VX4  
SUPPLY FAULT  
DETECTION  
VP1  
VX4  
MASK  
SENSE  
SEQUENCE  
DETECTOR  
1-BIT FAULT  
DETECTOR  
LOGIC INPUT CHANGE  
OR FAULT DETECTION  
TIMER  
FAULT  
WARNINGS  
WARNINGS  
INVERT  
MASK  
FORCE FLOW  
(UNCONDITIONAL JUMP)  
SELECT  
DIGITIZED  
VOLTAGE  
READING  
NO ATTENUATION  
12-BIT  
ADC  
VXn  
2.048V VREF  
ATTENUATION NETWORK  
(DEPENDS ON RANGE SELECTED)  
VPn/VH  
DIGITIZED  
VOLTAGE  
READING  
12-BIT  
ADC  
2.048V VREF  
CONTROLLER  
VIN  
ADM1069  
MUX  
VH/VPn/VXn  
DACOUTn  
DC/DC  
CONVERTER  
ADC  
DAC  
ATTENUATION  
RESISTOR  
OUTPUT  
FEEDBACK  
GND  
DEVICE  
CONTROLLER  
(SMBus)  
PCB  
TRACE NOISE  
DECOUPLING  
CAPACITOR  
VIN  
CONTROLLER  
V
OUT  
ADM1069  
DAC  
DEVICE  
CONTROLLER  
(SMBus)  
OUTPUT  
ATTENUATION  
RESISTOR  
DC/DC  
CONVERTER  
DACOUTn  
FEEDBACK  
GND  
PCB  
TRACE NOISE  
DECOUPLING  
CAPACITOR  
12V IN  
5V IN  
3V IN  
12V OUT  
5V OUT  
3V OUT  
IN  
DC-DC1  
EN  
OUT  
3.3V OUT  
VH  
ADM1069  
PDO1  
PDO2  
5V OUT  
3V OUT  
3.3V OUT  
VP1  
VP2  
VP3  
IN  
DC-DC2  
PDO3  
PDO4  
PDO5  
EN  
OUT  
1.25V OUT  
1.25V OUT  
1.2V OUT  
0.9V OUT  
VX1  
VX2  
VX3  
POWER_GOOD  
SYSTEM RESET  
PDO6  
PDO7  
IN  
DC-DC3  
POWER_ON  
EN  
OUT  
1.2V OUT  
0.9V OUT  
VX4  
PDO8  
DAC1  
3.3V OUT  
IN  
REFIN VCCP VDDCAP GND  
OUT  
10  
F
10  
F
10 F  
EN  
TRIM  
DC-DC4  
SMBus  
POWER-UP  
(V > 2.5V)  
CC  
DEVICE  
CONTROLLER  
E
E
P
R
O
M
L
R
A
M
L
U
P
D
D
A
T
D
A
LATCH A  
LATCH B  
FUNCTION  
(OV THRESHOLD  
ON VP1)  
D
EEPROM  
1
9
1
9
SCL  
SDA  
1
0
0
1
1
A1  
A0 R/W  
D7  
D6 D5 D4  
D3 D2 D1  
D0  
START BY  
MASTER  
ACK. BY  
SLAVE  
ACK. BY  
SLAVE  
FRAME 1  
SLAVE ADDRESS  
FRAME 2  
COMMAND CODE  
1
9
1
9
SCL  
(CONTINUED)  
SDA  
(CONTINUED)  
D7 D6  
D5 D4  
D3 D2  
D1  
D0  
D7  
D6 D5 D4 D3 D2 D1  
D0  
STOP  
BY  
MASTER  
ACK. BY  
SLAVE  
ACK. BY  
SLAVE  
FRAME 3  
FRAME N  
DATA BYTE  
DATA BYTE  
1
9
1
9
SCL  
SDA  
1
0
0
1
1
A1  
A0 R/W  
D7  
D6 D5 D4  
D3 D2 D1  
D0  
ACK. BY  
SLAVE  
ACK. BY  
MASTER  
START BY  
MASTER  
FRAME 1  
SLAVE ADDRESS  
FRAME 2  
DATA BYTE  
1
9
1
9
SCL  
(CONTINUED)  
SDA  
(CONTINUED)  
D7 D6  
D5 D4  
D3 D2  
D1  
D0  
D7  
D6 D5 D4  
D3 D2  
D1  
D0  
NO ACK.  
STOP  
BY  
MASTER  
ACK. BY  
MASTER  
FRAME 3  
FRAME N  
DATA BYTE  
DATA BYTE  
tR  
tF  
tHD;STA  
tLO W  
tHD;STA  
tHD;DAT  
SCL  
SDA  
tHIGH  
tSU;STA  
tSU;STO  
tSU;DAT  
tBUF  
P
S
S
P
1
2
3
4
5
6
REGISTER  
ADDRESS  
(0x00 TO 0xDF)  
SLAVE  
ADDRESS  
S
W
A
A
P
1
2
3
4
5
6
7
8
RAM  
SLAVE  
ADDRESS  
S
W
A
ADDRESS  
A
DATA  
A
P
(0x00 TO 0xDF)  
1
2
3
4
5
6
COMMAND  
BYTE  
(0xFE)  
SLAVE  
ADDRESS  
S
W
A
A
P
1
2
3
4
5
6
7
8
EEPROM  
EEPROM  
SLAVE  
ADDRESS  
ADDRESS  
HIGH BYTE  
ADDRESS  
S
W
A
A
A
P
LOW BYTE  
(0x00 TO 0xFF)  
(0xF8 TO 0xFB)  
1
2
3
4
5
6
7
8
9
10  
P
EEPROM  
ADDRESS  
HIGH BYTE  
(0xF8 TO 0xFB)  
EEPROM  
ADDRESS  
LOW BYTE  
(0x00 TO 0xFF)  
SLAVE  
ADDRESS  
S
W
A
A
A
DATA  
A
1
2
3
4
5
6
SLAVE  
ADDRESS  
S
R
A
DATA  
A
P
1
2
3
4
5
6
7
8
9
10  
P
SLAVE  
ADDRESS  
COMMAND 0xFC  
(BLOCK WRITE)  
BYTE  
COUNT  
DATA  
1
DATA  
2
DATA  
A
N
S
W
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10 11 12  
DATA  
SLAVE  
ADDRESS  
COMMAND 0xFD  
(BLOCK READ)  
SLAVE  
ADDRESS  
BYTE  
COUNT  
S
W
A
A
S
R A  
A
A
1
13 14  
DATA  
32  
A
P
1
2
3
4
5
6
7
8
9
10 11 12  
DATA  
SLAVE  
ADDRESS  
COMMAND 0xFD  
(BLOCK READ)  
SLAVE  
ADDRESS  
BYTE  
COUNT  
S
W
A
A
S
R A  
A
A
1
13 14 15  
DATA  
32  
A
PEC A P  
0.75  
0.60  
0.45  
1.60  
MAX  
9.00 BSC SQ  
32  
25  
1
24  
PIN 1  
7.00  
BSC SQ  
TOP VIEW  
(PINS DOWN)  
1.45  
1.40  
1.35  
0.20  
0.09  
7°  
8
17  
3.5°  
0°  
0.15  
0.05  
9
16  
SEATING  
PLANE  
0.10 MAX  
COPLANARITY  
0.45  
0.37  
0.30  
0.80  
BSC  
VIEW A  
LEAD PITCH  
IEW A  
V
OTATED 90° CCW  
R
COMPLIANT TO JEDEC STANDARDS MS-026-BBA  

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