EVAL-ADRF6850EB1Z [ADI]
100 MHz to 1000 MHz Integrated Broadband Receiver; 100兆赫至1000兆赫综合宽带接收机
| 型号： | EVAL-ADRF6850EB1Z |
| 厂家： | 
ADI |
| 描述： | 100 MHz to 1000 MHz Integrated Broadband Receiver |
| 文件： | 总36页 (文件大小：1162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
100 MHz to 1000 MHz
Integrated Broadband Receiver
ADRF6850
FEATURES
GENERAL DESCRIPTION
IQ quadrature demodulator
Integrated fractional-N PLL and VCO
Gain control range: 60 dB
The ADRF6850 is a highly integrated broadband quadrature
demodulator, frequency synthesizer, and variable gain amplifier
(VGA). The device covers an operating frequency range from
100 MHz to 1000 MHz for use in both narrow-band and wideband
communications applications, performing quadrature demodu-
lation from IF directly to baseband frequencies.
Input frequency range: 100 MHz to 1000 MHz
Input P1dB: +12 dBm at 0 dB gain
Input IP3: +22.5 dBm at 0 dB gain
Noise figure: 11 dB at >39 dB gain, 49 dB at 0 dB gain
Baseband 1 dB bandwidth: 250 MHz in wideband mode,
50 MHz in narrow-band mode
The ADRF6850 demodulator includes a high modulus
fractional-N frequency synthesizer with integrated VCO,
providing better than 1 Hz frequency resolution, and a 60 dB
gain control range provided by a front-end VGA.
SPI/I2C serial interface
Power supply: +3.3 V/350 mA
Control of all the on-chip registers is through a user-selected
SPI interface or I2C interface. The device operates from a single
power supply ranging from 3.15 V to 3.45 V.
APPLICATIONS
Broadband communications
Cellular communications
Satellite communications
FUNCTIONAL BLOCK DIAGRAM
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
LOMON
LOMON
IBB
IBB
CCOMP1
CCOMP2
CCOMP3
60dB
GAIN CONTROL
RANGE
RFI
RFI
DRIVER
RFDIV
0°/90°
VCO
CORE
VTUNE
VOCM
RFCM
SEQUENCED
GAIN
INTERFACE
QBB
QBB
VGAIN
R
SET
REFERENCE
×2
5-BIT
DIVIDER
÷2
+
REFIN
DOUBLER
PHASE
CHARGE
PUMP
FREQUENCY
DETECTOR
CP
–
LF3
CURRENT SETTING
LF2
N-COUNTER
LDET
TESTLO
TESTLO
THIRD-ORDER
SDI/SDA
CLK/SCL
SDO
RFCP4 RFCP3 RFCP2 RFCP1
FRACTIONAL
SPI/
INTERPOLATOR
2
I C
INTERFACE
CS
FRACTIONAL
REGISTER
MODULUS
INTEGER
REGISTER
25
2
ADRF6850
GND
MUXOUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADRF6850
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C Interface ................................................................................ 20
SPI Interface................................................................................ 22
Program Modes .......................................................................... 24
Register Map ................................................................................... 26
Register Map Summary ............................................................. 26
Register Bit Descriptions........................................................... 27
Suggested Power-Up Sequence..................................................... 30
Initial Register Write Sequence ................................................ 30
Evaluation Board ............................................................................ 31
General Description................................................................... 31
Hardware Description ............................................................... 31
PCB Schematic............................................................................ 33
PCB Artwork............................................................................... 34
Bill of Materials........................................................................... 35
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 36
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 18
Overview...................................................................................... 18
PLL Synthesizer and VCO......................................................... 18
Quadrature Demodulator.......................................................... 20
Variable Gain Amplifier (VGA) ............................................... 20
REVISION HISTORY
10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADRF6850
SPECIFICATIONS
VCC = 3.3 V; ambient temperature (TA) = 25°C; ZS = 50 Ω; ZL = 100 Ω differential; PLL loop bandwidth = 50 kHz; REFIN = 13.5 MHz;
PFD = 27 MHz; baseband frequency = 20 MHz, narrow-band mode, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT
RFI, RFI, VGAIN pins
Operating Frequency Range
Input P1dB
100
1000
MHz
dBm
dBm
dBm
dBm
dBm
dBm
dB
0 dB gain
60 dB gain
+12
−48
+22.5
−38
+40
−20
49
Input IP3
0 dB gain
60 dB gain
0 dB gain, single-ended input
60 dB gain, single-ended input
0 dB gain
Input IP2
Noise Figure (NF)
<39 dB gain NF rises 1:1 as gain in dB falls
>39 dB gain
ZS = 50 Ω single-ended, ZL = 100 Ω differential
ZS = 50 Ω single-ended, ZL = 100 Ω differential
VGAIN from 200 mV to 1.3 V
11
60
0
0.5
25
20
15
dB
dB
dB
dB
mV/dB
kΩ
dB
Maximum Gain
Minimum Gain
Gain Conformance Error1
Gain Slope
VGAIN Input Impedance
Return Loss
Relative to ZS = 50 Ω, 100 MHz to 1 GHz
REFIN pin
REFERENCE CHARACTERISTICS
Input Frequency
With R divide-by-2 divider enabled
With R divide-by-2 divider disabled
10
10
0.4
300
165
VCC
10
MHz
MHz
V p-p
pF
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
CHARGE PUMP
ICP Sink/Source
100
µA
CP and RSET pins
Programmable
High Value
Low Value
Absolute Accuracy
VCO
With RSET = 4.7 kΩ
5
mA
µA
%
312.5
2.5
With RSET = 4.7 kΩ
Gain
KVCO
15
1
MHz/V
SYNTHESIZER SPECIFICATIONS
Frequency Increment
Phase Frequency Detector
Spurs
Loop bandwidth = 50 kHz
Hz
MHz
10
30
Integer boundary < loop bandwidth
>10 MHz offset from carrier
LO frequency = 1000 MHz
@ 10 Hz offset
@ 100 Hz offset
@ 1 kHz offset
@ 10 kHz offset
@ 100 kHz offset
@ 1 MHz offset
>10 MHz offset
−55
−70
dBc
dBc
Phase Noise
−75
−80
−90
−98
−110
−136
−149
0.26
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
Integrated Phase Noise
1 kHz to 8 MHz integration bandwidth
Rev. 0 | Page 3 of 36
ADRF6850
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
μs
Frequency Settling
Any step size, maximum frequency error = 1 kHz
260
Maximum Frequency Step for No Frequency step with no autocalibration routine;
100
kHz
Autocalibration
BASEBAND OUTPUTS
Maximum Swing
Common-Mode Range
Output Impedance
Output DC Offset
1 dB Bandwidth
Register CR24, Bit 0 = 1
IBB, IBB, QBB, QBB, VOCM pins
Driving ZL = 100 Ω differential
2.5
V p-p
V
Ω
1.2
1.6
Differential
RFI terminated in ZS = 50 Ω
28
20
mV
Wideband Mode
Narrow-Band Mode
IQ Balance
250
50
MHz
MHz
Amplitude
Wideband Mode
Narrow-Band Mode
Phase
Baseband frequency ≤ 250 MHz
Baseband frequency ≤ 33.2 MHz
0.1
0.1
dB
dB
Wideband Mode
Narrow-Band Mode
IQ Output Impedance Mismatch
Group Delay Variation
Wideband Mode
Baseband frequency ≤ 250 MHz
Baseband frequency ≤ 33.2 MHz
Baseband frequency = 10 MHz
0.5
0.25
0.3
Degrees
Degrees
%
Baseband frequency ≤ 210 MHz
Baseband frequency ≤ 250 MHz
Baseband frequency ≤ 33.2 MHz
1× LO
2× LO
4× LO
0.25
0.35
0.2
−40
−60
−60
−40
ns
ns
ns
dBm
dBm
dBm
dBc
Narrow-Band Mode
LO to IQ Leakage
RF to IQ Leakage
Relative to IQ output level
LOMON and LOMON pins
MONITOR OUTPUT
Nominal Output Power
LOGIC INPUTS
−24
dBm
SDI/SDA, CLK/SCL, CS pins
CS
CS
SDI/SDA, CLK/SCL
SDI/SDA, CLK/SCL
CS, SDI/SDA, CLK/SCL
CS, SDI/SDA, CLK/SCL
Input High Voltage, VINH
Input Low Voltage, VINL
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
1.4
2.1
V
V
V
V
µA
pF
0.6
1.1
1
10
Output High Voltage, VOH
Output Low Voltage, VOL
SDO, LDET pins; IOH = 500 μA
SDO, LDET pins; IOL = 500 μA
SDA (SDI/SDA) pins; IOL = 3 mA
2.8
V
V
V
0.4
0.4
POWER SUPPLIES
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, and
VCC9 pins
Voltage Range
Supply Current
Operating Temperature
3.15
−40
3.3
350
3.45
440
+85
V
mA
°C
1 Difference between channel gain and linear fit to channel gain.
Rev. 0 | Page 4 of 36
ADRF6850
TIMING CHARACTERISTICS
I2C Interface Timing
Table 2.
Parameter1
Symbol
fSCL
tHIGH
Limit
400
600
1300
600
600
100
300
600
900
900
1300
Unit
SCL Clock Frequency
SCL Pulse Width High
SCL Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
Stop Condition Setup Time
Data Valid Time
kHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tSU;STO
tVD;DAT
tVD;ACK
tBUF
Data Valid Acknowledge Time
Bus Free Time
1 See Figure 2.
tVD;DAT AND
tVD;ACK (ACK SIGNAL ONLY)
tSU;DAT
tBUF
SDA
tSU;STA
tSU;STO
tHD;STA
tLOW
SCL
S
S
P
S
1/fSCL
tHD;DAT
tHIGH
START
CONDITION
STOP
CONDITION
Figure 2. I2C Port Timing Diagram
Rev. 0 | Page 5 of 36
ADRF6850
SPI Interface Timing
Table 3.
Parameter1
Symbol
Limit
20
15
15
5
10
5
5
Unit
CLK Frequency
fCLK
t1
t2
t3
t4
t5
t6
t7
t8
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
CLK Pulse Width High
CLK Pulse Width Low
Start Condition Hold Time
Data Setup Time
Data Hold Time
Stop Condition Setup Time
SDO Access Time
15
25
CS to SDO High Impedance
1 See Figure 3.
t3
CS
t1
CLK
SDI
t6
t2
t4
t5
SDO
t7
t8
Figure 3. SPI Port Timing Diagram
Rev. 0 | Page 6 of 36
ADRF6850
ABSOLUTE MAXIMUM RATINGS
Table 4. Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage Pins (VCC1, VCC2, VCC3,
VCC4, VCC5, VCC6, VCC7, VCC8, VCC9)
−0.3 V to +4.0 V
Analog Input/Output
Digital Input/Output
RFI, RFI, RFCM
−0.3 V to +4.0 V
−0.3 V to +4.0 V
0 V to 3.0 V
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Storage Temperature Range
26°C/W
125°C
−65°C to +150°C
ESD CAUTION
Rev. 0 | Page 7 of 36
ADRF6850
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC1
IBB
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
42 VCC8
41 GND
IBB
40 LDET
QBB
QBB
GND
VOCM
GND
RSET
39 MUXOUT
38 VTUNE
37 GND
ADRF6850
36 VCC7
35 CCOMP3
34 CCOMP2
33 CCOMP1
32 GND
TOP VIEW
(Not to Scale)
LF3 10
CP 11
LF2 12
31 VCC6
30 CLK/SCL
29 SDI/SDA
VCC2 13
VCC3 14
NOTES
1. CONNECT EXPOSED PAD TO GROUND PLANE VIA
A LOW IMPEDANCE PATH.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 13, 14, 15, 16,
31, 36, 42, 49
VCC1 to VCC9
Positive Power Supplies. Apply a 3.3 V power supply to all VCCx pins. Decouple each pin with a power
supply decoupling capacitor.
6, 8, 19, 20, 21,
24, 32, 37, 41,
44, 45, 46, 47,
48, 50, 52, 54, 56
GND
Analog Ground. Connect to a low impedance ground plane.
2, 3, 4, 5
IBB, IBB, QBB,
QBB
Differential In-Phase and Quadrature Baseband Outputs. These low impedance outputs can drive
2.5 V p-p into 100 Ω differential loads.
7
VOCM
Baseband Common-Mode Voltage Input. When ac coupling the baseband output pins, ground
VOCM. There is an option to apply an external voltage, which may be relevant when dc coupling the
baseband output pins. Note that Register CR29, Bit 6 must be set accordingly.
33
34
35
38
CCOMP1
CCOMP2
CCOMP3
VTUNE
Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor.
Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor.
Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering
the CP output voltage.
9
RSET
Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum
charge pump output current. The relationship between ICP and RSET is
23.5
ICPmax
=
RSET
where RSET = 4.7 kΩ and ICP max = 5 mA.
11
27
CP
CS
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn,
drives the internal VCO.
Chip Select. CMOS input. When CS is high, the data stored in the shift registers is loaded into one of
the 31 registers. In I2C mode, when CS is high, the slave address of the device is 0x78, and when CS is
low, the slave address is 0x58.
29
SDI/SDA
Serial Data Input for SPI Port, Serial Data Input/Output for I2C Port. In SPI mode. This input is a high
impedance CMOS data input, and data is loaded in an 8-bit word. In I2C mode, this pin is a
bidirectional port.
30
28
CLK/SCL
SDO
Serial Clock Input for SPI/I2C Port. This serial clock is used to clock in the serial data to the registers.
This input is a high impedance CMOS input.
Serial Data Output for SPI Port. Register states can be read back on the SDO data output line in an
8-bit word.
17
18
REFIN
REFIN
Reference Input. AC couple this high impedance CMOS input.
Reference Input Bar. Ground this pin.
Rev. 0 | Page 8 of 36
ADRF6850
Pin No.
Mnemonic
Description
51, 55
RFI, RFI
RF Inputs. 50 Ω internally biased RF inputs. For single-ended operation, RFI must be ac-coupled to
the source, and RFI must be ac-coupled to the ground plane.
53
RFCM
RF Input Common Mode. Connect to RFI when driving the input in single-ended mode. When driving
the input differentially using a balun, connect this pin to the common terminal of the output coil of
the balun. Decouple RFCM to the ground plane.
25, 26
LOMON,
LOMON
Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency
(1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately.
These open-collector outputs must be terminated with external resistors to VCCx. These outputs can
be disabled through serial port programming and should be connected to VCCx if not used.
10, 12
40
LF3/LF2
LDET
Extra Loop Filter Pins for Fastlock. Use these pins to reduce lock time.
Lock Detect. This pin provides an active high output when the PLL frequency is locked. The lock
detect timing is controlled by Register CR14 (Bit 7) and Register CR23 (Bit 3).
39
MUXOUT
Muxout. This output is a test output for diagnostic use only. Allow this pin to remain open circuit.
22, 23
43
TESTLO, TESTLO Differential Test Inputs. For internal use only. These pins should be grounded.
VGAIN
VGA Gain Input. Drive this pin by a voltage in the range from 0 V to 1.5 V. This voltage controls the
gain of the VGA. A 0 V input sets the VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to
+60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set to 0. If the VGA gain mode polarity bit is
set to 1, a 0 V input sets the VGA gain to +60 dB, whereas a 1.5 V input sets the VGA gain to 0 dB.
EP
Exposed Paddle. Connect the exposed pad to the ground plane via a low impedance path.
Rev. 0 | Page 9 of 36
ADRF6850
TYPICAL PERFORMANCE CHARACTERISTICS
A nominal condition is defined as 25°C, 3.30 V, and worst-case frequency. A worst-case condition is defined as having the worst-case
temperature, supply voltage, and frequency.
20
50
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
NOMINAL
WORST-CASE
45
40
35
30
25
10
0
–10
–20
20
15
10
–30
–40
–50
–60
5
0
0
10
20
30
40
50
60
8.6 9.0 9.4 9.8 10.2 10.6 11.0 11.4 11.8 12.2 12.6 13.0 13.4
INPUT P1dB AT CHANNEL GAIN OF 0dB (dBm)
CHANNEL GAIN (dB)
Figure 5. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF
Input Frequency, Nominal Conditions, Narrow-Band Mode
Figure 8. Input 1dB Compression Point (IP1dB) Distribution with Channel
Gain = 0 dB at Nominal and Worst-Case Conditions
20
60
3.30V, 25°C
NOMINAL
55
50
45
40
35
30
25
20
15
10
5
WORST-CASE
3.15V, –40°C
10
0
–10
3.45V, –40°C
3.15V, 85°C
3.45V, 85°C
–20
–30
–40
–50
–60
0
0
10
20
30
40
50
60
CHANNEL GAIN (dB)
INPUT P1dB AT CHANNEL GAIN OF 60dB (dBm)
Figure 6. Input 1dB Compression Point (IP1dB) vs. Channel Gain, Supply, and
Temperature, RF Input Frequency = 100 MHz, Narrow-Band Mode
Figure 9. Input 1dB Compression Point (IP1dB) Distribution with Channel
Gain = 60 dB at Nominal and Worst-Case Conditions
20
20
3.30V, +25°C
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
3.15V, –40°C
3.45V, –40°C
3.15V, +85°C
3.45V, +85°C
10
0
10
0
–10
–20
–30
–40
–50
–60
–10
–20
–30
–40
–50
–60
0
10
20
30
40
50
60
–10
0
10
20
30
40
50
60
70
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure 7. Input 1dB Compression Point (IP1dB) vs. Channel Gain, Supply, and
Temperature, RF Input Frequency = 1000 MHz, Narrow-Band Mode
Figure 10. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF
Input Frequency, VOCM = 1.2 V, Nominal Conditions, Narrow-Band Mode
Rev. 0 | Page 10 of 36
ADRF6850
20
10
30
20
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
0
10
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–10
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure 11. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF
Input Frequency, VOCM = 1.6 V, Nominal Conditions, Narrow-Band Mode
Figure 14. Input IP3 vs. Channel Gain, and RF Input Frequency,
Worst-Case Conditions
70
20
IQ = 20MHz
NOMINAL
WORST-CASE
IQ = 50MHz
10
60
50
40
30
20
10
0
IQ = 100MHz
IQ = 200MHz
IQ = 250MHz
0
–10
–20
–30
–40
–50
–60
19.6 20.0 20.4 20.8 21.2 21.6 22.0 22.4 22.8 23.2
IIP3 AT CHANNEL GAIN = 0dB (dBm)
24.0
23.6
0
10
20
30
40
50
60
CHANNEL GAIN (dB)
Figure 12. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and IQ
Output Frequency, LO = 1000 MHz, Nominal Conditions, Wideband Mode
Figure 15. Input IP3 Distribution with Channel Gain = 0 dB at Nominal and
Worst-Case Conditions
35
30
NOMINAL
WORST-CASE
RF = 100MHz
RF = 300MHz
20
30
RF = 550MHz
RF = 800MHz
RF = 1000MHz
10
0
25
20
15
10
5
–10
–20
–30
–40
–50
0
–40.4 –40.0 –39.6 –39.2 –38.8 –38.4 –38.0 –37.6 –37.2 –36.8 –36.4 –36.0
0
10
20
30
40
50
60
70
IIP3 AT CHANNEL GAIN = 60dB (dBm)
CHANNEL GAIN (dB)
Figure 16. Input IP3 Distribution with Channel Gain = 60 dB at Nominal and
Worst-Case Conditions
Figure 13. Input IP3 vs. Channel Gain, and RF Input Frequency,
Nominal Conditions
Rev. 0 | Page 11 of 36
ADRF6850
30
70
60
50
20
10
40
30
0
–10
–20
–30
20
10
0
IQ FREQUENCIES = 16MHz AND 19MHz
–10
–20
IQ FREQUENCIES = 46MHz AND 49MHz
IQ FREQUENCIES = 96MHz AND 99MHz
IQ FREQUENCIES = 196MHz AND 199MHz
IQ FREQUENCIES = 246MHz AND 249MHz
–40
DIRECT IIP2
DOWN-CONVERTED IIP2
–50
–10
–30
–10
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure 17. Input IP3 vs. Channel Gain, and IQ Output Frequency,
Wideband Mode, Nominal Conditions
Figure 20. Input IP2 vs. Channel Gain, Wideband Mode,
Worst-Case Conditions
30
20
60
50
40
30
20
10
0
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
10
0
–10
–20
–30
IQ FREQUENCIES = 16MHz AND 19MHz
IQ FREQUENCIES = 46MHz AND 49MHz
IQ FREQUENCIES = 96MHz AND 99MHz
IQ FREQUENCIES = 196MHz AND 199MHz
IQ FREQUENCIES = 246MHz AND 249MHz
–40
–50
–10
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure 18. Input IP3 vs. Channel Gain, and IQ Output Frequency,
Wideband Mode, Worst-Case Conditions
Figure 21. Noise Figure vs. Channel Gain, and RF Input Frequency,
Narrow-Band Mode, Nominal Conditions
60
70
RF = 100MHz
RF = 300MHz
60
50
40
30
20
10
0
RF = 550MHz
50
RF = 800MHz
RF = 1000MHz
40
30
20
10
0
DIRECT IIP2
–10
–20
DOWN-CONVERTED IIP2
0
10
20
30
40
50
60
70
–10
0
10
20
30
40
50
60
70
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure 19. Input IP2 vs. Channel Gain, Wideband Mode, Nominal Conditions
Figure 22. Noise Figure vs. Channel Gain, and RF Input Frequency,
Narrow-Band Mode, Worst-Case Conditions
Rev. 0 | Page 12 of 36
ADRF6850
70
60
50
40
30
20
10
0
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
60
50
40
30
20
10
0
–10
0
10
20
30
40
50
60
70
0
0.2
0.4
0.6
0.8
(V)
1.0
1.2
1.4
CHANNEL GAIN (dB)
V
GAIN
Figure 23. Noise Figure Distribution vs. Channel Gain, Narrow-Band Mode,
Nominal Conditions
Figure 26. Channel Gain vs. VGAIN and RF Input Frequency,
Nominal Conditions
60
50
40
30
20
10
0
60
NOMINAL
WORST-CASE
50
40
30
20
10
0
0
10
20
30
40
50
60
70
CHANNEL GAIN (dB)
CHANNEL GAIN RANGE (dB)
Figure 24. Noise Figure Distribution vs. Channel Gain, Narrow-Band Mode,
Worst-Case Conditions
Figure 27. Channel Gain Range Distribution at Nominal and
Worst-Case Conditions
60
1.0
RF = 100MHz
3.30V, 25°C
3.15V, –40°C
3.45V, –40°C
3.15V, 85°C
3.45V, 85°C
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
50
40
30
20
10
0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
10
20
30
40
50
60
70
100
200
300
400
500
600
700
800
900 1000
CHANNEL GAIN (dB)
RF INPUT FREQUENCY (MHz)
Figure 25. Noise Figure vs. Channel Gain, and RF Input Frequency,
Wideband Mode, Nominal Conditions
Figure 28. Minimum Channel Gain vs. RF Input Frequency,
Supply, and Temperature
Rev. 0 | Page 13 of 36
ADRF6850
30
3
2
NOMINAL
WORST-CASE
RF = 100MHz
RF = 300MHz
RF = 550MHz
RF = 800MHz
RF = 1000MHz
25
20
15
10
5
1
0
–1
–2
–3
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGAIN (V)
MINIMUM CHANNEL GAIN (dB)
Figure 29. Minimum Channel Gain Distribution at Nominal and
Worst-Case Conditions
Figure 32. Channel Gain Conformance Error vs. VGAIN and RF Input Frequency,
Nominal Conditions
63.0
0
3.30V, 25°C
3.15V, –40°C
3.45V, –40°C
V
V
V
V
= 0V
3.15V, 85°C
3.45V, 85°C
GAIN
GAIN
GAIN
GAIN
= 0.5V
= 1.0V
= 1.5V
–5
–10
–15
–20
–25
–30
–35
62.5
62.0
61.5
61.0
60.5
60.0
100
200
300
400
500
600
700
800
900 1000
100
200
300
400
500
600
700
800
900 1000
RF INPUT FREQUENCY (MHz)
RF INPUT FREQUENCY (MHz)
Figure 30. Maximum Channel Gain vs. RF Input Frequency,
Supply, and Temperature
Figure 33. Input Return Loss vs. RF Input Frequency and Channel Gain,
Nominal Conditions
25
0
INTEGER BOUNDARY SPUR AT 9.6kHz OFFSET
NOMINAL
WORST-CASE
INTEGER BOUNDARY SPUR AT 19.2kHz OFFSET
–10
INTEGER BOUNDARY SPUR AT 38.4kHz OFFSET
–20
20
15
10
5
–30
–40
–50
–60
–70
–80
–90
–100
0
100
200
300
400
500
600
700
800
900 1000
LO FREQUENCY (MHz)
MAXIMUM CHANNEL GAIN (dB)
Figure 31. Maximum Channel Gain Distribution at Nominal and
Worst-Case Conditions
Figure 34. Integer Boundary Spurs vs. LO Frequency, Channel Gain,
Supply, and Temperature
Rev. 0 | Page 14 of 36
ADRF6850
TABLE OF DISTRIBUTION DATA:
0
–20
OFFSET FREQUENCY (Hz):
TYPICAL RANGE (dBc/Hz):
10
100
1k
10k
100k
1M
10M
–75/–85 –78/–89 –84/–95 –97/–100 –110/–113 –136/–138 –149/–153
WORST-CASE RANGE (dBc/Hz): –72/–82 –74/–89 –89/–96 –97/–100 –110/–112 –136/–138 –149/–152
–60
–70
–80
–40
–90
–60
V
= 1.5V
GAIN
–100
–110
–120
–130
–140
–150
–160
–80
V
≤ 1.0V
GAIN
–100
–120
100
200
300
400
500
600
700
800
900 1000
LO FREQUENCY (MHz)
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Figure 35. Reference Spurs at 13.5 MHz from Carrier vs. LO Frequency,
Channel Gain, Supply, and Temperature
Figure 38. Phase Noise Performance Including Distribution Table at LO
Frequency = 1000 MHz at Nominal and Worst-Case Conditions
0
–20
–40
–60
0.4
3.30V; +25°C
3.15V; +85°C
3.45V; +85°C
3.15V; –40°C
3.45V; –40°C
0.3
0.2
0.1
0
V
= 1.5V
GAIN
–80
–100
–120
V
≤ 1.0V
GAIN
100
200
300
400
500
600
700
800
900 1000
100
200
300
400
500
600
700
800
900 1000
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 36. PFD Spurs at 27 MHz from Carrier vs. LO Frequency, Channel Gain,
Supply, and Temperature
Figure 39. Integrated Phase Noise vs. LO Frequency, Supply, and
Temperature
TABLE OF DISTRIBUTION DATA:
30
OFFSET FREQUENCY (Hz):
TYPICAL RANGE (dBc/Hz):
10
100
1k
10k
100k
1M
10M
NOMINAL
WORST-CASE
–91/–100 –99/–111 –107/–115 –118/–121 –129/–132 –150/–154 –151/–153
WORST-CASE RANGE (dBc/Hz): –90/–105 –95/–108 –105/–116 –118/–121 –128/–131 –151/–154 –151/–153
25
20
15
10
5
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
0
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
RMS JITTER (Degrees)
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Figure 37. Phase Noise Performance Including Distribution Table at LO
Frequency = 100 MHz at Nominal and Worst-Case Conditions
Figure 40. Integrated Phase Noise Distribution with LO Frequency =
1000 MHz at Nominal and Worst-Case Conditions
Rev. 0 | Page 15 of 36
ADRF6850
1G
100M
10M
1M
30
BEST CASE
TYPICAL
WORST CASE
25
20
ACQUISITION
TO 1kHz
100k
10k
15
10
5
1k
100
START OF ACQUISITION
ON CR0 WRITE
10
1
CR23[3] = 1
CR23[3] = 0
LDET
LDET
0.1
0.01
–50
0
0
50 100 150 200 250 300 350 400 450 500 550
TIME (µs)
ABSOLUTE IQ AMPLITUDE BALANCE (dB)
Figure 44. Absolute IQ Amplitude Balance, Narrow-Band Mode,
Nominal Conditions
Figure 41. PLL Frequency Settling Time with Typical, Best-Case, and Worst-
Case Frequency Hop with Lock Detect Shown, Nominal Conditions
20
18
16
14
12
10
8
20
I OUTPUT
Q OUTPUT
18
16
14
12
10
8
6
6
4
4
2
2
0
0
–0.45 –0.35 –0.25 –0.15 –0.05 0.05 0.15 0.25 0.35 0.45
–18 –14 –10 –6 –2
2
6
10 14 18 22 26 30
IQ PHASE BALANCE (Degrees)
OUTPUT DC OFFSET (mV)
Figure 45. IQ Phase Balance, Narrow-Band Mode, Nominal Conditions
Figure 42. Output DC Offset Distribution for I and Q Outputs,
Nominal Conditions
0
5
–10
–20
–30
0
–5
V
= 1.5V
GAIN
–40
–50
–60
–70
–80
–90
–100
–10
–15
–20
–25
–30
WB MODE
NB MODE= 50MHz
NB MODE = 43MHz
NB MODE = 37MHz
NB MODE= 30MHz
V
= 0V, 0.5V, 1V
GAIN
0.1
1
10
100
1000
100
200
300
400
500
600
700
800
900 1000
IQ OUTPUT FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 43. Normalized IQ Output Bandwidth, Narrow-Band, and
Wideband Modes, Nominal Conditions
Figure 46. 1× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and
Temperature (Narrow-Band Mode)
Rev. 0 | Page 16 of 36
ADRF6850
0
0
–20
–40
–20
–40
V
= 1.5V
GAIN
V
= 1.3V
GAIN
–60
–60
–80
–80
V
= 0V, 0.5V, 1V
GAIN
–100
–100
–120
–120
100
200
300
400
500
600
700
800
900 1000
330
430
530
630
730
830
930
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 47. 2× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and
Temperature (Narrow-Band Mode)
Figure 50. 1× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and
Temperature, Fourth-Order Filter at 300 MHz Applied, Wideband Mode
0
0
–20
–40
–20
–40
V
= 1.5V
GAIN
–60
–60
–80
–80
–100
–100
V
= 0V, 0.5V, 1V
GAIN
–120
–120
100
200
300
400
500
600
700
800
900 1000
100
200
300
400
500
600
700
800
900 1000
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 48. 4× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and
Temperature (Narrow-Band Mode)
Figure 51. 1× RF Feedthrough vs. RF Input Frequency, VGAIN, Supply, and
Temperature, Narrow-Band Mode
0
25
NOMINAL
WORST-CASE
–20
20
V
= 1.0V
GAIN
–40
–60
V
= 1.5V
GAIN
V
= 1.3V
15
10
5
GAIN
–80
–100
–120
–140
V
= 0V, 0.5V, 1V
GAIN
0
330
430
530
630
730
830
930
RF FREQUENCY (MHz)
1× LO FEEDTHOUGH (dBm)
Figure 49. 1× LO Feedthrough Distribution at Nominal and Worst-Case
Conditions with LO Frequency > 300 MHz,
Narrow-Band Mode
Figure 52. 1× RF Feedthrough vs. RF Input Frequency, VGAIN, Supply, and
Temperature, Fourth-Order Filter at 300 MHz Applied, Wideband Mode
Rev. 0 | Page 17 of 36
ADRF6850
THEORY OF OPERATION
FROM
REFIN
PIN
OVERVIEW
TO
PFD
×2
5-BIT
÷2
DOUBLER
R-DIVIDER
The ADRF6850 device can be separated into the following basic
building blocks:
Figure 54. Reference Input Path
The PFD frequency equation is
PFD = fREFIN × [(1 + D)/(R × (1 + T))]
where:
REFIN is the reference input frequency.
D is the doubler bit.
R is the programmed divide ratio of the binary 5-bit
programmable reference divider (1 to 32).
T is the ÷2 bit (0 or 1).
•
•
•
•
PLL synthesizer and VCO
Quadrature demodulator
Variable gain amplifier (VGA)
I2C/SPI interface
f
(1)
f
Each of these building blocks is described in detail in the
sections that follow.
PLL SYNTHESIZER AND VCO
Overview
RF Fractional-N Divider
The phase-locked loop (PLL) consists of a fractional-N frequency
synthesizer with a 25-bit fixed modulus, allowing a frequency
resolution of less than 1 Hz over the entire frequency range. It
also has an integrated voltage controlled oscillator (VCO) with
a fundamental output frequency ranging from 2000 MHz to
4000 MHz. An RF divider, controlled by Register CR28, Bits[2:0],
extends the lower limit of the frequency range to less than
400 MHz. This 400 MHz to 4000 MHz frequency output is
then applied to a divide-by-4 quadrature circuit to provide a
local oscillator (LO) ranging from 100 MHz to 1000 MHz to the
quadrature demodulator.
The RF fractional-N divider allows a division ratio in the PLL
feedback path that can range from 23 to 4095. The relationship
between the fractional-N divider and the LO frequency is
described in the following section.
INT and FRAC Relationship
The integer (INT) and fractional (FRAC) values make it
possible to generate output frequencies that are spaced by
fractions of the phase frequency detector (PFD) frequency.
See the Programming the Correct LO Frequency section for
more information.
The LO frequency equation is
Reference Input Section
LO = fPFD × (INT + (FRAC/225))/2 × 2RFDIV
where:
LO is the local oscillator frequency.
PFD is the PFD frequency.
INT is the integer component of the required division factor
and is controlled by the CR6 and CR7 registers.
(2)
The reference input stage is shown in Figure 53. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
open. This ensures that there is no loading of the REFIN pin at
power-down.
f
POWER-DOWN
CONTROL
FRAC is the fractional component of the required division
factor and is controlled by the CR0 to CR3 registers.
RFDIV is the setting in Register CR28, Bits[2:0], and controls
the setting of a divider at the output of the PLL.
100kΩ
NC
TO
R-DIVIDER
SW2
REFIN
NC
SW1
BUFFER
SW3
25
RF N-DIVIDER
N-COUNTER
N = INT + FRAC/2
TO
PFD
NC
FROM VCO
OUTPUT
DIVIDERS
Figure 53. Reference Input Stage
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
Reference Input Path
The on-chip reference frequency doubler allows the input
frequency of the reference signal to be doubled. This is useful
for increasing the PFD comparison frequency. Making the PFD
frequency higher improves the noise performance of the system.
Doubling the PFD frequency usually improves the in-band phase
noise performance by 3 dBc/Hz.
INT
FRAC
REG
VALUE
Figure 55. RF Fractional-N Divider
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R-divider and the N-counter and
produces an output proportional to the phase and frequency differ-
ence between them (see Figure 56 for a simplified schematic).
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, ensuring that there is no dead zone in
the PFD transfer function.
The 5-bit R-divider allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 32 are allowed.
An additional divide-by-2 (÷2) function in the reference input
path allows for a greater division range.
Rev. 0 | Page 18 of 36
ADRF6850
UP
The correct VCO and band are chosen automatically by the
HI
D1
Q1
U1
VCO and band select circuitry when Register CR0 is updated.
This is referred to as autocalibration. The autocalibration time
is set by Register CR25.
+IN
CLR1
CHARGE
PUMP
Autocalibration Time = (BSCDIV × 24)/PFD
(3)
CP
DELAY
U3
where:
BSCDIV = Register CR25, Bits[7:0].
PFD = PFD frequency.
CLR2
D2 Q2
DOWN
HI
For a PFD frequency of 27 MHz, BSCDIV = 112 to set an
autocalibration time of 100 µs.
U2
–IN
Note that BSCDIV must be recalculated if the PFD frequency is
changed. The recommended autocalibration setting is 100 µs.
During this time, the VCO VTUNE is disconnected from the output
of the loop filter and is connected to an internal reference voltage.
A typical frequency acquisition is shown in Figure 58.
1G
Figure 56. PFD Simplified Schematic
Lock Detect (LDET)
LDET (Pin 40) signals when the PLL has achieved lock to an
error frequency of less than 1 kHz. On a write to Register CR0,
a new PLL acquisition cycle starts, and the LDET signal goes
low. When lock has been achieved, this signal returns high.
100M
10M
Voltage Controlled Oscillator (VCO)
The VCO core in the ADRF6850 consists of three separate VCOs,
each with 16 overlapping bands. This configuration of 48 bands
allows the VCO frequency range to extend from 2000 MHz to
4000 MHz. The three VCOs are divided externally by a program-
mable divider (RFDIV controlled by Register CR28, Bits[2:0]).
This divider provides divisions of 1, 2, 4, and 8 to ensure that the
frequency range is extended from 250 MHz (2000 MHz/8) to
4000 MHz (4000 MHz/1). A lower limit of only 400 MHz is
required. A divide-by-4 quadrature circuit provides the full LO
frequency range from 100 MHz to 1000 MHz. Figure 57 shows
a sweep of VTUNE vs. LO frequency demonstrating the three VCOs
overlapping and the multiple overlapping bands within each
VCO at the LO frequency range of 100 MHz to 1000 MHz. Note
that this plot includes the RFDIV divider being incorporated to
provide further divisions of the fundamental VCO frequency;
thus, each VCO is used on four different occasions throughout the
full LO frequency range. The choice of three 16-band VCOs and
an RFDIV divider allows the wide frequency range to be covered
without large VCO sensitivity (KVCO) or resultant poor phase
noise and spurious performance.
AUTOCAL
TIME (µs)
1M
100k
10k
1k
ACQUISITION TO 1kHz
100
10
1
0
50
100 150 200 250 300 350 400 450 500
TIME (µs)
Figure 58. PLL Acquisition
After autocalibration, normal PLL action resumes, and the
correct frequency is acquired to within a frequency error of
1 kHz in 260 μs typically. For a maximum cumulative step of
100 kHz, autocalibration can be turned off by Register CR24,
Bit 0. This enables cumulative PLL acquisitions of 100 kHz or
less to occur without the autocalibration procedure, which
improves acquisition times significantly (see Figure 59).
1G
2.5
100M
10M
1M
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
100k
ACQUISITION TO 1kHz
10k
1k
100
10
1
0
20
40
60
80
100 120 140 160 180 200
TIME (µs)
100
200
300
400
500
600
700
800
900 1000
LO FREQUENCY (MHz)
Figure 59. PLL Acquisition Without Autocalibration for a 100 kHz Step
Rev. 0 | Page 19 of 36
Figure 57. VTUNE vs. LO Frequency
ADRF6850
The VCO displays a variation of KVCO as VTUNE varies within
the band and from band to band. Figure 60 shows how the
Example to Program the Correct LO Frequency
Assume that the PFD frequency is 27 MHz and the required LO
frequency is 330 MHz.
KVCO varies across the fundamental LO frequency range from
500 MHz to 1000 MHz. Note that KVCO is shown at the LO
frequency rather than at the VCO frequency. Figure 60 is useful
when calculating the loop filter bandwidth and individual loop
filter components using ADISimPLL™. ADISimPLL is an
Analog Devices, Inc., simulator that aids in PLL design,
particularly with respect to the loop filter. It reports parameters
such as phase noise, integrated phase noise, acquisition time,
and so forth for a particular set of input conditions.
ADISimPLL can be downloaded from www.analog.com.
25
Step 1. From Table 6, 2RFDIV = 2.
Step 2. N = (2 × 2 × 330E+6)/(27E+6) = 48.88888889.
The N-divider value is composed of integer (INT) and
fractional (FRAC) components according to the following
equation:
N = INT + FRAC/225
(5)
INT = 48 and FRAC = 29,826,162.
The appropriate registers must then be programmed according to
the register map, ensuring that Register CR0 is the last register
to be programmed because this write starts a new PLL acquisi-
tion cycle.
20
15
10
5
QUADRATURE DEMODULATOR
The quadrature demodulator can be powered up by Register CR29,
Bit 0. It has an output filter with narrow-band and wideband
modes, which are selected by Register CR29, Bit 3. Wideband
mode has a 1 dB filter cutoff of 250 MHz. Narrow-band mode
has selectable cutoff filters of 30 MHz through 50 MHz by pro-
gramming Register CR29, Bits[5:4]. A dc bias voltage of 1.4 V
(VOCM) can be set internally by setting Register CR29, Bit 6 = 1.
To select an external dc bias voltage, set Register CR29, Bit 6 = 0,
and drive Pin 7, VOCM, with the requisite external bias voltage.
0
500 550 600 650 700 750 800 850 900 950 1000
LO FREQUENCY (MHz)
Figure 60. KVCO vs. LO Frequency
VARIABLE GAIN AMPLIFIER (VGA)
Programming the Correct LO Frequency
The variable gain amplifier (VGA) at the input to the demodulator
can be driven either single-ended or differentially.
There are two steps to programming the correct LO frequency.
The user can calculate the N-divider ratio that is required in the
PLL and the RFDIV value based on the required LO frequency
and PFD frequency.
RFI
To drive single-ended, connect Pin 53, RFCM, to Pin 51,
,
and decouple both pins to ground with a 10 nF capacitor. Drive
the input signal through Pin 55, RFI.
1. Calculate the value of RFDIV, which is used to program
Register CR28, Bits[2:0], from the following lookup table
(Table 6). See also Table 24.
RFI
To drive differentially, use a balun with the RFI and
pins
driven by the balanced outputs of the balun, and connect the
RFCM pin to the common balun output terminal. Decouple
RFCM to ground.
Table 6. RFDIV Lookup Table
LO Frequency (MHz)
RFDIV = Register CR28[2:0]
000 = divide-by-1
The VGA gain range is approximately 60 dB and is achieved by
varying the VGAIN voltage from 0 V to 1.5 V. The Typical
Performance Characteristics section has more information on
the VGA gain performance. A 0 V input on VGAIN sets the
VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to
+60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set
to 0. If the VGA gain mode polarity bit is set to 1, a 0 V input
voltage on VGAIN sets the VGA gain to +60 dB, whereas a 1.5 V
input sets the VGA gain to 0 dB.
500 to 1000
250 to 500
001 = divide-by-2
125 to 250
010 = divide-by-4
100 to 125
011 = divide-by-8
2. Using the following equation, calculate the value of the
N-divider:
N = (2RFDIV × 2 × LO)/(fPFD
where:
N is the N-divider value.
)
(4)
The VGA can be powered down by setting Register CR30, Bit 0,
to 0 and can be powered up by setting this same bit to 1.
I2C INTERFACE
The ADRF6850 supports a 2-wire, I2C-compatible serial bus
that drives multiple peripherals. The part powers up in I2C mode
but is not locked in this mode. To remain in I2C mode, it is
RFDIV is the setting in Register CR28, Bits[2:0].
LO is the local oscillator frequency.
fPFD is the PFD frequency.
This equation is a different representation of Equation 2.
Rev. 0 | Page 20 of 36
ADRF6850
recommended that the user tie the CS line to either 3.3 V or
GND, thus disabling SPI mode.
monitors the SDA and SCL lines waiting for the start
condition and the correct transmitted address.
5. The R/W bit determines the direction of the data. Logic 0
on the LSB of the first byte indicates that the master writes
information to the peripheral. Logic 1 on the LSB of the
first byte indicates that the master reads information from
the peripheral.
The serial data (SDA) and serial clock (SCL) inputs carry infor-
mation between any devices that are connected to the bus. Each
slave device is recognized by a unique address. The ADRF6850
has two possible 7-bit slave addresses for both read and write
operations, 0x78 and 0x58. The MSB of the 7-bit slave address
is set to 1. Bit 5 of the slave address is set by the CS pin (Pin 27).
Bits[4:0] of the slave address are set to 11000. The slave address
consists of the seven MSBs of an 8-bit word. The LSB of the word
sets either a read or a write operation (see Figure 61). Logic 1 cor-
responds to a read operation, whereas Logic 0 corresponds to a
write operation.
The ADRF6850 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. The ADRF6850 has 34 subaddresses
to enable the user-accessible internal registers; therefore, it
interprets the first byte as the device address and the second
byte as the starting subaddress.
To control the device on the bus, the following protocol must
be followed:
Auto-increment mode is supported, which allows data to
be read from or written to the starting subaddress, and each
subsequent address, without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop con-
dition. The user can also access any unique subaddress register
on a one-by-one basis without updating all registers.
1. The master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA
while SCL remains high. This indicates that an address/
data stream follows.
2. All peripherals respond to the start condition and shift the
next eight bits (the 7-bit address and the R/W bit). The bits
are transferred from MSB to LSB.
3. The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth
clock pulse. This is known as an acknowledge bit.
4. All other devices then withdraw from the bus and maintain
an idle condition. During the idle condition, the device
Stop and start conditions can be detected at any stage of the data
transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. If an invalid subaddress is issued by the user,
the ADRF6850 does not issue an acknowledge and returns to the
idle condition. In a no acknowledge condition, the SDA line is
not pulled low on the ninth pulse. See Figure 62 and Figure 63
for sample write and read data transfers, Figure 64 for the timing
protocol, and Figure 2 for a more detailed timing diagram.
R/W
CTRL
SLAVE ADDRESS[6:0]
1
A5
0
0
0
0
0
X
MSB = 1 SET BY
PIN 27
0 = WR
1 = RD
Figure 61. Slave Address Configuration
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUBADDR A(S) DATA A(S)
DATA A(S)
P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
Figure 62. I2C Write Data Transfer
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUBADDR A(S)
S
SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M)
DATA A(M) P
S = START BIT
P = STOP BIT
A(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
Figure 63. I2C Read Data Transfer
START BIT
STOP BIT
SLAVE ADDRESS
SUBADDRESS
DATA
SDA
SCL
A6
A5
A7
A0
D7
D0
S
P
WR
ACK
ACK
ACK
SLAVE
ADDR[4:0]
SUBADDR[6:1]
DATA[6:1]
Figure 64. I2C Data Transfer Timing
Rev. 0 | Page 21 of 36
ADRF6850
of the part. The SDI line is used to write to the registers. The
SDO pin is a dedicated output for the read mode. The part
operates in slave mode and requires an externally applied serial
clock to the CLK pin. The serial interface is designed to allow
the part to be interfaced to systems that provide a serial clock
that is synchronized to the serial data.
SPI INTERFACE
The ADRF6850 supports the SPI protocol; however, the part
powers up in I2C mode. To select and lock the SPI mode, three
pulses must be sent to the CS pin, as shown in Figure 65. When
the SPI protocol is locked in, it cannot be unlocked while the
device remains powered up. To reset the serial interface, the
part must be powered down and powered up again.
Figure 66 shows an example of a write operation to the ADRF6850.
Data is clocked into the registers on the rising edge of CLK using
a 24-bit write command. The first eight bits represent the write
command (0xD4), the next eight bits are the register address, and
the final eight bits are the data to be written to the specific register.
Figure 67 shows an example of a read operation. In this example,
a shortened 16-bit write command is first used to select the appro-
priate register for a read operation, the first eight bits representing
the write command (0xD4) and the final eight bits representing
the specific register. Then the CS line is pulsed low for a second
time to retrieve data from the selected register using a 16-bit
read command, the first eight bits representing the read command
(0xD5) and the final eight bits representing the contents of the
register being read. Figure 3 shows the timing for both SPI read
and SPI write operations.
Serial Interface Selection
The CS pin controls selection of the I2C or SPI interface.
Figure 65 shows the selection process that is required to lock
in the SPI mode. To communicate with the part using the SPI
protocol, three pulses must be sent to the CS pin. On the third
rising edge, the part selects and locks the SPI protocol. Consistent
with most SPI standards, the CS pin must be held low during all
SPI communication to the part and held high at all other times.
SPI Serial Interface Functionality
The SPI serial interface of the ADRF6850 consists of the CS,
SDI (SDI/SDA), CLK (CLK/SCL), and SDO pins. CS is used to
select the device when more than one device is connected to the
serial clock and data lines. CLK is used to clock data in and out
A
B
C
CS
(STARTING
HIGH)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
CS
(STARTING
LOW)
A
B
C
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
Figure 65. Selecting the SPI Protocol
Rev. 0 | Page 22 of 36
ADRF6850
• • •
CS
• • •
CLK
• • •
SDI
D7
START
D6
D5
D4
D3
D2
D1
D0
D0
D7
D6
D5
D4
D3
D2
D1
WRITE
REGISTER
ADDRESS
COMMAND [0xD4]
CS
•
•
•
•
•
•
•
•
•
(CONTINUED)
CLK
(CONTINUED)
SDI
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DATA
BYTE
Figure 66. SPI Byte Write Example
• • •
CS
• • •
CLK
• • •
SDI
D7
D6
D5
D4
D3
D2
D1
D0
D0
D7
D6
D5
D4
D3
D2
D1
START
WRITE
COMMAND [0xD4]
REGISTER
ADDRESS
CS
CLK
SDI
D7
D6
X
D5
X
D4
X
D3
X
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
SDO
STOP
START
READ
COMMAND [0xD5]
DATA
BYTE
Figure 67. SPI Byte Read Example
Rev. 0 | Page 23 of 36
ADRF6850
5-bit divider is enabled by programming Register CR5, Bit 4;
and the division ratio is programmed through Register CR10,
Bits[4:0]. The R ÷2 divider is programmed through Register CR10,
Bit 6. Note that these registers are double buffered.
PROGRAM MODES
The ADRF6850 has 34 8-bit registers to allow program control
of a number of functions. Only 31 of these registers are writeable.
Either an SPI or an I2C interface can be used to program the
register set. For details about the interfaces and timing, see
Figure 61 to Figure 67. The registers are documented in Table 8
to Table 27.
Charge Pump Current
Register CR9, Bits[7:4], set the charge pump current setting.
With an RSET value of 4.7 kΩ, the maximum charge pump
current is 5 mA. The following equation applies:
Several settings in the ADRF6850 are double buffered. These
settings include the FRAC value, the INT value, the RFDIV
value, the 5-bit R-divider value, the reference doubler, the R ÷2
divider, and the charge pump current setting. This means that
two events must occur before the part uses a new value for any
of the double buffered settings. First, the new value is latched
into the device by writing to the appropriate register. Next, a new
write must be performed on Register CR0. When Register CR0 is
written, a new PLL acquisition occurs.
I
CP max = 23.5/RSET
(6)
The charge pump current has 16 settings from 325 μA to 5 mA.
Power-Down/Power-Up Control Bits
The four programmable power-up and power-down control bits
are as follows:
Register CR12, Bit 2. Master power control bit for the PLL,
including the VCO. This bit is normally set to a default
value of 0 to power up the PLL.
For example, updating the fractional value involves a write to
Register CR3, Register CR2, Register CR1, and Register CR0.
Register CR3 should be written to first, followed by Register CR2
and Register CR1 and, finally, Register CR0. The new acquisition
begins after the write to Register CR0. Double buffering ensures
that the bits written to do not take effect until after the write to
Register CR0.
Register CR27, Bit 2. Controls the LO monitor outputs,
LOMON and
. The default is 0 when the monitor
LOMON
outputs are powered down. Setting this bit to 1 powers up
the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm,
or −24 dBm, as controlled by Register CR27, Bits[1:0].
Register CR29, Bit 0. Controls the quadrature demodulator
power. The default is 0, which powers down the demodulator.
Write a 1 to this bit to power up the demodulator.
Register CR30, Bit 0. This bit controls the VGA power and
must be set to a 1 to power up the VGA.
12-Bit Integer Value
Register CR7 and Register CR6 program the integer value (INT)
of the feedback division factor (N); see Equation 5 for details.
The INT value is a 12-bit number whose MSBs are programmed
through Register CR7, Bits[3:0]. The LSBs are programmed
through Register CR6, Bits[7:0]. The LO frequency setting is
described by Equation 2. An alternative to this equation is pro-
vided by Equation 4, which details how to set the N-divider
value. Note that these registers are double buffered.
Lock Detect (LDET)
Lock detect is enabled by setting Register CR23, Bit 4, to 1.
Register CR23, Bit 3, in conjunction with Register CR14, Bit 7,
sets the number of up/down pulses generated by the PFD before
lock detect is declared by the LDET pin returning high. The
options are 2048 pulses, 3072 pulses, and 4096 pulses.
25-Bit Fractional Value
Register CR3 to Register CR0 program the fractional value (FRAC)
of the feedback division factor (N); see Equation 5 for details. The
FRAC value is a 25-bit number whose MSB is programmed
through Register CR3, Bit 0. The LSB is programmed through
Register CR0, Bit 0. The LO frequency setting is described by
Equation 2. Again, an alternative to this equation is described
by Equation 4, which details how to set the N-divider value.
Note that these registers are double buffered.
The default setting is 3072 pulses, which is selected by program-
ming Register CR23, Bit 3, to 0, and Register CR14, Bit 7, to 0. A
more aggressive setting of 2048 is selected when Register CR23,
Bit 3, is set to 1 and Register CR14, Bit 7, is set to 0. This improves
the lock detect time by 50 μs (for a PFD frequency of 27 MHz).
Note, however, that it does not affect the acquisition time to an
error frequency of 1 kHz. A setting of 4096 pulses is selected
when Register CR14, Bit 7, is set to 1. For best operation, set
Register CR23, Bit 2 to 0. This bit sets up the PFD up/down
pulses to a coarse or low precision setting.
RFDIV Value
The RFDIV value is dependent on the value of the LO frequency.
The RFDIV value can be selected from the list in Table 6. Apply
the selected RFDIV value to Equation 4, together with the LO
frequency and PFD frequency values, to calculate the correct N-
divider value.
Baseband VOCM Reference
Register CR29, Bit 6, selects whether the common-mode reference
for the baseband outputs is internal or external. When the base-
band outputs are ac-coupled, then the internal reference must
be selected by setting Register CR29, Bit 6, to 1, and by
grounding Pin 7, VOCM.
Reference Input Path
The reference input path consists of a reference doubler, a 5-bit
frequency divider, and a divide-by-2 function (see Figure 54).
The doubler is programmed through Register CR10, Bit 5. The
When the baseband outputs are dc-coupled, it is likely that an
external bias is needed unless the internal dc bias provided is
Rev. 0 | Page 24 of 36
ADRF6850
within a suitable range to match the specification of the follow-
on device. This is accomplished by setting Register CR29, Bit 6,
to 0, and driving Pin 7, VOCM, with the requisite external bias
voltage.
Table 7. Baseband Filter Settings
CR29[5:4]
Filter Cutoff Frequency (MHz)
00
01
10
11
50
43
37
30
Narrow-Band and Wideband Filter Mode
By default, the second-order low-pass filter in the output buffers
of the baseband output signal paths is selected, and the baseband
outputs are in narrow-band mode. By setting Register CR29,
Bits[5:4], this filter can be set to a cutoff frequency of 50 MHz,
43 MHz, 37 MHz, or 30 MHz. By setting Register CR29, Bit 3, to 1,
this filter is bypassed and wideband mode is selected.
VGA Gain Mode Polarity
The polarity of the VGA gain is set by programming Bit 2 of
Register CR30. By setting Register CR30, Bit 2, to 0, a positive
gain slope is selected where VGAIN = 0 V sets the VGA gain to be 0
dB, and VGAIN = 1.5 V sets the VGA gain to be 60 dB. By setting
Register CR30, Bit 2, to 1, a negative gain slope is selected.
Rev. 0 | Page 25 of 36
ADRF6850
REGISTER MAP
REGISTER MAP SUMMARY
Table 8. Register Map Summary
Register Address (Hex)
Register Name
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
Type
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read only
Read only
Read only
Fractional Word 4
Fractional Word 3
Fractional Word 2
Fractional Word 1
Reserved
Reference 5-bit, R-divider enable
Integer Word 2
Integer Word 1
Reserved
Charge pump current setting
Reference frequency control
Reserved
PLL power-up
Reserved
Lock Detector Control 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x08
0x09
CR8
CR9
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
CR18
CR19
CR20
CR21
CR22
CR23
CR24
CR25
CR26
CR27
CR28
CR29
CR30
CR31
CR32
CR33
Lock Detector Control 1
Autocalibration
Autocalibration timer
Reserved
LO monitor output
LO selection
Demodulator power and filter selection
VGA
Reserved
0x1C
0x1D
0x1E
0x1F
0x20
Reserved
Revision code
0x21
Rev. 0 | Page 26 of 36
ADRF6850
Table 13. Register CR5 (Address 0x05), Reference 5-Bit,
R-Divider Enable
REGISTER BIT DESCRIPTIONS
Table 9. Register CR0 (Address 0x00), Fractional Word 4
Bit
Description
Bit
Description
7
Reserved
7
6
5
4
3
2
1
0
Fractional Word F71
Fractional Word F61
Fractional Word F51
Fractional Word F41
Fractional Word F31
Fractional Word F21
Fractional Word F11
Fractional Word F0 (LSB)1
6
Reserved
5
4
Reserved
5-bit R-divider enable1
0 = disable 5-bit R-divider (default)
1 = enable 5-bit R-divider
Reserved
3
2
1
0
Reserved
Reserved
Reserved
1 Double buffered. Load on the write to Register CR0.
1 Double buffered. Load on the write to Register CR0.
Table 10. Register CR1 (Address 0x01), Fractional Word 3
Bit
Description
Table 14. Register CR6 (Address 0x06), Integer Word 2
7
6
5
4
3
2
1
0
Fractional Word F151
Fractional Word F141
Fractional Word F131
Fractional Word F121
Fractional Word F111
Fractional Word F101
Fractional Word F91
Fractional Word F81
Bit
Description
7
6
5
4
3
2
1
0
Integer Word N71
Integer Word N61
Integer Word N51
Integer Word N41
Integer Word N31
Integer Word N21
Integer Word N11
Integer Word N01
1 Double buffered. Load on the write to Register CR0.
1 Double buffered. Load on the write to Register CR0.
Table 11. Register CR2 (Address 0x02), Fractional Word 2
Bit
Description
Table 15. Register CR7 (Address 0x07), Integer Word 1
7
6
5
4
3
2
1
0
Fractional Word F231
Fractional Word F221
Fractional Word F211
Fractional Word F201
Fractional Word F191
Fractional Word F181
Fractional Word F171
Fractional Word F161
Bit
Description
[7:4]
MUXOUT control
0000 = tristate
0001 = logic high
0010 = logic low
1101 = RCLK/2
1110 = NCLK/2
Integer Word N111
Integer Word N101
Integer Word N91
Integer Word N81
3
2
1
0
1 Double buffered. Load on the write to Register CR0.
Table 12. Register CR3 (Address 0x03), Fractional Word 1
Bit
Description
1 Double buffered. Load on the write to Register CR0.
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
0
Reserved
Fractional Word F24 (MSB)1
1 Double buffered. Load on the write to Register CR0.
Rev. 0 | Page 27 of 36
ADRF6850
Table 16. Register CR9 (Address 0x09), Charge Pump
Current Setting
Table 18. Register CR12 (Address 0x0C), PLL Power-Up
Bit
Description
Bit
Description
7
6
5
4
3
2
Reserved
Reserved
Reserved
Reserved
[7:4]
Charge pump current1
0000 = 0.31 mA (default)
0001 = 0.63 mA
0010 = 0.94 mA
0011 = 1.25 mA
0100 = 1.57 mA
0101 = 1.88 mA
0110 = 2.19 mA
0111 = 2.50 mA
1000 = 2.81 mA
1001 = 3.13 mA
1010 = 3.44 mA
1011 = 3.75 mA
1100 = 4.06 mA
1101 = 4.38 mA
1110 = 4.69 mA
1111 = 5.00 mA
Reserved
Reserved
PLL power-down
0 = power up PLL (default)
1 = power down PLL
Reserved
1
0
Reserved
Table 19. Register CR14 (Address 0x0E), Lock Detector
Control 2
Bit
Description
7
Lock Detector Up/Down Count 2
0 = 2048/3072 up/down pulses
1 = 4096 up/down pulses
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
1
0
3
2
1
0
Reserved
Reserved
Reserved
1 Double buffered. Load on the write to Register CR0.
Table 17. Register CR10 (Address 0x0A), Reference
Frequency Control
Table 20. Register CR23 (Address 0x17), Lock Detector
Control 1
Bit
Description
Reserved1
Bit
Description
7
7
Reserved
6
R divide-by-2 divider enable1
0 = bypass R divide-by-2 divider
1 = enable R divide-by-2 divider
R-doubler enable1
6
Reserved
5
Reserved
4
Lock detector enable
0 = lock detector disabled (default)
1 = lock detector enabled
Lock detector up/down count
With Register CR14[7] = 0:
0 = 3072 up/down pulses
1 = 2048 up/down pulses
Lock detector precision
0 = low, coarse (16 ns)
1 = high, fine (6 ns)
Reserved
5
0 = disable doubler (default)
1 = enable doubler
3
2
[4:0]
5-bit R-divider setting1
00000 = divide by 32 (default)
00001 = divide by 1
00010 = divide by 2
…
11110 = divide by 30
11111 = divide by 31
1 Double buffered. Load on the write to Register CR0.
1
0
Reserved
Rev. 0 | Page 28 of 36
ADRF6850
Table 21. Register CR24 (Address 0x18), Autocalibration
Table 25. Register CR29 (Address 0x1D), Demodulator
Power and Filter Selection
Bit
Description
Bit
Description
7
Reserved
6
Reserved
7
Reserved
5
4
3
2
Reserved
Reserved
Reserved
Reserved
6
Internal baseband (VOCM) select
0 = select external baseband (VOCM) reference
1 = select internal baseband (VOCM) reference
Narrow-band filter cut off
00 = 50 MHz
[5:4]
1
Reserved
0
Disable autocalibration
0 = enable autocalibration (default)
1 = disable autocalibration
01 = 43 MHz
10 = 37 MHz
11 = 30 MHz
3
Baseband wideband/narrow-band modes
0 = narrow-band mode
1 = wideband mode
Reserved; set to 0
Table 22. Register CR25 (Address 0x19), Autocalibration
Timer
Bit
Description
2
1
0
[7:0]
Autocalibration timer
Reserved; set to 0
Power-up demodulator
0 = power down (default)
1 = power up
Table 23. Register CR27 (Address 0x1B), LO Monitor Output
Bit
Description
7
Reserved
6
5
Reserved
Reserved
Table 26. Register CR30 (Address 0x1E), VGA
Bit
Description
4
3
2
Reserved
Reserved
7
6
5
4
3
2
Reserved
Reserved
Reserved
Reserved
Power-up monitor output
0 = power down (default)
1 = power up
Monitor output power into 50 Ω
00 = −24 dBm (default)
01 = −18 dBm
Reserved
[1:0]
VGA gain mode polarity
0 = positive gain slope
1 = negative gain slope
Reserved
Power-up VGA
0 = power down
1 = power up
10 = −12 dBm
11 = −6 dBm
1
0
Table 24. Register CR28 (Address 0x1C), LO Selection
Bit
Description
Table 27. Register CR33 (Address 0x21), Revision Code1
7
6
Reserved
Reserved
Bit
Description
5
4
3
[2:0]
Reserved
Reserved
Reserved; set to 1
RFDIV
000 = divide by 1; LO = 500 MHz to 1000 MHz
001 = divide by 2; LO = 250 MHz to 500 MHz
010 = divide by 4; LO = 125 MHz to 250 MHz
011 = divide by 8; LO = 100 MHz to 125 MHz
7
6
5
4
3
2
1
0
Revision code
Revision code
Revision code
Revision code
Revision code
Revision code
Revision code
Revision code
1 Read-only register.
Rev. 0 | Page 29 of 36
ADRF6850
SUGGESTED POWER-UP SEQUENCE
16. Write the following to Register CR15: 0x00. Reserved
register.
INITIAL REGISTER WRITE SEQUENCE
After applying power to the device, adhere to the following
write sequence, particularly with respect to the reserved register
settings. Note that Register CR33, Register CR32, and
Register CR31 are read-only registers. Also note that all
writeable registers should be written to on power-up. Refer to
the Register Map section for more details on all registers.
17. Write Register CR14: 0x00. Lock Detector Control 2.
18. Write Register CR13: 0x08. Reserved register.
19. Write the following to Register CR12: 0x18. PLL powered up.
20. Write the following to Register CR11: 0x00. Reserved
register.
21. Write the following to Register CR10: 0x21. The reference
path doubler is enabled and the 5-bit divider and R divide-
by-2 divider are bypassed.
1. Write the following to Register CR30 = 0x00. Set VGA
power to off and the VGA gain slope to be positive.
2. Write the following to Register CR29: 0x41. The
demodulator is powered up. The baseband narrow-band
mode is selected and set to a cutoff frequency of 50 MHz.
The internal baseband VOCM reference is selected.
3. Write the following to Register CR28: 0x0X RFDIV
depends on the value of the LO frequency to be used and is
set according to Table 6. Note that Register CR28, Bit 3, is
set to 1.
22. Write the following to Register CR9: 0x70. With the
recommended loop filter component values and RSET
=
4.7 kΩ, the charge pump current is set to 2.5 mA for a loop
bandwidth of 50 kHz.
23. Write the following to Register CR8: 0x00. Reserved
register.
24. Write the following to Register CR7: 0x0X. Set according to
Equation 4 and Equation 5 in the Theory of Operation
section.
25. Write the following to Register CR6: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section.
26. Write Register CR5: 0x00. Disable the 5-bit reference
divider.
27. Write the following to Register CR4: 0x01. Reserved
register.
28. Write the following to Register CR3: 0x0X. Set according to
Equation 4 and Equation 5 in the Theory of Operation
section.
29. Write the following to Register CR2: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section.
30. Write the following to Register CR1: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section.
4. Write the following to Register CR27: 0x00. Power the LO
monitor in a power-down state.
5. Write the following to Register CR26: 0x00. Reserved
register.
6. Write the following to Register CR25: 0x70. Set the
autocalibration time to 100 μs with a PFD frequency
setting of 27 MHz. If the PFD frequency is different, set
CR25 according to Equation 3.
7. Write the following to Register CR24: 0x38. Enable
autocalibration.
8. Write the following to Register CR23: 0x70. Enable lock
detector and set lock detector counter = 3072 up/down
pulses.
9. Write the following to Register CR22: 0x00. Reserved
register.
10. Write the following to Register CR21: 0x00. Reserved
register.
11. Write the following to Register CR20: 0x00. Reserved
register.
12. Write the following to Register CR19: 0x00. Reserved
register.
13. Write the following to Register CR18: 0x60. Reserved
register.
14. Write the following to Register CR17: 0x00. Reserved
register.
15. Write the following to Register CR16: 0x00. Reserved
register.
31. Write the following to Register CR0: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section. Register CR0 must be the last register written for
all the double buffered bit writes to take effect.
32. Monitor the LDET output or wait 260 μs to ensure that the
PLL is locked.
33. Write the following to Register CR30: 0x01. Set the VGA to
power on.
Rev. 0 | Page 30 of 36
ADRF6850
EVALUATION BOARD
and 56 pF capacitors that are placed as close to the DUT as
GENERAL DESCRIPTION
possible for good local decoupling. The impedance of all these
capacitors should be low and constant across a broad frequency
range. Surface-mount multilayered ceramic chip (MLCC) Class II
capacitors provide very low ESL and ESR, which assist in
decoupling supply noise effectively. They also provide good
temperature stability and good aging characteristics. Capacitance
changes per the bias voltage that is applied. Larger case sizes have
less capacitance change vs. applied bias voltage, and also lower
ESR but higher ESL. A combination of 0402 size cases for the
56 pF capacitors and 0603 size cases for the 100 nF capacitors
give a good compromise allowing the 56 pF capacitors to be
placed as close as possible to the supply pins on the top side of
the PCB with the 100 nF capacitors placed on the bottom side
of the PCB quite close to the supply pins. X5R and X7R
capacitors are examples of these types of capacitors and are
recommended for decoupling.
The evaluation board is designed to allow the user to evaluate
the performance of the ADRF6850. It contains the following:
•
The ADRF6850 DUT. This is an I/Q demodulator with an
integrated fractional-N PLL and VCO.
•
•
•
•
SPI and I2C interface connectors.
Baseband output connectors.
Fourth-order low-pass loop filter circuitry.
13.5 MHz reference clock, and the ability to drive the
reference input external to the board.
•
Circuitry to support differential signaling to the TESTLO
inputs, including dc biasing circuitry.
•
•
Circuitry to monitor the LOMON outputs.
SMA connectors for power supplies, the VGAIN input and
a single-ended RF input.
The evaluation board comes with associated software to allow
easy programming of the ADRF6850.
SPI and I2C Interface
The SPI interface connector is a nine-way, D-type connector that
can be connected to the printer port of a PC. Figure 68 shows
the PC cable diagram that must be used with the provided
software.
HARDWARE DESCRIPTION
For more information, refer to the circuit diagram in Figure 69.
Power Supplies
There is also an option to use the I2C interface by using the I2C
receptacle connector. This is a standard I2C connector. A supply
voltage of +3.3 V is provided by the I2C bus master. Pull-up
resistors are required on the signal lines. The CS pin can be
used to set the slave address of the ADRF6850. CS high sets the
slave address to 0x78, and CS low sets the slave address to 0x58.
An external +3.3 V supply (DUT + 3.3 V) powers each of the
nine VCCx supplies on the ADRF6850 as well as the 13.5 MHz
clock reference.
Recommended Decoupling for Supplies
Initially, the external +3.3 V supply is decoupled by a 10 µF
capacitor and then further by a parallel combination of 100 nF
1
2
1
CLK
14
15
6
2
DATA
LE
3
4
5
6
7
8
3
4
5
16
17
9
PC
18
9-WAY
FEMALE
D-TYPE
GND
19
20
7
8
21
22
23
24
25
9
10
11
12
13
25-WAY
MALE
D-TYPE
TO PC
PRINTER PORT
Figure 68. SPI PC Cable Diagram
Rev. 0 | Page 31 of 36
ADRF6850
Baseband Outputs and VOCM
LOMON Outputs
The pair of I and Q baseband outputs are connected to the
board by SMA connectors. They are ac-coupled to the output
connectors. VOCM, which sets the common-mode output
voltage, is grounded and the internal baseband (VOCM) reference
is selected by Register CR29, Bit 6. If the external baseband
(VOCM) reference is selected by setting this bit to a 0, then a
voltage needs to be applied through J6 and R20 needs to be
removed.
These pins are differential LO monitor outputs that provide a
replica of the internal LO frequency at 1× LO. The single-ended
power in a 50 Ω load can be programmed to −24 dBm, −18dBm,
−12 dBm, or −6 dBm. These open-collector outputs must be
terminated to 3.3 V. Because both outputs must be terminated
to 50 Ω, options are provided to terminate to 3.3 V using on-
board 50 Ω resistors or by series inductors (or a ferrite bead), in
which case the 50 Ω termination is provided by the measuring
instrument.
Loop Filter
CCOMPx Pins
A fourth-order loop filter is provided at the output of the charge
pump and is required to adequately filter noise from the Σ-Δ
modulator used in the N-divider. With the charge pump current
set to a midscale value of 2.5 mA and using the on-chip VCO,
the loop bandwidth is approximately 50 kHz, and the phase
margin is 55°. C0G capacitors are recommended for use in the
loop filter because they have low dielectric absorption, which is
required for fast and accurate settling time. The use of non C0G
capacitors may result in a long tail being introduced into the
PLL settling time transient.
The CCOMPx pins are internal compensation nodes that must
be decoupled to ground with a 100 nF capacitor.
MUXOUT
MUXOUT is a test output that allows different internal nodes
to be monitored. It is a CMOS output stage that requires no
termination.
Lock Detect (LDET)
Lock detect is a CMOS output that indicates the state of the
PLL. A high level indicates a locked condition, and a low level
indicates a loss of lock condition.
Reference Input
The reference input can be supplied by a 13.5 MHz Jauch clock
generator or by an external clock through the use of Connector J7.
The frequency range of the reference input is from 10 MHz to
300 MHz with the PFD frequency limited to a maximum of
30 MHz. Double the 13.5 MHz clock to 27 MHz by using the on-
chip reference frequency doubler to optimize phase noise
performance.
RFI
RF Inputs (RFI, RFCM, and
RFI
)
RFI and
ended operation as demonstrated on the evaluation board, RFI
RFI
are 50 Ω internally biased RF inputs. For single-
must be ac-coupled to the source and
to the ground plane. RFCM is the RF input common-mode pin.
RFI
must be ac-coupled
It should be connected to
when driving the input in single-
TESTLO Inputs
ended mode. When driving the input differentially using a
balun, connect this pin to the common terminal of the output
coil of the balun.
These pins are differential test inputs that allow a variety of debug
options. On this board, the capability is provided to drive these
pins with an external 4× LO signal that is then applied to an
Anaren balun to provide a differential input signal.
VGAIN
The VGAIN pin sets the gain of the VGA. The VGAIN voltage
range is from 0 V to 1.5 V. This allows the gain of the VGA to
vary from 0 dB to +60 dB.
When driving the TESTLO pins, the PLL can be bypassed, and
the demodulator can be driven directly by this external LO
signal. The frequency of the LO signal needs to be 4 times the
operating frequency. These inputs also require a dc bias. A dc
bias of 3.3 V is the default option used on the board.
Rev. 0 | Page 32 of 36
ADRF6850
PCB SCHEMATIC
0 5 8 0 9 3 1 6
Figure 69. Applications Circuit
Rev. 0 | Page 33 of 36
ADRF6850
PCB ARTWORK
Component Placement
Figure 70. Evaluation Board, Top Side Component
Figure 73. Evaluation Board, Bottom Side Component Placement
Figure 74. Evaluation Board Power—Layer 3
Figure 71. Evaluation Board, Top Side—Layer 1
Figure 75. Evaluation Board, Bottom Side—Layer 4
Figure 72. Evaluation Board, Ground—Layer 2
Rev. 0 | Page 34 of 36
ADRF6850
BILL OF MATERIALS
Table 28. Bill of Materials
Qty.
Reference Designator
Description
Manufacturer
Analog Devices
Jauch
Part Number
1
1
DUT
Y2
ADRF6850 LFCSP, 56-lead 8 mm × 8 mm
VCO, 13.5 MHz
ADRF6850BCPZ
0 13.50-VX7-G-3.3-1-
T1-LF
1
1
2
10
SPI
Connector, 9-pin, D-sub plug, D-SUB9MR
Connector, I2C, SEMCONN receptacle
Capacitor, 10 µF, 25 V, tantalum, TAJ-C
Capacitor, 56 pF, 50 V, ceramic, C0G, 0402
ITW McMurdo
Digikey
AVX
FEC 1071806
5-1761185-1-ND
FEC 197518
I2C
C1, C34
C4, C6, C10, C12, C14, C16, C40,
C48, C53, C55
AVX
FEC 1658861
14
C5, C7, C11, C13, C15, C17, C22,
C27, C47, C49 to C52, C54
Capacitor, 100 nF, 25 V, X7R, ceramic, 0603
AVX
FEC 317287
1
1
4
2
2
1
4
12
2
C3
C35
Capacitor, 1.8 nF, 50 V, C0G, ceramic, 0603
Capacitor, 68 nF, 50 V, NPO, ceramic, 1206
Capacitor, 1 nF, 50 V, C0G, ceramic, 0603
Capacitor, 100 pF, 50 V, C0G, ceramic, 0402
Capacitor, 10 nF, 50 V, X7R, ceramic, 0402
Capacitor, 10 pF, 50 V, C0G, ceramic, 0402
Capacitor, 10 μF, 6.3 V, X5R, ceramic, 0603
SMA end launch connector
Murata
Kemet
FEC 1402814
FEC 1535582
FEC 8819920
FEC 8819572
FEC 1414575
FEC 8819564
FEC 1458902
C2, C21, C38, C39
C44, C46
C43, C56
C18
C30 to C33
J2 to J12, J14
J20, J21
Murata
Murata
Murata
Murata
Phycomp
Johnson/Emerson 142-0701-851
Harwin
Jumper, 3-pin plus shunt
FEC 148533 +
FEC 150411
2
2
2
1
2
1
2
2
3
L1, L2
L3, L4
R20, R36
R13
R14, R39
R1
R3, R4
R17, R18
R35, R44, R45
Inductor, 20 nH, 0402, LQW series
Inductor, 10 µH, 0805, LQM series
Resistor, 0 Ω, 1/16 W, 1%, 0402
Resistor, 4.7 kΩ, 1/10 W, 1%, 0603
Resistor, 1.2 kΩ, 1/10 W, 5%, 0603
Resistor, 220 Ω, 1/16 W, 1%, 0603
Resistor, 200 Ω, 1/16 W, 5%, 0402
Resistor, 0603, spacing (do not install)
Resistor, 51 Ω, 1/16 W, 1%, 0402
Murata
Murata
LQW15AN20N
LQM21FN1N100M
FEC 1158241
FEC 1576293
FEC 9233393
FEC 9330801
FEC 1514682
Vishay Draloric
Multicomp
Phycomp
Multicomp
Vishay Dale
Multicomp
FEC 1358008
FEC 1739223
Digi Key
4
2
R48 to R51
R60, R61
Resistor, 330 Ω, 1/10 W, 5%, 0805
Resistor, 100 Ω, 1/10 W, 5%, 0805
Vishay Draloric
Bourns
RR12P100DTR-ND
2
7
R46, R47
CS, LDET, MUXOUT, VTUNE, SCLK,
SDA, SDO
Resistor, 10 kΩ, 1/16 W, 1%, 0402
Test point, 1-pin, 0.035 inch diameter
Phycomp
Not inserted
FEC 9239359
1
BAL1
Balun, 0805, 50 Ω to 100 Ω balanced (1.3 GHz to Anaren
3.1 GHz)
BD1631J50100A00
Rev. 0 | Page 35 of 36
ADRF6850
OUTLINE DIMENSIONS
0.30
0.23
0.18
8.10
8.00 SQ
7.90
0.60 MAX
0.60
MAX
PIN 1
INDICATOR
43
42
56
1
0.50
BSC
PIN 1
INDICATOR
7.85
EXPOSED
PAD
7.75 SQ
7.65
5.25
5.10 SQ
4.95
14
29
28
15
0.50
0.40
0.30
0.25 MIN
BOTTOM VIEW
6.50 REF
TOP VIEW
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.20 REF
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 76. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
CP-56-5
CP-56-5
ADRF6850BCPZ
ADRF6850BCPZ-R7
EVAL-ADRF6850EB1Z
−40°C to +85°C
−40°C to +85°C
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09316-0-10/10(0)
Rev. 0 | Page 36 of 36
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