HMC1132 [ADI]
No external matching required;
| 型号： | HMC1132 |
| 厂家： | 
ADI |
| 描述： | No external matching required |
| 文件： | 总15页 (文件大小：694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 Watt, GaAs pHEMT MMIC
Power Amplifier, 27 GHz to 32 GHz
HMC1132
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Saturated output power (PSAT): 30.5 dBm at 22% power
added efficiency (PAE)
High output IP3: 35 dBm
High gain: 22 dB
DC supply: 6 V at 600 mA
No external matching required
32-lead, 5 mm × 5 mm LFCSP package
GND
NC
NC
1
2
3
4
5
6
7
8
24 GND
23 NC
HMC1132
22
NC
21 GND
GND
RFIN
GND
NC
20
19
RFOUT
GND
18 NC
17 GND
GND
APPLICATIONS
Point-to-point radios
Point-to-multipoint radios
VSAT and SATCOM
PACKAGE
BASE
Figure 1.
Military and space
GENERAL DESCRIPTION
systems. The amplifier configuration and high gain make it an
excellent candidate for last stage signal amplification before the
antenna.
The HMC1132 is a four-stage, GaAs pHEMT MMIC, 1 watt
power amplifier that operates between 27 GHz and 32 GHz.
The HMC1132 provides 22 dB of gain and 30.5 dBm of
saturated output power at 22% PAE from a 6 V power supply.
The HMC1132 amplifier input/outputs (I/Os) are internally
matched to 50 Ω. The device is supplied in a compact, leadless
QFN, 5 mm × 5 mm surface-mount package.
The HMC1132 exhibits excellent linearity and it is optimized
for high capacity, point-to-point and point-to-multipoint radio
Rev. 0
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Last Content Update: 11/01/2016
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• HMC1132: 1 Watt, GaAs pHEMT MMIC Power Amplifier,
27 GHz to 32 GHz Data Sheet
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
HMC1132
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................5
Typical Performance Characteristics..............................................6
Theory of Operation ...................................................................... 10
Applications Information...............................................................11
Application Circuit......................................................................11
Evaluation Board ............................................................................ 12
Bill of Materials........................................................................... 12
Evaluation Board Schematic ..................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide............................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
7/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 14
Data Sheet
HMC1132
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = VDD1 = VDD2 = 6 V, IDD = 600 mA.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Symbol Min Typ
Max Unit
Test Conditions/Comments
27
32
GHz
dB
20
22
Gain Variation over
Temperature
0.036
dB/°C
RETURN LOSS
Input
Output
6
14
dB
dB
POWER
Output Power for 1 dB
Compression
P1dB
28
30
dBm
Saturated Output Power
PSAT
IP3
30.5
35
dBm
dBm
OUTPUT THIRD-ORDER
INTERCEPT
Measurement taken at 6 V at 600 mA, POUT ÷ tone = 20 dBm
SUPPLY VOLTAGE
VDD
4
6
V
QUIESCENT SUPPLY CURRENT IDD
400
700
mA
Rev. 0 | Page 3 of 14
HMC1132
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Table 2.
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Drain Voltage Bias
RF Input Power (RFIN)1
Channel Temperature
6.5 V
18 dBm
175°C
Continuous PDISS (T = 85°C) (Derate 61 mw/°C 5.49 W
Above 85°C)
Thermal Resistance (RTH) Junction to Ground 16.4°C/W
Paddle
ESD CAUTION
Maximum Peak Reflow Temperature
Storage Temperature Range
260°C
−40°C to +150°C
−40°C to +85°C
Class 0, passed
150 V
Operating Temperature Range
ESD Sensitivity (Human Body Model)
1 Maximum PIN is limited to 18 dBm or thermal limits constrained by maximum
power dissipation (see Figure 31), whichever is lower.
Rev. 0 | Page 4 of 14
Data Sheet
HMC1132
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
NC
NC
1
2
3
4
5
6
7
8
24 GND
23 NC
22
NC
HMC1132
21 GND
GND
RFIN
GND
NC
TOP VIEW
20
19
RFOUT
GND
(Not to Scale)
18 NC
17 GND
GND
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 3. Pad Function Descriptions
Pin No.
Mnemonic Description
1, 4, 6, 8, 9, 16, 17,
19, 21, 24, 25, 32
GND
Ground. These pins are exposed ground paddles that must be connected to RF/dc ground.
2, 3, 7, 10, 11, 13, 14,
18, 22, 23, 26 to 30
NC
No Connect. These pins are not connected internally. However, all data was measured with these pins
connected to RF/dc ground externally.
5
RFIN
RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic.
12, 15
VDD1, VDD2
Drain Bias Voltage. External by pass capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 5
for the VDD1 and VDD2 interface schematic.
20
31
RFOUT
VGG
RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface
schematic.
Gate Control for Amplifier. Adjust VGG to achieve the recommended bias current. External bypass
capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 7 for the VGG interface schematic.
EPAD
Exposed Paddle. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
GND
RFOUT
Figure 3. GND Interface
Figure 6. RFOUT Interface
RFIN
V
GG
Figure 4. RFIN Interface
Figure 7. VGG Interface
V
,V
DD1 DD2
Figure 5. VDD1 and VDD2 Interface
Rev. 0 | Page 5 of 14
HMC1132
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
28
26
24
22
20
18
16
14
20
10
0
S22
S21
S11
–10
–20
–30
+85°C
+25°C
–40°C
25
26
27
28
29
30
31
32
33
34
27
28
29
30
31
32
33
34
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Broadband Gain and Return Loss vs. Frequency
Figure 11. Gain vs. Frequency at Various Temperatures
0
0
–5
–2
–4
+85°C
+25°C
–40°C
–6
–10
–15
–20
–25
–8
+85°C
+25°C
–40°C
–10
–12
–14
–16
27
28
29
30
31
32
33
34
27
28
29
30
31
32
33
34
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
35
35
+85°C
5V
5.5V
6V
33
33
31
29
27
25
+25°C
–40°C
31
29
27
25
26
27
28
29
30
31
32
33
26
27
28
29
30
31
32
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. P1dB vs. Frequency at Various Temperatures
Figure 13. P1dB vs. Frequency at Various Supply Voltages
Rev. 0 | Page 6 of 14
Data Sheet
HMC1132
35
33
31
29
27
25
35
33
31
29
27
25
5V
5.5V
6V
+85°C
+25°C
–40°C
26
27
28
29
30
31
32
33
26
27
28
29
30
31
32
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. PSAT vs. Frequency at Various Temperatures
Figure 17. PSAT vs. Frequency at Various Supply Voltages
35
33
31
29
27
25
35
500mA
600mA
700mA
500mA
600mA
700mA
33
31
29
27
25
26
27
28
29
30
31
32
33
26
27
28
29
30
31
32
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. P1dB vs. Frequency at Various Supply Currents (IDD
)
Figure 18. PSAT vs. Frequency at Various Supply Currents (IDD
)
40
40
35
35
30
30
500mA
600mA
+85°C
+25°C
25
25
20
700mA
–40°C
20
26
27
28
29
30
31
32
33
26
27
28
29
30
31
32
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Output IP3 vs. Frequency at Various Temperatures,
OUT/Tone = 20 dBm
Figure 19. Output IP3 vs. Frequency at Various Supply Currents,
OUT/Tone = 20 dBm
P
P
Rev. 0 | Page 7 of 14
HMC1132
Data Sheet
40
60
50
40
30
20
10
0
35
30
25
5V
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
5.5V
6V
20
26
27
28
29
30
31
32
33
10
12
14
16
18
20
22
24
P
/TONE (dBm)
FREQUENCY (GHz)
OUT
Figure 20. Output IP3 vs. Frequency at Various Supply Voltages,
POUT/Tone = 20 dBm
Figure 23. Output IM3 at VDD = 5 V
60
50
40
60
50
40
30
20
10
0
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
30
20
10
0
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
10
12
14
16
18
20
22
24
10
12
14
16
18
20
22
24
P
/TONE (dBm)
P
/TONE (dBm)
OUT
OUT
Figure 24. Output IM3 at VDD = 6 V
Figure 21. Output Third-Order Intermodulation Distortion (IM3)
at VDD = 5.5 V
40
35
30
25
20
15
10
5
1000
875
750
625
500
40
35
30
25
20
15
10
5
1000
875
750
P
GAIN
PAE
P
GAIN
PAE
OUT
OUT
625
I
I
DD
DD
0
500
10 12 14
0
–10 –8 –6 –4 –2
0
2
4
6
8
–10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 22. Power Compression at 27 GHz
Figure 25. Power Compression at 29.5 GHz
Rev. 0 | Page 8 of 14
Data Sheet
HMC1132
40
35
30
25
20
15
10
5
1000
875
750
625
500
30
25
20
15
10
5
+85°C
+25°C
–40°C
P
GAIN
PAE
OUT
I
DD
0
26
0
27
28
29
30
31
32
33
–10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 26. Power Compression at 32 GHz
Figure 29. PAE vs. Frequency at Various Temperatures, PIN = 10 dBm
40
35
30
25
20
15
40
35
30
GAIN
P1dB
SAT
GAIN
P1dB
SAT
P
P
25
20
15
5.0
5.2
5.5
(V)
5.7
6.0
500
550
600
(mA)
650
700
V
I
DD
DD
Figure 30. Gain and Power vs. Supply Voltage at 29.5 GHz
Figure 27. Gain and Power vs. Supply Current at 29.5 GHz
5
0
–10
+85°C
+25°C
–40°C
4
3
–20
–30
–40
–50
–60
–70
–80
27GHz
28GHz
29GHz
30GHz
31GHz
32GHz
2
1
–10
–5
0
5
10
15
26
27
28
29
30
31
32
33
34
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 31. Power Dissipation at 85°C
Figure 28. Reverse Isolation vs. Frequency at Various Temperatures
Rev. 0 | Page 9 of 14
HMC1132
Data Sheet
THEORY OF OPERATION
The architecture of the HMC1132 power amplifier is shown in
Figure 32. The amplifier consists of a cascade of four, single-
stage amplifiers. This approach provides a high P1dB as well as
a high gain that is flat across the operating frequency range.
VDD2 provides drain bias to the fourth gain stage. VGG provides
gate bias to all four gain stages, allowing control of the total
quiescent drain current. RFIN and RFOUT provide dc paths to
GND as a way of increasing the overall ESD robustness of the
device.
VDD1 provides drain bias to the first three gain stages, whereas
V
V
DD2
DD1
RFIN
RFOUT
V
GG
Figure 32. Architecture and Simplified Block Diagram
Rev. 0 | Page 10 of 14
Data Sheet
HMC1132
APPLICATIONS INFORMATION
The HMC1132 is a GaAs, pHEMT, MMIC power amplifier.
Capacitive bypassing is required for VDD1 and VDD2 as well as for
The following is the recommended bias sequence during
power-down:
V
GG (see Figure 33). Drain bias voltage must be applied to both
1. Turn off the RF signal.
2. Decrease the gate bias voltage to −2 V to achieve an IDD
0 mA (approximately).
3. Decrease the drain bias voltages to 0 V.
4. Increase the gate bias voltage to 0 V.
VDD1 and VDD2, and gate bias voltage must be applied to VGG
.
=
Though the RFIN and RFOUT ports ac couple the signal, dc
paths to GND are provided to increase the ESD robustness of
the device. External dc blocking of RFIN and/or RFOUT is
desirable when appreciable levels of dc are expected to be
present.
The VDD = 6 V and IDD = 600 mA bias conditions are the
operating points recommended to optimize the overall
performance of the device. Unless otherwise noted, the data
shown was obtained using the recommended bias condition.
Operation of the HMC1132 at different bias conditions may
provide performance that differs from what is shown in the
Typical Performance Characteristics section. Biasing the
HMC1132 for higher drain current typically results in higher
P1dB, PSAT, and gain, though at the expense of increased power
consumption.
All measurements for this device were taken using the typical
application circuit shown in Figure 33, configured as shown on
the evaluation printed circuit board (PCB).
The following is the recommended bias sequence during
power-up:
1. Connect the evaluation board to ground.
2. Set the gate bias voltage to −2 V.
3. Set the drain bias voltages to 6 V.
4. Increase the gate bias voltage to achieve a quiescent IDD
=
600 mA.
5. Apply the RF signal.
APPLICATION CIRCUIT
V
GG
C30
C20
C10
4.7µF 10nF 100pF
1
2
3
4
5
6
7
8
24
HMC1132
23
22
21
20
19
18
17
J1
RFIN
J2
RFOUT
V
DD1
C23
C13
C3
4.7µF 10nF 100pF
V
DD2
C25
C15
C5
4.7µF 10nF 100pF
Figure 33. Typical Application Circuit
Rev. 0 | Page 11 of 14
HMC1132
Data Sheet
EVALUATION BOARD
The HMC1132 evaluation board is a 2-layer board fabricated
using Rogers 4350 and best practices for high frequency RF
design. The RF input and RF output traces have a 50 Ω
characteristic impedance. The circuit board is attached to a heat
sink using SN96 solder and provides a low thermal resistance
path. Components are mounted using SN63 solder allowing
rework of the surface-mount components without compromising
the circuit board to heat sink attachment.
The evaluation board and populated components are designed
to operate over the ambient temperature range of −40°C to
+85°C. During operation, to control the temperature of the
HMC1132, attach the evaluation board to a temperature
controlled plate. For proper bias sequence, see the Applications
Information section.
The evaluation board schematic is shown in Figure 35. A fully
populated and tested evaluation board (see Figure 34), is
available from Analog Devices, Inc., upon request.
Figure 34. Evaluation Printed Circuit Board (PCB)
BILL OF MATERIALS
Table 4. Bill of Materials for Evaluation PCB EV1HMC1132LP5D
Item
Description
J1, J2
J3, J4
Connector, SRI K connector. SRI PN 25-146-1000-92.
DC pins.
J5, J6
Connector, SRI K connector. Not populated.
100 pF capacitors, 0402 package.
10,000 pF capacitors, 0402 package.
4.7 μF capacitors, Case A package.
C3, C5, C10
C13, C15, C20
C23, C25, C30
U1
HMC1132LP5DE amplifier.
Heat Sink
PCB
Used for thermal transfer from the HMC1132LP5DE amplifier.
131393 evaluation board. Circuit board material: Rogers 4350.
Rev. 0 | Page 12 of 14
Data Sheet
HMC1132
EVALUATION BOARD SCHEMATIC
VG1
C30
4.7µF
C20
10nF
C10
100pF
+
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
NC
GND
NC
NC
NC
U1
GND
RFIN
GND
NC
GND
RFOUT
GND
NC
J1
J2
RFIN
HMC1132LP5DE
RFOUT
K_SRI-NS
K_SRI-NS
GND
GND
VD3
VD7
+
+
C23
4.7µF
C13
10nF
C3
100pF
C5
100pF
C15
10nF
C25
4.7µF
J3
J4
VG1
10
9
VD7
VD5
VD3
VD1
VG2
10
9
7
5
3
1
VD2
VD4
VD6
VD8
8
7
5
3
1
8
6
4
2
6
4
2
87759-1050
87759-1050
THRUCAL
J5
J6
K_SRI-NS
DEPOP
K_SRI-NS
DEPOP
Figure 35. Evaluation Board Schematic
Rev. 0 | Page 13 of 14
HMC1132
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.15
3.00 SQ
2.85
EXPOSED
PAD
8
17
16
9
0.55
0.50
0.35
0.50 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
1.53
1.34
1.15
6° BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 1.34 mm Package Height
(HCP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
MSL
Package
Option
Package
Model1
Rating2
Package Description3, 4
Marking5
HMC1132LP5DE
−40°C to +85°C
MSL3
32-Lead Lead Frame Chip Scale Package [LFCSP]
HCP-32-2
H1132
XXXX
H1132
XXXX
HMC1132LP5DETR −40°C to +85°C
EV1HMC1132LP5D
MSL3
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation board
HCP-32-2
1 When ordering the evaluation fixture only, reference the model number, EV1HMC1132LP5D.
2 Maximum peak reflow temperature of 260°C.
3 HMC1132LP5DE lead finish is NiPdAu.
4 The HMC1132LP5DE is a premolded copper alloy lead frame.
5 HMC1132LP5DE 4-digit lot number is represented by XXXX.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13528-0-7/16(0)
Rev. 0 | Page 14 of 14
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