HMC701LP6CETR [ADI]
8 GHz 16-bit Fractional-N PLL with Sweeper;
| 型号： | HMC701LP6CETR |
| 厂家： | 
ADI |
| 描述： | 8 GHz 16-bit Fractional-N PLL with Sweeper 电信 电信集成电路 |
| 文件： | 总41页 (文件大小：1448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Features
•ꢀ Fꢀꢁꢂꢃꢄꢅꢆꢁl ꢅꢀ iꢆꢃegeꢀ Mꢅdes
•ꢀ Lꢅw Fꢀꢁꢂꢃꢄꢅꢆꢁl Spuꢀꢄꢅus
•ꢀ 8 GHz, 16-Bꢄꢃ rF n-cꢅuꢆꢃeꢀ
•ꢀ refeꢀeꢆꢂe spuꢀs: -90 dBꢂ ꢃyp
•ꢀ 24-Bꢄꢃ Sꢃep Sꢄze resꢅluꢃꢄꢅꢆ, 3 Hz ꢃyp
•ꢀ auꢃꢅ ꢁꢆd tꢀꢄggeꢀed Sweepeꢀ Fuꢆꢂꢃꢄꢅꢆs
•ꢀ cyꢂle Slꢄp Pꢀeveꢆꢃꢄꢅꢆ (cSP) fꢅꢀ fꢁsꢃ seꢃꢃlꢄꢆg
•ꢀ auxꢄlꢄꢁꢀy clꢅꢂk Sꢅuꢀꢂe
•ꢀ Ulꢃꢀꢁ Lꢅw Phꢁse nꢅꢄse 6 GHz, 50 MHz ref.
-103 / -110 dBꢂ/Hz @ 20 kHz (Fꢀꢁꢂ / iꢆꢃegeꢀ)
•ꢀ refeꢀeꢆꢂe Pꢁꢃh iꢆpuꢃ: 200 MHz
•ꢀ 14-Bꢄꢃ refeꢀeꢆꢂe Pꢁꢃh Dꢄvꢄdeꢀ
•ꢀ 40 Leꢁd 6x6 mm SMt Pꢁꢂkꢁge: 36 mm²
Typical Applications
•ꢀ Bꢁse Sꢃꢁꢃꢄꢅꢆs fꢅꢀ Mꢅbꢄle rꢁdꢄꢅ
•ꢀ catV Equꢄpmeꢆꢃ
•ꢀ FMcW Seꢆsꢅꢀs
(GSM, PcS, DcS, cDMa, WcDMa)
•ꢀ Wꢄꢀeless Lans, WꢄMꢁx
•ꢀ auꢃꢅmꢅꢃꢄve rꢁdꢁꢀ
•ꢀ Phꢁsed-aꢀꢀꢁy Sysꢃems
•ꢀ cꢅmmuꢆꢄꢂꢁꢃꢄꢅꢆs tesꢃ Equꢄpmeꢆꢃ
Functional Diagram
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
1
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
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DESIGN RESOURCES
• HMC701 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• HMC701LP6CE Evaluation Board
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Data Sheet
DISCUSSIONS
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• HMC701 Data Sheet
SAMPLE AND BUY
TOOLS AND SIMULATIONS
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• ADIsimPLL™
TECHNICAL SUPPORT
REFERENCE MATERIALS
Product Selection Guide
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number.
• RF, Microwave, and Millimeter Wave IC Selection Guide
DOCUMENT FEEDBACK
2017
Quality Documentation
Submit feedback for this data sheet.
• Package/Assembly Qualification Test Report: LP6, LP6C,
LP6G (QTR: 2014-00368)
• Package/Assembly Qualification Test Report: Plastic
Encapsulated QFN (QTR: 05006 REV: 02)
• Semiconductor Qualification Test Report: BiCMOS-A (QTR:
2013-00235)
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
General Description
the HMc701LP6cE ꢄs ꢁ SꢄGe BꢄcMoS fꢀꢁꢂꢃꢄꢅꢆꢁl-n PLL. the PLL ꢄꢆꢂludes ꢁ 8GHz 16-bꢄꢃ rF n-Dꢄvꢄdeꢀ, ꢁ 24-bꢄꢃ delꢃꢁ-
sꢄgmꢁ mꢅdulꢁꢃꢅꢀ, ꢁ veꢀy lꢅw ꢆꢅꢄse dꢄgꢄꢃꢁl phꢁse fꢀequeꢆꢂy deꢃeꢂꢃꢅꢀ (PFD), ꢁꢆd ꢁ pꢀeꢂꢄsꢄꢅꢆ ꢂꢅꢆꢃꢀꢅlled ꢂhꢁꢀge pump.
the fꢀꢁꢂꢃꢄꢅꢆꢁl-n PLL feꢁꢃuꢀes ꢁꢆ ꢁdvꢁꢆꢂed delꢃꢁ-sꢄgmꢁ mꢅdulꢁꢃꢅꢀ desꢄgꢆ ꢃhꢁꢃ ꢁllꢅws ulꢃꢀꢁ-fiꢆe fꢀequeꢆꢂy sꢃep sꢄzes.
the fꢀꢁꢂꢃꢄꢅꢆꢁl-n PLL feꢁꢃuꢀes ꢃhe ꢁbꢄlꢄꢃy ꢃꢅ ꢁlꢃeꢀ bꢅꢃh ꢃhe phꢁse-fꢀequeꢆꢂy deꢃeꢂꢃꢅꢀ (PFD) gꢁꢄꢆ ꢁꢆd ꢃhe ꢂyꢂle slꢄppꢄꢆg
ꢂhꢁꢀꢁꢂꢃeꢀꢄsꢃꢄꢂs ꢅf ꢃhe PFD. thꢄs feꢁꢃuꢀe ꢂꢁꢆ ꢀeduꢂe ꢃhe ꢃꢄme ꢃꢅ ꢁꢀꢀꢄve ꢁꢃ ꢃhe ꢆew fꢀequeꢆꢂy by 50% vs. ꢂꢅꢆveꢆꢃꢄꢅꢆꢁl
PFDs. Ulꢃꢀꢁ lꢅw ꢄꢆ-ꢂlꢅse phꢁse ꢆꢅꢄse ꢁlsꢅ ꢁllꢅws wꢄdeꢀ lꢅꢅp bꢁꢆdwꢄdꢃhs fꢅꢀ fꢁsꢃeꢀ fꢀequeꢆꢂy hꢅppꢄꢆg.
the fꢀꢁꢂꢃꢄꢅꢆꢁl-n PLL ꢂꢅꢆꢃꢁꢄꢆs ꢁ buꢄlꢃ-ꢄꢆ lꢄꢆeꢁꢀ sweepeꢀ fuꢆꢂꢃꢄꢅꢆ, whꢄꢂh ꢁllꢅws ꢄꢃ ꢃꢅ peꢀfꢅꢀm fꢀequeꢆꢂy ꢂhꢄꢀps wꢄꢃh ꢁ
wꢄde vꢁꢀꢄeꢃy ꢅf sweep ꢃꢄmes, pꢅlꢁꢀꢄꢃꢄes ꢁꢆd dwells, ꢁll wꢄꢃh ꢁꢆ exꢃeꢀꢆꢁl ꢅꢀ ꢁuꢃꢅmꢁꢃꢄꢂ sweep ꢃꢀꢄggeꢀ.
iꢆ ꢁddꢄꢃꢄꢅꢆ ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl-n PLL hꢁs ꢁ ꢆumbeꢀ ꢅf ꢁuxꢄlꢄꢁꢀy ꢂlꢅꢂk geꢆeꢀꢁꢃꢄꢅꢆ mꢅdes ꢃhꢁꢃ ꢂꢁꢆ be ꢁꢂꢂessed vꢄꢁ ꢃhe GPo.
Electrical Specifications, TA = +25°C
VccHF = VccPrS = rVDD = +3.3V
VPPcP = Vccoa = VDDPDr = VPPDrV = VDDPD = VDDPDV = +5V
DVDD = DVDDio = DVDDQ = +3.3V
GnDDrV = GnDcP = GnDPD = GnDPDV = GnDPDr = 0V
Table 1. Electrical Specifications
Pꢁꢀꢁmeꢃeꢀ
cꢅꢆdꢄꢃꢄꢅꢆs / nꢅꢃes
Mꢄꢆ
typ
Mꢁx
Uꢆꢄꢃs
Prescaler Characteristics
Mꢁx rF iꢆpuꢃ Fꢀequeꢆꢂy (3.3V)
Mꢁx rF iꢆpuꢃ Fꢀequeꢆꢂy (2.7 - 3.3V)
Mꢄꢆ rF iꢆpuꢃ Fꢀequeꢆꢂy
rF iꢆpuꢃ Pꢅweꢀ
8
9
8
GHz
GHz
MHz
dBm
7
0.1
-10
32
-6
10
16-bꢄꢃ n-Dꢄvꢄdeꢀ rꢁꢆge (iꢆꢃegeꢀ)
65,535
Fꢀꢁꢂꢃꢄꢅꢆ nꢅmꢄꢆꢁl Dꢄvꢄde ꢀꢁꢃꢄꢅ vꢁꢀꢄes
(-3 / +4) dyꢆꢁmꢄꢂꢁlly mꢁx
16-bꢄꢃ n-Dꢄvꢄdeꢀ rꢁꢆge (Fꢀꢁꢂꢃꢄꢅꢆꢁl)
35
65,531
REF Input Characteristics
Mꢁx ref iꢆpuꢃ Fꢀequeꢆꢂy (pꢄꢆ XrEFP)
Mꢁx ref iꢆpuꢃ Fꢀequeꢆꢂy (pꢄꢆ XSin)
250
250
200
220
MHz
MHz
50 Ω Sꢅuꢀꢂe. XSin mꢄꢆꢄmum
20MHz due ꢃꢅ phꢁse ꢆꢅꢄse degꢀꢁ-
dꢁꢃꢄꢅꢆ
Mꢄꢆ ref iꢆpuꢃ Fꢀequeꢆꢂy
100
kHz
ref iꢆpuꢃ Vꢅlꢃꢁge rꢁꢆge (pꢄꢆ XrEFP)
ref iꢆpuꢃ Pꢅweꢀ rꢁꢆge (pꢄꢆ XSin)
ref iꢆpuꢃ cꢁpꢁꢂꢄꢃꢁꢆꢂe
ac cꢅupled
750
-6
1000
0
3300
12
mVpp
dBm
pF
5
14-Bꢄꢃ r-Dꢄvꢄdeꢀ rꢁꢆge
1
16,383
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
2
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
(Continued)
Table 1. Electrical Specifications
Pꢁꢀꢁmeꢃeꢀ
cꢅꢆdꢄꢃꢄꢅꢆs / nꢅꢃes
Mꢄꢆ
typ
Mꢁx
Uꢆꢄꢃs
Phase Detector
Fꢀꢁꢂꢃꢄꢅꢆꢁl Mꢅde
Phꢁse Deꢃeꢂꢃꢅꢀ Fꢀequeꢆꢂy
iꢆꢃegeꢀ Mꢅde
0.1
0.1
70
MHz
MHz
Phꢁse Deꢃeꢂꢃꢅꢀ Fꢀequeꢆꢂy
Charge Pump
100
Mꢁx ouꢃpuꢃ cuꢀꢀeꢆꢃ
Mꢄꢆ ouꢃpuꢃ cuꢀꢀeꢆꢃ
chꢁꢀge Pump Gꢁꢄꢆ Sꢃep Sꢄze (5-bꢄꢃs)
chꢁꢀge Pump tꢀꢄm Sꢃep Sꢄze (3-bꢄꢃs)
chꢁꢀge Pump offseꢃ Sꢃep Sꢄze (4-bꢄꢃs)
PFD / chꢁꢀge Pump nꢅꢄse (iꢆꢃegeꢀ)
1 kHz
4
ma
µa
µa
µa
µa
125
125
14
29
6 GHz, 50 MHz ref, iꢆpuꢃ ꢀefeꢀꢀed
-141
-149
-155
dBꢂ/Hz
dBꢂ/Hz
dBꢂ/Hz
10 kHz
100 kHz
Less ꢃhꢁꢆ 3 dB degꢀꢁdꢁꢃꢄꢅꢆ ꢃyp. ꢁꢃ
ꢃhese lꢄmꢄꢃs
cꢅmplꢄꢁꢆꢂe Vꢅlꢃꢁge
-406 µa offseꢃ
-406 µa offseꢃ
0.4
0.8
VPPcP-0.8
VPPcP-0.4
V
V
Logic Inputs
ViH iꢆpuꢃ Hꢄgh Vꢅlꢃꢁge
ViL iꢆpuꢃ Lꢅw Vꢅlꢃꢁge
Logic Outputs
V
V
VDDio-0.4
VDDio-0.1
0.4
0.1
ViH ouꢃpuꢃ Hꢄgh Vꢅlꢃꢁge
ViL ouꢃpuꢃ Lꢅw Vꢅlꢃꢁge
Power Supply Voltages
Vcc - aꢆꢁlꢅg 3V Supplꢄes
DVDD - Dꢄgꢄꢃꢁl iꢆꢃeꢀꢆꢁl Supply
DVDDio - Dꢄgꢄꢃꢁl i/ꢅ Supply
V
V
VccPrS, rVDD, VccHF
DVDD, DVDDQ
DVDDio
3
3
3
3.3
3.3
3.3
3.45
3.45
3.45
V
V
V
Vccoa, VPPcP, VPPDrV,
VDDPD, VDDPDV, VDDPDr
aꢆꢁlꢅg 5V Supplꢄes
4.5
5.0
5.5
V
Power Supply Current (6 GHz Fꢀꢁꢂꢃꢄꢅꢆꢁl Mꢅde, 50 MHz PFD)
Vccoa, VPPcP, VPPDrV,
aꢆꢁlꢅg +5V
37
ma
VDDPD, VDDPDV, VDDPDr
VccPrS, rVDD, VccHF
DVDD, DVDDio, DVDDQ
aꢆꢁlꢅg +3.3V
Dꢄgꢄꢃꢁl +3.3V
71
19
ma
ma
reg 01h = 0
cꢀysꢃꢁl ꢆꢅꢃ ꢂlꢅꢂked
Pꢅweꢀ Dꢅwꢆ - cꢀysꢃꢁl off
6
µa
µa
reg 01h = 0
cꢀysꢃꢁl ꢂlꢅꢂked 100 MHz
Pꢅweꢀ Dꢅwꢆ - cꢀysꢃꢁl oꢆ, 100 MHz
20
200
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
3
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
(Continued)
Table 1. Electrical Specifications
Pꢁꢀꢁmeꢃeꢀ
cꢅꢆdꢄꢃꢄꢅꢆs / nꢅꢃes
Mꢄꢆ
typ
Mꢁx
Uꢆꢄꢃs
Temperature Sensor (3-bit)
Mꢄꢆ tempeꢀꢁꢃuꢀe
reꢁdꢅuꢃ: 000
reꢁdꢅuꢃ: 111
-32
+82
17.5
10
°c
°c
Mꢁx tempeꢀꢁꢃuꢀe
temp chꢁꢆge / LSB
°c/LSB
°c
Wꢅꢀsꢃ cꢁse absꢅluꢃe temp Eꢀꢀꢅꢀ
cuꢀꢀeꢆꢃ cꢅꢆsumpꢃꢄꢅꢆ (wheꢆ Eꢆꢁbled)
2
ma
Power on Reset all dꢄgꢄꢃꢁl ꢄꢆpuꢃs musꢃ be <0.7V pꢀꢄꢅꢀ ꢃꢅ ꢁpplꢄꢂꢁꢃꢄꢅꢆ ꢅf pꢅweꢀ fꢅꢀ pꢀꢅpeꢀ ꢀeseꢃ
typꢄꢂꢁl reseꢃ Vꢅlꢃꢁge ꢅꢆ DVDD
700
mV
V
Mꢄꢆ DVDD Vꢅlꢃꢁge fꢅꢀ nꢅ reseꢃ
1.5
Closed Loop Phase Noise
6 GHz Vco, iꢆꢃegeꢀ, 50 MHz PFD
6 GHz Vco, iꢆꢃegeꢀ, 50 MHz PFD
6 GHz Vco, iꢆꢃegeꢀ, 50 MHz PFD
6 GHz Vco, Fꢀꢁꢂꢃꢄꢅꢆꢁl, 50 MHz PFD
6 GHz Vco, Fꢀꢁꢂꢃꢄꢅꢆꢁl, 50 MHz PFD
6 GHz Vco, Fꢀꢁꢂꢃꢄꢅꢆꢁl, 50 MHz PFD
Closed Loop Phase Noise
iꢆꢃegeꢀ Mꢅde
1 kHz ꢅffseꢃ
10 kHz ꢅffseꢃ
-98
-108
-110
-93
dBꢂ/Hz
dBꢂ/Hz
dBꢂ/Hz
dBꢂ/Hz
dBꢂ/Hz
dBꢂ/Hz
100 kHz ꢅffseꢃ
1 kHz ꢅffseꢃ
10 kHz ꢅffseꢃ
-103
-105
100 kHz ꢅffseꢃ
nꢅꢀmꢁlꢄzed ꢃꢅ 1 Hz
Meꢁsuꢀed wꢄꢃh 50 MHz PFD
Meꢁsuꢀed wꢄꢃh 50 MHz PFD
-227
-221
dBꢂ/Hz
dBꢂ/Hz
Fꢀꢁꢂꢃꢄꢅꢆꢁl Mꢅde
Table 2. Absolute Maximum Ratings
Sꢃꢀesses ꢁbꢅve ꢃhꢅse lꢄsꢃed uꢆdeꢀ absꢅluꢃe Mꢁxꢄmum
rꢁꢃꢄꢆgs mꢁy ꢂꢁuse peꢀmꢁꢆeꢆꢃ dꢁmꢁge ꢃꢅ ꢃhe devꢄꢂe. thꢄs
ꢄs ꢁ sꢃꢀess ꢀꢁꢃꢄꢆg ꢅꢆly; fuꢆꢂꢃꢄꢅꢆꢁl ꢅpeꢀꢁꢃꢄꢅꢆ ꢅf ꢃhe devꢄꢂe
ꢁꢃ ꢃhese ꢅꢀ ꢁꢆy ꢅꢃheꢀ ꢂꢅꢆdꢄꢃꢄꢅꢆs ꢁbꢅve ꢃhꢅse ꢄꢆdꢄꢂꢁꢃed ꢄꢆ
ꢃhe ꢅpeꢀꢁꢃꢄꢅꢆꢁl seꢂꢃꢄꢅꢆ ꢅf ꢃhꢄs speꢂꢄfiꢂꢁꢃꢄꢅꢆ ꢄs ꢆꢅꢃ ꢄmplꢄed.
Expꢅsuꢀe ꢃꢅ ꢁbsꢅluꢃe mꢁxꢄmum ꢀꢁꢃꢄꢆg ꢂꢅꢆdꢄꢃꢄꢅꢆs fꢅꢀ
exꢃeꢆded peꢀꢄꢅds mꢁy ꢁffeꢂꢃ devꢄꢂe ꢀelꢄꢁbꢄlꢄꢃy.
Parameter
Rating
rVDD, VccHF, DVDD,
DVDDQ, VccPrS
-0.3 ꢃꢅ +3.6V
Vccoa, VPPcP, VPPDrV, VDDPD,
VDDPDV, VDDPDr, DVDDio
-0.3 ꢃꢅ +6V
opeꢀꢁꢃꢄꢆg tempeꢀꢁꢃuꢀe
Sꢃꢅꢀꢁge tempeꢀꢁꢃuꢀe
-40 ꢃꢅ +85 °c
-65 ꢃꢅ +120 °c
+125 °c
Mꢁxꢄmum Juꢆꢂꢃꢄꢅꢆ tempeꢀꢁꢃuꢀe
theꢀmꢁl resꢄsꢃꢁꢆꢂe (rꢃh)
reflꢅw Sꢅldeꢀꢄꢆg
20°c/W
Peꢁk tempeꢀꢁꢃuꢀe
260 °c
40 seꢂ
tꢄme ꢁꢃ Peꢁk tempeꢀꢁꢃuꢀe
ESD Seꢆsꢄꢃꢄvꢄꢃy (HBM)
clꢁss 1B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
4
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 3. Pin Description
Pꢄꢆ nꢅ.
Pꢄꢆ nꢁme
VccPrS
Vccoa
VPPcP
cP
Piꢆ type
Supply
Supply
Supply
aꢆꢁlꢅg o/P
GnD
Desꢂꢀꢄpꢃꢄꢅꢆ
1
rF Pꢀesꢂꢁleꢀ Pꢅweꢀ Supply. nꢅmꢄꢆꢁlly +3.3V
2
chꢁꢀgePump opamp Pꢅweꢀ Supply. nꢅmꢄꢆꢁlly +5V
Pꢅweꢀ Supply fꢅꢀ chꢁꢀge Pump. nꢅmꢄꢆꢁlly +5V
chꢁꢀge Pump ꢅuꢃpuꢃ
3
4
5
GnDcP
GnDDrV
VPPDrV
VDDPD
GnDPD
n/c
Pꢅweꢀ Supply GnD fꢅꢀ chꢁꢀge Pump
6
GnD
chꢁꢀge Pump GnD
7
Supply
Supply
GnD
Pꢅweꢀ supply fꢅꢀ chꢁꢀge Pump, nꢅmꢄꢆꢁlly +5V
Pꢅweꢀ Supply fꢅꢀ Phꢁse Deꢃeꢂꢃꢅꢀs, nꢅmꢄꢆꢁlly +5V
Pꢅweꢀ Supply GnD fꢅꢀ Phꢁse Deꢃeꢂꢃꢅꢀ
nꢅ cꢅꢆꢆeꢂꢃꢄꢅꢆ
8
9
10, 20, 21, 26
n/c
11
12
13
14
15
16
17
18
19
22
23
24
VDDPDV
GnDPDV
VDDPDr
GnDPDr
XrEFP
rVDD
Supply
GnD
Pꢅweꢀ Supply fꢅꢀ Phꢁse Deꢃeꢂꢃꢅꢀ Vco Pꢁꢃh, nꢅmꢄꢆꢁlly +5V
Pꢅweꢀ Supply GnD fꢅꢀ Phꢁse Deꢃeꢂꢃꢅꢀ Vco Pꢁꢃh
Pꢅweꢀ Supply fꢅꢀ Phꢁse Deꢃeꢂꢃꢅꢀ ref Pꢁꢃh, nꢅmꢄꢆꢁlly +5V
Pꢅweꢀ Supply GnD fꢅꢀ Phꢁse Deꢃeꢂꢃꢅꢀ ref Pꢁꢃh
Squꢁꢀe Wꢁve cꢀysꢃꢁl ref iꢆpuꢃ
Supply
GnD
aꢆꢁlꢅg i/P
Supply
aꢆꢁlꢅg i/P
aꢆꢁlꢅg i/o
cMoS i/P
Supply
Do
Pꢅweꢀ Supply fꢅꢀ ref Pꢁꢃh, nꢅmꢄꢆꢁlly +3.3V
Sꢄꢆusꢅꢄdꢁl cꢀysꢃꢁl ꢀefeꢀeꢆꢂe ꢄꢆpuꢃ
XSin
rEFcaP
rStB
refeꢀeꢆꢂe Pꢁꢃh bypꢁss
reseꢃ iꢆpuꢃ (ꢁꢂꢃꢄve lꢅw). cyꢂle lꢅw fꢅꢀ >tꢀef ꢃꢅ ꢀeseꢃ. reꢂꢅmmeꢆded ꢁfꢃeꢀ pꢅweꢀ-up.
Dꢄgꢄꢃꢁl Pꢅweꢀ Supply, nꢅmꢄꢆꢁlly +3.3V
Geꢆeꢀꢁl Puꢀpꢅse ouꢃpuꢃ 1 wꢄꢃh tꢀꢄsꢃꢁꢃe
Geꢆeꢀꢁl Puꢀpꢅse ouꢃpuꢃ 2 wꢄꢃh tꢀꢄsꢃꢁꢃe
DVDD
GPo1
GPo2
Do
Geꢆeꢀꢁl Puꢀpꢅse iꢆpuꢃ/ouꢃpuꢃ wꢄꢃh tꢀꢄsꢃꢁꢃe
mꢁy be ꢂꢅꢆfiguꢀed fꢅꢀ Exꢃeꢀꢆꢁl rꢁmp ꢃꢀꢄggeꢀ iꢆpuꢃ. See ꢀegꢄsꢃeꢀ rEG 14h[5]
25
GPo3
Dio
27
28
29
30
31
32
33
34
35
36
SEn
SDi
cMoS i/P
cMoS i/P
cMoS i/P
Do
Mꢁꢄꢆ Seꢀꢄꢁl pꢅꢀꢃ eꢆꢁble ꢄꢆpuꢃ
Mꢁꢄꢆ Seꢀꢄꢁl pꢅꢀꢃ dꢁꢃꢁ ꢄꢆpuꢃ
ScK
Mꢁꢄꢆ Seꢀꢄꢁl pꢅꢀꢃ ꢂlꢅꢂk ꢄꢆpuꢃ
VSLE
Leꢁve pꢄꢆ dꢄsꢂꢅꢆꢆeꢂꢃed.
VSDo
VScK
LD_SDo
DVDDio
DVDD
DVDDQ
Do
Leꢁve pꢄꢆ dꢄsꢂꢅꢆꢆeꢂꢃed.
Do
Leꢁve pꢄꢆ dꢄsꢂꢅꢆꢆeꢂꢃed.
cMoS o/P
Supply
Supply
Supply
Lꢅꢂk Deꢃeꢂꢃ ꢅꢀ Mꢁꢄꢆ Seꢀꢄꢁl Pꢅꢀꢃ Dꢁꢃꢁ ouꢃpuꢃ
Pꢅweꢀ Supply fꢅꢀ dꢄgꢄꢃꢁl i/o, mꢁꢃꢂhes exꢃeꢀꢆꢁl Dꢄgꢄꢃꢁl Supply ꢄꢆ 1.8V ꢃꢅ 5.5V ꢀꢁꢆge
iꢆꢃeꢀꢆꢁl Dꢄgꢄꢃꢁl Pꢅweꢀ Supply. nꢅmꢄꢆꢁlly 3.3V
Pꢅweꢀ Supply isꢅlꢁꢃꢄꢅꢆ pꢄꢆ. nꢅmꢄꢆꢁlly 3.3V, bypꢁssed ꢃꢅ GnD, zeꢀꢅ ꢂuꢀꢀeꢆꢃ.
cꢅmplemeꢆꢃꢁꢀy iꢆpuꢃ ꢃꢅ ꢃhe rF Pꢀesꢂꢁleꢀ. if sꢄꢆgle eꢆded ꢄꢆpuꢃ, ꢃhꢄs pꢅꢄꢆꢃ musꢃ be
deꢂꢅupled ꢃꢅ ꢃhe gꢀꢅuꢆd plꢁꢆe wꢄꢃh ꢁ ꢂeꢀꢁmꢄꢂ bypꢁss ꢂꢁpꢁꢂꢄꢃꢅꢀ, ꢃypꢄꢂꢁlly 100 pF
37
VcoiP
rF i/P
38
39
40
Vcoin
VccHF
BiaS
rF i/P
Supply
iꢆpuꢃ ꢃꢅ ꢃhe rF Pꢀesꢂꢁleꢀ. thꢄs sꢄgꢆꢁl ꢄꢆpuꢃ ꢄs ꢁꢂ-ꢂꢅupled ꢃꢅ ꢃhe exꢃeꢀꢆꢁl Vco
rF Seꢂꢃꢄꢅꢆ Pꢅweꢀ Supply. nꢅmꢄꢆꢁlly 3.3V
aꢆꢁlꢅg i/P
Deꢂꢅuplꢄꢆg Pꢄꢆ fꢅꢀ rF seꢂꢃꢄꢅꢆ, ꢆꢅmꢄꢆꢁlly exꢃeꢀꢆꢁl 1ꢆF bypꢁssed ꢃꢅ VccHF
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
5
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Typical Phase Noise - Integer Mode
Typical Phase Noise - Fractional Mode
-90
-90
6 GHz Integer
6 GHz Fractional
-100
-100
2 GHz Integer
2 GHz Fractional
-110
-120
-130
-140
-150
-160
-170
1 GHz Integer
-110
-120
-130
All Plots 50 MHz PFD
-140
All Plots 50 MHz PFD
-150
-160
-170
1000
104
105
106
107
108
1000
104
105
106
107
108
FREQUENCY (Hz)
FREQUENCY (Hz)
RF Divider Sensitivity
Frequency Sweep
6150
20
+85C
FRAC
INTEG
10
0
6100
6050
6000
5950
5900
5850
+25C
-40C
-10
-20
-30
-40
0
2000
4000
6000
8000
10000
-2
-1
0
1
2
3
FREQUENCY (MHz)
TIME (ms)
Cycle Slip Prevention: Frequency Hop
from 5200 MHꢀ to 3950 MHꢀ
5300
5100
4900
CSP OFF
4700
4500
CSP ON
4300
4100
3900
-10
0
10
20
30
40
50
60
70
TIME (μs)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
6
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Theory of Operation
the HMc701LP6cE syꢆꢃhesꢄzeꢀ ꢂꢅꢆsꢄsꢃs ꢅf ꢃhe fꢅllꢅwꢄꢆg fuꢆꢂꢃꢄꢅꢆꢁl blꢅꢂks
1. refeꢀeꢆꢂe Pꢁꢃh iꢆpuꢃ Buffeꢀs
2. refeꢀeꢆꢂe Pꢁꢃh Dꢄvꢄdeꢀ
3. Vco Pꢁꢃh iꢆpuꢃ Buffeꢀ
4. Vco Pꢁꢃh Mulꢃꢄ-Mꢅdulus Pꢀesꢂꢁleꢀ/Dꢄvꢄdeꢀ
5. Δ∑ Fꢀꢁꢂꢃꢄꢅꢆꢁl Mꢅdulꢁꢃꢅꢀ
6. Phꢁse Fꢀequeꢆꢂy Deꢃeꢂꢃꢅꢀ
7. chꢁꢀge Pump
9. auxꢄlꢄꢁꢀy Seꢀꢄꢁl Pꢅꢀꢃ
10. tempeꢀꢁꢃuꢀe Seꢆsꢅꢀ
11. Pꢅweꢀ oꢆ reseꢃ cꢄꢀꢂuꢄꢃ
12. cW Sweepeꢀ Subsysꢃem
13. auxꢄlꢄꢁꢀy clꢅꢂk Geꢆeꢀꢁꢃꢅꢀ
14. Geꢆeꢀꢁl Puꢀpꢅse ouꢃpuꢃ (GPo) Bus
15. Mulꢃꢄple Vco cꢅꢆꢃꢀꢅlleꢀ
8. Mꢁꢄꢆ Seꢀꢄꢁl Pꢅꢀꢃ
Eꢁꢂh ꢅf ꢃhese blꢅꢂks ꢄs desꢂꢀꢄbed bꢀꢄefly ꢄꢆ ꢃhe fꢅllꢅwꢄꢆg seꢂꢃꢄꢅꢆ.
Reference Path
the full refeꢀeꢆꢂe Pꢁꢃh blꢅꢂk dꢄꢁgꢀꢁm ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 1 the ulꢃꢀꢁ lꢅw ꢆꢅꢄse phꢁse deꢃeꢂꢃꢅꢀ ꢀequꢄꢀes ꢃhe besꢃ
pꢅssꢄble ꢀefeꢀeꢆꢂe sꢄgꢆꢁl. Sꢄꢆꢂe ꢁ gꢄveꢆ ꢁpplꢄꢂꢁꢃꢄꢅꢆ mꢁy desꢄꢀe ꢃꢅ use ꢁ squꢁꢀe wꢁve ꢅꢀ ꢁ 50 ohm sꢄꢆusꢅꢄdꢁl ꢂꢀysꢃꢁl
sꢅuꢀꢂe, HMc701LP6cE ꢅffeꢀs ꢃwꢅ ꢄꢆpuꢃ pꢅꢀꢃs, eꢁꢂh ꢅꢆe ꢅpꢃꢄmꢄzed fꢅꢀ ꢃhe lꢅwesꢃ pꢅssꢄble ꢆꢅꢄse fꢅꢀ ꢃhe sꢅuꢀꢂe ꢃype
beꢄꢆg used.
Fꢅꢀ ꢁbsꢅluꢃe besꢃ lꢅw ꢆꢅꢄse peꢀfꢅꢀmꢁꢆꢂe, ꢃhe sꢄꢆe wꢁve pꢁꢃh shꢅuld be used.
the useꢀ shꢅuld use ꢅꢆly ꢅꢆe ref pꢁꢃh ꢄꢆpuꢃ, ꢃhꢁꢃ ꢄs ꢃhe ꢄꢆpuꢃ ꢃhꢁꢃ mꢁꢃꢂhes ꢃheꢄꢀ ꢀefeꢀeꢆꢂe sꢅuꢀꢂe ꢃype. nꢅꢃe ꢃhe ꢄꢆpuꢃ
ꢄs defꢁulꢃed ꢃꢅ ꢃhe squꢁꢀe wꢁve ꢄꢆpuꢃ ꢅꢆ pꢅweꢀ up. Shꢅuld ꢃhe sꢄꢆe ꢀefeꢀeꢆꢂe pꢁꢃh be used, ꢄꢃ ꢄs ꢆeꢂessꢁꢀy ꢃꢅ eꢆꢁble
ꢃhe sꢄꢆe ꢄꢆpuꢃ, shuꢃ dꢅwꢆ ꢃhe squꢁꢀe wꢁve ꢄꢆpuꢃ ꢁꢆd seꢃ ꢃhe mux (rfp_buf_sin_en=1, rfp_buf_sq_en=0, rfp_buf_sin_
sel=1, tꢁble 12). the uꢆused pꢅꢀꢃ shꢅuld be lefꢃ ꢅpeꢆ.
the ꢀefeꢀeꢆꢂe pꢁꢃh suppꢅꢀꢃs ꢄꢆpuꢃ fꢀequeꢆꢂꢄes ꢅf up ꢃꢅ 250 MHz ꢃypꢄꢂꢁl, hꢅweveꢀ ꢃhe mꢁxꢄmum fꢀequeꢆꢂy ꢁꢃ ꢃhe
phꢁse deꢃeꢂꢃꢅꢀ (PFD) depeꢆds upꢅꢆ ꢃhe mꢅde ꢅf ꢅpeꢀꢁꢃꢄꢅꢆ, wꢅꢀsꢃ ꢂꢁse ꢁꢃ +85°c, 70 MHz ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢁꢆd
100 MHz ꢄꢆ ꢄꢆꢃegeꢀ mꢅde. Heꢆꢂe ꢀefeꢀeꢆꢂe ꢄꢆpuꢃs ꢅf gꢀeꢁꢃeꢀ ꢃhꢁꢆ ꢃhe PFD mꢁxꢄmum fꢀequeꢆꢂy musꢃ use ꢃhe
ꢁppꢀꢅpꢀꢄꢁꢃe r dꢄvꢄdeꢀ seꢃꢃꢄꢆg.
Figure 1. Reference Sine Input Stages
the uꢆused ꢀefeꢀeꢆꢂe pꢅꢀꢃ ꢄs ꢆꢅꢀmꢁlly ꢆꢅꢃ ꢂꢅꢆꢆeꢂꢃed.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
7
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Sine Reference Input
the ꢂꢀysꢃꢁl ꢀefeꢀeꢆꢂe sꢄꢆe ꢄꢆpuꢃ sꢃꢁge ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 2. thꢄs ꢄs ꢃhe lꢅwesꢃ ꢆꢅꢄse ꢀefeꢀeꢆꢂe pꢁꢃh. thꢄs ꢄs ꢁ ꢂꢅmmꢅꢆ
emꢄꢃꢃeꢀ sꢄꢆgle eꢆded bꢄpꢅlꢁꢀ buffeꢀ. the XSin ꢄꢆpuꢃ pꢄꢆ ꢄs Dc ꢂꢅupled ꢁꢆd hꢁs ꢁbꢅuꢃ 950 mV bꢄꢁs ꢅꢆ ꢄꢃ. Expeꢂꢃed
ꢄꢆpuꢃ ꢄs ꢁ 0 dBm sꢄꢆusꢅꢄd fꢀꢅm ꢁ 50 ohm sꢅuꢀꢂe. nꢅꢀmꢁlly ꢃhe ꢄꢆpuꢃ shꢅuld be ac ꢂꢅupled exꢃeꢀꢆꢁlly. the sꢄꢆe buffeꢀ
ꢄꢆpuꢃ ꢄmpedꢁꢆꢂe ꢄs dꢅmꢄꢆꢁꢃed by ꢁ 25 ohm shuꢆꢃ ꢀesꢄsꢃꢅꢀ ꢄꢆ seꢀꢄes wꢄꢃh ꢁ 50 pF ꢅꢆ ꢂhꢄp ꢂꢁp. Shꢅuld ꢁ lꢅweꢀ ꢄꢆpuꢃ
ꢄmpedꢁꢆꢂe be ꢆeeded, ꢁꢆ exꢃeꢀꢆꢁl 50 ohm shuꢆꢃ ꢀesꢄsꢃꢅꢀ ꢂꢁꢆ be used, Dc ꢄsꢅlꢁꢃed by ꢁꢆ exꢃeꢀꢆꢁl bypꢁss ꢂꢁp. the
sꢄꢆe ꢄꢆpuꢃ ꢀefeꢀeꢆꢂe pꢁꢃh phꢁse ꢆꢅꢄse flꢅꢅꢀ ꢄs ꢁppꢀꢅxꢄmꢁꢃely equꢄvꢁleꢆꢃ ꢃꢅ -159 dBꢂ/Hz. Fꢅꢀ besꢃ peꢀfꢅꢀmꢁꢆꢂe ꢂꢁꢀe
shꢅuld be ꢃꢁkeꢆ ꢃꢅ pꢀꢅvꢄde ꢁ ꢂꢀysꢃꢁl ꢀefeꢀeꢆꢂe sꢅuꢀꢂe wꢄꢃh equꢄvꢁleꢆꢃ ꢅꢀ beꢃꢃeꢀ phꢁse ꢆꢅꢄse flꢅꢅꢀ.
Figure 2. Ref Sine Input
Square Wave Reference Input
the squꢁꢀe wꢁve ref iꢆpuꢃ sꢃꢁge ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 3. the sꢃꢁge ꢄs desꢄgꢆed ꢃꢅ ꢁꢂꢂepꢃ squꢁꢀe wꢁve ꢄꢆpuꢃs fꢀꢅm cML
ꢃꢅ cMoS levels. Slꢄghꢃly degꢀꢁded phꢁse ꢆꢅꢄse peꢀfꢅꢀmꢁꢆꢂe mꢁy be ꢅbꢃꢁꢄꢆed wꢄꢃh quꢁsꢄ sꢄꢆe 1 Vpp ꢄꢆpuꢃs. iꢃ mꢁy be
ꢆeꢂessꢁꢀy ꢃꢅ ꢁꢃꢃeꢆuꢁꢃe veꢀy lꢁꢀge cMoS levels ꢄf ꢁbsꢅluꢃe besꢃ ꢄꢆ ꢂlꢅse phꢁse ꢆꢅꢄse peꢀfꢅꢀmꢁꢆꢂe ꢄs ꢀequꢄꢀed. iꢆpuꢃ
ꢀefeꢀeꢆꢂe shꢅuld hꢁve ꢁ ꢆꢅꢄse flꢅꢅꢀ beꢃꢃeꢀ ꢃhꢁꢆ -160 dBꢂ/Hz ꢃꢅ ꢁvꢅꢄd degꢀꢁdꢁꢃꢄꢅꢆ ꢅf ꢃhe ꢄꢆpuꢃ ꢀefeꢀeꢆꢂe pꢁꢃh.
Figure 3. Square Wave Ref Input Stage
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
8
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Reference Path ’R’ Divider
the ꢀefeꢀeꢆꢂed pꢁꢃh feꢁꢃuꢀes ꢁ 14-bꢄꢃ dꢄvꢄdeꢀ (rfp_div_ratio, Reg03h<13:0> tꢁble 14) ꢁꢆd ꢂꢁꢆ dꢄvꢄde ꢄꢆpuꢃ sꢄgꢆꢁls
ꢁꢃ up ꢃꢅ 250 MHz by ꢆumbeꢀs fꢀꢅm 1 ꢃꢅ 16,383. the seleꢂꢃed ꢄꢆpuꢃ ꢀefeꢀeꢆꢂe sꢅuꢀꢂe mꢁy be dꢄvꢄded ꢅꢀ bypꢁssed
(rfp_div_select), ꢁꢆd ꢁpplꢄed ꢃꢅ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢀefeꢀeꢆꢂe ꢄꢆpuꢃ.
Reference Path Test Features
a fꢀꢁꢂꢃꢄꢅꢆꢁl syꢆꢃhesꢄzeꢀ ꢄs ꢁ ꢂꢅmplex ꢂꢅmbꢄꢆꢁꢃꢄꢅꢆ ꢅf ꢁ lꢅw phꢁse ꢆꢅꢄse ꢁꢆꢁlꢅg ꢅsꢂꢄllꢁꢃꢅꢀ ꢀuꢆꢆꢄꢆg ꢄꢆ ꢂlꢅse pꢀꢅxꢄmꢄꢃy wꢄꢃh
ꢁ ꢆeꢁꢀly ꢀꢁꢆdꢅmly mꢅdulꢁꢃed delꢃꢁ-sꢄgmꢁ dꢄgꢄꢃꢁl mꢅdulꢁꢃꢅꢀ.
cleꢁꢆ spuꢀ fꢀee ꢅpeꢀꢁꢃꢄꢅꢆ ꢅf ꢃhe syꢆꢃhesꢄzeꢀ ꢀequꢄꢀes pꢀꢅpeꢀ bꢅꢁꢀd lꢁyꢅuꢃ ꢅf pꢅweꢀ ꢁꢆd gꢀꢅuꢆds. Spuꢀꢄꢅus sꢅuꢀꢂes
ꢁꢀe ꢅfꢃeꢆ dꢄffꢄꢂulꢃ ꢃꢅ ꢄdeꢆꢃꢄfy ꢁꢆd mꢁy be ꢀelꢁꢃed ꢃꢅ hꢁꢀmꢅꢆꢄꢂs ꢅf ꢃhe dꢄgꢄꢃꢁl mꢅdulꢁꢃꢄꢅꢆ whꢄꢂh lꢁꢆd ꢆeꢁꢀ ꢃhe ꢅpeꢀꢁꢃꢄꢆg
fꢀequeꢆꢂy ꢅf ꢃhe Vco, ꢅꢀ ꢃhey mꢁy ꢁꢀꢄse fꢀꢅm ꢀepeꢁꢃꢄꢆg pꢁꢃꢃeꢀꢆs ꢄꢆ ꢃhe dꢄgꢄꢃꢁl mꢅdulꢁꢃꢄꢅꢆ ꢄꢃself . the lꢅꢅp filꢃeꢀ ꢁꢆd ꢃhe
fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢅꢀ ꢁꢀe desꢄgꢆed ꢃꢅ suppꢀess ꢃhese fꢀꢁꢂꢃꢄꢅꢆꢁl spuꢀs, buꢃ ꢄꢃ ꢄs sꢅmeꢃꢄmes ꢃhe ꢂꢁse ꢃhꢁꢃ ꢃhe ꢄsꢅlꢁꢃꢄꢅꢆ
ꢅf ꢃhe spuꢀꢄꢅus pꢀꢅduꢂꢃs ꢂꢅmes fꢀꢅm lꢁyꢅuꢃ ꢄssues. the pꢀꢅblem ꢄs hꢅw ꢃꢅ ꢄdeꢆꢃꢄfy ꢃhe sꢅuꢀꢂes ꢅf spuꢀꢄꢅus pꢀꢅduꢂꢃs
ꢄf ꢃhey ꢅꢂꢂuꢀ?
the ꢀefeꢀeꢆꢂe pꢁꢃh ꢅf ꢃhe HMc701LP6cE feꢁꢃuꢀes sꢅme ꢄꢆꢃeꢀesꢃꢄꢆg ꢃesꢃ ꢅpꢃꢄꢅꢆs fꢅꢀ ꢂlꢅꢂkꢄꢆg ꢃhe dꢄgꢄꢃꢁl pꢅꢀꢃꢄꢅꢆ ꢅf ꢃhe
syꢆꢃhesꢄzeꢀ whꢄꢂh mꢁy pꢀꢅvꢄde fꢅꢀ ꢁ beꢃꢃeꢀ uꢆdeꢀsꢃꢁꢆdꢄꢆg ꢅf ꢃhe sꢅuꢀꢂe ꢅf ꢀefeꢀeꢆꢂe spuꢀs shꢅuld ꢃhey ꢅꢂꢂuꢀ. See
Fꢄguꢀe 4, tꢁble 12 ꢁꢆd tꢁble 29 fꢅꢀ mꢅꢀe ꢀegꢄsꢃeꢀ deꢃꢁꢄls.
Fꢅꢀ ꢆꢅꢀmꢁl ꢅpeꢀꢁꢃꢄꢅꢆ, reg3h[15]=1. Wheꢆ reg3h[15]=1, (ꢀfp_ꢁuꢃꢅ_ꢀefdꢄv seleꢂꢃ eꢆꢁbled) ꢃheꢆ reg 3 [14] & reg 1 [2]
ꢁꢀe ꢄgꢆꢅꢀed. if reg 3 [13:0] ꢄs pꢀꢅgꢀꢁmmed ꢃꢅ >=2, refDꢄv wꢄll be eꢆꢁbled ꢁꢆd ꢃhe dꢄvꢄded ꢅuꢃpuꢃ wꢄll be fed ꢃꢅ ꢃhe PFD.
if reg 3 [13:0] ꢄs pꢀꢅgꢀꢁmmed ꢃꢅ 1, refDꢄv wꢄll be dꢄsꢁbled ꢁꢆd ꢃhe uꢆdꢄvꢄded ꢀefeꢀeꢆꢂe sꢄgꢆꢁl wꢄll be fed ꢃꢅ ꢃhe PFD.
Wheꢆ reg3h[15]=0 (ꢀfp_ꢁuꢃꢅ_ꢀefdꢄv seleꢂꢃ dꢄsꢁbled), ꢃheꢆ ꢃhe sꢃꢁꢃe ꢅf ꢃhe refDꢄv ꢄs ꢂꢅꢆꢃꢀꢅlled by reg 3 [14] & reg
1 [2]. theꢆ ꢃꢅ eꢆꢁble refDꢄv reg 1 [2] = 1. tꢅ pꢁss ꢃhe dꢄvꢄded ꢀefeꢀeꢆꢂe sꢄgꢆꢁl ꢃꢅ ꢃhe PFD, reg 3 [14]=1. if reg
3 [14]=0, ꢃhe uꢆdꢄvꢄded ꢀefeꢀeꢆꢂe ꢄs pꢁssed dꢄꢀeꢂꢃly ꢃꢅ ꢃhe PFD. thꢄs ꢂꢅꢆfiguꢀꢁꢃꢄꢅꢆ wꢅuld ꢃypꢄꢂꢁlly ꢅꢆly be used fꢅꢀ
eꢆgꢄꢆeeꢀꢄꢆg ꢃesꢃ. iꢃ ꢁllꢅws ꢃhe refDꢄv ꢃꢅ be ꢀuꢆꢆꢄꢆg whꢄle ꢃhe PFD ꢄs ꢅpeꢀꢁꢃꢄꢆg wꢄꢃh ꢃhe uꢆdꢄvꢄded ꢀefeꢀeꢆꢂe. thꢄs
ꢁllꢅws ꢄꢆspeꢂꢃꢄꢅꢆ fꢅꢀ spuꢀs ꢃhꢁꢃ mꢁy be mꢁꢆꢄfesꢃ fꢀꢅm ꢃhe dꢄvꢄdeꢀ ꢀuꢆꢆꢄꢆg.
iꢃ ꢄs pꢅssꢄble fꢅꢀ exꢁmple ꢃꢅ seꢃ ꢃhe syꢆꢃhesꢄzeꢀ ꢃꢅ ꢄꢆꢃegeꢀ mꢅde ꢅf ꢅpeꢀꢁꢃꢄꢅꢆ, wheꢀe ꢃhe dꢄgꢄꢃꢁl hꢁꢀmꢅꢆꢄꢂs ꢆꢅꢀmꢁlly
fꢁll dꢄꢀeꢂꢃly ꢅꢆ ꢃhe Vco fꢀequeꢆꢂy. We mꢄghꢃ ꢂhꢅse fꢅꢀ exꢁmple ꢃꢅ use ꢃhe sꢄꢆe sꢅuꢀꢂe (rfp_buf_sine_sel=1, div_
todig_en=0) ꢃꢅ dꢀꢄve ꢃhe ꢀefeꢀeꢆꢂe dꢄvꢄdeꢀ. iꢆ suꢂh ꢁ ꢂꢁse ꢃhe delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢅꢀ ꢄs ꢆꢅꢃ ꢆꢅꢀmꢁlly used, hꢅweveꢀ ꢄf
we wꢄsh ꢃꢅ ꢃesꢃ ꢃhe effeꢂꢃs ꢅf ꢃhe dꢄgꢄꢃꢁl pꢅweꢀ supply ꢄsꢅlꢁꢃꢄꢅꢆ, we ꢂꢅuld ꢄꢆpuꢃ ꢁ 2ꢆd ꢀefeꢀeꢆꢂe sꢅuꢀꢂe ꢅꢆ ꢃhe squꢁꢀe
wꢁve ꢄꢆpuꢃ, eꢆꢁble ꢄꢃs buffeꢀ (rfp_buf_sq_en=1), ꢁꢆd eꢆꢁble ꢃhe 2ꢆd ꢂꢀysꢃꢁl ꢃꢅ ꢂlꢅꢂk ꢃhe uꢆused delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢅꢀ
(sqr_todig_en=1 ꢁꢆd dsm_xref_sin_select=0). thꢄs wꢅuld ꢁllꢅw ꢃhe squꢁꢀe wꢁve ꢂlꢅꢂk ꢃꢅ be seꢃ ꢄꢆdepeꢆdeꢆꢃly ꢅf
ꢃhe lꢅꢂked ꢄꢆꢃegeꢀ mꢅde Vco, ꢁꢆd heꢆꢂe meꢁsuꢀe ꢃhe ꢂꢅuplꢄꢆg ꢅf ꢃhe dꢄgꢄꢃꢁl ꢃꢅ ꢃhe sꢄdebꢁꢆds ꢅf ꢃhe Vco ꢁꢃ vꢁꢀꢄꢅus
fꢀequeꢆꢂꢄes. Suꢂh ꢁ ꢃesꢃ ꢂꢁꢆ help ꢄꢆ ꢄdeꢆꢃꢄfyꢄꢆg ꢁꢆd debuggꢄꢆg gꢀꢅuꢆdꢄꢆg ꢁꢆd lꢁyꢅuꢃ ꢄssues ꢄꢆ ꢃhe ꢁpplꢄꢂꢁꢃꢄꢅꢆ ꢂꢄꢀꢂuꢄꢃ
ꢀelꢁꢃed ꢃꢅ ꢃhe dꢄgꢄꢃꢁl pꢅꢀꢃꢄꢅꢆ ꢅf ꢃhe PcB shꢅuld ꢃhey ꢅꢂꢂuꢀ. iꢆ geꢆeꢀꢁl ꢄꢃ ꢄs ꢀeꢂꢅmmeꢆded ꢃꢅ fꢅllꢅw ꢃhe suggesꢃed lꢁyꢅuꢃ
ꢂlꢅsely ꢃꢅ ꢁvꢅꢄd ꢁꢆy suꢂh pꢀꢅblems.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
9
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Figure 4. Reference Path Block Diagram
VCO Path
the rF pꢁꢃh fꢀꢅm ꢃhe Vco ꢃꢅ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ, ꢄs ꢀefeꢀꢀed ꢃꢅ ꢁs ꢃhe Vco pꢁꢃh. the Vco pꢁꢃh ꢂꢅꢆsꢄsꢃs ꢅf ꢁꢆ ꢄꢆpuꢃ
ꢄsꢅlꢁꢃꢄꢅꢆ buffeꢀ ꢁꢆd ꢁ mulꢃꢄ-mꢅdulus pꢀesꢂꢁleꢀ, ꢅꢀ sꢄmply ꢃhe n dꢄvꢄdeꢀ. the n dꢄvꢄdeꢀ ꢄs ꢂꢅꢆꢃꢀꢅlled by ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl
mꢅdulꢁꢃꢅꢀ. thꢄs pꢁꢃh ꢅpeꢀꢁꢃes wꢄꢃh ꢄꢆpuꢃs dꢄꢀeꢂꢃly fꢀꢅm ꢃhe exꢃeꢀꢆꢁl Vco.
RF Input Stage
the syꢆꢃhesꢄzeꢀ rF ꢄꢆpuꢃ sꢃꢁge ꢀꢅuꢃes ꢃhe exꢃeꢀꢆꢁl Vco ꢃꢅ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ vꢄꢁ ꢁ 16-bꢄꢃ fꢀꢁꢂꢃꢄꢅꢆꢁl dꢄvꢄdeꢀ. the rF
ꢄꢆpuꢃ pꢁꢃh ꢄs ꢀꢁꢃed ꢃꢅ ꢅpeꢀꢁꢃe ꢆꢅmꢄꢆꢁlly fꢀꢅm 100 kHz ꢃꢅ 8 GHz ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl ꢁꢆd 9 GHz ꢄꢆ ꢄꢆꢃegeꢀ mꢅdes. the rF ꢄꢆpuꢃ
sꢃꢁge ꢁlsꢅ pꢀꢅvꢄdes ꢄsꢅlꢁꢃꢄꢅꢆ beꢃweeꢆ ꢃhe Vco ꢁꢆd ꢃhe pꢀesꢂꢁleꢀ. the rF ꢄꢆpuꢃ sꢃꢁge ꢄs ꢁ dꢄffeꢀeꢆꢃꢄꢁl ꢂꢅmmꢅꢆ emꢄꢃꢃeꢀ
sꢃꢁge, Dc ꢂꢅupled fꢅꢀ mꢁxꢄmum flexꢄbꢄlꢄꢃy. the ꢄꢆpuꢃ ꢄs pꢀꢅꢃeꢂꢃed by ESD dꢄꢅdes ꢁs shꢅwꢆ ꢄꢆ Fꢄguꢀe 5. nꢅꢀmꢁlly ꢃhe
rF ꢄꢆpuꢃ ꢄs ac ꢂꢅupled ꢃꢅ ꢁ sꢄꢆgle eꢆded exꢃeꢀꢆꢁl sꢅuꢀꢂe. the rFinP buffeꢀ ꢄs well mꢁꢃꢂhed fꢀꢅm ꢁ sꢄꢆgle eꢆded
50 ohm sꢅuꢀꢂe ꢁbꢅve ꢁbꢅuꢃ 3.5 GHz, wꢄꢃh ꢃhe ꢂꢅmplꢄmeꢆꢃꢁꢀy ꢄꢆpuꢃ gꢀꢅuꢆded. if ꢁ beꢃꢃeꢀ mꢁꢃꢂh ꢄs ꢀequꢄꢀed ꢁꢃ lꢅw
fꢀequeꢆꢂy ꢁ sꢄmple shuꢆꢃ 50 ohm ꢀesꢄsꢃꢅꢀ ꢂꢁꢆ be used exꢃeꢀꢆꢁl ꢃꢅ ꢃhe pꢁꢂkꢁge. if ꢁ dꢄffeꢀeꢆꢃꢄꢁl exꢃeꢀꢆꢁl sꢅuꢀꢂe ꢄs used
ꢃheꢆ ꢃhe ꢃwꢅ ꢄꢆpuꢃ pꢄꢆs mꢁy be used fꢅꢀ besꢃ peꢀfꢅꢀmꢁꢆꢂe.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
10
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Figure 5. RF Input Stage
RF Path ’N’ Divider
the mꢁꢄꢆ rF pꢁꢃh dꢄvꢄdeꢀ ꢄs ꢂꢁpꢁble ꢅf ꢁveꢀꢁge dꢄvꢄde ꢀꢁꢃꢄꢅs beꢃweeꢆ 65,531 ꢁꢆd 36 ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde, ꢁꢆd 65,535
ꢃꢅ 32 ꢄꢆ ꢄꢆꢃegeꢀ mꢅde. the ꢀeꢁsꢅꢆ fꢅꢀ ꢃhe dꢄffeꢀeꢆꢂe beꢃweeꢆ ꢄꢆꢃegeꢀ ꢁꢆd fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdes ꢄs ꢃhꢁꢃ ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl dꢄvꢄdeꢀ
ꢁꢂꢃuꢁlly dꢄvꢄdes by up ꢃꢅ 4 fꢀꢅm ꢃhe ꢁveꢀꢁge dꢄvꢄde ꢆumbeꢀ. aꢂꢃuꢁl dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅs wheꢆ used wꢄꢃh ꢁ gꢄveꢆ Vco wꢄll
depeꢆd upꢅꢆ ꢃhe ꢀefeꢀeꢆꢂe fꢀequeꢆꢂy used ꢁꢆd ꢃhe desꢄꢀed ꢅuꢃpuꢃ bꢁꢆd.
General Purpose Output (GPO) Interface
the HMc701LP6cE feꢁꢃuꢀes ꢁ 3-wꢄꢀe Geꢆeꢀꢁl Puꢀpꢅse ouꢃpuꢃ (GPo) ꢄꢆꢃeꢀfꢁꢂe. GPo ꢀegꢄsꢃeꢀs ꢁꢀe desꢂꢀꢄbed ꢄꢆ
Reg1Bh tꢁble 37. the GPo ꢄs ꢁ flexꢄble ꢄꢆꢃeꢀfꢁꢂe ꢃhꢁꢃ suppꢅꢀꢃs ꢁ ꢆumbeꢀ ꢅf dꢄffeꢀeꢆꢃ fuꢆꢂꢃꢄꢅꢆs ꢁꢆd ꢀeꢁl ꢃꢄme wꢁvefꢅꢀm
ꢁꢂꢂess ꢄꢆꢂludꢄꢆg:
ꢁ. Geꢆeꢀꢁl Dꢁꢃꢁ ouꢃpuꢃ fꢀꢅm SPi ꢀegꢄsꢃeꢀ gpꢅ_sel_0_
e. iꢆꢃeꢀꢆꢁl syꢆꢂhꢀꢅꢆꢄzed fꢀꢁꢂ sꢃꢀꢅbe wꢄꢃh ꢂlꢅꢂks
dꢁꢃꢁ (gpo_sel=0)
(gposel=4)
b. Pꢀesꢂꢁleꢀ & ꢀefeꢀeꢆꢂe pꢁꢃh ꢅuꢃpuꢃs (gpo_sel=1)
ꢂ. Lꢅꢂk Deꢃeꢂꢃ Wꢄꢆdꢅws (gpo_sel=2)
f. Δ∑ Mꢅdulꢁꢃꢅꢀ Phꢁse aꢂꢂumulꢁꢃꢅꢀ (gposel=6)
g. auxꢄlꢄꢁꢀy ꢅsꢂꢄllꢁꢃꢅꢀs (gposel=7)
d. aꢆꢃꢄ-ꢂyꢂle Slꢄp wꢁvefꢅꢀms (gpo_sel=3)
h. Δ∑ Mꢅdulꢁꢃꢅꢀ ouꢃpuꢃs (gposel=10)
General Data to GPO (gpo_sel=0)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=0 in tꢁble 37 ꢁssꢄgꢆs ꢃhe 3-bꢄꢃ dꢁꢃꢁ fꢀꢅm ꢀegꢄsꢃeꢀ gpo_sel_0_data Reg1B<6:4> ꢃꢅ ꢃhe GPo
bus.
Prescaler and Reference Path Outputs (gpo_sel = 1)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=1 (Reg1B<3:0> tꢁble 37) ꢀesulꢃs ꢄꢆ ꢃhe ꢄꢆpuꢃ ꢂꢀysꢃꢁl beꢄꢆg buffeꢀed ꢅuꢃ ꢃꢅ GPo3 ꢁs shꢅwꢆ
ꢄꢆ Fꢄguꢀe 6. thꢄs ꢄs useful fꢅꢀ exꢁmple ꢃꢅ geꢆeꢀꢁꢃe ꢁ ꢂꢅpy ꢅf ꢃhe ꢄꢆpuꢃ ꢂꢀysꢃꢁl sꢄgꢆꢁl ꢃꢅ dꢀꢄve ꢅꢃheꢀ ꢂꢄꢀꢂuꢄꢃs ꢄꢆ ꢃhe
ꢁpplꢄꢂꢁꢃꢄꢅꢆ, whꢄle ꢁꢃ ꢃhe sꢁme ꢃꢄme ꢄsꢅlꢁꢃꢄꢆg ꢃhe ꢆꢅꢄsy ꢂꢄꢀꢂuꢄꢃs fꢀꢅm ꢃhe seꢆsꢄꢃꢄve ꢂꢀysꢃꢁl ꢅuꢃpuꢃ. ofꢃeꢆ ꢅꢆly ꢃhe
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
11
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
syꢆꢃhesꢄzeꢀ ꢀequꢄꢀes veꢀy lꢅw phꢁse ꢆꢅꢄse fꢀꢅm ꢃhe ꢂꢀysꢃꢁl, heꢆꢂe ꢄꢃ ꢄs desꢄꢀꢁble ꢃꢅ ꢄsꢅlꢁꢃe ꢅꢃheꢀ ꢂꢄꢀꢂuꢄꢃs fꢀꢅm ꢃhe
ꢂꢀysꢃꢁl ꢄꢃself ꢁꢆd ꢁllꢅw ꢃhe syꢆꢃhesꢄzeꢀ sꢅle use ꢅf ꢃhe lꢅw phꢁse ꢆꢅꢄse ꢂꢀysꢃꢁl.
gpo_sel=1 ꢁlsꢅ ꢀꢅuꢃes ꢃhe 250 MHz 14-bꢄꢃ ꢀefeꢀeꢆꢂe pꢁꢃh dꢄvꢄdeꢀ ꢃꢅ GP02 ꢁꢆd ꢃhe 16-bꢄꢃ 7 GHz Vco pꢁꢃh pꢀesꢂꢁleꢀ
ꢅuꢃpuꢃ ꢃꢅ GP01. thꢄs ꢅpꢃꢄꢅꢆ ꢁllꢅws ꢃhe syꢆꢃhesꢄzeꢀ ꢃꢅ fuꢆꢂꢃꢄꢅꢆ ꢁs ꢁ sꢃꢁꢆd ꢁlꢅꢆe fꢀꢁꢂꢃꢄꢅꢆꢁl ꢅꢀ ꢄꢆꢃegeꢀ pꢀesꢂꢁleꢀ ꢁꢆd
pꢀꢅvꢄdes vꢄsꢄbꢄlꢄꢃy ꢄꢆꢃꢅ ꢃhe pꢀesꢂꢁleꢀ ꢁꢆd ꢀefeꢀeꢆꢂe pꢁꢃh ꢃꢄmꢄꢆg fꢅꢀ seꢆsꢄꢃꢄve ꢁpplꢄꢂꢁꢃꢄꢅꢆs.
Figure 6. gpo_01 Outputs
Lock Detect Windows (gpo_sel=2)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel = 2 (Reg1Bh<3:0> tꢁble 37) ꢀesulꢃs ꢄꢆ ꢃhe lꢅꢂk deꢃeꢂꢃ wꢄꢆdꢅw (Fꢄguꢀe 11) ꢁꢆd ꢃhe phꢁse
fꢀequeꢆꢂy deꢃeꢂꢃꢅꢀ UP ꢁꢆd Dn ꢅuꢃpuꢃ ꢂꢅꢆꢃꢀꢅl sꢄgꢆꢁls (Fꢄguꢀe 14) ꢃꢅ be ꢀꢅuꢃed ꢃꢅ pꢄꢆs GPo1, GPo3 ꢁꢆd GPo2
ꢀespeꢂꢃꢄvely. thꢄs ꢅpꢃꢄꢅꢆ gꢄves ꢄꢆsꢄghꢃ ꢄꢆꢃꢅ ꢃhe Lꢅꢂk Deꢃeꢂꢃꢄꢅꢆ Pꢀꢅꢂess ꢁꢆd ꢂꢅuld ꢁllꢅw ꢃhe syꢆꢃhesꢄzeꢀ ꢃꢅ be used wꢄꢃh
ꢁꢆ exꢃeꢀꢆꢁl ꢂhꢁꢀge pump.
Figure 7. gpo_02 Outputs
Anti-cycle Slip Waveforms (gpo_sel = 3)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=3 (Reg1Bh<3:0> tꢁble 37) gꢄves vꢄsꢄbꢄlꢄꢃy ꢄꢆꢃꢅ ꢃhe ꢁꢆꢃꢄ-ꢂyꢂle slꢄppꢄꢆg fuꢆꢂꢃꢄꢅꢆ ꢅf ꢃhe PFD
ꢁs desꢂꢀꢄbed ꢄꢆ seꢂꢃꢄꢅꢆ Cycle Slip Prevention (cSP). thꢀee wꢁvefꢅꢀms, ꢀefeꢀeꢆꢂe pꢁꢃh fꢀeq > Vco pꢁꢃh fꢀeq, vꢂꢅ
pꢁꢃh fꢀeq > ꢀef pꢁꢃh fꢀeq, ꢁꢆd ꢁ PFD sꢃꢀꢅbe whꢄꢂh hꢅlds ꢃhe PFD ꢁꢃ mꢁxꢄmum gꢁꢄꢆ, ꢁꢀe ꢀꢅuꢃed ꢃꢅ GPo3, GPo2, ꢁꢆd
GPo1 ꢀespeꢂꢃꢄvely. these lꢄꢆes wꢄll be ꢁꢂꢃꢄve duꢀꢄꢆg fꢀequeꢆꢂy pull-ꢄꢆ ꢁꢆd wꢄll ꢄꢆdꢄꢂꢁꢃe ꢄꢆsꢃꢁꢆꢃꢁꢆeꢅusly whꢄꢂh sꢄgꢆꢁl,
ꢀefeꢀeꢆꢂe ꢅꢀ vꢂꢅ pꢁꢃh ꢄs gꢀeꢁꢃeꢀ ꢄꢆ fꢀequeꢆꢂy. the PFD sꢃꢀꢅbe gꢄves ꢄꢆsꢄghꢃ ꢄꢆꢃꢅ wheꢆ ꢃhe PFD ꢄs ꢆeꢁꢀ mꢁxꢄmum gꢁꢄꢆ
ꢁꢃ 2π. the PFD sꢃꢀꢅbe wꢄll be ꢁꢂꢃꢄve uꢆꢃꢄl ꢃhe Vco pulls ꢄꢆꢃꢅ lꢅꢂk.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
12
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Internal Synchroniꢀed Frac strobe with clocks (gpo_sel= 4)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=4 ꢄꢆ (Reg1Bh<3:0> tꢁble 37) gꢄves vꢄsꢄbꢄlꢄꢃy ꢄꢆꢃꢅ ꢃhe ꢄꢆꢃeꢀꢆꢁlly syꢆꢂhꢀꢅꢆꢄzed sꢃꢀꢅbe ꢃhꢁꢃ
ꢄs geꢆeꢀꢁꢃed wheꢆ ꢂꢅmmꢁꢆdꢄꢆg ꢁ fꢀequeꢆꢂy ꢂhꢁꢆge by wꢀꢄꢃꢄꢆg ꢃꢅ ꢃhe fꢀꢁꢂ ꢀegꢄsꢃeꢀ. the ꢄꢆꢃeꢀꢆꢁl sꢃꢀꢅbe ꢄꢆꢄꢃꢄꢁꢃes ꢃhe
updꢁꢃe ꢃꢅ ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢅꢀ. the ꢄꢆꢃeꢀꢆꢁl fꢀꢁꢂ sꢃꢀꢅbe, ꢃhe ꢀef pꢁꢃh dꢄvꢄdeꢀ ꢅuꢃpuꢃ ꢁꢆd ꢃhe sꢄꢆe ꢀefeꢀeꢆꢂe ꢄꢆpuꢃ ꢁꢀe
buffeꢀed ꢅuꢃ ꢃꢅ GPo1,GPo2 ꢁꢆd GPo3 ꢀespeꢂꢃꢄvely ꢁs shꢅwꢆ ꢄꢆ Fꢄguꢀe 8. iꢆ ꢃhꢄs mꢅde, GPo1 mꢁy be used ꢃꢅ ꢃꢀꢄggeꢀ
ꢁꢆ exꢃeꢀꢆꢁl ꢄꢆsꢃꢀumeꢆꢃ wheꢆ dꢅꢄꢆg fꢀequeꢆꢂy hꢅppꢄꢆg ꢃesꢃs fꢅꢀ exꢁmple.
Figure 8. gpo_04 Outputs
Δ∑ Modulator Phase Accumulator (gpo_sel=6)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=6 (Reg1Bh<3:0> tꢁble 37) ꢁssꢄgꢆs ꢃhe ꢃhꢀee msb’s ꢅf ꢃhe delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢅꢀ fiꢀsꢃ
ꢁꢂꢂumulꢁꢃꢅꢀ ꢃꢅ GPo<3:1>, wheꢀe GPo3 ꢄs ꢃhe msb. thꢄs feꢁꢃuꢀe pꢀꢅvꢄdes ꢄꢆsꢄghꢃ ꢄꢆꢃꢅ ꢃhe phꢁse ꢅf ꢃhe Vco.
Auxiliary Oscillators (gpo_sel=7)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=7 (Reg1Bh<3:0> tꢁble 37) ꢁssꢄgꢆs ꢁꢆ ꢁuxꢄlꢄꢁꢀy ꢂlꢅꢂk, ꢁꢆ ꢄꢆꢃeꢀꢆꢁl ꢀꢄꢆg ꢅsꢂꢄllꢁꢃꢅꢀ, ꢁꢆd ꢃhe
ꢄꢆꢃeꢀꢆꢁl sꢄgmꢁ delꢃꢁ ꢂlꢅꢂk ꢃꢅ GPo3, 2, 1 ꢀespeꢂꢃꢄvely. the ꢂꢅꢆꢃꢀꢅl ꢅf ꢃhe ꢁuxꢄlꢄꢁꢀy ꢂlꢅꢂk ꢄs deꢃeꢀmꢄꢆed by reg18h tꢁble
34 ꢁꢆd Reg19h tꢁble 35. iꢆ geꢆeꢀꢁl ꢃeꢀms, ꢃhꢄs hꢄghly flexꢄble ꢂlꢅꢂk sꢅuꢀꢂe ꢁllꢅws ꢃhe seleꢂꢃꢄꢅꢆ ꢅf ꢅꢆe ꢅf ꢃhe vꢁꢀꢄꢅus
Vco ꢅꢀ ꢂꢀysꢃꢁl ꢀelꢁꢃed ꢂlꢅꢂks ꢄꢆsꢄde ꢃhe syꢆꢃhesꢄzeꢀ ꢅꢀ ꢃhe seleꢂꢃꢄꢅꢆ ꢅf ꢁ flexꢄble uꢆsꢃꢁbꢄlꢄzed ꢁuxꢄlꢄꢁꢀy ꢀꢄꢆg ꢅsꢂꢄllꢁꢃꢅꢀ
ꢂlꢅꢂk. aꢆy ꢅf ꢃhe sꢅuꢀꢂes mꢁy be ꢀꢅuꢃed ꢅuꢃ vꢄꢁ gpꢅ_sel=7. addꢄꢃꢄꢅꢆꢁl Reg18h tꢁble 34 ꢂlꢅꢂk ꢂꢅꢆꢃꢀꢅls ꢁllꢅw ꢃhe ꢁux
ꢂlꢅꢂk ꢃꢅ be delꢁyed by ꢁ vꢁꢀꢄꢁble ꢁmꢅuꢆꢃ (auxclk_modesel Reg18h<3:2>), ꢅꢀ ꢃꢅ be dꢄvꢄded dꢅwꢆ by eveꢆ vꢁlues fꢀꢅm
2 ꢃꢅ 14 (auxclk_divsel Reg18h<6:4>).
Δ∑ Modulator Outputs (gpo_sel=10)
Seꢃꢃꢄꢆg ꢀegꢄsꢃeꢀ gpo_sel=10 (Reg1B<3:0> tꢁble 37) ꢁssꢄgꢆs ꢃhe ꢃhꢀee lsb’s ꢅf ꢃhe delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢅꢀ ꢅuꢃpuꢃ ꢃꢅ
GPo<3:1> , wheꢀe GPo1 ꢄs ꢃhe lsb. thꢄs feꢁꢃuꢀe ꢁllꢅws ꢃhe pꢅssꢄbꢄlꢄꢃy ꢅf usꢄꢆg ꢃhe HMc701LP6cE ꢁs ꢁ geꢆeꢀꢁl
puꢀpꢅse dꢄgꢄꢃꢁl delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢅꢀ fꢅꢀ mꢁꢆy pꢅssꢄble ꢁpplꢄꢂꢁꢃꢄꢅꢆs.
External VCO
the HMc701LP6cE ꢄs ꢃꢁꢀgeꢃed fꢅꢀ ulꢃꢀꢁ lꢅw phꢁse ꢆꢅꢄse ꢁpplꢄꢂꢁꢃꢄꢅꢆs wꢄꢃh ꢁꢆ exꢃeꢀꢆꢁl Vco. the syꢆꢃhesꢄzeꢀ hꢁs
beeꢆ desꢄgꢆed ꢃꢅ wꢅꢀk wꢄꢃh Vcos ꢃhꢁꢃ ꢂꢁꢆ be ꢃuꢆed ꢆꢅmꢄꢆꢁlly ꢅveꢀ 0.5 ꢃꢅ 4.5 Vꢅlꢃs ꢅꢆ ꢃhe vꢁꢀꢁꢂꢃꢅꢀ ꢃuꢆꢄꢆg pꢅꢀꢃ wꢄꢃh ꢁ
+5V ꢂhꢁꢀge pump supply vꢅlꢃꢁge. Slꢄghꢃly wꢄdeꢀ ꢀꢁꢆges ꢁꢀe pꢅssꢄble wꢄꢃh ꢁ +5.5V ꢂhꢁꢀge pump supply ꢅꢀ wꢄꢃh slꢄghꢃly
degꢀꢁded peꢀfꢅꢀmꢁꢆꢂe. aꢆ exꢃeꢀꢆꢁl ꢅpꢁmp ꢁꢂꢃꢄve filꢃeꢀ ꢄs ꢀequꢄꢀed ꢃꢅ suppꢅꢀꢃ Vcos wꢄꢃh ꢃuꢆꢄꢆg vꢅlꢃꢁges ꢁbꢅve 5V.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
13
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
External VCO with Active Inverting OpAmp Loop Filter
aꢆ exꢃeꢀꢆꢁl ꢅpꢁmp ꢁꢂꢃꢄve filꢃeꢀ ꢄs ꢀequꢄꢀed ꢃꢅ suppꢅꢀꢃ exꢃeꢀꢆꢁl Vcos wꢄꢃh ꢃuꢆꢄꢆg vꢅlꢃꢁges ꢁbꢅve 5V. if ꢁꢆ ꢄꢆveꢀꢃꢄꢆg
ꢅpꢁmp ꢄs used wꢄꢃh ꢁ pꢅsꢄꢃꢄve slꢅpe Vco, phꢁse_sel reg05h <0> = 1 tꢁble 16 musꢃ be seꢃ ꢃꢅ ꢄꢆveꢀꢃ ꢃhe PFD phꢁse
pꢅlꢁꢀꢄꢃy ꢁꢆd ꢅbꢃꢁꢄꢆ ꢂꢅꢀꢀeꢂꢃ ꢂlꢅsed lꢅꢅp ꢅpeꢀꢁꢃꢄꢅꢆ.
Temperature Sensor
the HMc701LP6cE feꢁꢃuꢀes ꢁ buꢄlꢃ ꢄꢆ ꢃempeꢀꢁꢃuꢀe seꢆsꢅꢀ whꢄꢂh mꢁy be used ꢁs ꢁ geꢆeꢀꢁl puꢀpꢅse ꢃempeꢀꢁꢃuꢀe
seꢆsꢅꢀ.
the ꢃempeꢀꢁꢃuꢀe seꢆsꢅꢀ ꢄs eꢆꢁbled vꢄꢁ tsens_spi_enable (Reg1Eh=1 tꢁble 40) ꢁꢆd wheꢆ eꢆꢁbled dꢀꢁws 2 ma.
the ꢃempeꢀꢁꢃuꢀe seꢆsꢅꢀ feꢁꢃuꢀes ꢁ buꢄlꢃ ꢄꢆ 3-bꢄꢃ quꢁꢆꢃꢄzeꢀ ꢃhꢁꢃ ꢁllꢅws ꢃhe ꢃempeꢀꢁꢃuꢀe ꢃꢅ be ꢀeꢁd ꢄꢆ ꢀegꢄsꢃeꢀ tsens_
temperature (Reg21h tꢁble 43). the ꢃempeꢀꢁꢃuꢀe seꢆsꢅꢀ dꢁꢃꢁ ꢂꢅꢆveꢀꢃeꢀ ꢄs ꢆꢅꢃ ꢂlꢅꢂked. Updꢁꢃes ꢃꢅ ꢃhe ꢃempeꢀꢁꢃuꢀe
seꢆsꢅꢀ ꢀegꢄsꢃeꢀ ꢁꢀe mꢁde by sꢃꢀꢅbbꢄꢆg ꢀegꢄsꢃeꢀ tsens_spi_strobe (reg00h<3> tꢁble 11). the 3-bꢄꢃ quꢁꢆꢃꢄzeꢀ ꢅpeꢀꢁꢃes
ꢅveꢀ ꢁ -40°c ꢃꢅ +100°c ꢀꢁꢆge ꢁs fꢅllꢅws:
tꢆ = flꢅꢅꢀ {(tempeꢀꢁꢃuꢀe +40) / 17.5 wheꢀe T ꢄs ꢃhe deꢂꢄmꢁl vꢁlue ꢅf ꢀegꢄsꢃeꢀ tsens_temperature}
(EQ 7)
n
7
6
5
4
3
2
1
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 9. Typical Temperature Sensor Quantizer output
tempeꢀꢁꢃuꢀe seꢆsꢅꢀ slꢅpe ꢄs 17.5 mV/lsb. absꢅluꢃe ꢃꢅleꢀꢁꢆꢂes ꢅꢆ ꢃhe ꢃempeꢀꢁꢃuꢀe seꢆsꢅꢀ ꢃhꢀeshꢅlds mꢁy vꢁꢀy by up
ꢃꢅ 10°c wꢅꢀsꢃ ꢂꢁse.
nꢅmꢄꢆꢁl ꢃempeꢀꢁꢃuꢀe ꢄs gꢄveꢆ by:
(EQ 8)
Charge Pump & Phase Frequency Detector (PFD)
the Phꢁse Fꢀequeꢆꢂy Deꢃeꢂꢃꢅꢀ ꢅꢀ PFD hꢁs ꢃwꢅ ꢄꢆpuꢃs, ꢅꢆe fꢀꢅm ꢃhe ꢀefeꢀeꢆꢂe pꢁꢃh dꢄvꢄdeꢀ ꢁꢆd ꢅꢆe fꢀꢅm ꢃhe Vco pꢁꢃh
dꢄvꢄdeꢀ. the PFD ꢂꢅmpꢁꢀes ꢃhe phꢁse ꢅf ꢃhe Vco pꢁꢃh sꢄgꢆꢁl wꢄꢃh ꢃhꢁꢃ ꢅf ꢃhe ꢀefeꢀeꢆꢂe pꢁꢃh sꢄgꢆꢁl ꢁꢆd ꢂꢅꢆꢃꢀꢅls ꢃhe
ꢂhꢁꢀge pump ꢅuꢃpuꢃ ꢂuꢀꢀeꢆꢃ ꢁs ꢁ lꢄꢆeꢁꢀ fuꢆꢂꢃꢄꢅꢆ ꢅf ꢃhe phꢁse dꢄffeꢀeꢆꢂe beꢃweeꢆ ꢃhe ꢃwꢅ sꢄgꢆꢁls. the ꢅuꢃpuꢃ ꢂuꢀꢀeꢆꢃ
vꢁꢀꢄes lꢄꢆeꢁꢀly ꢅveꢀ ꢁ full 2π ꢀꢁdꢄꢁꢆs ꢄꢆpuꢃ phꢁse dꢄffeꢀeꢆꢂe.
PFD Functions
phase_sel (Reg05h<0> tꢁble 16) ꢄꢆveꢀꢃs ꢃhe phꢁse deꢃeꢂꢃꢅꢀ, pꢅlꢁꢀꢄꢃy fꢅꢀ use wꢄꢃh ꢁꢆ ꢄꢆveꢀꢃꢄꢆg ꢅpꢁmp ꢅꢀ ꢆegꢁꢃꢄve
slꢅpe Vco.
upout_en ꢄꢆ Reg05h<1> tꢁble 16 ꢁllꢅws mꢁskꢄꢆg ꢅf ꢃhe PFD up ꢅuꢃpuꢃ, whꢄꢂh effeꢂꢃꢄvely pꢀeveꢆꢃs
ꢃhe ꢂhꢁꢀge pump fꢀꢅm pumpꢄꢆg up.
dnout_en ꢄꢆ Reg05h<2> tꢁble 16 ꢁllꢅws mꢁskꢄꢆg ꢅf ꢃhe PFD dꢅwꢆ ꢅuꢃpuꢃ, whꢄꢂh effeꢂꢃꢄvely
pꢀeveꢆꢃs ꢃhe ꢂhꢁꢀge pump fꢀꢅm pumpꢄꢆg dꢅwꢆ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
14
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Charge Pump Tri-State
De-ꢁsseꢀꢃꢄꢆg bꢅꢃh upout_en ꢁꢆd dnout_en effeꢂꢃꢄvely ꢃꢀꢄ-sꢃꢁꢃes ꢃhe ꢂhꢁꢀge pump whꢄle leꢁvꢄꢆg ꢁll ꢅꢃheꢀ fuꢆꢂꢃꢄꢅꢆs
ꢅpeꢀꢁꢃꢄꢆg ꢄꢆꢃeꢀꢆꢁlly.
PFD Jitter & Lock Detect Background
iꢆ ꢆꢅꢀmꢁl phꢁse lꢅꢂked ꢅpeꢀꢁꢃꢄꢅꢆ ꢃhe dꢄvꢄded Vco sꢄgꢆꢁl ꢁꢀꢀꢄves ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢄꢆ phꢁse wꢄꢃh ꢃhe dꢄvꢄded
ꢂꢀysꢃꢁl sꢄgꢆꢁl, kꢆꢅwꢆ ꢁs ꢃhe ꢀefeꢀeꢆꢂe sꢄgꢆꢁl. Despꢄꢃe ꢃhe fꢁꢂꢃ ꢃhꢁꢃ ꢃhe devꢄꢂe ꢄs ꢄꢆ lꢅꢂk, ꢃhe phꢁse ꢅf ꢃhe Vco sꢄgꢆꢁl
ꢁꢆd ꢃhe ꢀefeꢀeꢆꢂe sꢄgꢆꢁl vꢁꢀy ꢄꢆ ꢃꢄme due ꢃꢅ ꢃhe phꢁse ꢆꢅꢄse ꢅf ꢃhe ꢂꢀysꢃꢁl ꢁꢆd Vco ꢅsꢂꢄllꢁꢃꢅꢀs, ꢃhe lꢅꢅp bꢁꢆdwꢄdꢃh
used ꢁꢆd ꢃhe pꢀeseꢆꢂe ꢅf fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢄꢅꢆ ꢅꢀ ꢆꢅꢃ. the ꢃꢅꢃꢁl ꢄꢆꢃegꢀꢁꢃed ꢆꢅꢄse ꢅꢆ ꢃhe Vco pꢁꢃh ꢆꢅꢀmꢁlly dꢅmꢄꢆꢁꢃes
ꢃhe vꢁꢀꢄꢁꢃꢄꢅꢆs ꢄꢆ ꢃhe ꢃwꢅ ꢁꢀꢀꢄvꢁl ꢃꢄmes ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢄf fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢄꢅꢆ ꢄs ꢃuꢀꢆed ꢅff.
if we wꢄsh ꢃꢅ deꢃeꢂꢃ ꢄf ꢃhe Vco ꢄs ꢄꢆ lꢅꢂk ꢅꢀ ꢆꢅꢃ we ꢆeed ꢃꢅ dꢄsꢃꢄꢆguꢄsh beꢃweeꢆ ꢆꢅꢀmꢁl phꢁse jꢄꢃꢃeꢀ wheꢆ ꢄꢆ lꢅꢂk ꢁꢆd
phꢁse jꢄꢃꢃeꢀ wheꢆ ꢆꢅꢃ ꢄꢆ lꢅꢂk.
Fꢄꢀsꢃ, we ꢆeed ꢃꢅ uꢆdeꢀsꢃꢁꢆd whꢁꢃ ꢄs ꢃhe jꢄꢃꢃeꢀ ꢅf ꢃhe syꢆꢃhesꢄzeꢀ, meꢁsuꢀed ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢄꢆ ꢄꢆꢃegeꢀ ꢅꢀ fꢀꢁꢂꢃꢄꢅꢆꢁl
mꢅdes.
the sꢃꢁꢆdꢁꢀd devꢄꢁꢃꢄꢅꢆ ꢅf ꢃhe ꢁꢀꢀꢄvꢁl ꢃꢄme ꢅf ꢃhe Vco sꢄgꢆꢁl, ꢅꢀ ꢃhe jꢄꢃꢃeꢀ, ꢄꢆ ꢄꢆꢃegeꢀ mꢅde mꢁy be esꢃꢄmꢁꢃed wꢄꢃh ꢁ
sꢄmple ꢁppꢀꢅxꢄmꢁꢃꢄꢅꢆ ꢄf we ꢁssume ꢃhꢁꢃ ꢃhe lꢅꢂked Vco hꢁs ꢁ ꢂꢅꢆsꢃꢁꢆꢃ phꢁse ꢆꢅꢄse,
Ф
2 (ƒ0), ꢁꢃ ꢅffseꢃs less ꢃhꢁꢆ
ꢃhe lꢅꢅp 3 dB bꢁꢆdwꢄdꢃh ꢁꢆd ꢁ 20 dB peꢀ deꢂꢁde ꢀꢅll ꢅff ꢁꢃ gꢀeꢁꢃeꢀ ꢅffseꢃs. the sꢄmple lꢅꢂked Vco phꢁse ꢆꢅꢄse
ꢁppꢀꢅxꢄmꢁꢃꢄꢅꢆ ꢄs shꢅwꢆ ꢅꢆ ꢃhe lefꢃ ꢅf Fꢄguꢀe 10.
Figure 10. Synthesizer Phase Noise & Jitter
Wꢄꢃh ꢃhꢄs sꢄmplꢄfiꢂꢁꢃꢄꢅꢆ ꢃhe sꢄꢆgle sꢄdebꢁꢆd ꢄꢆꢃegꢀꢁꢃed Vco phꢁse ꢆꢅꢄse,
Ф
2 , ꢄꢆ ꢀꢁds2 ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢄs gꢄveꢆ by
(EQ 9)
wheꢀe
2
Ф
SSB(ƒ0) ꢄs ꢃhe sꢄꢆgle sꢄdebꢁꢆd phꢁse ꢆꢅꢄse ꢄꢆ ꢀꢁds2/Hz ꢄꢆsꢄde ꢃhe lꢅꢅp bꢁꢆdwꢄdꢃh, B ꢄs ꢃhe 3 dB ꢂꢅꢀꢆeꢀ fꢀequeꢆꢂy ꢅf
ꢃhe ꢂlꢅsed lꢅꢅp PLL ꢁꢆd n ꢄs ꢃhe dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅ ꢅf ꢃhe pꢀesꢂꢁleꢀ
the ꢀms phꢁse jꢄꢃꢃeꢀ ꢅf ꢃhe Vco ꢄꢆ ꢀꢁds,
Ф
, ꢀesulꢃs fꢀꢅm ꢃhe pꢅweꢀ sum ꢅf ꢃhe ꢃwꢅ sꢄdebꢁꢆds:
2
√
2Ф
(EQ 10)
Ф =
SSB
Sꢄꢆꢂe ꢃhe sꢄmple ꢄꢆꢃegꢀꢁl ꢅf (EQ 9) ꢄs jusꢃ ꢁ pꢀꢅduꢂꢃ ꢅf ꢂꢅꢆsꢃꢁꢆꢃs, we ꢂꢁꢆ eꢁsꢄly dꢅ ꢃhe ꢄꢆꢃegꢀꢁl ꢄꢆ ꢃhe lꢅg dꢅmꢁꢄꢆ.
Fꢅꢀ exꢁmple ꢄf ꢃhe Vco phꢁse ꢆꢅꢄse ꢄꢆsꢄde ꢃhe lꢅꢅp ꢄs -100 dBꢂ/Hz ꢁꢃ 10 kHz ꢅffseꢃ ꢁꢆd ꢃhe lꢅꢅp bꢁꢆdwꢄdꢃh ꢄs
100 kHz, ꢁꢆd ꢃhe dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅ n=100, ꢃheꢆ ꢃhe ꢄꢆꢃegꢀꢁꢃed sꢄꢆgle sꢄdebꢁꢆd phꢁse ꢆꢅꢄse ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢄꢆ dB ꢄs
Ф Ф
gꢄveꢆ by Ф2dB = 10lꢅg ( 2(ƒ0)Bπ ⁄ n2) = -100 + 50 + 5 - 40 = -85 dBꢀꢁds, ꢅꢀ equꢄvꢁleꢆꢃly = 10-82/20 = 56 uꢀꢁds ꢀms ꢅꢀ
3.2 mꢄllꢄ-degꢀees ꢀms.
Whꢄle ꢃhe phꢁse ꢆꢅꢄse ꢀeduꢂes by ꢁ fꢁꢂꢃꢅꢀ ꢅf 20lꢅgn ꢁfꢃeꢀ dꢄvꢄsꢄꢅꢆ ꢃꢅ ꢃhe ꢀefeꢀeꢆꢂe, ꢃhe jꢄꢃꢃeꢀ ꢄs ꢁ ꢂꢅꢆsꢃꢁꢆꢃ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
15
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
the ꢀms jꢄꢃꢃeꢀ fꢀꢅm ꢃhe phꢁse ꢆꢅꢄse ꢄs ꢃheꢆ gꢄveꢆ by Tjnp = Tref Ф / 2
π
iꢆ ꢃhꢄs exꢁmple ꢄf ꢃhe ꢀefeꢀeꢆꢂe wꢁs 50 MHz, Tref = 20 ꢆseꢂ, ꢁꢆd heꢆꢂe Tjpn = 178 femꢃꢅ-seꢂ.
a ꢆꢅꢀmꢁl 3 sꢄgmꢁ peꢁk-ꢃꢅ-peꢁk vꢁꢀꢄꢁꢃꢄꢅꢆ ꢄꢆ ꢃhe ꢁꢀꢀꢄvꢁl ꢃꢄme ꢃheꢀefꢅꢀe wꢅuld be
if ꢃhe syꢆꢃhesꢄzeꢀ wꢁs ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde, ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢄꢅꢆ ꢅf ꢃhe Vco dꢄvꢄdeꢀ wꢄll dꢅmꢄꢆꢁꢃe ꢃhe jꢄꢃꢃeꢀ. the exꢁꢂꢃ
sꢃꢁꢆdꢁꢀd devꢄꢁꢃꢄꢅꢆ ꢅf ꢃhe dꢄvꢄded Vco sꢄgꢆꢁl wꢄll vꢁꢀy bꢁsed upꢅꢆ ꢃhe mꢅdulꢁꢃꢅꢀ ꢂhꢅseꢆ, hꢅweveꢀ ꢁ ꢃypꢄꢂꢁl mꢅdulꢁꢃꢅꢀ
wꢄll vꢁꢀy by ꢁbꢅuꢃ 3 Vco peꢀꢄꢅds, 4 Vco peꢀꢄꢅds, wꢅꢀsꢃ ꢂꢁse.
if, fꢅꢀ exꢁmple, ꢁ ꢆꢅmꢄꢆꢁl Vco ꢁꢃ 5 GHz ꢄs dꢄvꢄded by 100 ꢃꢅ equꢁl ꢃhe ꢀefeꢀeꢆꢂe ꢁꢃ 50 MHz, ꢃheꢆ ꢃhe wꢅꢀsꢃ ꢂꢁse
dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅs wꢄll vꢁꢀy by 100 4. Heꢆꢂe ꢃhe peꢁk vꢁꢀꢄꢁꢃꢄꢅꢆ ꢄꢆ ꢃhe ꢁꢀꢀꢄvꢁl ꢃꢄmes ꢂꢁused by Δ∑ mꢅdulꢁꢃꢄꢅꢆ ꢅf ꢃhe
fꢀꢁꢂꢃꢄꢅꢆꢁl syꢆꢃhesꢄzeꢀ ꢁꢃ ꢃhe ꢀefeꢀeꢆꢂe wꢄll be
(EQ 11)
iꢆ ꢃhꢄs exꢁmple, t
= 200 ps(104-96)/2 = 800 pseꢂ. if we ꢆꢅꢃe ꢃhꢁꢃ ꢃhe dꢄsꢃꢀꢄbuꢃꢄꢅꢆ ꢅf ꢃhe delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢄꢅꢆ
jΔ∑pk
ꢄs ꢁppꢀꢅxꢄmꢁꢃely gꢁussꢄꢁꢆ, we ꢂꢅuld ꢁppꢀꢅxꢄmꢁꢃe tjΔ∑pk ꢁs ꢁ 3 sꢄgmꢁ jꢄꢃꢃeꢀ, ꢁꢆd heꢆꢂe we ꢂꢅuld esꢃꢄmꢁꢃe ꢃhe ꢀms jꢄꢃꢃeꢀ
ꢅf ꢃhe Δ∑ mꢅdulꢁꢃꢅꢀ ꢁs ꢁbꢅuꢃ 1/3 ꢅf tjΔ∑pk ꢅꢀ ꢁbꢅuꢃ 266 pseꢂ ꢄꢆ ꢃhꢄs exꢁmple.
Heꢆꢂe ꢃhe ꢃꢅꢃꢁl ꢀms jꢄꢃꢃeꢀ T, expeꢂꢃed fꢀꢅm ꢃhe delꢃꢁ sꢄgmꢁ mꢅdulꢁꢃꢄꢅꢆ plus ꢃhe phꢁse ꢆꢅꢄse ꢅf ꢃhe Vco wꢅuld be gꢄveꢆ
j
by ꢃhe ꢀms sum , wheꢀe
(EQ 12)
iꢆ ꢃhꢄs exꢁmple ꢃhe jꢄꢃꢃeꢀ ꢂꢅꢆꢃꢀꢄbuꢃꢄꢅꢆ ꢅf ꢃhe phꢁse ꢆꢅꢄse ꢂꢁlꢂulꢁꢃed pꢀevꢄꢅusly wꢅuld ꢁdd ꢅꢆly 0.764pseꢂ mꢅꢀe jꢄꢃꢃeꢀ ꢁꢃ
ꢃhe ꢀefeꢀeꢆꢂe, heꢆꢂe we see ꢃhꢁꢃ ꢃhe jꢄꢃꢃeꢀ ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢄs dꢅmꢄꢆꢁꢃed by ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢄꢅꢆ.
iꢆ summꢁꢀy, we hꢁve ꢃꢅ expeꢂꢃ ꢁbꢅuꢃ 0.8 ꢆseꢂ ꢅf ꢆꢅꢀmꢁl vꢁꢀꢄꢁꢃꢄꢅꢆ ꢄꢆ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ ꢁꢀꢀꢄvꢁl ꢃꢄmes wheꢆ ꢄꢆ
fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde. iꢆ ꢁddꢄꢃꢄꢅꢆ, lꢅweꢀ Vco fꢀequeꢆꢂꢄes wꢄꢃh hꢄgh ꢀefeꢀeꢆꢂe fꢀequeꢆꢂꢄes wꢄll hꢁve muꢂh lꢁꢀgeꢀ vꢁꢀꢄꢁꢃꢄꢅꢆs.,
fꢅꢀ exꢁmple, ꢁ 1 GHz Vco ꢅpeꢀꢁꢃꢄꢆg ꢁꢃ ꢆeꢁꢀ ꢃhe mꢄꢆꢄmum ꢆꢅmꢄꢆꢁl dꢄvꢄdeꢀ ꢀꢁꢃꢄꢅ ꢅf 36, wꢅuld, ꢁꢂꢂꢅꢀdꢄꢆg ꢃꢅ (EQ 11),
exhꢄbꢄꢃ ꢁbꢅuꢃ 4 ꢆseꢂ ꢅf peꢁk vꢁꢀꢄꢁꢃꢄꢅꢆ ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ, uꢆdeꢀ ꢆꢅꢀmꢁl ꢅpeꢀꢁꢃꢄꢅꢆ. the lꢅꢂk deꢃeꢂꢃ ꢂꢄꢀꢂuꢄꢃ musꢃ ꢆꢅꢃ
ꢂꢅꢆfuse ꢃhꢄs mꢅdulꢁꢃꢄꢅꢆ ꢁs beꢄꢆg ꢅuꢃ ꢅf lꢅꢂk.
PFD Lock Detect
lkd_en (Reg01h<11> tꢁble 12) eꢆꢁbles ꢃhe lꢅꢂk deꢃeꢂꢃ fuꢆꢂꢃꢄꢅꢆs ꢅf ꢃhe HMc701LP6cE.
the Lꢅꢂk Deꢃeꢂꢃ ꢂꢄꢀꢂuꢄꢃ ꢄꢆ ꢃhe HMc701LP6cE plꢁꢂes ꢁ ꢅꢆe shꢅꢃ wꢄꢆdꢅw ꢁꢀꢅuꢆd ꢃhe ꢀefeꢀeꢆꢂe. the ꢅꢆe shꢅꢃ wꢄꢆdꢅw
mꢁy be geꢆeꢀꢁꢃed by eꢄꢃheꢀ ꢁꢆ ꢁꢆꢁlꢅg ꢅꢆe shꢅꢃ ꢂꢄꢀꢂuꢄꢃ ꢅꢀ ꢁ dꢄgꢄꢃꢁl ꢅꢆe shꢅꢃ bꢁsed upꢅꢆ ꢁꢆ ꢄꢆꢃeꢀꢆꢁl ꢀꢄꢆg ꢅsꢂꢄllꢁꢃꢅꢀ ꢃꢄmeꢀ.
cleꢁꢀꢄꢆg lkd_ringosc_mono_select (Reg1Ah<14> tꢁble 36) wꢄll ꢀesulꢃ ꢄꢆ ꢁ ꢆꢅmꢄꢆꢁl 10ꢆseꢂ ‘ꢁꢆꢁlꢅg’ wꢄꢆdꢅw ꢅf fixed
leꢆgꢃh, ꢁs shꢅwꢆ ꢄꢆ Fꢄguꢀe 11. Seꢃꢃꢄꢆg lkd_ringosc_mono_select wꢄll ꢀesulꢃ ꢄꢆ ꢁ vꢁꢀꢄꢁble leꢆgꢃh ’dꢄgꢄꢃꢁl’ wꢄꢆdꢅw. the
dꢄgꢄꢃꢁl ꢅꢆe shꢅꢃ wꢄꢆdꢅw ꢄs ꢂꢅꢆꢃꢀꢅlled by lkd_ringosc_cfg (Reg1Ah<16:15>). the ꢀesulꢃꢄꢆg lꢅꢂk deꢃeꢂꢃ wꢄꢆdꢅw peꢀꢄꢅd ꢄs
ꢃheꢆ geꢆeꢀꢁꢃed by ꢃhe ꢆumbeꢀ ꢅf ꢀꢄꢆg ꢅsꢂꢄllꢁꢃꢅꢀ peꢀꢄꢅds defiꢆed ꢄꢆ lkd_monost_duration Reg1Ah<18:17> (tꢁble 36).
the lꢅꢂk deꢃeꢂꢃ ꢀꢄꢆg ꢅsꢂꢄllꢁꢃꢅꢀ mꢁy be ꢅbseꢀved ꢅꢆ ꢃhe GPo2 pꢅꢀꢃ by seꢃꢃꢄꢆg ringosc_testmode (Reg1Ah<19> tꢁble
36) ꢁꢆd ꢂꢅꢆfiguꢀꢄꢆg ꢃhe gpo_sel<3:0> = 0111 ꢄꢆ (Reg1Bh tꢁble 37). Lꢅꢂk deꢃeꢂꢃ dꢅes ꢆꢅꢃ fuꢆꢂꢃꢄꢅꢆ wheꢆ ꢃhꢄs ꢃesꢃ mꢅde
ꢄs eꢆꢁbled.
lkd_wincnt_max (Reg1Ah<9:0> tꢁble 36) defiꢆes ꢃhe ꢆumbeꢀ ꢅf ꢂꢅꢆseꢂuꢃꢄve ꢂꢅuꢆꢃs ꢅf ꢃhe Vco ꢃhꢁꢃ musꢃ lꢁꢆd ꢄꢆsꢄde
ꢃhe lꢅꢂk deꢃeꢂꢃ wꢄꢆdꢅw ꢃꢅ deꢂlꢁꢀe lꢅꢂk. if fꢅꢀ exꢁmple we seꢃ lkd_wincnt_max = 1000 , ꢃheꢆ ꢃhe Vco ꢁꢀꢀꢄvꢁl wꢅuld
hꢁve ꢃꢅ ꢅꢂꢂuꢀ ꢄꢆsꢄde ꢃhe seleꢂꢃed lꢅꢂk wꢄdꢅw 1000 ꢃꢄmes ꢄꢆ ꢁ ꢀꢅw ꢃꢅ be deꢂlꢁꢀed lꢅꢂked. Wheꢆ lꢅꢂked ꢃhe Lꢅꢂk Deꢃeꢂꢃ
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
16
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
flꢁg ro_lock_detect (Reg1Fh<0> tꢁble 41) wꢄll be seꢃ. a sꢄꢆgle ꢅꢂꢂuꢀꢀeꢆꢂe ꢅuꢃsꢄde ꢅf ꢃhe wꢄꢆdꢅw wꢄll ꢀesulꢃ ꢄꢆ ꢂleꢁꢀꢄꢆg
ꢃhe Lꢅꢂk Deꢃeꢂꢃ flꢁg, ro_lock_detect.
the Lꢅꢂk Deꢃeꢂꢃ flꢁg ro_lock_detect (Reg1Fh<0> tꢁble 41) ꢄs ꢁ ꢀeꢁd ꢅꢆly ꢀegꢄsꢃeꢀ, ꢀeꢁdꢁble fꢀꢅm ꢃhe seꢀꢄꢁl pꢅꢀꢃ. the
Lꢅꢂk Deꢃeꢂꢃ flꢁg ꢄs ꢁlsꢅ ꢅuꢃpuꢃ ꢃꢅ ꢃhe LD_SDO pꢄꢆ ꢁꢂꢂꢅꢀdꢄꢆg ꢃꢅ lkd_to_sdo_always (Reg1Ah<13>) ꢁꢆd lkd_to_sdo_
automux_en (Reg1Ah<12>), bꢅꢃh ꢄꢆ tꢁble 36. Seꢃꢃꢄꢆg lkd_to_sdo_always wꢄll ꢁlwꢁys dꢄsplꢁy ꢃhe Lꢅꢂk Deꢃeꢂꢃ flꢁg
ꢅꢆ LD_DSO. cleꢁꢀꢄꢆg lkd_to_sdo_always ꢁꢆd seꢃꢃꢄꢆg lkd_to_sdo_automux_en wꢄll dꢄsplꢁy ꢃhe Lꢅꢂk Deꢃeꢂꢃ flꢁg ꢅꢆ
LD_SDO exꢂepꢃ wheꢆ ꢁ seꢀꢄꢁl pꢅꢀꢃ ꢀeꢁd ꢄs ꢀequesꢃed, ꢄꢆ whꢄꢂh ꢂꢁse ꢃhe pꢄꢆ ꢀeveꢀꢃs ꢃempꢅꢀꢁꢀꢄly ꢃꢅ ꢃhe Seꢀꢄꢁl Dꢁꢃꢁ ouꢃ
pꢄꢆ, ꢁꢆd ꢀeꢃuꢀꢆs ꢃꢅ ꢃhe lꢅꢂk deꢃeꢂꢃ fuꢆꢂꢃꢄꢅꢆ ꢁfꢃeꢀ ꢃhe ꢀeꢁd ꢄs ꢂꢅmpleꢃed.
Figure 11. Normal Lock Detect Window
Lock Detect with Phase Offset
Wheꢆ ꢅpeꢀꢁꢃꢄꢆg ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢃhe lꢄꢆeꢁꢀꢄꢃy ꢅf ꢃhe ꢂhꢁꢀge pump ꢁꢆd phꢁse deꢃeꢂꢃꢅꢀ ꢁꢀe mꢅꢀe ꢂꢀꢄꢃꢄꢂꢁl ꢃhꢁꢆ ꢄꢆ
ꢄꢆꢃegeꢀ mꢅde. the phꢁse deꢃeꢂꢃꢅꢀ lꢄꢆeꢁꢀꢄꢃy ꢄs wꢅꢀse wheꢆ ꢅpeꢀꢁꢃed wꢄꢃh zeꢀꢅ phꢁse ꢅffseꢃ. Heꢆꢂe ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde
ꢄꢃ ꢄs ꢆeꢂessꢁꢀy ꢃꢅ ꢅffseꢃ ꢃhe phꢁse ꢅf ꢃhe ꢀefeꢀeꢆꢂe ꢁꢆd ꢃhe Vco ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ. iꢆ suꢂh ꢁ ꢂꢁse, fꢅꢀ exꢁmple
wꢄꢃh ꢁꢆ ꢅffseꢃ delꢁy, ꢁs shꢅwꢆ ꢄꢆ Fꢄguꢀe 12, ꢃhe meꢁꢆ phꢁse ꢅf ꢃhe Vco wꢄll ꢁlwꢁys ꢅꢂꢂuꢀ ꢁfꢃeꢀ ꢃhe ꢀefeꢀeꢆꢂe. the
lꢅꢂk deꢃeꢂꢃ ꢂꢄꢀꢂuꢄꢃ wꢄꢆdꢅw ꢂꢁꢆ be mꢁde mꢅꢀe seleꢂꢃꢄve wꢄꢃh ꢁ fixed ꢅffseꢃ delꢁy by seꢃꢃꢄꢆg win_asym_enable ꢁꢆd
win_asym_up_select (Reg1Ah<11> tꢁble 36). Sꢄmꢄlꢁꢀly ꢃhe ꢅffseꢃ ꢂꢁꢆ be ꢄꢆ ꢁdvꢁꢆꢂe ꢅf ꢃhe ꢀefeꢀeꢆꢂe by ꢂleꢁꢀꢄꢆg
win_asym_up_select whꢄle leꢁvꢄꢆg win_asym_enable Reg1Ah<10> seꢃ bꢅꢃh ꢄꢆ tꢁble 36.
Figure 12. Delayed Lock Detect Window
Fꢅꢀ mꢅsꢃ ꢁpplꢄꢂꢁꢃꢄꢅꢆs ꢃhe ꢁꢆꢁlꢅg ꢅꢆe shꢅꢃ wꢄꢆdꢅw ꢄs suffꢄꢂꢄeꢆꢃ. tꢅ deꢃeꢀmꢄꢆe ꢃhe ꢀequꢄꢀed Lꢅꢂk Deꢃeꢂꢃ ꢅꢆe shꢅꢃ
wꢄꢆdꢅw sꢄze:
requꢄꢀed LD oꢆe Shꢅꢃ Wꢄꢆdꢅw = (cP Phꢁse offseꢃ (ꢆs) + 4xtvꢂꢅ) x 1.3
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
17
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Cycle Slip Prevention (CSP)
Wheꢆ ꢂhꢁꢆgꢄꢆg fꢀequeꢆꢂꢄes ꢃhe Vco ꢄs ꢆꢅꢃ yeꢃ lꢅꢂked ꢃꢅ ꢃhe ꢀefeꢀeꢆꢂe ꢁꢆd ꢃhe phꢁse dꢄffeꢀeꢆꢂe ꢁꢃ ꢃhe PFD vꢁꢀꢄes
ꢀꢁpꢄdly ꢅveꢀ ꢁ ꢀꢁꢆge muꢂh gꢀeꢁꢃeꢀ ꢃhꢁꢆ 2π ꢀꢁdꢄꢁꢆs. Sꢄꢆꢂe ꢃhe gꢁꢄꢆ ꢅf ꢃhe PFD vꢁꢀꢄes lꢄꢆeꢁꢀly wꢄꢃh phꢁse up ꢃꢅ 2π,
ꢃhe gꢁꢄꢆ ꢅf ꢂꢅꢆveꢆꢃꢄꢅꢆꢁl PFDs wꢄll ꢂyꢂle fꢀꢅm hꢄgh gꢁꢄꢆ, wheꢆ ꢃhe phꢁse dꢄffeꢀeꢆꢂe ꢁppꢀꢅꢁꢂhes ꢁ mulꢃꢄple ꢅf 2π, ꢃꢅ
lꢅw gꢁꢄꢆ, wheꢆ ꢃhe phꢁse dꢄffeꢀeꢆꢂe ꢄs slꢄghꢃly lꢁꢀgeꢀ ꢃhꢁꢆ ꢁ mulꢃꢄple ꢅf 0 ꢀꢁdꢄꢁꢆs. thꢄs pheꢆꢅmeꢆꢁ ꢄs kꢆꢅwꢆ ꢁs ꢂyꢂle
slꢄppꢄꢆg. cyꢂle slꢄppꢄꢆg ꢂꢁuses ꢃhe pull-ꢄꢆ ꢀꢁꢃe duꢀꢄꢆg ꢃhe lꢅꢂkꢄꢆg phꢁse ꢃꢅ vꢁꢀy ꢂyꢂlꢄꢂꢁlly ꢁs shꢅwꢆ ꢄꢆ ꢃhe ꢀed ꢂuꢀve ꢄꢆ
Fꢄguꢀe 13. cyꢂle slꢄppꢄꢆg ꢄꢆꢂꢀeꢁses ꢃhe ꢃꢄme ꢃꢅ lꢅꢂk ꢃꢅ ꢁ vꢁlue fꢁꢀ gꢀeꢁꢃeꢀ ꢃhꢁꢆ ꢃhꢁꢃ pꢀedꢄꢂꢃed by ꢆꢅꢀmꢁl smꢁll sꢄgꢆꢁl
Lꢁplꢁꢂe ꢁꢆꢁlysꢄs.
the HMc701LP6cE PFD feꢁꢃuꢀes cyꢂle Slꢄp Pꢀeveꢆꢃꢄꢅꢆ (cSP), ꢁꢆ ꢁbꢄlꢄꢃy ꢃꢅ vꢄꢀꢃuꢁlly elꢄmꢄꢆꢁꢃe ꢂyꢂle slꢄppꢄꢆg duꢀꢄꢆg
ꢁꢂquꢄsꢄꢃꢄꢅꢆ. Wheꢆ eꢆꢁbled, ꢃhe cSP feꢁꢃuꢀe esseꢆꢃꢄꢁlly hꢅlds ꢃhe PFD gꢁꢄꢆ ꢁꢃ mꢁxꢄmum uꢆꢃꢄl suꢂh ꢃꢄme ꢁs ꢃhe
fꢀequeꢆꢂy dꢄffeꢀeꢆꢂe ꢄs ꢆeꢁꢀ zeꢀꢅ. cSP ꢁllꢅws sꢄgꢆꢄfiꢂꢁꢆꢃly fꢁsꢃeꢀ lꢅꢂk ꢃꢄmes ꢁs shꢅwꢆ ꢄꢆ Fꢄguꢀe 13. the use ꢅf ꢃhe
cSP feꢁꢃuꢀe ꢄs eꢆꢁbled wꢄꢃh pfds_rstb (Reg01<15> tꢁble 12). the cSP feꢁꢃuꢀe mꢁy be ꢅpꢃꢄmꢄzed fꢅꢀ ꢁ gꢄveꢆ seꢃ
ꢅf PLL dyꢆꢁmꢄꢂs by ꢁdjusꢃꢄꢆg ꢃhe PFD seꢆsꢄꢃꢄvꢄꢃy ꢃꢅ ꢂyꢂle slꢄppꢄꢆg. thꢄs ꢄs ꢁꢂhꢄeved by ꢁdjusꢃꢄꢆg pfds_sat_deltaN
(Reg1C<3:0> tꢁble 38).
cSP wꢄll ꢂꢁuse ꢃhe Vco n dꢄvꢄdeꢀ ꢃꢅ mꢅmeꢆꢃꢁꢀꢄly dꢄvꢄde by ꢁ hꢄgheꢀ ꢅꢀ lꢅweꢀ n vꢁlue ꢄꢆ ꢅꢀdeꢀ ꢃꢅ pull ꢃhe dꢄvꢄded Vco
phꢁse bꢁꢂk ꢃꢅwꢁꢀds ꢃhe ꢀefeꢀeꢆꢂe edge. the mꢁxꢄmum ꢀeꢂꢅmmeꢆded Vco n dꢄvꢄdeꢀ devꢄꢁꢃꢄꢅꢆ ꢄs ꢆꢅ mꢅꢀe ꢃhꢁꢆ 20%
ꢅf ꢃhe ꢃꢁꢀgeꢃ n vꢁlue. Fꢅꢀ exꢁmple, ꢄf n=50 fꢅꢀ ꢃhe ꢃꢁꢀgeꢃ fꢀequeꢆꢂy, ꢃheꢆ ꢃhe cSP Mꢁgꢆꢄꢃude shꢅuld be 10 ꢅꢀ less sꢅ
regꢄsꢃeꢀ 1ch Bꢄꢃs [3:0] wꢅuld be pꢀꢅgꢀꢁmmed ꢃꢅ ah.
iꢆ sꢄꢃuꢁꢃꢄꢅꢆs wheꢀe ꢃhe ꢃꢁꢀgeꢃ n vꢁlue ꢄs lꢅw, fꢅꢀ exꢁmple 36 ꢃhe cSP behꢁvꢄꢅꢀ wꢄll be ꢂꢅmpꢀꢅmꢄsed beꢂꢁuse ꢃhe
mꢄꢆꢄmum Vco dꢄvꢄde vꢁlue ꢄs 32
Figure 13. Cycle Slip Prevention (CSP)
Charge Pump Gain
a sꢄmplꢄfied dꢄꢁgꢀꢁm ꢅf ꢃhe ꢂhꢁꢀge pump ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 14. chꢁꢀge pump up ꢁꢆd dꢅwꢆ gꢁꢄꢆs ꢁꢀe seꢃ by cp_
UPcurrent_sel ꢁꢆd cp_DNcurrent_sel ꢀespeꢂꢃꢄvely (Reg07 tꢁble 18). nꢅꢀmꢁlly ꢃhe ꢀegꢄsꢃeꢀs ꢁꢀe seꢃ ꢃꢅ ꢃhe sꢁme
vꢁlue. Eꢁꢂh ꢅf ꢃhe UP ꢁꢆd Dn ꢂhꢁꢀge pumps ꢂꢅꢆsꢄsꢃ ꢅf 5-bꢄꢃ ꢂhꢁꢀge pumps wꢄꢃh lsb ꢅf 125 µa. the ꢂuꢀꢀeꢆꢃ gꢁꢄꢆ ꢅf ꢃhe
pump, ꢄꢆ amps/ꢀꢁdꢄꢁꢆ, ꢄs equꢁl ꢃꢅ ꢃhe gꢁꢄꢆ seꢃꢃꢄꢆg ꢅf ꢃhꢄs ꢀegꢄsꢃeꢀ dꢄvꢄded by 2π.
Fꢅꢀ exꢁmple ꢄf bꢅꢃh cp_UPcurrent_sel ꢁꢆd cp_DNcurrent_sel ꢁꢀe seꢃ ꢃꢅ ’01000’ ꢃhe ꢅuꢃpuꢃ ꢂuꢀꢀeꢆꢃ ꢅf eꢁꢂh pump wꢄll
be 1ma ꢁꢆd ꢃhe gꢁꢄꢆ Kp = 1ma/2π ꢀꢁdꢄꢁꢆs, ꢅꢀ 159 ua/ꢀꢁd.
Charge Pump Gain Trim
iꢆ mꢅsꢃ ꢁpplꢄꢂꢁꢃꢄꢅꢆs Gꢁꢄꢆ tꢀꢄm ꢄs ꢆꢅꢃ used. Hꢅweveꢀ ꢄꢃ ꢄs ꢁvꢁꢄlꢁble fꢅꢀ speꢂꢄꢁl ꢁpplꢄꢂꢁꢃꢄꢅꢆs.
Eꢁꢂh ꢅf ꢃhe UP ꢁꢆd Dn pumps mꢁy be ꢃꢀꢄmmed sepꢁꢀꢁꢃely ꢃꢅ mꢅꢀe pꢀeꢂꢄse vꢁlues ꢃꢅ ꢄmpꢀꢅve ꢂuꢀꢀeꢆꢃ sꢅuꢀꢂe mꢁꢃꢂhꢄꢆg
ꢅf ꢃhe UP ꢁꢆd Dn vꢁlues, ꢅꢀ ꢃꢅ ꢁllꢅw fiꢆeꢀ ꢂꢅꢆꢃꢀꢅl ꢅf pump gꢁꢄꢆ.
the pump ꢃꢀꢄm ꢂꢅꢆꢃꢀꢅls ꢁꢀe 3-bꢄꢃs, bꢄꢆꢁꢀy weꢄghꢃed fꢅꢀ UP ꢁꢆd Dn, ꢄꢆ cp_UPtrim_sel ꢁꢆd cp_DNtrim_sel ꢀespeꢂꢃꢄvely
(reg 08h tꢁble 19). LSB weꢄghꢃ ꢄs 14.7 ua, x000 = 0 ꢃꢀꢄm, x001 = 14.7 uꢁ ꢁdded ꢃꢀꢄm, x111 = 100ua.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
18
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Charge Pump Phase Offset
Eꢄꢃheꢀ ꢅf ꢃhe UP ꢅꢀ Dn ꢂhꢁꢀge pumps mꢁy hꢁve ꢁ Dc leꢁkꢁge ꢅꢀ “ꢅffseꢃ” ꢁdded. the leꢁkꢁge fꢅꢀꢂes ꢃhe phꢁse deꢃeꢂꢃꢅꢀ
ꢃꢅ ꢅpeꢀꢁꢃe wꢄꢃh ꢁ phꢁse ꢅffseꢃ beꢃweeꢆ ꢃhe ꢀefeꢀeꢆꢂe ꢁꢆd ꢃhe dꢄvꢄded Vco ꢄꢆpuꢃs. iꢃ ꢄs ꢀeꢂꢅmmeꢆded ꢃꢅ ꢅpeꢀꢁꢃe wꢄꢃh
ꢁ phꢁse ꢅffseꢃ wheꢆ usꢄꢆg fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢃꢅ ꢀeduꢂe ꢆꢅꢆ-lꢄꢆeꢁꢀ effeꢂꢃs fꢀꢅm ꢃhe UP ꢁꢆd Dn pump mꢄsmꢁꢃꢂh. Phꢁse
ꢆꢅꢄse ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢄs sꢃꢀꢅꢆgly ꢁffeꢂꢃed by ꢂhꢁꢀge pump ꢅffseꢃ.
Dc leꢁkꢁge ꢅꢀ “ꢅffseꢃ” mꢁy be ꢁdded ꢃꢅ ꢃhe UP ꢅꢀ Dn pumps usꢄꢆg cp_UPoffset_sel ꢁꢆd cp_DNoffset_sel (Reg08
tꢁble 19). these ꢁꢀe 4 bꢄꢃ ꢀegꢄsꢃeꢀs wꢄꢃh 28.7ua LSB. Mꢁxꢄmum ꢅffseꢃ ꢄs 430ua.
as ꢁꢆ exꢁmple, ꢄf ꢃhe mꢁꢄꢆ pump gꢁꢄꢆ wꢁs seꢃ ꢁꢃ 1ma, ꢁꢆ ꢅffseꢃ ꢅf 373ua wꢅuld ꢀepꢀeseꢆꢃ ꢁ phꢁse ꢅffseꢃ ꢅf ꢁbꢅuꢃ
(392/1000)*360 = 133 degꢀees. Fꢅꢀ besꢃ speꢂꢃꢀꢁl peꢀfꢅꢀmꢁꢆꢂe ꢄꢆ Fꢀꢁꢂꢃꢄꢅꢆꢁl Mꢅde ꢃhe leꢁkꢁge ꢂuꢀꢀeꢆꢃ shꢅuld be
pꢀꢅgꢀꢁmmed ꢃꢅ:
requꢄꢀed Leꢁkꢁge cuꢀꢀeꢆꢃ (µa) = (2.5E-9 + 4xtvꢂꢅ) x Fꢂꢅmpꢁꢀꢄsꢅꢆ (Hz) x cP ꢂuꢀꢀeꢆꢃ (µa)
Leakage Current should never exceed 25% of the programmed CP current.
Figure 14. Charge Pump Gain, Trim and Phase Offset Control
Frequency Programming
the HMc701LP6cE ꢂꢁꢆ ꢅpeꢀꢁꢃe ꢄꢆ eꢄꢃheꢀ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢅꢀ ꢄꢆꢃegeꢀ mꢅde. iꢆ ꢄꢆꢃegeꢀ mꢅde ꢅf ꢅpeꢀꢁꢃꢄꢅꢆ ꢃhe delꢃꢁ
sꢄgmꢁ mꢅdulꢁꢃꢅꢀ ꢄs dꢄsꢁbled. Fꢀequeꢆꢂy pꢀꢅgꢀꢁmmꢄꢆg ꢁꢆd mꢅde ꢂꢅꢆꢃꢀꢅl ꢄs desꢂꢀꢄbed belꢅw.
Fractional Frequency
the fꢀꢁꢂꢃꢄꢅꢆꢁl fꢀequeꢆꢂy syꢆꢃhesꢄzeꢀ, wheꢆ ꢅpeꢀꢁꢃꢄꢆg ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde, ꢂꢁꢆ lꢅꢂk ꢃꢅ fꢀequeꢆꢂꢄes whꢄꢂh ꢁꢀe fꢀꢁꢂꢃꢄꢅꢆꢁl
mulꢃꢄples ꢅf ꢃhe ꢀefeꢀeꢆꢂe fꢀequeꢆꢂy.
Fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢄs ꢃhe defꢁulꢃ mꢅde. tꢅ ꢀuꢆ ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde eꢆsuꢀe ꢃhꢁꢃ dsm_integer_mode reg12h<3> tꢁble 29
ꢄs ꢂleꢁꢀ ꢁꢆd dsm_rstb reg01<13> tꢁble 12). theꢆ pꢀꢅgꢀꢁm ꢃhe fꢀequeꢆꢂy ꢁs explꢁꢄꢆed belꢅw:
the ꢅuꢃpuꢃ fꢀequeꢆꢂy ꢅf ꢃhe syꢆꢃhesꢄzeꢀ ꢄs gꢄveꢆ by, fvco, wheꢀe
Fractional Frequency
(EQ 13)
of VCO
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
19
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
wheꢀe
Nint
ꢄs ꢃhe ꢄꢆꢃegeꢀ dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅ, ꢁꢆ ꢄꢆꢃegeꢀ ꢆumbeꢀ beꢃweeꢆ 36 ꢁꢆd 65,533
(dsm_intg (Reg0Fh tꢁble 26))
Nfrac
R
ꢄs ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl pꢁꢀꢃ, ꢁ ꢆumbeꢀ fꢀꢅm 1 ꢃꢅ 224 (dsm_frac Reg10h tꢁble 27)
ꢄs ꢃhe ꢀefeꢀeꢆꢂe pꢁꢃh dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅ, (rfp_div_ratio Reg03h<13:0> tꢁble 14)
ꢄs ꢃhe fꢀequeꢆꢂy ꢅf ꢃhe ꢂꢀysꢃꢁl ꢅsꢂꢄllꢁꢃꢅꢀ ꢄꢆpuꢃ (XSin ꢅꢀ XrEF Fꢄguꢀe 4)
fxtal
as ꢁꢆ Exꢁmple:
fxtal
R
= 50 MHz
= 1
fref
Nint
Nfrac
= 50 MHz
= 46
= 1
(EQ 14)
iꢆ ꢃhꢄs exꢁmple ꢃhe ꢅuꢃpuꢃ fꢀequeꢆꢂy ꢅf 2,300,000,002.98 Hz ꢄs ꢁꢂhꢄeved by pꢀꢅgꢀꢁmmꢄꢆg ꢃhe 16-bꢄꢃ bꢄꢆꢁꢀy vꢁlue ꢅf
46d = 2Eh = 0000 0000 0010 1110 ꢄꢆꢃꢅ dsm_intg.
Sꢄmꢄlꢁꢀly ꢃhe 24-bꢄꢃ bꢄꢆꢁꢀy vꢁlue ꢅf ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl wꢅꢀd ꢄs wꢀꢄꢃꢃeꢆ ꢄꢆꢃꢅ dsm_frac,
1d = 000 001h = 0000 0000 0000 0000 0000 0001
Example 2: Seꢃ ꢃhe ꢅuꢃpuꢃ ꢃꢅ 4.600 025 GHz usꢄꢆg ꢁ 100 MHz ꢀefeꢀeꢆꢂe, r=2.
Fꢄꢆd ꢃhe ꢆeꢁꢀesꢃ ꢄꢆꢃegeꢀ vꢁlue, nꢄꢆꢃ, nꢄꢆꢃ = 92, fint = 4.600 000 GHz
thꢄs leꢁves ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl pꢁꢀꢃ ꢃꢅ be ffꢀꢁꢂ =25 kHz
(EQ 15)
Sꢄꢆꢂe Nfrac musꢃ be ꢁꢆ ꢄꢆꢃegeꢀ ꢆumbeꢀ, ꢃhe ꢁꢂꢃuꢁl fꢀꢁꢂꢃꢄꢅꢆꢁl fꢀequeꢆꢂy wꢄll be 25,001.17 Hz, ꢁꢆ eꢀꢀꢅꢀ ꢅf 1.17 Hz.
Heꢀe we pꢀꢅgꢀꢁm ꢃhe 16-bꢄꢃ nꢄꢆꢃ = 92d = 5ch = 0000 0000 0101 1100 ꢁꢆd
ꢃhe 24-bꢄꢃ nfꢀꢁꢂ = 8389d = 20c5h = 0000 0010 0000 1100 0101
iꢆ ꢁddꢄꢃꢄꢅꢆ ꢃꢅ ꢃhe ꢁbꢅve fꢀequeꢆꢂy pꢀꢅgꢀꢁmmꢄꢆg wꢅꢀds, ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde musꢃ be eꢆꢁbled usꢄꢆg ꢃhe fꢀꢁꢂ ꢀegꢄsꢃeꢀ.
oꢃheꢀ DSM ꢂꢅꢆfiguꢀꢁꢃꢄꢅꢆ ꢀegꢄsꢃeꢀs shꢅuld be seꢃ ꢃꢅ ꢃhe ꢀeꢂꢅmmeꢆded vꢁlues. regꢄsꢃeꢀ seꢃup files ꢁꢀe ꢁvꢁꢄlꢁble ꢅꢆ
ꢀequesꢃ.
Integer Frequency
the syꢆꢃhesꢄzeꢀ ꢄs ꢂꢁpꢁble ꢅf ꢅpeꢀꢁꢃꢄꢆg ꢄꢆ ꢄꢆꢃegeꢀ mꢅde. iꢆ ꢄꢆꢃegeꢀ mꢅde ꢃhe dꢄgꢄꢃꢁl Δ∑ mꢅdulꢁꢃꢅꢀ ꢄs ꢆꢅꢀmꢁlly shuꢃ
ꢅff ꢁꢆd ꢃhe dꢄvꢄsꢄꢅꢆ ꢀꢁꢃꢄꢅ ꢅf ꢃhe Vco dꢄvꢄdeꢀ ꢄs seꢃ ꢁꢃ ꢁ fixed vꢁlue. tꢅ ꢀuꢆ ꢄꢆ ꢄꢆꢃegeꢀ mꢅde seꢃ dsm_integer_mode
(Reg12h<3> tꢁble 29) ꢁꢆd ꢂleꢁꢀ dsm_rstb (Reg01h<13> tꢁble 12). theꢆ pꢀꢅgꢀꢁm ꢃhe ꢄꢆꢃegeꢀ pꢅꢀꢃꢄꢅꢆ ꢅf ꢃhe fꢀequeꢆꢂy,
N
INT, ꢁs explꢁꢄꢆed by (EQ 13), ꢄgꢆꢅꢀꢄꢆg ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl pꢁꢀꢃ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
20
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Frequency Hopping Trigger
if ꢃhe syꢆꢃhesꢄzeꢀ ꢄs ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde, ꢁ wꢀꢄꢃe ꢃꢅ ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl fꢀequeꢆꢂy ꢀegꢄsꢃeꢀ, Reg10h tꢁble 27, wꢄll ꢄꢆꢄꢃꢄꢁꢃe ꢃhe
fꢀequeꢆꢂy hꢅp ꢅꢆ ꢃhe fꢁllꢄꢆg edge ꢅf ꢃhe 31sꢃ ꢂlꢅꢂk edge ꢅf ꢃhe seꢀꢄꢁl pꢅꢀꢃ wꢀꢄꢃe (see Fꢄguꢀe 19).
if ꢃhe ꢄꢆꢃegeꢀ fꢀequeꢆꢂy ꢀegꢄsꢃeꢀ, Reg0Fh tꢁble 26, ꢄs wꢀꢄꢃꢃeꢆ wheꢆ ꢄꢆ fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅde ꢃhe ꢄꢆfꢅꢀmꢁꢃꢄꢅꢆ wꢄll be buffeꢀed
ꢁꢆd ꢅꢆly exeꢂuꢃed wheꢆ ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl fꢀequeꢆꢂy ꢀegꢄsꢃeꢀ ꢄs wꢀꢄꢃꢃeꢆ.
if ꢃhe syꢆꢃhesꢄzeꢀ ꢄs ꢄꢆ ꢄꢆꢃegeꢀ mꢅde, ꢁ wꢀꢄꢃe ꢃꢅ ꢃhe ꢄꢆꢃegeꢀ fꢀequeꢆꢂy ꢀegꢄsꢃeꢀ, Reg0Fh tꢁble 26, wꢄll ꢄꢆꢄꢃꢄꢁꢃe ꢃhe
fꢀequeꢆꢂy hꢅp ꢅꢆ ꢃhe fꢁllꢄꢆg edge ꢅf ꢃhe 31sꢃ ꢂlꢅꢂk edge ꢅf ꢃhe seꢀꢄꢁl pꢅꢀꢃ wꢀꢄꢃe (see Fꢄguꢀe 19).
Power On Reset (POR)
nꢅꢀmꢁlly ꢁll lꢅgꢄꢂ ꢂells ꢄꢆ ꢃhe HMc701LP6cE ꢁꢀe ꢀeseꢃ wheꢆ ꢃhe devꢄꢂe dꢄgꢄꢃꢁl pꢅweꢀ supply, DVDD, ꢄs ꢁpplꢄed. thꢄs
ꢄs ꢀefeꢀꢀed ꢃꢅ ꢁs Pꢅweꢀ oꢆ reseꢃ, ꢅꢀ jusꢃ Por. Por ꢆꢅꢀmꢁlly ꢃꢁkes ꢁbꢅuꢃ 500us ꢁfꢃeꢀ ꢃhe DVDD supply exꢂeeds 1.5V,
guꢁꢀꢁꢆꢃeed ꢃꢅ be ꢀeseꢃ ꢄꢆ 1mseꢂ. oꢆꢂe ꢃhe DVDD supply exꢂeeds 1.5V, ꢃhe Por wꢄll ꢆꢅꢃ ꢀeseꢃ ꢃhe dꢄgꢄꢃꢁl ꢁgꢁꢄꢆ uꢆless
ꢃhe supply dꢀꢅps belꢅw 100mV.
Soft Reset
the SPi ꢀegꢄsꢃeꢀs mꢁy ꢁlsꢅ be sꢅfꢃ ꢀeseꢃ by ꢁꢆ SPi wꢀꢄꢃe ꢃꢅ sꢃꢀꢅbe global_swrst_regs (Reg00h<0> tꢁble 11).
all ꢅꢃheꢀ dꢄgꢄꢃꢁl, ꢄꢆꢂludꢄꢆg ꢃhe fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢅꢀ, mꢁy be ꢀeseꢃ wꢄꢃh ꢁꢆ SPi wꢀꢄꢃe ꢃꢅ sꢃꢀꢅbe global_swrst_dig
(Reg00h<1> tꢁble 11).
Hardware Reset
the SPi ꢀegꢄsꢃeꢀs mꢁy ꢁlsꢅ be hꢁꢀdwꢁꢀe ꢀeseꢃ by hꢅldꢄꢆg rStB, pꢄꢆ 19, lꢅw.
Power Down
the HMc701LP6cE mꢁy be pꢅweꢀed dꢅwꢆ by wꢀꢄꢃꢄꢆg ꢁ zeꢀꢅ ꢃꢅ Reg01h tꢁble 12. iꢆ pꢅweꢀ dꢅwꢆ sꢃꢁꢃe ꢃhe
HMc701LP6cE shꢅuld dꢀꢁw less ꢃhꢁꢆ 10ua. iꢃ shꢅuld be ꢆꢅꢃed ꢃhꢁꢃ Reg01h ꢄs ꢃhe Eꢆꢁble ꢁꢆd reseꢃ regꢄsꢃeꢀ whꢄꢂh
ꢂꢅꢆꢃꢀꢅls 16 sepꢁꢀꢁꢃe fuꢆꢂꢃꢄꢅꢆs ꢄꢆ ꢃhe ꢂhꢄp. Depeꢆdꢄꢆg upꢅꢆ ꢃhe desꢄꢀed mꢅde ꢅf ꢅpeꢀꢁꢃꢄꢅꢆ ꢅf ꢃhe ꢂhꢄp, ꢆꢅꢃ ꢁll ꢅf ꢃhe
fuꢆꢂꢃꢄꢅꢆs mꢁy be eꢆꢁbled wheꢆ ꢄꢆ ꢅpeꢀꢁꢃꢄꢅꢆ. Heꢆꢂe pꢅweꢀ up ꢅf ꢃhe ꢂhꢄp ꢀequꢄꢀes ꢁ seleꢂꢃꢄve wꢀꢄꢃe ꢃꢅ Reg01 bꢄꢃs. aꢆ
eꢁsy wꢁy ꢃꢅ ꢀeꢃuꢀꢆ ꢃhe ꢂhꢄp ꢃꢅ ꢄꢃs pꢀꢄꢅꢀ sꢃꢁꢃe ꢁfꢃeꢀ ꢁ pꢅweꢀ dꢅwꢆ ꢄs ꢃꢅ fiꢀsꢃ ꢀeꢁd Reg01h ꢁꢆd sꢁve ꢃhe sꢃꢁꢃe, ꢃheꢆ wꢀꢄꢃe ꢁ
zeꢀꢅ ꢃꢅ Reg01h fꢅꢀ ꢀeseꢃ ꢁꢆd ꢃheꢆ sꢄmply ꢀewꢀꢄꢃe ꢃhe pꢀevꢄꢅus vꢁlue ꢃꢅ ꢀesꢃꢅꢀe ꢃhe ꢂhꢄp ꢃꢅ ꢃhe desꢄꢀed ꢅpeꢀꢁꢃꢄꢆg mꢅde.
CW Sweeper Mode
the HMc701LP6cE feꢁꢃuꢀes ꢁ buꢄlꢃ ꢄꢆ fꢀequeꢆꢂy sweepeꢀ fuꢆꢂꢃꢄꢅꢆ. thꢄs fuꢆꢂꢃꢄꢅꢆ suppꢅꢀꢃs exꢃeꢀꢆꢁl ꢅꢀ ꢁuꢃꢅmꢁꢃꢄꢂ
ꢃꢀꢄggeꢀed sweeps. the mꢁxꢄmum sweep ꢀꢁꢆge ꢄs lꢄmꢄꢃed ꢃꢅ 255 x Fxꢃꢁl/r. Fꢅꢀ exꢁmple, wꢄꢃh ꢁ 25 MHz ꢂꢅmpꢁꢀꢄsꢅꢆ
fꢀequeꢆꢂy, ꢃhe mꢁxꢄmum sweep ꢀꢁꢆge ꢄs 6375 MHz. the sꢃꢁꢀꢃ ꢁꢆd eꢆd fꢀequeꢆꢂy pꢅꢄꢆꢃs musꢃ be wꢄꢃhꢄꢆ 6375 MHz ꢅf
ꢅꢆe ꢁꢆꢅꢃheꢀ. Fꢅꢀ sweep ꢅpeꢀꢁꢃꢄꢅꢆ ꢃhe Delꢃꢁ-Sꢄgmꢁ Mꢅdulꢁꢃꢅꢀ mꢅde shꢅuld be Feed Fꢅꢀwꢁꢀd (regꢄsꢃeꢀ 12h Bꢄꢃs [9:8]
= 11) ꢅꢃheꢀwꢄse dꢄsꢂꢅꢆꢃꢄꢆuꢄꢃꢄes mꢁy ꢅꢂꢂuꢀ wheꢆ ꢂꢀꢅssꢄꢆg ꢄꢆꢃegeꢀ-n bꢅuꢆdꢁꢀꢄes (hꢁꢀmꢅꢆꢄꢂ mulꢃꢄples ꢅf ꢃhe ꢂꢅmpꢁꢀꢄsꢅꢆ
fꢀequeꢆꢂy).
Sweepeꢀ Mꢅdes ꢄꢆꢂlude:
ꢁ. 2-Wꢁy Sweep Mꢅde: ꢁlꢃeꢀꢆꢁꢃꢄꢆg pꢅsꢄꢃꢄve ꢁꢆd ꢆegꢁꢃꢄve fꢀequeꢆꢂy ꢀꢁmps.
b. 1-Wꢁy Sweep Mꢅde
ꢂ. Sꢄꢆgle Sꢃep rꢁmp Mꢅde
applꢄꢂꢁꢃꢄꢅꢆs ꢄꢆꢂlude ꢃesꢃ ꢄꢆsꢃꢀumeꢆꢃꢁꢃꢄꢅꢆ, FMcW seꢆsꢅꢀs, ꢁuꢃꢅmꢅꢃꢄve ꢀꢁdꢁꢀs ꢁꢆd ꢅꢃheꢀs. the pꢁꢀꢁmeꢃeꢀs ꢅf ꢃhe
sweep fuꢆꢂꢃꢄꢅꢆ ꢁꢀe ꢄllusꢃꢀꢁꢃed ꢄꢆ Fꢄguꢀe 15.
the sweep geꢆeꢀꢁꢃꢅꢀ ꢄs eꢆꢁbled wꢄꢃh ramp_enable ꢄꢆ (Reg14h<1> tꢁble 30). the sweep fuꢆꢂꢃꢄꢅꢆ ꢂyꢂles ꢃhꢀꢅugh ꢁ
seꢀꢄes ꢅf dꢄsꢂꢀeꢃe fꢀequeꢆꢂy vꢁlues, whꢄꢂh mꢁy be
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responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
ꢁ. Sꢃepped by ꢁꢆ ꢁuꢃꢅmꢁꢃꢄꢂ sequeꢆꢂeꢀ, ꢅꢀ
b. Sꢄꢆgle sꢃepped by ꢄꢆdꢄvꢄduꢁl ꢃꢀꢄggeꢀs ꢄꢆ Sꢄꢆgle Sꢃep Mꢅde.
tꢀꢄggeꢀꢄꢆg ꢅf eꢁꢂh sweep, ꢅꢀ sꢃep, mꢁy be ꢂꢅꢆfiguꢀed ꢃꢅ ꢅpeꢀꢁꢃe:
ꢁ. Vꢄꢁ ꢁ seꢀꢄꢁl pꢅꢀꢃ wꢀꢄꢃe ꢃꢅ Reg14h<2> ramp_trigg (ꢄf reg 14h<2> = 0 )
b. auꢃꢅmꢁꢃꢄꢂꢁlly geꢆeꢀꢁꢃed ꢄꢆꢃeꢀꢆꢁlly,
ꢂ. tꢀꢄggeꢀed vꢄꢁ ttL ꢄꢆpuꢃ ꢅꢆ GPo3 reg14h<5> = 1.
Sweep pꢁꢀꢁmeꢃeꢀs ꢁꢀe seꢃ ꢁs fꢅllꢅws:
iꢆꢄꢃꢄꢁl Fꢀequeꢆꢂy, fo = cuꢀꢀeꢆꢃ fꢀequeꢆꢂy vꢁlue ꢅf ꢃhe syꢆꢃhesꢄzeꢀ, (EQ 12)
Fꢄꢆꢁl Fꢀequeꢆꢂy, ff = Fꢀequeꢆꢂy ꢅf ꢃhe syꢆꢃhesꢄzeꢀ ꢁꢃ ꢃhe eꢆd ꢅf ꢃhe ꢀꢁmp
the fꢀequeꢆꢂy sꢃep sꢄze whꢄle ꢀꢁmpꢄꢆg ꢄs ꢂꢅꢆꢃꢀꢅlled by rampstep, (Reg15h tꢁble 31).
Fꢀequeꢆꢂy Sꢃep Sꢄze Δƒstep = rampstep • fxtal / 224
R
•
wheꢀe r ꢄs ꢃhe vꢁlue ꢅf ꢃhe ꢀefeꢀeꢆꢂe dꢄvꢄdeꢀ (rfp_div_ratio in tꢁble 14)
cleꢁꢀꢄꢆg ꢅꢀ seꢃꢃꢄꢆg ramp_startdir_dn, (Reg14h<4> tꢁble 30), seꢃs ꢃhe ꢄꢆꢄꢃꢄꢁl ꢀꢁmp dꢄꢀeꢂꢃꢄꢅꢆ ꢃꢅ be ꢄꢆꢂꢀeꢁsꢄꢆg ꢅꢀ
deꢂꢀeꢁsꢄꢆg ꢄꢆ fꢀequeꢆꢂy ꢀespeꢂꢃꢄvely. Seꢃꢃꢄꢆg ramp_singledir (Reg14h<7> tꢁble 30), ꢀesꢃꢀꢄꢂꢃs ꢃhe dꢄꢀeꢂꢃꢄꢅꢆ ꢅf ꢃhe
sweep ꢃꢅ ꢃhe ꢄꢆꢄꢃꢄꢁl sweep dꢄꢀeꢂꢃꢄꢅꢆ ꢅꢆly.
the sweepeꢀ ꢃꢄmebꢁse Tref ꢄs ꢃhe peꢀꢄꢅd ꢅf ꢃhe dꢄvꢄded ꢀefeꢀeꢆꢂe, fPFD, ꢁꢃ ꢃhe phꢁse deꢃeꢂꢃꢅꢀ Tref
the ꢃꢅꢃꢁl ꢆumbeꢀ ꢅf ꢀꢁmp sꢃeps ꢃꢁkeꢆ ꢄꢆ ꢁ sꢄꢆgle sweep ꢄs gꢄveꢆ by ꢀꢁmp_sꢃeps_ꢆumbeꢀ ꢄꢆ reg16h tꢁble 32.
the ꢃꢅꢃꢁl ꢃꢄme ꢃꢅ ꢀꢁmp fꢀꢅm fo ꢃꢅ ff ꢄs gꢄveꢆ by Tramp = Tref • ramp_steps_number
CW Sweeper Mode (Continued)
the fiꢆꢁl ꢀꢁmp fꢀequeꢆꢂy, ff, ꢄs gꢄveꢆ by ƒƒ = ƒi + Δƒstep • ramp_steps_number
Sweepeꢀ ꢁꢂꢃꢄꢅꢆ ꢁꢃ ꢃhe eꢆd ꢅf sweep depeꢆds upꢅꢆ ꢃhe mꢅde ꢅf ꢃhe sweep:
ꢁ. Wꢄꢃh bꢅꢃh ramp_singledir ꢁꢆd ramp_repeat_en dꢄsꢁbled, ꢁꢃ ꢃhe eꢆd ꢅf ꢃhe ꢀꢁmp ꢃꢄme, Tramp
,
ꢃhe sweepeꢀ wꢄll dwell ꢁꢃ ꢃhe fiꢆꢁl fꢀequeꢆꢂy ff, uꢆꢃꢄl ꢁ ꢆew ꢃꢀꢄggeꢀ ꢄs ꢀeꢂeꢄved. the ꢆexꢃ ꢃꢀꢄggeꢀ wꢄll
ꢀeveꢀse ꢃhe ꢂuꢀꢀeꢆꢃ sequeꢆꢂe, sꢃꢁꢀꢃꢄꢆg fꢀꢅm ff, ꢁꢆd sꢃeppꢄꢆg bꢁꢂk ꢃꢅ fo. odd ꢃꢀꢄggeꢀs wꢄll ꢀꢁmp ꢄꢆ ꢃhe
sꢁme dꢄꢀeꢂꢃꢄꢅꢆ ꢁs ꢃhe ꢄꢆꢄꢃꢄꢁl ꢀꢁmp, eveꢆ ꢃꢀꢄggeꢀs wꢄll ꢀꢁmp ꢄꢆ ꢃhe ꢅppꢅsꢄꢃe dꢄꢀeꢂꢃꢄꢅꢆ.
b. wꢄꢃh ramp_singledir eꢆꢁbled ꢁꢆd ramp_repeat_en dꢄsꢁbled, ꢁꢃ ꢃhe eꢆd ꢅf ꢃhe ꢀꢁmp ꢃꢄme, Tramp
,
ꢃhe sweepeꢀ wꢄll dwell ꢁꢃ ꢃhe fiꢆꢁl fꢀequeꢆꢂy ff, uꢆꢃꢄl ꢁ ꢆew ꢃꢀꢄggeꢀ ꢄs ꢀeꢂeꢄved. the seꢂꢅꢆd ꢃꢀꢄggeꢀ
wꢄll hꢅp ꢃhe syꢆꢃhesꢄzeꢀ bꢁꢂk ꢃꢅ ꢃhe ꢄꢆꢄꢃꢄꢁl fꢀequeꢆꢂy, fo. the ꢃhꢄꢀd ꢃꢀꢄggeꢀ wꢄll ꢀesꢃꢁꢀꢃ ꢃhe sweep fꢀꢅm
fo. Heꢆꢂe ꢁll ꢅdd ꢆumbeꢀed ꢃꢀꢄggeꢀs wꢄll sꢃꢁꢀꢃ ꢁ ꢆew ꢀꢁmp ꢄꢆ ꢃhe sꢁme dꢄꢀeꢂꢃꢄꢅꢆ ꢁs ꢃhe ꢄꢆꢄꢃꢄꢁl ꢀꢁmp,
eveꢆ ꢆumbeꢀed ꢃꢀꢄggeꢀs wꢄll hꢅp ꢃhe syꢆꢃhesꢄzeꢀ fꢀꢅm ꢃhe ꢂuꢀꢀeꢆꢃ fꢀequeꢆꢂy ꢃꢅ fo , wheꢀe ꢄꢃ wꢄll wꢁꢄꢃ
fꢅꢀ ꢁ ꢃꢀꢄggeꢀ ꢃꢅ sꢃꢁꢀꢃ ꢁ sweep.
Ramp Busy
iꢆ ꢁll ꢃypes ꢅf sweeps ramp_busy wꢄll ꢄꢆdꢄꢂꢁꢃe ꢁꢆ ꢁꢂꢃꢄve sweep ꢁꢆd wꢄll sꢃꢁy hꢄgh beꢃweeꢆ ꢃhe 1sꢃ ꢁꢆd ꢆꢃh ꢀꢁmp sꢃep.
ramp_busy mꢁy be mꢅꢆꢄꢃꢅꢀed ꢅꢆe ꢅf ꢃwꢅ wꢁys. ramp_busy ꢄs ꢀeꢁdꢁble vꢄꢁ ꢀeꢁd ꢅꢆly ꢀegꢄsꢃeꢀ Reg1Fh<5> tꢁble 41.
ramp_busy mꢁy ꢁlsꢅ be mꢅꢆꢄꢃꢅꢀed ꢅꢆ GPo2, hꢁꢀdwꢁꢀe pꢄꢆ 24, by seꢃꢃꢄꢆg Reg1Bh<3:0> =8h tꢁble 37.
Autosweep Mode
the auꢃꢅsweep mꢅde ꢄs sꢄmꢄlꢁꢀ ꢃꢅ Fꢄguꢀe 15 exꢂepꢃ ꢃhꢁꢃ ꢅꢆꢂe sꢃꢁꢀꢃed, ꢃꢀꢄggeꢀs ꢁꢀe ꢆꢅꢃ ꢀequꢄꢀed. oꢆꢂe eꢆꢁbled, (ramp_
repeat_en=1 Reg14h<3> tꢁble 30) ꢃhe auꢃꢅsweep mꢅde ꢄꢆꢄꢃꢄꢁꢃes ꢃhe fiꢀsꢃ ꢃꢀꢄggeꢀ, sꢃeps ꢆ ꢃꢄmes, ꢅꢆe sꢃep peꢀ ꢀef ꢂlꢅꢂk
ꢂyꢂle, ꢁꢆd ꢃheꢆ wꢁꢄꢃs fꢅꢀ ꢃhe pꢀꢅgꢀꢁmmed dwell peꢀꢄꢅd ꢁꢆd ꢁuꢃꢅmꢁꢃꢄꢂꢁlly ꢃꢀꢄggeꢀs ꢃhe ꢀꢁmp ꢄꢆ ꢃhe ꢅppꢅsꢄꢃe dꢄꢀeꢂꢃꢄꢅꢆ.
the sweep pꢀꢅꢂess ꢂꢅꢆꢃꢄꢆues ꢁlꢃeꢀꢆꢁꢃꢄꢆg sweep dꢄꢀeꢂꢃꢄꢅꢆs uꢆꢃꢄl dꢄsꢁbled. dwell_time (Reg17h tꢁble 33) ꢂꢅꢆꢃꢀꢅls ꢃhe
ꢆumbeꢀ ꢅf Tref peꢀꢄꢅds ꢃꢅ wꢁꢄꢃ ꢁꢃ ꢃhe eꢆd ꢅf ꢃhe ꢀꢁmp befꢅꢀe ꢁuꢃꢅmꢁꢃꢄꢂꢁlly ꢀeꢃꢀꢄggeꢀꢄꢆg ꢁ ꢆew sweep.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
2-Way Sweeps
if ramp_repeat_en (Reg14h<3> tꢁble 30) ꢄs ꢂleꢁꢀed, ꢃheꢆ ꢃhe ꢀꢁmps ꢁꢀe ꢃꢀꢄggeꢀed by
ꢁ. Wꢀꢄꢃꢄꢆg ꢃꢅ ramp_trigg (Reg14h<2> tꢁble 30), ꢄf bꢄꢃ <2> = 0, ꢅꢀ
b. by ꢀꢄsꢄꢆg edge ttL sꢄgꢆꢁl ꢄꢆpuꢃ ꢅꢆ GPo3, ꢄf ramp_trig_ext_en ꢄs seꢃ, ꢁꢆd GPo3 ꢄs eꢆꢁbled.
all fuꢆꢂꢃꢄꢅꢆs ꢁꢀe ꢃhe sꢁme ꢄꢆ Fꢄguꢀe 15 fꢅꢀ auꢃꢅsweep ꢅꢀ 2-Wꢁy tꢀꢄggeꢀed sweeps, ꢃhe ꢅꢆly dꢄffeꢀeꢆꢂe ꢄs ꢃhe ꢃꢀꢄggeꢀ
sꢅuꢀꢂe ꢄs geꢆeꢀꢁꢃed ꢄꢆꢃeꢀꢆꢁlly fꢅꢀ ꢁuꢃꢅsweep, ꢁꢆd ꢄs ꢄꢆpuꢃ vꢄꢁ seꢀꢄꢁl pꢅꢀꢃ ꢅꢀ GPo3 fꢅꢀ ꢃꢀꢄggeꢀed sweeps. Sweep_busy
wꢄll gꢅ hꢄgh ꢁꢃ ꢃhe sꢃꢁꢀꢃ ꢅf eveꢀy ꢀꢁmp ꢁꢆd sꢃꢁy hꢄgh uꢆꢃꢄl ꢃhe ꢆꢃh sꢃep ꢄꢆ ꢃhe ꢀꢁmp.
Figure 15. 2-Way Sweep Control via Trigger
Triggered 1-Way Sweeps
1-Wꢁy sweeps ꢁꢀe shꢅwꢆ ꢄꢆFꢄguꢀe 16.
Uꢆlꢄke 2-Wꢁy sweeps, 1-Wꢁy sweeps ꢀequꢄꢀe ꢃhꢁꢃ ꢃhe Vco hꢅp bꢁꢂk ꢃꢅ ꢃhe sꢃꢁꢀꢃ fꢀequeꢆꢂy ꢁfꢃeꢀ ꢃhe dwell peꢀꢄꢅd.
tꢀꢄggeꢀed 1-Wꢁy sweeps ꢁlsꢅ ꢀequꢄꢀe ꢁ 3ꢀd ꢃꢀꢄggeꢀ ꢃꢅ sꢃꢁꢀꢃ ꢃhe ꢆew sweep. the 3ꢀd ꢃꢀꢄggeꢀ musꢃ be ꢃꢄmed ꢁppꢀꢅpꢀꢄꢁꢃely
ꢃꢅ ꢁllꢅw ꢃhe Vco ꢃꢅ seꢃꢃle ꢁfꢃeꢀ ꢃhe lꢁꢀge fꢀequeꢆꢂy hꢅp bꢁꢂk ꢃꢅ ꢃhe sꢃꢁꢀꢃ fꢀequeꢆꢂy. Subsequeꢆꢃ ꢅdd ꢆumbeꢀed
ꢃꢀꢄggeꢀs wꢄll sꢃꢁꢀꢃ ꢃhe 1-Wꢁy sweep ꢁꢆd ꢀepeꢁꢃ ꢃhe pꢀꢅꢂess.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
23
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Figure 16. 1-Way Sweep Control
Single Step Ramp Mode
a Sꢄꢆgle Sꢃep 1-Wꢁy rꢁmp ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 17. iꢆ ꢃhꢄs mꢅde, ꢁ ꢃꢀꢄggeꢀ ꢄs ꢀequꢄꢀed fꢅꢀ eꢁꢂh sꢃep ꢅf ꢃhe ꢀꢁmp. Sꢄꢆgle
sꢃep wꢄll fuꢆꢂꢃꢄꢅꢆ ꢄꢆ eꢄꢃheꢀ 1-Wꢁy ꢅꢀ 2-Wꢁy ꢀꢁmps. Sꢄmꢄlꢁꢀ ꢃꢅ ꢁuꢃꢅsweep, ꢃhe ꢀꢁmp_busy flꢁg wꢄll gꢅ hꢄgh ꢅꢆ ꢃhe fiꢀsꢃ
ꢃꢀꢄggeꢀ, ꢁꢆd wꢄll sꢃꢁy hꢄgh uꢆꢃꢄl ꢃhe ꢆꢃh ꢃꢀꢄggeꢀ. the ꢆ+1 ꢃꢀꢄggeꢀ wꢄll ꢂꢁuse ꢃhe ꢀꢁmp ꢃꢅ jump ꢃꢅ ꢃhe sꢃꢁꢀꢃ fꢀequeꢆꢂy ꢄꢆ
1-wꢁy ꢀꢁmp mꢅde. the ꢆ+2 ꢃꢀꢄggeꢀ wꢄll ꢀesꢃꢁꢀꢃ ꢃhe 1-wꢁy ꢀꢁmp.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Figure 17. Single Step Ramp Mode
the useꢀ shꢅuld be ꢁwꢁꢀe ꢃhꢁꢃ ꢃhe syꢆꢃhesꢄzed ꢀꢁmp ꢄs subjeꢂꢃ ꢃꢅ ꢆꢅꢀmꢁl phꢁse lꢅꢂked lꢅꢅp dyꢆꢁmꢄꢂs. if ꢃhe lꢅꢅp
bꢁꢆdwꢄdꢃh ꢄꢆ use ꢄs muꢂh wꢄdeꢀ ꢃhꢁꢆ ꢃhe ꢀꢁꢃe ꢅf ꢃhe sꢃeps ꢃheꢆ ꢃhe lꢅꢂkꢄꢆg wꢄll be veꢀy fꢁsꢃ ꢁꢆd ꢃhe ꢀꢁmp wꢄll hꢁve ꢁ
sꢃꢁꢄꢀꢂꢁse shꢁpe. if ꢃhe updꢁꢃe ꢀꢁꢃe ꢄs hꢄgheꢀ ꢃhꢁꢆ ꢃhe lꢅꢅp bꢁꢆdwꢄdꢃh, ꢁs ꢄs ꢆꢅꢀmꢁlly ꢃhe ꢂꢁse, ꢃheꢆ ꢃhe lꢅꢅp wꢄll ꢆꢅꢃ
fully seꢃꢃle befꢅꢀe ꢁ ꢆew fꢀequeꢆꢂy sꢃep ꢄs ꢀeꢂeꢄved. Heꢆꢂe ꢃhe swepꢃ ꢅuꢃpuꢃ wꢄll hꢁve ꢁ smꢁll lꢁg ꢁꢆd wꢄll sweep ꢄꢆ ꢁ
ꢆeꢁꢀ ꢂꢅꢆꢃꢄꢆuꢅus fꢁshꢄꢅꢆ.
MAIN SERIAL PORT
the HMc701LP6cE feꢁꢃuꢀes ꢁ fꢅuꢀ wꢄꢀe seꢀꢄꢁl pꢅꢀꢃ fꢅꢀ sꢄmple ꢂꢅmmuꢆꢄꢂꢁꢃꢄꢅꢆ wꢄꢃh ꢃhe hꢅsꢃ ꢂꢅꢆꢃꢀꢅlleꢀ. regꢄsꢃeꢀ ꢃypes
mꢁy be reꢁd oꢆly, Wꢀꢄꢃe oꢆly, reꢁd/Wꢀꢄꢃe ꢅꢀ Sꢃꢀꢅbe, ꢁs desꢂꢀꢄbed ꢄꢆ ꢃhe ꢀegꢄsꢃeꢀs desꢂꢀꢄpꢃꢄꢅꢆs.
typꢄꢂꢁl mꢁꢄꢆ seꢀꢄꢁl pꢅꢀꢃ ꢅpeꢀꢁꢃꢄꢅꢆ ꢂꢁꢆ be ꢀuꢆ wꢄꢃh ScLK ꢁꢃ speeds up ꢃꢅ 50 MHz. Seꢀꢄꢁl pꢅꢀꢃ ꢀegꢄsꢃeꢀs ꢁꢀe desꢂꢀꢄbed
ꢄꢆ ꢃhe seꢂꢃꢄꢅꢆ rEGiStEr MaP.
LD_SDO Pin Operation
cꢅꢆfiguꢀꢁꢃꢄꢅꢆ ꢅf ꢃhe LD_SDo pꢄꢆ ꢀequꢄꢀes mꢁꢆꢄpulꢁꢃꢄꢅꢆ ꢅf bꢅꢃh reg2h[1:0] ꢁꢆd reg1ah[13:12], ꢁs fꢅllꢅws:
Seꢀꢄꢁl dꢁꢃꢁ ꢅuꢃpuꢃ (SDo) wheꢆ ꢁ seꢀꢄꢁl ꢀeꢁd ꢅꢂꢂuꢀs ꢁꢆd hꢄgh ꢄmpedꢁꢆꢂe ꢁꢃ ꢁll ꢅꢃheꢀ ꢃꢄmes:
reg2h[1:0] = 0x (x=dꢅꢆ’ꢃ ꢂꢁꢀe)
reg1ah[13:12] = 0x (x=dꢅꢆ’ꢃ ꢂꢁꢀe)
Seꢀꢄꢁl dꢁꢃꢁ ꢅuꢃpuꢃ (SDo) wheꢆ ꢁ seꢀꢄꢁl ꢀeꢁd ꢅꢂꢂuꢀs ꢁꢆd LD sꢃꢁꢃus ꢁꢃ ꢁll ꢅꢃheꢀ ꢃꢄmes (LD_SDo pꢄꢆ ꢁuꢃꢅmꢁꢃꢄꢂꢁlly mux’ed
beꢃweeꢆ LD ꢁꢆd SDo):
reg2h[1:0] = 11
reg1ah[13:12] = 01
LD sꢃꢁꢃus ꢁlwꢁys:
reg2h[1:0] = 11
reg1ah[13:12] = 1x
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Hꢄgh ꢄmpedꢁꢆꢂe ꢁlwꢁys:
reg2h[1:0] = 10
reg1ah[13:12] = xx (x=dꢅꢆ’ꢃ ꢂꢁꢀe)
Figure 18 LD/SDo ouꢃpuꢃ cꢅꢆꢃꢀꢅl
Serial Port WRITE Operation
aVDD = DVDD = 3V 10%, aGnD = DGnD = 0V
Table 4. Timing Characteristics
Parameter
Conditions
Min.
8
Typ.
Max
Units
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
SEn ꢃꢅ ScLK seꢃup ꢃꢄme
1
2
3
4
5
6
7
SDi ꢃꢅ ScLK seꢃup ꢃꢄme
SDi ꢃꢅ cLK hꢅld ꢃꢄme
ScLK hꢄgh duꢀꢁꢃꢄꢅꢆ
ScLK lꢅw duꢀꢁꢃꢄꢅꢆ
SEn Hꢄgh duꢀꢁꢃꢄꢅꢆ
SEn lꢅw duꢀꢁꢃꢄꢅꢆ
10
10
8
8
640
20
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
26
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
a ꢃypꢄꢂꢁl WritE ꢂyꢂle ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 19.
ꢁ. the Mꢁsꢃeꢀ (hꢅsꢃ) bꢅꢃh ꢁsseꢀꢃs SEn (Seꢀꢄꢁl Pꢅꢀꢃ Eꢆꢁble) ꢁꢆd ꢂleꢁꢀs SDi ꢃꢅ ꢄꢆdꢄꢂꢁꢃe ꢁ WritE
ꢂyꢂle, fꢅllꢅwed by ꢁ ꢀꢄsꢄꢆg edge ꢅf ScLK.
b. the slꢁve (syꢆꢃhesꢄzeꢀ) ꢀeꢁds SDi ꢅꢆ ꢃhe 1sꢃ ꢀꢄsꢄꢆg edge ꢅf ScLK ꢁfꢃeꢀ SEn. SDi lꢅw ꢄꢆꢄꢃꢄꢁꢃes
ꢃhe WritE ꢂyꢂle (/Wr)
ꢂ. Hꢅsꢃ plꢁꢂes ꢃhe sꢄx ꢁddꢀess bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ sꢄx fꢁllꢄꢆg edges ꢅf ScLK, MSB fiꢀsꢃ.
d. Slꢁve ꢀegꢄsꢃeꢀs ꢃhe ꢁddꢀess bꢄꢃs ꢄꢆ ꢃhe ꢆexꢃ sꢄx ꢀꢄsꢄꢆg edges ꢅf ScLK (2-7).
e. Hꢅsꢃ plꢁꢂes ꢃhe 24 dꢁꢃꢁ bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ 24 fꢁllꢄꢆg edges ꢅf ScK, MSB fiꢀsꢃ .
f. Slꢁve ꢀegꢄsꢃeꢀs ꢃhe dꢁꢃꢁ bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ 24 ꢀꢄsꢄꢆg edges ꢅf ScK (8-31).
g. SEn ꢄs de-ꢁsseꢀꢃed ꢅꢆ ꢅꢀ ꢁfꢃeꢀ ꢃhe 32ꢆd fꢁllꢄꢆg edge ꢅf ScLK.
h. the 32ꢆd ꢀꢄsꢄꢆg edge ꢅf ScLK ꢂꢅmpleꢃes ꢃhe ꢂyꢂle
Figure 19. Serial Port Timing Diagram - WRITE
Main Serial Port READ Operation
aVDD = DVDD = 3V 10%, aGnD = DGnD = 0V
Table 5. Timing Characteristics
Parameter
Conditions
Min.
8
Typ.
Max
Units
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢆseꢂ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
SEn ꢃꢅ ScLK seꢃup ꢃꢄme
1
2
3
4
5
6
7
8
9
SDi ꢃꢅ ScLK seꢃup ꢃꢄme
ScLK ꢃꢅ SDi hꢅld ꢃꢄme
ScLK hꢄgh duꢀꢁꢃꢄꢅꢆ
ScLK lꢅw duꢀꢁꢃꢄꢅꢆ
SEn Hꢄgh duꢀꢁꢃꢄꢅꢆ
SEn Lꢅw duꢀꢁꢃꢄꢅꢆ
ScLK ꢃꢅ SDo delꢁy
reꢂꢅveꢀy tꢄme
10
10
8
8
640
20
8ꢆs+0.2ꢆs/pF
10
the syꢆꢃhesꢄzeꢀ uses ꢃhe mulꢃꢄ-puꢀpꢅse pꢄꢆ, LD_SDO, fꢅꢀ bꢅꢃh Lꢅꢂk Deꢃeꢂꢃ ꢁꢆd Seꢀꢄꢁl Dꢁꢃꢁ ouꢃ (SDo) fuꢆꢂꢃꢄꢅꢆs. the
ꢀegꢄsꢃeꢀs lkd_to_sdo_automux_en (Reg1A<12>) ꢁꢆd lkd_to_sdo_always (Reg1A<13> tꢁble 36) deꢃeꢀmꢄꢆe hꢅw ꢃhe
Dꢁꢃꢁ ouꢃpuꢃ pꢄꢆ ꢄs muxed wꢄꢃh ꢃhe Lꢅꢂk Deꢃeꢂꢃ fuꢆꢂꢃꢄꢅꢆ. if bꢅꢃh ꢅf ꢃhe ꢀegꢄsꢃeꢀs ꢁꢀe ꢂleꢁꢀed, ꢃheꢆ ꢃhe pꢄꢆ ꢄs exꢂlusꢄvely
SDo. if ꢁuꢃꢅmux ꢄs eꢆꢁbled, ꢃhe pꢄꢆ swꢄꢃꢂhes ꢃꢅ SDo wheꢆ ꢃhe rD fuꢆꢂꢃꢄꢅꢆ ꢄs seꢆsed ꢅꢆ ꢃhe 1sꢃ ꢀꢄsꢄꢆg edge ꢅf ScLK.
if lkd_to_sdo_always ꢄs seꢃ, ꢃheꢆ ꢃhe pꢄꢆ LD_SDO ꢄs dedꢄꢂꢁꢃed fꢅꢀ Lꢅꢂk Deꢃeꢂꢃ ꢅꢆly, ꢁꢆd ꢄꢃ ꢄs ꢆꢅꢃ pꢅssꢄble ꢃꢅ ꢀeꢁd fꢀꢅm
ꢃhe syꢆꢃhesꢄzeꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
27
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
a ꢃypꢄꢂꢁl rEaD ꢂyꢂle ꢄs shꢅwꢆ ꢄꢆ Fꢄguꢀe 20.
ꢁ. the Mꢁsꢃeꢀ (hꢅsꢃ) ꢁsseꢀꢃs bꢅꢃh SEn (Seꢀꢄꢁl Pꢅꢀꢃ Eꢆꢁble) ꢁꢆd SDi ꢃꢅ ꢄꢆdꢄꢂꢁꢃe ꢁ rEaD
ꢂyꢂle, fꢅllꢅwed by ꢁ ꢀꢄsꢄꢆg edge ScLK
b. the slꢁve (syꢆꢃhesꢄzeꢀ) ꢀeꢁds SDi ꢅꢆ ꢃhe 1sꢃ ꢀꢄsꢄꢆg edge ꢅf ScLK ꢁfꢃeꢀ SEn. SDi hꢄgh ꢄꢆꢄꢃꢄꢁꢃes
ꢃhe rEaD ꢂyꢂle (rD)
ꢂ. Hꢅsꢃ plꢁꢂes ꢃhe sꢄx ꢁddꢀess bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ sꢄx fꢁllꢄꢆg edges ꢅf ScLK, MSB fiꢀsꢃ.
d. Slꢁve ꢀegꢄsꢃeꢀs ꢃhe ꢁddꢀess bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ sꢄx ꢀꢄsꢄꢆg edges ꢅf ScLK (2-7).
e. Slꢁve plꢁꢂes ꢃhe 24 dꢁꢃꢁ bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ 24 ꢀꢄsꢄꢆg edges ꢅf ScK (8-31), MSB fiꢀsꢃ .
f. Hꢅsꢃ ꢀegꢄsꢃeꢀs ꢃhe dꢁꢃꢁ bꢄꢃs ꢅꢆ ꢃhe ꢆexꢃ 24 fꢁllꢄꢆg edges ꢅf ScK (8-31).
g. SEn ꢄs de-ꢁsseꢀꢃed ꢅꢆ ꢅꢀ ꢁfꢃeꢀ ꢃhe 32ꢆd fꢁllꢄꢆg edge ꢅf ScLK.
h. the 32ꢆd fꢁllꢄꢆg edge ꢅf ScLK ꢂꢅmpleꢃes ꢃhe ꢂyꢂle
Figure 20. Serial Port Timing Diagram - READ
REGISTER MAP
Reg 00h Chip ID (Read Only) Register
Bit
Type
Name
Width
Default
Description
Description
[23:0]
ro
chꢄp iD
24
581502h
chꢄp iD
Table 11. Reg 00h Strobe (Write Only) Register
Bit
Type
Str
Str
Str
Name
glꢅbꢁl_swꢀsꢃ_ꢀegs
glꢅbꢁl_swꢀsꢃ_dꢄg
mꢂꢆꢃ_ꢀesyꢆꢂh
Width
Default
0
1
1
1
0
0
0
Sꢃꢀꢅbe ꢃꢅ sꢅfꢃ ꢀeseꢃ ꢃhe SPi ꢀegꢄsꢃeꢀs
Sꢃꢀꢅbe ꢃꢅ sꢅfꢃ ꢀeseꢃ ꢃhe ꢀesꢃ ꢅf dꢄgꢄꢃꢁl
reseꢀved
1
2
Sꢃꢀꢅbe ꢃꢅ ꢂlꢅꢂk ꢃhe ꢃemp meꢁsuꢀemeꢆꢃ ꢅꢆ
demꢁꢆd
3
Str
ꢃseꢆs_spꢄ_sꢃꢀꢅbe
1
0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 12. Reg 01h Enable & Reset Register
Bit
Type
r/W
r/W
Name
mꢁlg_vꢂꢅbuf_eꢆ
mꢁg_bꢄꢁs_eꢆ
Width
Default
Description
Vco Buffeꢀ Eꢆꢁble
0
1
1
1
1
1
Bꢄꢁs eꢆꢁble. Wheꢆ 0 PLL ꢄs dꢄsꢁbled.
Eꢆꢁbles / Hꢅlds ꢀefdꢄv ꢄꢆ ꢀeseꢃ
2
3
r/W
r/W
ꢀfp_dꢄv_eꢆ
1
1
0
1
Hꢅldꢄꢆg ref dꢄvꢄdeꢀ ꢄꢆ ꢀeseꢃ ꢄs equꢄvꢁleꢆꢃ ꢃꢅ
bypꢁssꢄꢆg ꢃhe dꢄvꢄdeꢀ, see Fꢄguꢀe 4
Eꢆꢁbles ꢂlꢅꢂk gꢁꢃe fꢅꢀ xꢃꢁl muxed (sq ꢅꢀ sꢄꢆ)
ꢀefeꢀeꢆꢂe ꢃꢅ dꢄgꢄꢃꢁl.
xꢀefmux_ꢃꢅdꢄg_eꢆ
Pꢀꢅgꢀꢁm 1
Eꢆꢁbles dꢄvꢄded ꢀefeꢀeꢆꢂe ꢂlꢅꢂk ꢃꢅ ꢃhe dꢄgꢄꢃꢁl
see Fꢄguꢀe 4
4
5
6
r/W
r/W
r/W
ꢀfp_dꢄv_ꢃꢅdꢄg_eꢆ
ꢀfp_sqꢀ_ꢃꢅdꢄg_eꢆ
ꢀfp_sꢄꢆ_ꢃꢅdꢄg_eꢆ
1
1
1
1
0
0
Eꢆꢁbles squꢁꢀe wꢁve xꢃꢁl ꢂlꢅꢂk ꢃꢅ mꢁꢄꢆ dꢄgꢄꢃꢁl
see Fꢄguꢀe 4. Pꢀꢅgꢀꢁm 0
Eꢆꢁbles sꢄꢆe wꢁve xꢃꢁl ꢂlꢅꢂk ꢃꢅ mꢁꢄꢆ dꢄgꢄꢃꢁl
see Fꢄguꢀe 4
Eꢆꢁbles Squꢁꢀe wꢁve ref Buffeꢀ. alsꢅ ꢀequꢄꢀes
reg3h[16]=0 fꢅꢀ Squꢁꢀe wꢁve ref Buffeꢀ. See
Fꢄguꢀe 4
7
8
r/W
r/W
ꢀfp_buf_sq_eꢆ
ꢀfp_buf_sꢄꢆ_eꢆ
1
1
1
0
Eꢆꢁbles Sꢄꢆe wꢁve ref Buffeꢀ. alsꢅ ꢀequꢄꢀes
reg3h[16]=1 fꢅꢀ Sꢄꢆe wꢁve ref Buffeꢀ. See
Fꢄguꢀe 4
1= dꢄvꢄded Vco ꢁs dꢄgꢄꢃꢁl, Δ∑ mꢅdulꢁꢃꢅꢀ ꢂlꢅꢂk
0= Dꢄvꢄded ref pꢁꢃh ꢁs ꢃhe Δ∑ mꢅdulꢁꢃꢅꢀ ꢂlꢅꢂk
Pꢀꢅgꢀꢁm 1
9
r/W
r/W
r/W
vꢂꢅp_ꢃꢅdꢄg_eꢆ
vꢂꢅp_pꢀesꢂ_eꢆ
pfd_lkd_eꢆ
1
1
1
1
1
1
10
11
Eꢆꢁbles ꢃhe pꢀesꢂꢁleꢀ bꢄꢁs
Eꢆꢁble / reseꢃb ꢃꢅ dꢄgꢄꢃꢁl lꢅꢂkdeꢃeꢂꢃ ꢂꢄꢀꢂuꢄꢃ ꢁꢆd
PFD’s lꢅꢂkdeꢃeꢂꢃ ꢅuꢃpuꢃ gꢁꢃes
Pꢀꢅgꢀꢁm 1
12
13
14
r/W
r/W
r/W
ꢂp_eꢆ
1
1
1
1
1
1
chꢁꢀge Pump Eꢆꢁble, dꢄsꢁble ꢄs ꢃꢀꢄ-sꢃꢁꢃed ꢅuꢃpuꢃ
1 - Eꢆꢁbles fꢀꢁꢂꢃꢄꢅꢆꢁl mꢅdulꢁꢃꢅꢀ
see ꢁlsꢅ dsm_integer_mode Reg12h<3>
dsm_ꢀsꢃb
lkd_ꢀsꢃb
1 - eꢆꢁbles lꢅꢂk deꢃeꢂꢃ ꢂꢄꢀꢂuꢄꢃ
cSP PFD FF ꢀsꢃb
15
r/W
pfds_ꢀsꢃb
1
1
1 - Eꢆꢁbles ꢃhe cyꢂle Slꢄp Pꢀeveꢆꢃꢄꢅꢆ (cSP)
feꢁꢃuꢀe ꢅf ꢃhe PFD
Table 13. Reg 02h Serial Data Out Force Register
Bit
Type
Name
Default
Description
LD/SDo Dꢀꢄveꢀ Eꢆꢁble ꢂꢅꢆꢃꢀꢅl vꢁlue (1=eꢆꢁbled).
Dꢀꢄveꢀ Eꢆꢁble ꢂꢅꢆꢃꢀꢅlled by ꢃhꢄs bꢄꢃ ꢅꢆly wheꢆ
reg02h[1]=1
0
r/W
mꢁlg_sdꢅ_dꢀꢄveꢀ_fꢅꢀꢂe_vꢁl
1
Wheꢆ 1 LD/SDo Dꢀꢄveꢀ Eꢆꢁble ꢂꢅꢆꢃꢀꢅlled by reg
02h[0].
Wheꢆ 0 LD/SDo Dꢀꢄveꢀ Eꢆꢁble ꢂꢅꢆꢃꢀꢅlled by
ꢄꢆꢃeꢀꢆꢁl SPi ꢀeꢁd ꢁꢂꢃꢄve sꢄgꢆꢁl (ꢄe. eꢆꢁbled ꢅꢆly
wheꢆ ꢁꢆ SPi ꢀeꢁd ꢅꢂꢂuꢀs ꢁꢆd hꢄgh ꢄmpedꢁꢆꢂe ꢁll
ꢅꢃheꢀ ꢃꢄmes)
1
r/W
mꢁlg_sdꢅ_dꢀꢄveꢀ_fꢅꢀꢂe_eꢆ
1
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 14. Reg 03h Reference Path Register
Bit
Type
Name
Default
Description
Dꢄvꢄdes ꢃhe ꢂꢀysꢃꢁl ꢄꢆpuꢃ by ꢃhꢄs ꢆumbeꢀ ‘r’ ꢄf
ꢀfp_dꢄv_eꢆ=1 ꢁꢆd ꢀfp_dꢄv_seleꢂꢃ = 1
ꢀfp_dꢄv_ꢀꢁꢃꢄꢅ = 0 ꢆꢅꢃ ꢁllꢅwed
2<=dꢄv_ꢀꢁꢃꢄꢅ<=2^14
ꢀfp_dꢄv_ꢀꢁꢃꢄꢅ
13:0
r/W
1
ꢁlsꢅ ꢀefeꢀꢀed ꢃꢅ ꢁs ‘r’
ꢀfp_dꢄv_seleꢂꢃ
see Fꢄguꢀe 4
1 = ꢀefeꢀeꢆꢂe dꢄvꢄdeꢀ eꢆꢁbled
0 = bypꢁss ꢀef dꢄvꢄdeꢀ
see Fꢄguꢀe 4
14
r/W
0
1 = ꢁuꢃꢅ ꢀef dꢄvꢄdeꢀ eꢆꢁble ꢅꢀ bypꢁss ꢄs ꢁuꢃꢅmꢁꢃꢄꢂ
ꢄf ꢀfp_dꢄv_ꢀꢁꢃꢄꢅ = 1, bypꢁss dꢄvꢄdeꢀ
ꢄf ꢀfp_dꢄv_bypꢁss ~=1 use dꢄvꢄdeꢀ
see Fꢄguꢀe 4
15
16
r/W
r/W
ꢀfp_ꢁuꢃꢅ_ꢀefdꢄv_sel_eꢆ
ꢀfp_buf_sꢄꢆ_sel
1
0
Seleꢂꢃs sꢄꢆe wꢁve ꢀefeꢀeꢆꢂe fꢅꢀ ꢆꢅꢀmꢁl ꢅpeꢀꢁꢃꢄꢅꢆ
see Fꢄguꢀe 4
Table 15. Reg 04h Prescaler Duty Cycle Register
Bit
Type
Name
Default
Description
Exꢃeꢆds ꢃhe lꢅw ꢃꢄme fꢀꢅm 15 ꢃꢅ 47 Vco ꢂyꢂles
fꢅꢀ lꢁꢀge dꢄvꢄde ꢀꢁꢃꢄꢅs. Pꢀꢅgꢀꢁm 0
0
r/W
vꢂꢅp_duꢃyꢂyꢂmꢅde
0
Table 16. Reg 05h Phase Freq Detector Register (pfd)
Bit
Type
Name
Default
Description
iꢆveꢀꢃs PFD Pꢅlꢁꢀꢄꢃy
0 = Pꢁssꢄve Fꢄlꢃeꢀ +ve slꢅpe Vco
0
r/W
pfd_phꢁse_sel
0
1 = Pꢁssꢄve Fꢄlꢃeꢀ -ve slꢅpe Vco
1 = aꢂꢃꢄve ꢄꢆveꢀꢃꢄꢆg filꢃeꢀ, +ve slꢅpe Vco
0 = aꢂꢃꢄve ꢄꢆveꢀꢃꢄꢆg filꢃeꢀ, -ve slꢅpe Vco
allꢅws mꢁskꢄꢆg ꢅf ꢃhe up ꢅuꢃpuꢃs beꢃweeꢆ PFD
ꢁꢆd cP
1
2
r/W
r/W
pfd_upꢅuꢃ_eꢆ
pfd_dꢆꢅuꢃ_eꢆ
1
1
allꢅws mꢁskꢄꢆg ꢅf ꢃhe dꢆ ꢅuꢃpuꢃs beꢃweeꢆ PFD
ꢁꢆd cP
Table 17. Reg 06h Phase Freq Detector Delay Register
Bit
Type
Name
Default
Description
2:0
r/W
pfd_del_sel
2h
Delꢁy lꢄꢆe seꢃpꢅꢄꢆꢃ ꢃꢅ PFD Pꢀꢅgꢀꢁm 001
Table 18. Reg 07h Charge Pump UP/DN Control Register
Bit
Type
Name
ꢂp_UPꢂuꢀꢀeꢆꢃ_sel
ꢂp_Dnꢂuꢀꢀeꢆꢃ_sel
Default
Description
Seꢃs chꢁꢀge-Pump Up gꢁꢄꢆ, 125ua lsb, bꢄꢆꢁꢀy,
4ma mꢁx. Pꢀꢅgꢀꢁm ꢁs ꢆeeded
4:0
r/W
10h
Seꢃs chꢁꢀge-Pump Dꢆ gꢁꢄꢆ, 125ua lsb, bꢄꢆꢁꢀy,
4ma mꢁx. Pꢀꢅgꢀꢁm ꢁs ꢆeeded
9:5
r/W
10h
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
30
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 19. Reg 08h Charge Pump Trim & Offset Register
Bit
Type
Name
Default
Description
tꢀꢄm Up gꢁꢄꢆ, 14.3ua lsb, bꢄꢆꢁꢀy, 100ua mꢁx
Pꢀꢅgꢀꢁm 0
3:0
r/W
ꢂp_UPꢃꢀꢄm_sel
ꢂp_Dnꢃꢀꢄm_sel
0
tꢀꢄm Dꢆ gꢁꢄꢆ, 14.3ua lsb, bꢄꢆꢁꢀy, 100ua mꢁx
Pꢀꢅgꢀꢁm 0
7:4
r/W
r/W
0
Up offseꢃ leꢁkꢁge ꢂuꢀꢀeꢆꢃ, 28.7ua lsb, bꢄꢆꢁꢀy,
430ua mꢁx Pꢀꢅgꢀꢁm ꢁs ꢆeeded. See chꢁꢀge
Pump Phꢁse offseꢃ
11:8
ꢂp_UPꢅffseꢃ_sel
4h
Dꢆ offseꢃ leꢁkꢁge ꢂuꢀꢀeꢆꢃ, 28.7ua , bꢄꢆꢁꢀy,
430uamꢁx Pꢀꢅgꢀꢁm ꢁs ꢆeeded. See chꢁꢀge
Pump Phꢁse offseꢃ
15:12
17:16
r/W
r/W
ꢂp_Dnꢅffseꢃ_sel
ꢂp_ꢁmp_bꢄꢁs_sel
0
chꢁꢀge Pump Dummy Bꢀꢁꢆꢂh op ꢁmp bꢄꢁs
seleꢂꢃꢄꢅꢆ, 100ua Pꢀꢅgꢀꢁm 10
2h
Table 20. Reg 09h Charge Pump EN Register
Bit
Type
Name
Default
Description
0
r/W
ꢂp_pull_updꢆ_eꢆ
0
Eꢆꢁbles cP UP/Dꢅwꢆ cꢅꢆꢃꢀꢅl reg09
0 - Fꢅꢀꢂes chꢁꢀge Pump Up wheꢆ reg09[0]=1
1 - Fꢅꢀꢂes chꢁꢀge Pump Dn wheꢆ reg09[0]=1
1
r/W
ꢂp_pull_dꢆ_upb
0
Table 21. Reg 0Ah Reserved
Bit
Type
Name
Default
Description
23:0
r/W
reseꢀved
304h
reseꢀved
Table 22. Reg 0Bh Reserved
Bit
Type
Name
Default
Description
23:0
r/W
reseꢀved
0
reseꢀved
Table 23. Reg 0Ch Reserved
Bit
Type
Name
Default
Description
23:0
r/W
reseꢀved
100h
reseꢀved
Table 24. Reg 0Dh Reserved
Bit
Type
Name
Default
Description
23:0
r/W
reseꢀved
20h
reseꢀved
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
31
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 25. Reg 0Eh Reserved
Bit
Type
Name
Default
Description
23:0
r/W
reseꢀved
0
reseꢀved
Table 26. Reg 0Fh Integer Division Register
Bit
Type
Name
Default
Description
uꢆsꢄgꢆed ꢄꢆꢃegeꢀ pꢅꢀꢃꢄꢅꢆ ꢅf Vco dꢄvꢄdeꢀ vꢁlue,
ꢁlsꢅ kꢆꢅwꢆ ꢁs N
15:0
r/W
dsm_ꢄꢆꢃg
c8
INT
Table 27. Reg 10h Fractional Division Register
Bit
Type
Name
Default
Description
uꢆsꢄgꢆed fꢀꢁꢂꢃꢄꢅꢆꢁl pꢅꢀꢃꢄꢅꢆ ꢅf Vco dꢄvꢄdeꢀ ꢁlsꢅ
kꢆꢅwꢆ ꢁs N
23:0
r/W
dsm_fꢀꢁꢂ
0
FRAC
Table 28. Reg 11h Seed Register
Bit
Type
Name
Default
Description
Uꢆsꢄgꢆed seed vꢁlue fꢅꢀ Δ∑ mꢅdulꢁꢃꢅꢀ
Seꢃs ꢃhe sꢃꢁꢀꢃ phꢁse ꢅf ꢃhe mꢅdulꢁꢃꢅꢀ. Use ꢁ
ꢀꢁꢆdꢅm, ꢆꢅꢆ-ꢀepeꢁꢃꢄꢆg ꢆumbeꢀ fꢅꢀ besꢃ ꢀesulꢃs
(exꢁmples: 3a1953h, DEaDBEh, 50894ch)
23:0
r/W
dsm_seed
0
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For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
32
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 29. Reg 12h Delta Sigma Modulator Register
Bit
Type
r/W
r/W
r/W
Name
Default
Description
use ꢀefeꢀeꢆꢂe ꢄꢆsꢃeꢁd ꢅf dꢄvꢄdeꢀ Pꢀꢅgꢀꢁm 0
ꢄꢆveꢀꢃ Δ∑ ꢂlk
0
dsm_ꢀef_ꢂlk_seleꢂꢃ
0
1
0
1
dsm_ꢄꢆveꢀꢃ_ꢂlk_sd3
dsm_ꢄꢆveꢀꢃ_ꢂlk_ꢀph
2
ꢄꢆveꢀꢃs ꢃhe ꢀef ꢂlꢅꢂk phꢁse
1- eꢆꢁbles iꢆꢃegeꢀ Mꢅde, bypꢁsses ꢃhe Δ∑
mꢅdulꢁꢃꢅꢀ, leꢁves ꢄꢃ ꢀuꢆꢆꢄꢆg
see ꢁlsꢅ dsm_ꢀsꢃb reg01h<13> ꢃꢅ dꢄsꢁble ꢃhe
mꢅdulꢁꢃꢅꢀ
3
r/W
dsm_ꢄꢆꢃegeꢀ_mꢅde
0
4
5
r/W
r/W
reseꢀved
reseꢀved
0
0
wheꢆ xꢀef ꢄs seleꢂꢃed speꢂꢄfies ꢃhꢁꢃ ꢃhe sꢄꢆe
sꢅuꢀꢂe ꢄs used
6
7
r/W
r/W
dsm_xꢀef_sꢄꢆ_seleꢂꢃ
dsm_ꢁuꢃꢅseed
0
1
ꢁuꢃꢅmꢁꢃꢄꢂ seed lꢅꢁd wheꢆ ꢂhꢁꢆgꢄꢆg ꢃhe fꢀꢁꢂ
pꢁꢀꢃ, uses vꢁlue ꢄꢆ seed
Delꢃꢁ-Sꢄgmꢁ Mꢅdulꢁꢃꢅꢀ ꢂꢅꢆfiguꢀꢁꢃꢄꢅꢆ:
00-1sꢃ ꢅꢀdeꢀ 01-2ꢆd ꢅꢀdeꢀ 10-3ꢀd ꢅꢀdeꢀ Feedbꢁꢂk
11-3ꢀd ꢅꢀdeꢀ Feedfꢅꢀwꢁꢀd
Use eꢄꢃheꢀ 10 ꢅꢀ 11. Fꢅꢀ Sweepeꢀ ꢅpeꢀꢁꢃꢄꢅꢆ use
11 ꢅꢆly.
9:8
r/W
dsm_ꢅꢀdeꢀ
2
Dꢅ ꢆꢅꢃ use 1sꢃ ꢅꢀ 2ꢆd ꢅꢀdeꢀ (fꢅꢀ ꢃesꢃ ꢅꢆly)
mꢁx vꢁlue ꢁllꢅwed ꢅuꢃ ꢅf Δ∑ mꢅdulꢁꢃꢅꢀ quꢁꢆꢃꢄzeꢀ
lꢄmꢄꢃs ꢁꢀe +7 ꢃꢅ -8, ꢃyp 3 ꢅꢀ 4 Pꢀꢅgꢀꢁm 3h
13:10
17:14
r/W
r/W
dsm_quꢁꢆꢃ_mꢁx
dsm_quꢁꢆꢃ_mꢄꢆ
3h
mꢄꢆ vꢁlue ꢁllꢅwed ꢅuꢃ ꢅf Δ∑ mꢅdulꢁꢃꢅꢀ quꢁꢆꢃꢄzeꢀ
lꢄmꢄꢃs ꢁꢀe +7 ꢃꢅ -8, ꢃyp 3 ꢅꢀ 4 Pꢀꢅgꢀꢁm ch
ch
Table 30. Reg 14h CW Sweep Control Register
the mꢁxꢄmum sweep ꢀꢁꢆge ꢄs lꢄmꢄꢃed ꢃꢅ 255 x Fxꢃꢁl/r. Delꢃꢁ-Sꢄgmꢁ Mꢅdulꢁꢃꢅꢀ mꢅde shꢅuld be Feed
Fꢅꢀwꢁꢀd wheꢆ usꢄꢆg Sweep feꢁꢃuꢀe (regꢄsꢃeꢀ 12h Bꢄꢃs [9:8] = 11.
Bit
Type
Name
Default
Description
0
r/W
ꢂleꢁꢀ_ꢅvf_uꢆdf
ꢀꢁmp_eꢆꢁble
0
ꢁsyꢆꢂhꢀꢅꢆꢅus ꢂleꢁꢀ fꢅꢀ ꢅvf/uꢆdf flꢁgs
rꢁmp Eꢆ/ꢀsꢃb
1= eꢆꢁbles ꢃhe cW rꢁmp Fuꢆꢂꢃꢄꢅꢆ
1
r/W
0
Wꢀꢄꢃe ꢁlwꢁys ꢃꢀꢄggeꢀs ꢀꢁmps ꢄf bꢄꢃ <2> = 0, ꢄf bꢄꢃ
<2> = 1, rꢁmp wꢄll ꢆꢅꢃ ꢃꢀꢄggeꢀ, bꢄꢃ <2> musꢃ be
ꢀeseꢃ ꢃꢅ 0 fiꢀsꢃ
2
r/W
ꢀꢁmp_ꢃꢀꢄgg
0
rꢁmp repeꢁꢃ Seq eꢆꢁble
3
4
r/W
r/W
ꢀꢁmp_ꢀepeꢁꢃ_eꢆ
0
0
1= eꢆꢁbles ꢁuꢃꢅꢃꢀꢄggeꢀ ꢅf ꢀꢁmps
0 = ꢀꢁmp_ꢃꢀꢄgg sꢃꢁꢀꢃs eꢁꢂh ꢀꢁmp
rꢁmp sꢃꢁꢀꢃ dꢄꢀeꢂꢃꢄꢅꢆ
1= Sꢃꢁꢀꢃ wꢄꢃh rꢁmp Dꢅwꢆ
0= Sꢃꢁꢀꢃ wꢄꢃh rꢁmp Up
ꢀꢁmp_sꢃꢁꢀꢃdꢄꢀ_dꢆ
5
6
r/W
r/W
ꢀꢁmp_ꢃꢀꢄg_exꢃ_eꢆ
ꢀꢁmp_sꢄꢆglesꢃep
0
0
Eꢆꢁble hꢁꢀdwꢁꢀe ꢃꢀꢄggeꢀ ꢅꢆ GPo3 pꢄꢆ
rꢁmp sꢄꢆgle sꢃep, ꢁdvꢁꢆꢂes ꢃhe ꢀꢁmp ꢃꢅ ꢃhe ꢆexꢃ
sꢃep, ꢁꢆd hꢅlds fꢀequeꢆꢂy
rꢁmps ꢄꢆ ꢅꢆe dꢄꢀeꢂꢃꢄꢅꢆ ꢅꢆly wꢄꢃh hꢅp ꢃꢅ sꢃꢁꢀꢃ ꢁꢃ
eꢆd ꢅf ꢀꢁmp
7
r/W
ꢀꢁmp_sꢄꢆgledꢄꢀ
0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 31. Reg 15h CW Sweep Ramp Step Register
the mꢁxꢄmum sweep ꢀꢁꢆge ꢄs lꢄmꢄꢃed ꢃꢅ 255 x Fxꢃꢁl/r. Delꢃꢁ-Sꢄgmꢁ Mꢅdulꢁꢃꢅꢀ mꢅde shꢅuld be Feed
Fꢅꢀwꢁꢀd wheꢆ usꢄꢆg Sweep feꢁꢃuꢀe (regꢄsꢃeꢀ 12h Bꢄꢃs [9:8] = 11.
Bit
Type
Name
Default
Description
23:0
r/W
ꢀꢁmp_sꢃep
800h
rꢁmp Sꢃep sꢄze
Table 32. Reg 16h CW Sweep Ramp Step Number Register
the mꢁxꢄmum sweep ꢀꢁꢆge ꢄs lꢄmꢄꢃed ꢃꢅ 255 x Fxꢃꢁl/r. Delꢃꢁ-Sꢄgmꢁ Mꢅdulꢁꢃꢅꢀ mꢅde shꢅuld be Feed
Fꢅꢀwꢁꢀd wheꢆ usꢄꢆg Sweep feꢁꢃuꢀe (regꢄsꢃeꢀ 12h Bꢄꢃs [9:8] = 11.
Bit
Type
Name
ꢀꢁmp_sꢃeps_ꢆumbeꢀ
Default
Description
23:0
r/W
800h
rꢁmp numbeꢀ ꢅf sꢃeps ꢄꢆ ꢀꢁmp
Table 33. Reg 17h CW Sweep Dwell Time Register
Bit
Type
Name
Default
Description
rꢁmp numbeꢀ ꢅf ꢂyꢂles ꢃꢅ hꢅld ꢁꢃ ꢃꢅp/bꢅꢃꢃꢅm
ꢄꢆ ꢀepeꢁꢃ mꢅde
23:0
r/W
ꢀꢁmp_dwell_ꢃꢄme
800h
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For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 34. Reg 18h Auxiliary Oscillator Register 1
Bit
Type
Name
Default
Description
Seleꢂꢃs ꢃhe ꢄꢆpuꢃ ꢂlk fꢅꢀ ꢁuxꢂlk Pꢀꢅgꢀꢁm 0
0:vꢂꢅdꢄv
1:xꢀefsq ꢅꢀ sꢄꢆ
2:ꢀefdꢄv
1:0
r/W
dsmꢂlk_ꢁuxꢂlk_ꢄꢆsel
0
3:ꢀꢄꢆg ꢅsꢂꢄllꢁꢃꢅꢀ fꢀꢅm mꢅꢆꢅ, esꢃ 300 MHz ꢃꢅ
1 GHz
Pꢀꢅgꢀꢁm 0
0: bypꢁss-ꢆꢅ delꢁy
1: pꢁss ꢃhꢀꢅugh w/ delꢁy
2: ꢀꢄꢆg-ꢅuꢃ ꢂꢅꢆsꢃꢁꢆꢃ
3: ꢀꢄꢆg-ꢅuꢃ seeded/gꢁꢃed
3:2
6:4
r/W
dsmꢂlk_ꢁuxꢂlk_mꢅdesel
0
2
dꢄvꢄdeꢀ seleꢂꢃꢄꢅꢆ ꢁuxꢂlk vꢁlue dꢄvby Pꢀꢅgꢀꢁm
010
000
001
010
011
100
101
110
111
1
2
4
6
r/W
dsmꢂlk_ꢁuxꢂlk_dꢄvsel
8
10
12
14
seleꢂꢃs ꢁuxꢂlk (ꢄf=1) ꢁs ꢆꢁꢃuꢀꢁl ꢀefeꢀeꢆꢂe ꢂlk
ꢄꢆpuꢃ ꢅf sꢄgmꢁ delꢃꢁ Pꢀꢅgꢀꢁm 1
7
8
r/W
r/W
dsmꢂlk_ꢁuxꢂlk_sel
1
0
eꢆꢁbles 10-bꢄꢃ lfsꢀ ꢄꢆsꢄde ꢃhe delꢁy mꢅdulꢁꢃꢅꢀ
(ꢂlꢅꢂked by ꢁuxꢂlk ꢅꢀ ꢁuxꢂlkb) Pꢀꢅgꢀꢁm 0
dsmꢂlk_ꢁuxmꢅd_lfsꢀ_eꢆ
eꢆꢁbles 8-bꢄꢃ ꢁꢂꢂumulꢁꢃꢅꢀ ꢄꢆsꢄde ꢃhe delꢁy
mꢅdulꢁꢃꢅꢀ (ꢂlꢅꢂked by ꢁuxꢂlk ꢅꢀ ꢁuxꢂlkb)
Pꢀꢅgꢀꢁm 0
9
r/W
r/W
dsmꢂlk_ꢁuxmꢅd_ꢁꢂꢂum_eꢆ
dsmꢂlk_ꢁuxmꢅd_mꢅde
0
0
delꢁy mꢅdulꢁꢃꢄꢅꢆ mꢅde Pꢀꢅgꢀꢁm 0
0: ꢁuxmꢅd_lꢅdly_ꢄꢆ pꢁssꢃhꢀꢅugh
1: ꢁꢂꢂumulꢁꢃꢅꢀ bꢁsed squꢁꢀe-wꢁve
2: lfsꢀ (lꢅ-ꢁmp)
11:10
3: lfsꢀ (hꢄ-ꢁmp)
sꢃep-sꢄze ꢅf ꢁꢂꢂumulꢁꢃꢅꢀ (ꢂhꢁꢆges squꢁꢀe-wꢁve
vꢁlue ꢅꢆꢂe ꢄꢃ wꢀꢁps ꢃhꢀꢅugh 256) Pꢀꢅgꢀꢁm 0
19:12
22:20
r/W
r/W
dsmꢂlk_ꢁuxmꢅd_fꢀꢁꢂsꢃep
dsmꢂlk_ꢁuxmꢅd_lꢅdly
0
0
vꢁlue ꢅf delꢁy-elemeꢆꢃ (wheꢆ ꢁuxmꢅd_mꢅde=0)
ꢅꢀ lꢅw vꢁlue used duꢀꢄꢆg sq-wꢁve mꢅdulꢁꢃꢄꢅꢆ
Pꢀꢅgꢀꢁm 0
Table 35. Reg 19h Auxiliary Oscillator Register 2
Bit
Type
Name
Default
Description
hꢄ vꢁlue ꢅf delꢁy elemeꢆꢃ duꢀꢄꢆg sq-wꢁve
mꢅdulꢁꢃꢄꢅꢆ Pꢀꢅgꢀꢁm 7h
2:0
r/W
dsmꢂlk_ꢁuxmꢅd_hꢄdly
7
ꢅpꢃꢄꢅꢆꢁlly ꢄꢆveꢀꢃs ꢁuxꢂlk ꢁs used by ꢃhe
mꢅdulꢁꢃꢅꢀ Pꢀꢅgꢀꢁm 1
3
4
r/W
r/W
dsmꢂlk_ꢁuxmꢅd_ꢂlkꢄꢆv
1
0
dsmꢂlk_ꢁuxmꢅd_ꢂlkwꢀꢄꢆg
seleꢂꢃ LKD ꢀꢄꢆgꢅsꢂ ꢃꢅ ꢂlꢅꢂk ꢃhe LFSr Pꢀꢅgꢀꢁm 0
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For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
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Application Support: Phone: 1-800-ANALOG-D
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 36. Reg 1Ah Lock Detect Register
Bit
Type
Name
Default
Description
ꢃhꢀeshꢅld ꢂꢅuꢆꢃ ꢄꢆ ꢃhe ꢃꢄmeꢀ wꢄꢆdꢅw ꢃꢅ deꢂlꢁꢀe
lꢅꢂk (ꢀefeꢀeꢆꢂe ꢂyꢂles)
9:0
r/W
lkd_wꢄꢆꢂꢆꢃ_mꢁx
40h
Eꢆꢁbles ꢁsymmeꢃꢀꢄꢂ lꢅꢂk deꢃeꢂꢃ wꢄꢆdꢅw (ꢆꢅmꢄꢆꢁl
10ꢆseꢂ)
10
11
r/W
r/W
lkd_wꢄꢆ_ꢁsym_eꢆꢁble
0
0
lkd_wꢄꢆ_ꢁsym_up_seleꢂꢃ
Seꢃs pꢅlꢁꢀꢄꢃy ꢅf ꢃhe wꢄꢆdꢅw
Muxes ꢃhe lkd ꢅuꢃpuꢃ sꢄgꢆꢁl ꢃꢅ SDo wheꢆ SDo ꢄs
ꢆꢅꢃ beꢄꢆg used fꢅꢀ Mꢁꢄꢆ Seꢀꢄꢁl Pꢅꢀꢃ Dꢁꢃꢁ ouꢃpuꢃs
(reꢁd opeꢀꢁꢃꢄꢅꢆ)
12
13
14
r/W
r/W
r/W
lkd_ꢃꢅ_sdꢅ_ꢁuꢃꢅmux_eꢆ
lkd_ꢃꢅ_sdꢅ_ꢁlwꢁys
1
0
0
Muxes ꢃhe lkd ꢅuꢃpuꢃ sꢄgꢆꢁl ꢃꢅ SDo ꢁlwꢁys, ꢆꢅꢃ
pꢅssꢄble ꢃꢅ dꢅ Mꢁꢄꢆ Seꢀꢄꢁl Pꢅꢀꢃ reꢁd ꢄꢆ ꢃhꢄs sꢃꢁꢃe
1 seleꢂꢃ ꢀꢄꢆgꢅsꢂ bꢁsed ꢅꢆeshꢅꢃ fꢅꢀ lꢅꢂk deꢃeꢂꢃ
wꢄꢆdꢅw
lkd_ꢀꢄꢆgꢅsꢂ_mꢅꢆꢅ_seleꢂꢃ
0 seleꢂꢃs ꢁꢆꢁlꢅg bꢁsed ꢅꢆeshꢅꢃ
16:15
18:17
19
r/W
r/W
r/W
lkd_ꢀꢄꢆgꢅsꢂ_ꢂfg
0
0
0
“00” fꢁsꢃesꢃ “11” slꢅwesꢃ
lkd_mꢅꢆꢅsꢃ_duꢀꢁꢃꢄꢅꢆ
lkd_ꢀꢄꢆgꢅsꢂ_ꢃesꢃmꢅde
“00” shꢅꢀꢃesꢃ “11” lꢅꢆgesꢃ
eꢆꢁbles ꢃhe ꢀꢄꢆg ꢅsꢂ by ꢄꢃself fꢅꢀ ꢃesꢃꢄꢆg
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For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
36
Application Support: Phone: 1-800-ANALOG-D
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 37. Reg 1Bh GPO Control Register
Bit
Type
Name
Default
Description
gpꢅ_sel
0000
Seleꢂꢃs dꢁꢃꢁ ꢃꢅ be dꢀꢄveꢆ ꢅꢆ GPo pꢅꢀꢃs
GPo3 <=gpꢅsel_0_dꢁꢃꢁ<2>
GPo2 <= gpꢅsel_0_dꢁꢃꢁ<1>
GPo1 <= gpꢅsel_0_dꢁꢃꢁ<0>
gpꢅ_sel<3:0> = 0000
gpꢅ_sel<3:0> = 0001
gpꢅ_sel<3:0> = 0010
GPo3 <= xꢀef_ꢂlk_ꢄꢆ
GPo2 <= ꢀef_ꢂlk_ꢄꢆ
GPo1 <= vꢂꢅ_dꢄv_ꢂlkꢄꢆ
GP03 <= pfd_up_ꢄꢆ
GP02 <= pfd_dꢆ_ꢄꢆ
GP01 <= LKD_mꢅꢆꢅsꢃ_wꢄꢆdꢅw
GP03 <= pfd_sꢁꢃ_ꢀef_ꢄꢆ
GP02 <= pfd_sꢁꢃ_vꢂꢅ_dꢄv_ꢄꢆ
GP01 <= delꢃꢁ_ꢄꢆꢃegeꢀ_ꢂyꢂslꢄp_sel, ꢃhꢄs sꢃꢀꢅbe
hꢅlds ꢃhe gꢁꢄꢆ ꢅf ꢃhe PFD ꢁꢃ mꢁx fꢅꢀ ꢁꢆꢃꢄ-ꢂyꢂle
slꢄppꢄꢆg
gpꢅ_sel<3:0> = 0011
GP03 <= xꢀef_ꢂlk_ꢄꢆ
GP02 <= xꢀef_sꢄꢆ_ꢄꢆ
GP01 <= sd_fꢀꢁꢂ_sꢃꢀꢅbe_syꢆꢂ, ꢄꢆꢃeꢀꢆꢁlly
syꢆꢂhꢀꢅꢆꢄzed fꢀꢁꢂ sꢃꢀꢅbe
gpꢅ_sel<3:0> = 0100
gpꢅ_sel<3:0> = 0101
gpꢅ_sel<3:0> = 0110
3:0
r/W
reseꢀved
GP03 <= SD_iꢆꢃz1<1>
GP02 <=SD_iꢆꢃz1<2>
GP01 <= SD_iꢆꢃz1<3>
3-bꢄꢃ quꢁꢆꢃꢄzed veꢀsꢄꢅꢆ ꢅf ꢃhe Vco phꢁse
GP03 <= ꢁux_ꢂlk
GP02 <= ꢀꢄꢆgꢅsꢂ_ꢃesꢃ
GP01 <= ꢂlk_SD
gpꢅ_sel<3:0> = 0111
GP03 <= 00
gpꢅ_sel<3:0> = 1000
gpꢅ_sel<3:0> = 1001
gpꢅ_sel<3:0> = 1010
GP02 <= ꢀꢁmp_busy
GP01 <= reseꢀved
reseꢀved
GP03 <= Δ∑ Quꢁꢆꢃꢄzeꢀ ouꢃpuꢃ 3ꢀd lsb
GP02 <= Δ∑ Quꢁꢆꢃꢄzeꢀ ouꢃpuꢃ 2ꢆd lsb
GP01 <= Δ∑ Quꢁꢆꢃꢄzeꢀ ouꢃpuꢃ lsb
6:4
7
r/W
r/W
gpꢅ_sel_0_dꢁꢃꢁ
0
0
ꢃhꢄs dꢁꢃꢁ ꢄs dꢀꢄveꢆ ꢅꢆ gpꢅ ꢄf gpꢅ_sel==0
gpꢅ_dꢄg_dꢀꢄve_eꢆ
eꢆꢁbles tꢀꢄ-sꢃꢁꢃe dꢀꢄveꢀs ꢅꢆ GPo ꢅuꢃpuꢃ pꢁds
000
gpꢅ_ꢄꢆd_dꢀꢄve_dꢄs
000 = ꢁll GPo pꢁd dꢀꢄveꢀs eꢆꢁbled
xx1 = dꢄsꢁble GPo1 pꢁd dꢀꢄveꢀ
x1x = dꢄsꢁble GPo2 pꢁd dꢀꢄveꢀ
1xx = dꢄsꢁble GPo3 pꢁd dꢀꢄveꢀ
10:8
r/W
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
37
Application Support: Phone: 1-800-ANALOG-D
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HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 38. Reg 1Ch Phase Detector CSP Register
Bit
Type
Name
Default
Description
0= cyꢂle Slꢄp Pꢀeveꢆꢃꢄꢅꢆ (cSP) dꢄsꢁbled
4-bꢄꢃ vꢁlue ꢃꢅ ꢁdvꢁꢆꢂe ꢅꢀ ꢀeꢃꢁꢀd phꢁse deꢃeꢂꢃꢅꢀ ꢄꢆ
Vco ꢂyꢂles ꢄf ꢄꢃ ꢀeꢁꢂhes 2pꢄ , ꢄ.e. ꢂyꢂle slꢄp
pꢀeveꢆꢃꢄꢅꢆ. 1sꢃ bꢄꢃ ꢄs pꢅlꢁꢀꢄꢃy, eꢆꢁbled by ꢀsꢃb
3:0
r/W
pfds_sꢁꢃ_delꢃꢁn
0
cSP PFD Flꢄp-flꢅps rStB:
1 - ꢂꢅꢆꢃꢀꢅlled by ꢃhe pfds_ꢀsꢃb bꢄꢃ:
0 - ꢁuꢃꢅ-ꢂꢅꢆꢃꢀꢅlled by ꢃhe cSP lꢅgꢄꢂ
4
5
r/W
r/W
pfds_ꢀsꢃb_fꢅꢀꢂe
pfds_ꢀsꢃb
0
1
Fꢅꢀꢂes ꢃhe PFD ꢄꢆꢃꢅ ꢀeseꢃ, whꢄꢂh ꢃꢀꢄsꢃꢁꢃes ꢂhꢁꢀge
pump, fꢀeezes ꢂhꢁꢀge ꢅꢆ ꢃhe lꢅꢅp filꢃeꢀ, ꢁꢆd
heꢆꢂe ꢅpeꢆs ꢃhe lꢅꢅp. Pꢀꢅgꢀꢁm 0
cSP PFD FF ꢀsꢃb
1 - Eꢆꢁbles ꢃhe cyꢂle Slꢄp Pꢀeveꢆꢃꢄꢅꢆ (cSP)
feꢁꢃuꢀe ꢅf ꢃhe PFD (ꢁlsꢅ ꢆeed reg 1[15]=1)
Table 39. Reg 1Dh Reserved
Bit
Type
Name
Default
Description
23:0
r/W
reseꢀved
0
reseꢀved
Table 40. Reg 1Eh Temperature Sensor Register
Bit
Type
Name
Default
Description
Eꢆꢁble ꢃhe ꢃempeꢀꢁꢃuꢀe seꢆsꢅꢀ, dꢀꢁws ~2ma
ꢂuꢀꢀeꢆꢃ, musꢃ sꢃꢀꢅbe ꢃseꢆs_spꢄ_sꢃꢀꢅbe reg 00h
<3>
0
r/W
ꢃseꢆs_spꢄ_eꢆꢁble
0
Table 41. Reg 1Fh LD & Ramp Busy Read Only Register
Bit
Type
Name
Default
Description
0
ro
ꢀꢅ_lꢅꢂk_deꢃeꢂꢃ
0
0
0
1 = lꢅꢂked, 0 = uꢆlꢅꢂked
3:1
4
ro
ꢀꢅ_dsm_ꢅveꢀflꢅw
reseꢀved
1 = mꢅdulꢁꢃꢅꢀ ꢅveꢀflꢅw
reseꢀved
ro
Sweepeꢀ sꢃꢁꢃus flꢁg, seꢃ wheꢆ ꢀꢁmp ꢄs busy,
ꢂleꢁꢀed wheꢆ ꢁꢃ eꢆd ꢅf ꢀꢁmp ꢅꢀ ꢆꢅꢃ used
5
ro
ꢀꢅ_ꢀꢁmp_busy
0
Table 42. Reg 20h Reserved
Bit
Type
Name
Default
Description
23:0
ro
reseꢀved
20h
reseꢀved
Table 43. Reg 21h Temperature Sensor Read Only Register
Bit
Type
Name
Default
Description
cuꢀꢀeꢆꢃ tempeꢀꢁꢃuꢀe fꢀꢅm ꢃemp seꢆsꢅꢀ
lsb = 17.5°c
0000111 = temp >= 82.5°c
0000110 = temp
6:0
ro
ꢃseꢆs_ꢃempeꢀꢁꢃuꢀe
0
0000000 = temp <=-22.5°c
ꢃseꢆs_ꢃempeꢀꢁꢃuꢀe = flꢅꢅꢀ ((temp+40)/17.5)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
38
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Table 44. Reg 22h Reserved
Bit
Type
Name
Default
Description
23:0
ro
reseꢀved
0
reseꢀved
Outline Drawing
notES:
1. PacKaGE BoDY MatEriaL: LoW StrESS inJEction MoLDED
PLaStic SiLica anD SiLicon iMPrEGnatED.
2. LEaD anD GroUnD PaDDLE MatEriaL: coPPEr aLLoY.
3. LEaD anD GroUnD PaDDLE PLatinG: 100% MattE tin.
4. DiMEnSionS arE in incHES [MiLLiMEtErS].
5. LEaD SPacinG toLErancE iS non-cUMULatiVE.
6. PaD BUrr LEnGtH SHaLL BE 0.15mm MaX.
PaD BUrr HEiGHt SHaLL BE 0.25mm MaX.
7. PacKaGE WarP SHaLL not EXcEED 0.05mm
8. aLL GroUnD LEaDS anD GroUnD PaDDLE
MUSt BE SoLDErED to PcB rF GroUnD.
9. rEFEr to HittitE aPPLication notE
For SUGGEStED PcB LanD PattErn.
Package Information
Pꢁꢀꢃ numbeꢀ
Pꢁꢂkꢁge Bꢅdy Mꢁꢃeꢀꢄꢁl
Leꢁd Fꢄꢆꢄsh
MSL rꢁꢃꢄꢆg
MSL1 [2]
Pꢁꢂkꢁge Mꢁꢀkꢄꢆg [1]
H701
XXXX
HMc701LP6cE
rꢅHS-ꢂꢅmplꢄꢁꢆꢃ Lꢅw Sꢃꢀess iꢆjeꢂꢃꢄꢅꢆ Mꢅlded Plꢁsꢃꢄꢂ
100% mꢁꢃꢃe Sꢆ
[1] 4-Dꢄgꢄꢃ lꢅꢃ ꢆumbeꢀ XXXX
[2] Mꢁx peꢁk ꢀeflꢅw ꢃempeꢀꢁꢃuꢀe ꢅf 260 °c
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
39
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC701LP6CE
v09.1112
8 GHz 16-BIT FRACTIONAL-N PLL
Notes:
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesforits use, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication orotherwiseunderany patent orpatent rights of AnalogDevices.
Phone: 781-329-4700 • Order online at www.analog.com
40
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
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