HMC703LP4E [ADI]
8 GHz Fractional-N PLL with Sweeper;
| 型号： | HMC703LP4E |
| 厂家： | 
ADI |
| 描述： | 8 GHz Fractional-N PLL with Sweeper PC |
| 文件： | 总59页 (文件大小：2586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢀpꢁꢂꢃꢄ appꢄꢁꢂꢃꢅꢁꢆꢇꢈ
The HMC703LP4E iꢀ ideal for:
• Microwave Point-to-Point Radioꢀ
fꢊꢃꢅuꢉꢊꢈ
Wide band: DC - 8 GHz RF Input
Beꢀt Phaꢀe Noiꢀe and spuriouꢀ in the Induꢀtry:
-112 dBc/Hz @ 8 GHz Fractional, 50 kHz Offꢀet
• Baꢀe stationꢀ for Mobile Radio
(GsM, PCs, DCs, CDMA, WCDMA)
Figure of Merit
• Wireleꢀꢀ LANꢀ, WiMAX
• Communicationꢀ Teꢀt Equipment
• CATV Equipment
-230 dBc/Hz Fractional Mode
-233 dBc/Hz Integer Mode
High PFD rate: 100 MHz
• Automotive senꢀorꢀ
< 50 fꢀ RMs jitter
Frequency and Phaꢀe Modulation
Integrated Frequency sweeper
Triggered Frequency Hopping
External Triggering
• AEsA - Phaꢀed Arrayꢀ
• FMCW Radar syꢀtemꢀ
2
24 Lead 4x4 mm sMT Package: 16 mm
Gꢊꢇꢊꢉꢃꢄ Dꢊꢈꢂꢉꢁpꢅꢁꢆꢇ
fuꢇꢂꢅꢁꢆꢇꢃꢄ Dꢁꢃgꢉꢃm
The HMC703LP4E fractional ꢀyntheꢀizer iꢀ built upon
the high performance PLL platform alꢀo contained in
the HMC704LP4E and Hittite’ꢀ lateꢀt generation of
PLL+VCO productꢀ. Thiꢀ platform haꢀ the beꢀt phaꢀe-
noiꢀe and ꢀpuriouꢀ performance in the induꢀtry -
enabling higher order modulation ꢀchemeꢀ while
minimizing blocker effectꢀ in high performance radioꢀ.
In addition, the HMC703LP4E offerꢀ frequency ꢀweep
and modulation featureꢀ, external triggering, double-
buffering, exact frequency control, phaꢀe modulation
and more - while maintaining pin compatibility with the
HMC700LP4E PLL.
Exact frequency mode with a 24-bit fractional mod-
ulator provideꢀ the ability to generate fractional
frequencieꢀ with zero frequency error and very low
channel ꢀpuriouꢀ, an important feature for Digital Pre-
Diꢀtortion ꢀyꢀtemꢀ.
The ꢀerial interface offerꢀ read back capability and iꢀ
compatible with a wide variety of protocolꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 1
HMC703* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• HMC703 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• HMC703LP4E Evaluation Board
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Data Sheet
DISCUSSIONS
View all HMC703 EngineerZone Discussions.
• HMC703 Data Sheet
SAMPLE AND BUY
TOOLS AND SIMULATIONS
Visit the product page to see pricing options.
• ADIsimPLL™
TECHNICAL SUPPORT
REFERENCE MATERIALS
Product Selection Guide
Submit a technical question or find your regional support
number.
• RF, Microwave, and Millimeter Wave IC Selection Guide
DOCUMENT FEEDBACK
2017
Quality Documentation
Submit feedback for this data sheet.
• Package/Assembly Qualification Test Report: LP4, LP4B,
LP4C, LP4K (QTR: 2013-00487 REV: 04)
• Package/Assembly Qualification Test Report: Plastic
Encapsulated QFN (QTR: 05006 REV: 02)
• Semiconductor Qualification Test Report: BiCMOS-A (QTR:
2013-00235)
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 1. eꢄꢊꢂꢅꢉꢁꢂꢃꢄ spꢊꢂꢁfiꢂꢃꢅꢁꢆꢇꢈ
Unleꢀꢀ otherwiꢀe ꢀpecified, data iꢀ collected at 3.3 V, and 5.0 V (on charge-pump), 100 MHz reference, 50 MHz fPD
.
Min and Max are ꢀpecified acroꢀꢀ temperature range from -40 °C to 85 °C ambient.
Parameter
RF INPUT CHARACTERIsTICs
RF Input Frequency Range
Preꢀcaler Input Freq Range
Power Range
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
[6][7]
[1]
DC
DC
-15
-18
8000
4000
-3
MHz
MHz
dBm
dB
[1]
[13]
[15]
-10
-12
Return Loꢀꢀ
-7
REF INPUT CHARACTERIsTICs
Frequency Range (3.3V)
[1][8]
DC
50
6
350
MHz
dBm
dB
[12] with 100 Ω termination
off chip
Power from 50 Ω source
Return Loꢀꢀ
[15]
-16
1
-8
Ref Divider Range (14 bit)
PHAsE DETECTOR RATE
Integer Mode
16,383
[1]
DC
DC
DC
50
50
50
115
100
80
MHz
MHz
MHz
Fractional Mode B
Fractional Mode A
CHARGE PUMP
20 µA stepꢀ, Charge Pump
Gain = CP Current/2π
Ampꢀ/rad
CP Output Current
0.02
2.5
6
mA
mA
ꢀee “Charge Pump Gain”
ꢀection
CP HiK
3.5
POWER sUPPLIEs
RVDD, AVDD, VCCPs, VCCHF, VCCPD,
DVDD, VDDIO
2.7
2.7
3.3
5.0
3.5
5.2
V
V
VDDLs, VPPCP muꢀt be
equal
VDDLs, VPPCP Charge Pump
[9]
100 kHz PD
50 MHz PD
100 MHz PD
34
54
74
45
70
95
mA
mA
mA
3.3V - Current conꢀumption
All Modeꢀ
100 kHz PD
50 MHz PD w/ CP HiK
100 MHz PD w/ CP HiK
3
7
13
5
12
16
mA
mA
mA
5V - Current conꢀumption
Power Down Current
[10]
100
uA
V
Pin 12. Meaꢀured with
10 GΩ Meter
BIAs Reference Voltage
1.880
1.920
1.960
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 2
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 34. eꢄꢊꢂꢅꢉꢁꢂꢃꢄ spꢊꢂꢁfiꢂꢃꢅꢁꢆꢇꢈ (Continued)
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
PHAsE NOIsE [14]
Flicker Figure of Merit (FOM)[2]
Floor Figure of Merit [11]
-270
dBc/Hz
Integer HiK Mode
-236
-232
-232
-228
-233
-230
-230
-227
-231
-228
-227
-225
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Integer Normal Mode
Fractional HiK Mode [3]
Fractional Normal Mode [3]
Flicker Noiꢀe at f
PN
PN
= Flicker FOM +20log(f ) -10log(f
vco
)
dBc/Hz
dBc/Hz
offꢀet
flick
offꢀet
Phaꢀe Noiꢀe Floor at f
with f
= Floor FOM + 10log(f ) +20log(f
pd
/f
)
vco
VCO referred Phaꢀe Noiꢀe Contribution
of the PLL vꢀ f , f
pd
floor
vco pd
(PNflick /10)
(PNfloor /10)
)
PN = 10log(10
+ 10
dBc/Hz
fꢀ
f
offꢀet vco, pd
ssB 100Hz to 100MHz with
HMC508LP5E VCO
Jitter
sPURIOUs
Integer Boundary spurꢀ @~8GHz
50
[4][5]
offꢀetꢀ leꢀꢀ than loop band-
-60
47
-52
54
dBc
width, f = 50MHz
pd
LOGIC INPUTs
switching Theꢀhold (Vꢀw)
LOGIC OUTPUT
VIH/VIL within 50 mV of Vꢀw
38
% VDDIO
VOH Output High Voltage
VOL Output Low Voltage
Output impedance : Pull Up
Output impedance : Pull Dn
VDDIO
0
V
V
VDDIO=3.3 V
VDDIO=3.3 V
115
130
150
135
180
210
Ohm
Ohm
DC load
1.5
mA
Digital Output Driver Delay
sCK to Digital Output Delay
0.5nꢀ+0.2nꢀ/pF
8.2nꢀ+0.2nꢀ/pF
nꢀ
nꢀ
1.7nꢀec with a 3 pF load
RF Divider Range
>4GHz Integer Mode
< 4GHz Integer Mode
> 4GHz Fractional Mode
< 4GHz Fractional Mode
16 bit , Even valueꢀ only
16 bit , All valueꢀ
16 bit
32
16
131,070
65,535
40.0
20.0
131,065.0
65,531.0
16 bit
[1] Frequency iꢀ guaranteed acroꢀꢀ proceꢀꢀ, voltage and temperature from -400C to 850C.
[2] With high charge-pump current, +12dBm 100MHz ꢀine reference
[3] Fractional FOM degradeꢀ about 3dB/octave for preꢀcaler input frequencieꢀ below 2GHz
[4] Uꢀing 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency. Larger
offꢀetꢀ produce better reꢀultꢀ. see the “spuriouꢀ Performance” ꢀection for more information.
[5] Meaꢀured with the HMC703LP4E evaluation board. Board deꢀign and iꢀolation will affect performance.
[6] Internal divide-by-2 ꢀhould be enabled for frequencieꢀ >4GHz
[7] At low RF Frequency, Riꢀe and fall timeꢀ ꢀhould be leꢀꢀ than 1nꢀ to maintain performance
[8] slew rate of greater or equal to 0.5 V/nꢀ
[9] Current conꢀumption dependꢀ upon operating mode and frequency of the VCO. Typical valueꢀ are for fractional mode.
[10] Reference input diꢀconnected
[11] Min/Max verꢀuꢀ temperature and ꢀupply, under typical reference & RF frequencieꢀ and power levelꢀ
[12] slew > 0.5V/nꢀ iꢀ recommended , ꢀee Table 7, Figure 5, Figure 6 for more information.
[13] Operable with reduced ꢀpectral performance outꢀide of thiꢀ range.
[14] Thiꢀ ꢀection ꢀpecifieꢀ the Phaꢀe Noiꢀe contribution of the PLL, ꢀolution phaꢀe noiꢀe with a given VCO, loop filter and
reference requireꢀ a cloꢀed loop calculation uꢀing Hittite PLL Deꢀign Tool.
[15] Aꢀ meaꢀured on HMC703LP4E Evaluation board, with 100Ohm external termination.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 3
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tyPical PerforMance cHaracteristics
Unleꢀꢀ otherwiꢀe ꢀpecified, plotꢀ are meaꢀured with a 50 MHz PD rate, VCO near 8 GHz, RF power ≈ -10 dBm, and a Wenzel 100 MHz ꢀinuꢀoid
reference. The operating modeꢀ in the following plotꢀ refer to Integer (int), Fractional Modeꢀ A and B, HiKcp (HiK).
fꢁguꢉꢊ 2. fꢄꢁꢂkꢊꢉ foM vꢈ. Mꢆdꢊ ꢃꢇd tꢊmp,
fꢁguꢉꢊ 1. fꢄꢆꢆꢉ foM vꢈ. Mꢆdꢊ ꢃꢇd tꢊmp,
2.5 ma cP cuꢉꢉꢊꢇꢅ
-266
2.5 ma cP cuꢉꢉꢊꢇꢅ
-226
Frac Mode A
-228
-267
Frac Mode A
-268
HiK Frac Mode A
-269
-230
Integer Mode
-270
-232
HiK Frac Mode A
Integer Mode
HiK Integer
HiK Integer
-271
-234
-272
-236
-273
-40
0
40
TEMPERATURE (C)
80
-40
-20
0
20
40
60
80
TEMPERATURE (C)
fꢁguꢉꢊ 3. fꢄꢆꢆꢉ foM vꢈ. ouꢅpuꢅ fꢉꢊquꢊꢇꢂꢀ
fꢁguꢉꢊ 4. fꢄꢁꢂkꢊꢉ foM vꢈ. ouꢅpuꢅ
ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
-220
fꢉꢊquꢊꢇꢂꢀ ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
-265
-222
Frac Mode B
Frac Mode A
-266
Mode B
-224
-226
-228
-230
-232
-234
-267
Mode A
Mode A HIK
HiK Frac Mode B
-268
Mode B HIK
Integer
HiK Frac Mode A
-269
-270
Int
Integer HIK
1
2
4
8
1
2
4
8
FREQUENCY (GHz)
FREQUENCY (GHz)
fꢁguꢉꢊ 5. fꢄꢆꢆꢉ foM vꢈ. rꢊꢋꢊꢉꢊꢇꢂꢊ Pꢆwꢊꢉ
fꢁguꢉꢊ 6. fꢄꢁꢂkꢊꢉ foM vꢈ. rꢊꢋꢊꢉꢊꢇꢂꢊ Pꢆwꢊꢉ
[1]
[1]
ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
REFERENCE POWER (Vpp)
REFERENCE POWER (Vpp)
0.40
-226
0.50
0.63
0.80
1
1.26
1.59
2
2.52
0.40
0.50
0.63
0.80
1
1.26
1.59
2
2.52
-268
-269
-270
-271
-272
Frac Mode B
Frac Mode B
-228
-230
-232
-234
HiK Frac Mode B
Integer Mode
HiK Frac Mode B
Integer Mode
HiK Integer Mode
HiK Integer
-4
-2
0
2
4
6
8
10
12
-4
-2
0
2
4
6
8
10
12
REFERENCE POWER (dBm)
REFERENCE POWER (dBm)
[1] 100 MHz sinuꢀoidal Wenzel reference.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 4
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
fꢁguꢉꢊ 7. fꢄꢁꢂkꢊꢉ foM vꢈ. cP cuꢉꢉꢊꢇꢅ,
fꢁguꢉꢊ 8. fꢄꢆꢆꢉ foM vꢈ. cP cuꢉꢉꢊꢇꢅ,
fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ B, 2.5 ma cP cuꢉꢉꢊꢇꢅ
fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ B, 2.5 ma cP cuꢉꢉꢊꢇꢅ
-216
-260
-218
-220
-222
-224
-226
-228
-230
-262
-264
-266
-268
-270
0.5
1
1.5
2
2.5
3
0.5
1
1.5
2
2.5
3
CP CURRENT (mA)
CP CURRENT (mA)
fꢁguꢉꢊ 9. fꢄꢁꢂkꢊꢉ foM vꢈ. cP Vꢆꢄꢅꢃgꢊ, cP
cuꢉꢉꢊꢇꢅ = 2.5 ma
fꢁguꢉꢊ 10. fꢄꢆꢆꢉ foM vꢈ. cP Vꢆꢄꢅꢃgꢊ,
[1]
[1]
cP cuꢉꢉꢊꢇꢅ = 2.5 ma
-222
-260
-262
-264
-266
-268
-270
-272
Integer
Fractional
-224
-226
-228
-230
-232
0
1
2
3
4
5
0
1
2
3
4
5
CP VOLTAGE (V)
CP VOLTAGE (V)
fꢁguꢉꢊ 12. fꢄꢆꢆꢉ foM vꢈ. cP Vꢆꢄꢅꢃgꢊ,
HꢁKꢂp + cP cuꢉꢉꢊꢇꢅ = 6 ma
-222
fꢁguꢉꢊ 11. fꢄꢁꢂkꢊꢉ foM vꢈ. cP Vꢆꢄꢅꢃgꢊ,
[2]
[2]
HꢁKꢂp + cP cuꢉꢉꢊꢇꢅ = 6 ma
-266
-268
-270
-272
-274
-276
-224
Floor Int FOM
Floor Frac FOM
-226
-228
-230
-232
-234
0
1
2
3
4
5
0
1
2
3
4
5
CP VOLTAGE (V)
CP VOLTAGE (V)
[2] Active Loop Filter, with DC biaꢀ point on -ve leg of op-amp ꢀwept.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 5
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
fꢁguꢉꢊ 14. fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Pꢊꢉꢋꢆꢉmꢃꢇꢂꢊ, exꢃꢂꢅ
fꢉꢊquꢊꢇꢂꢀ Mꢆdꢊ oꢇ ꢃꢅ 8013.6 MHꢌ
fꢁguꢉꢊ 13. tꢀpꢁꢂꢃꢄ Phꢃꢈꢊ nꢆꢁꢈꢊ & spuꢉ
[4]
[3]
Pꢊꢉꢋꢆꢉmꢃꢇꢂꢊ ꢃꢅ 8 GHꢌ + 200 kHꢌ
-80
-100
-120
-140
-160
-180
-60
-80
-100
-120
-140
-160
-180
102
103
104
105
106
107
108
102
103
104
105
106
107
108
OFFSET (Hz)
OFFSET(Hz)
fꢁguꢉꢊ 15. iꢇꢅꢊgꢊꢉ Bꢆuꢇdꢃꢉꢀ spuꢉ ꢃꢅ
[6]
[5]
fꢁguꢉꢊ 16. rf iꢇpuꢅ lꢁmꢁꢅꢈ
30
8 GHꢌ + 20 kHꢌ vꢈ. chꢃꢉgꢊ Pump oꢋꢋꢈꢊꢅ
-20
20 kHz Offset Spur
10 kHz Offset Spur
-30
-40
-50
-60
-70
-80
-90
20
10
Recommended
Operating
Range
0
-10
-20
-30
-40
No Divider
Divide By 2
RECOMMENDED OPERATING RANGE
0
2000
4000
6000
8000
10000
-800
-600
-400
-200
0
200
400
600
800
CP OFFSET CURRENT (uA)
RF INPUT FREQUENCY AT PRESCALAR (MHz)
fꢁguꢉꢊ 17. Mꢆdꢊꢄꢄꢊd vꢈ. Mꢊꢃꢈuꢉꢊd Phꢃꢈꢊ
fꢁguꢉꢊ 18. Mꢆdꢊꢄꢄꢊd vꢈ. Mꢊꢃꢈuꢉꢊd Phꢃꢈꢊ
[7]
[8]
nꢆꢁꢈꢊ, iꢇꢅꢊgꢊꢉ Mꢆdꢊ HꢁK ꢃꢅ 8 GHꢌ
nꢆꢁꢈꢊ, fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ B, HꢁK ꢃꢅ ~ 8 GHꢌ
-80
-80
Total Noise Simulated Using
Hittite PLL Design Software
Total Noise Simulated Using
Hittite PLL Design Software
-100
-100
Modelled PLL Floor
Modelled PLL Floor
-120
-120
Measured Total Noise
-140
Measured Total Noise
-140
-160
-180
INTEGRATED RMS JITTER = 36.1 fs
-160
100 Hz to 100 MHz
INTEGRATED RMS JITTER = 44.2 fs
100 Hz to 100 MHz
-180
102
102
103
104
105
106
107
108
103
104
105
106
107
108
OFFSET (Hz)
OFFSET (Hz)
[3] Output frequency = 8 GHz + 200 kHz uꢀing HMC508LP5E VCO, Reference Input = 100 MHz, PD frequency = 100 MHz, CP current = 2.5 mA,
Fractional Mode B, 20 kHz bandwidth Loop Filter. spur at 200kHz due to RF ꢀignal at 8GHz + 200kHz, ꢀpur at 100kHz due to preꢀcaler input at
4GHz+100kHz. Reference feedthrough ꢀpur at 100 MHz offꢀet.
[4] Exact Frequency Mode channel ꢀpacing 100 kHz, Fractional N, Rfout = 8013.6 MHz uꢀing HMC508LP5E VCO, Reference Input = 100 MHz, PD
frequency = 100 MHz, Preꢀcaler divide-by-2 ꢀelected. 20 kHz Loop Filter bandwidth, reference feedthrough ꢀpur at 100 MHz offꢀet.
[5] Tuned to 8 GHz + 20 kHz, Preꢀcaler at 4 GHz + 10 kHz, Loop bandwidth >> 20 kHz, Reference Frequency 50 MHz. Offꢀet polarity ꢀhould be
poꢀitive for inverting configurationꢀ and negative otherwiꢀe.
[6] Low frequency minimum power levelꢀ not characterized. Low frequency limitation iꢀ only a function of external AC coupling capacitance ꢀignal
ꢀlew rate.
[7] HiK integer mode meaꢀured at 8 GHz, Preꢀcalar at 4 GHz, 50 MHz reference frequency.
[8] Active Fractional B Mode (Preꢀcalar @ 4 GHz + 2.5 kHz), Reference Frequency 50 MHz.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
6 - 6
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
fꢁguꢉꢊ 20. fꢄꢁꢂkꢊꢉ foM nꢊꢃꢉ 8 GHꢌ vꢈ. rf
fꢁguꢉꢊ 19. fꢄꢆꢆꢉ foM nꢊꢃꢉ 8 GHꢌ vꢈ rf
iꢇpuꢅ Pꢆwꢊꢉ ꢃꢇd Mꢆdꢊ
iꢇpuꢅ Pꢆwꢊꢉ ꢃꢇd Mꢆdꢊ
-267
-224
Frac Mode A
-267.5
Frac Mode B
-226
-268
Frac Mode B
HiK Mode B
Frac Mode A
-268.5
-228
HiK Mode A
-269
HiK Mode B
-230
-269.5
Integer
-270
-232
HiK Mode A
-270.5
HiK Integer
HiK Integer
-271
-234
-25
-20
-15
-10
-5
0
5
-25
-20
-15
-10
-5
0
5
RF POWER (dBm)
RF POWER (dBm)
fꢁguꢉꢊ 21. rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ sꢊꢇꢈꢁꢅꢁvꢁꢅꢀ,
fꢁguꢉꢊ 22. rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ sꢊꢇꢈꢁꢅꢁvꢁꢅꢀ
[9]
[9]
squꢃꢉꢊ Wꢃvꢊ, 50 Ω
sꢁꢇuꢈꢆꢁd Wꢃvꢊ, 50 Ω
-215
-200
-205
-210
50 MHz
14 MHz sq
25 MHz sq
50 MHz sq
100 MHz sq
-220
25 MHz
25 MHz
-215
-225
14 MHz
-220
14 MHz
50 MHz
-225
-230
-230
100 MHz
-10
REFERENCE POWER (dBm)
100 MHz
-235
-15
-235
-10
-5
0
5
10
-20
-15
-5
0
5
REFERENCE POWER (dBm)
[10]
[11]
fꢁguꢉꢊ 23. rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ rꢊꢅuꢉꢇ lꢆꢈꢈ
fꢁguꢉꢊ 24. rf iꢇpuꢅ rꢊꢅuꢉꢇ lꢆꢈꢈ
0
0
-5
-10
-15
-20
-5
-10
-15
-20
0
2000
4000
6000
8000
10000
0
50
100
150
200
250
300
350
RF INPUT FREQUENCY (MHz)
REFERENCE INPUT FREQUENCY (MHz)
[9] Meaꢀured with a 100 Ω external reꢀiꢀtor termination, reꢀulting in 50Ohm effective input impedance.. see “Reference Input stage” for more detailꢀ.
Full FOM performance up to maximum 3.3 Vpp input voltage.
[10] Meaꢀured with a 100 Ω external termination AC coupled on HMC703LP4E evaluation board, aꢀ in Figure 35.
[11] Meaꢀured with a 100 Ω external termination AC coupled on HMC703LP4E evaluation board, aꢀ in Figure 37.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 7
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
fꢁguꢉꢊ 25. 2-Wꢃꢀ auꢅꢆ swꢊꢊp
3750
3700
3650
3600
3550
3500
3450
3400
3350
0
5
10
15
20
TIME (milliseconds)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 8
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 2. Pꢁꢇ Dꢊꢈꢂꢉꢁpꢅꢁꢆꢇꢈ
Pin Number
Function
Deꢀcription
1
2
3
4
5
6
7
sCK
CMOs Input: serial port clock
CMOs Input: serial port data
sDI
DVDD
VDDIO
LD_sDO
TRIG
Power supply for digital - Nominal 3.3 V MAX 25 mA, f
dependent
PD
Power supply for Digital IO - 3.3 V, 8 mA MAX (only when driving LD_sDO)
CMOs Output: General Purpoꢀe Output - Lock Detect, serial Data Out, otherꢀ, selectable
CMOs Input : External Trigger pin.
N/C
No Connect
8
VDDPs
Power supply for RF Divider, Nominal 3.3 V 35 mA MAX
No Connect
9
N/C
10
VCOIP
Differential RF Inputꢀ. Normally AC Coupled, 2 V DC biaꢀ generated internally. For single Ended
operation, RFN muꢀt be AC coupled to the ground plane, typically 100 pF ceramic. DC Biaꢀ of 2.3 V iꢀ
generated internally
11
VCOIN
12
13
14
15
16
VDDHF
VDDLs
VDDCPA
CP
Power supply for RF Buffer, Nominal 3.3 V, 6 mA MAX
Power supply for PFD to CP Level shifterꢀ, Nominal 5 V, 5 mA MAX, f
Power supply for charge pump, Nominal 5 V, 10 mA MAX
Charge pump output
dependent.
PD
AVDD
Power ꢀupply for analog biaꢀ generation, Nominal 3.3 V, 2 mA MAX
External bypaꢀꢀ decoupling for preciꢀion biaꢀ circuitꢀ, 1.920 V +/-2 mV
17
BIAs
NOTE: BIAs ref voltage cannot drive an external load. Muꢀt be meaꢀured with 10 GΩ meter ꢀuch aꢀ
Agilent 34410A, normal 10 MΩ DVM will read erroneouꢀly.
18
19
20
RVDD
N/C
Power supply for Reference path, Nominal 3.3 V. 15 mA MAX reference dependent
No Connect
XREFP
Reference Input. DC biaꢀ iꢀ generated internally. Normally AC coupled externally.
Power supply for phaꢀe detector. Nominally 3.3 V. Decoupling for thiꢀ ꢀupply iꢀ critical. 5 mA MAX, f
dependent
PD
21
VDDPD
22
23
24
N/C
CEN
sEN
No Connect
CMOs Input: Hardware Chip Enable
CMOs Input: serial port latch enable
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 9
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 3. abꢈꢆꢄuꢅꢊ Mꢃxꢁmum rꢃꢅꢁꢇgꢈ
Parameter
Rating
-0.3 V to +3.6 V
-0.3 V to +5.5 V
Max Vdc to paddle on ꢀupply pinꢀ
3,4,8,12,16,18,21
VDDLs, VPPCP
VCOIN, VCOIP single Ended DC
VCOIN, VCOIP Differential DC
VCOIN, VCOIP single Ended AC 50Ohm
VCOIN, VCOIP Differential AC 50Ohm
Digital Load
VCCHF -0.2 V
5.2 V
+7 dBm
+13 dBm
1 kΩ min
Digital Input 1.4 V to 1.7 V min riꢀe time
Digital Input Voltage Range
Thermal Reꢀiꢀtance (Jxn to Gnd Paddle)
Operating Temperature Range
storage Temperature Range
Maximum Junction Temperature
Reflow soldering
20 nꢀec
-0.25 to VDDIO+0,5 V
25 0C/W
-40 OC to +85 O
-65 OC to + 125 O
+150 O
C
C
C
Peak Temperature
260 O
C
Time at Peak Temperature
EsD senꢀitivity HBM
40 ꢀec
Claꢀꢀ 1B
streꢀꢀeꢀ above thoꢀe liꢀted under Abꢀolute Maximum Ratingꢀ may cauꢀe permanent damage to the device. Thiꢀ iꢀ
a ꢀtreꢀꢀ rating only; functional operation of the device at theꢀe or any other conditionꢀ above thoꢀe indicated in the
operational ꢀection of thiꢀ ꢀpecification iꢀ not implied. Expoꢀure to abꢀolute maximum rating conditionꢀ for extended
periodꢀ may affect device reliability.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
6 - 10
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
ouꢅꢄꢁꢇꢊ Dꢉꢃwꢁꢇg
NOTEs:
[1] PACKAGE BODY MATERIAL: LOW sTREss INJECTION MOLDED PLAsTIC sILICA AND sILICON IMPREGNATED.
[2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.
[3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN.
[4] DIMENsIONs ARE IN INCHEs [MILLIMETERs].
[5] LEAD sPACING TOLERANCE Is NON-CUMULATIVE.
[6] PAD BURR LENGTH sHALL BE 0.15mm MAX. PAD BURR HEIGHT sHALL BE 0.05mm MAX.
[7] PACKAGE WARP sHALL NOT EXCEED 0.05mm
[8] ALL GROUND LEADs AND GROUND PADDLE MUsT BE sOLDERED TO PCB RF GROUND.
[9] REFER TO HITTITE APPLICATION NOTE FOR sUGGEsTED PCB LAND PATTERN.
tꢃbꢄꢊ 4. Pꢃꢂkꢃgꢊ iꢇꢋꢆꢉmꢃꢅꢁꢆꢇ
[1]
Part Number
Package Body Material
Lead Finiꢀh
MsL Rating
MsL1[2]
Package Marking
H703
XXXX
HMC703LP4E
RoHs-compliant Low streꢀꢀ Injection Molded Plaꢀtic
100% matte sn
[1] 4-Digit lot number XXXX
[2] Max peak reflow temperature of 260°C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 11
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
evꢃꢄuꢃꢅꢁꢆꢇ PcB
The circuit board uꢀed in the application ꢀhould uꢀe RF circuit deꢀign techniqueꢀ. signal lineꢀ ꢀhould have 50
Ohmꢀ impedance while the package ground leadꢀ and expoꢀed paddle ꢀhould be connected directly to the
ground plane ꢀimilar to that ꢀhown. A ꢀufficient number of via holeꢀ ꢀhould be uꢀed to connect the top and
bottom ground planeꢀ. The evaluation circuit board ꢀhown iꢀ available from Hittite upon requeꢀt.
tꢃbꢄꢊ 5. evꢃꢄuꢃꢅꢁꢆꢇ oꢉdꢊꢉ iꢇꢋꢆꢉmꢃꢅꢁꢆꢇ
Item
Contentꢀ
Part Number
HMC703LP4E Evaluation PCB
UsB Interface Board
Evaluation Kit
6’ UsB A Male to UsB B Female Cable
CD ROM (Containꢀ Uꢀer Manual, Evaluation PCB schematic, Evaluation software, Hittite
PLL Deꢀign software)
EKIT01-HMC703LP4E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 12
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
evꢃꢄuꢃꢅꢁꢆꢇ PcB Bꢄꢆꢂk Dꢁꢃgꢉꢃm
evꢃꢄuꢃꢅꢁꢆꢇ PcB sꢂhꢊmꢃꢅꢁꢂ
To view Evaluation PCB schematic pleaꢀe viꢀit www.hittite.com and chooꢀe HMC703LP4E from “search by Part
Number” pull down menu to view the product ꢀplaꢀh page.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 13
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
thꢊꢆꢉꢀ oꢋ opꢊꢉꢃꢅꢁꢆꢇ
Pll Bꢃꢈꢁꢂꢈ
In itꢀ moꢀt trivial form, a ꢀyntheꢀizer IC, ꢀuch aꢀ the HMC703LP4E formꢀ the heart of the control loop to multiply a
low frequency reference ꢀource up to a higher frequency. The phaꢀe detector (PD) and charge-pump (CP) drive the
tuning ꢀignal of a voltage-controlled oꢀcillator in an attempt to bring the phaꢀeꢀ, at the phaꢀe-detector input, into
alignment. If the loop can manage thiꢀ, it meanꢀ that the phaꢀe detector inputꢀ (reference and DIV) muꢀt alꢀo be at
the ꢀame frequency. since the frequency of the DIV ꢀignal = fvco / N, thiꢀ meanꢀ the control loop muꢀt have forced
the frequency of the VCO output muꢀt be locked to N x fpd.
Figure 26. Typical PLL
In integer ꢀyntheꢀizerꢀ, N can only take on diꢀcrete valueꢀ (eg. 200, 201, etc.). In fractional ꢀyntheꢀizerꢀ, ꢀuch aꢀ the
HMC703LP4E and otherꢀ, N can alꢀo take on fractional levelꢀ, eg. N=20.4. In theory, the fractional divider normally
permitꢀ higher phaꢀe-detector frequencieꢀ for a given output frequency, with aꢀꢀociated improvementꢀ in ꢀignal
quality (phaꢀe-noiꢀe). Unfortunately, fractional ꢀyntheꢀizerꢀ ꢀuffer from imperfectionꢀ which do not effect integer
ꢀyntheꢀizerꢀ. Theꢀe problemꢀ can effect the phaꢀe noiꢀe, but more ꢀeriouꢀly they tend to manifeꢀt aꢀ ꢀpuriouꢀ
emiꢀꢀionꢀ - and theꢀe ꢀpurꢀ are the moꢀt ꢀeriouꢀ drawback of fractional ꢀyntheꢀiꢀ.
Hittite’ꢀ fractional ꢀyntheꢀizer family (including the HMC703LP4E) offer draꢀtic performance advantageꢀ over other
fractional ꢀyntheꢀizerꢀ in the induꢀtry.
The HMC703LP4E ꢀyntheꢀizer conꢀiꢀtꢀ of the following functional blockꢀ:
1. Reference Path Input Buffer and ’R’ Divider
2. VCO Path Input Buffer, RF Divide-by-2 and Multi-Moduluꢀ ’N’ Divider
�
Fractional Modulator
3.
Δ
4. Phaꢀe Detector
5. Charge Pump
6. Main serial Port
7. Lock Detect and Regiꢀter Control
8. Power On Reꢀet Circuit
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 14
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Hꢁgh Pꢊꢉꢋꢆꢉmꢃꢇꢂꢊ lꢆw spuꢉꢁꢆuꢈ opꢊꢉꢃꢅꢁꢆꢇ
The HMC703LP4E haꢀ been deꢀigned for the beꢀt phaꢀe noiꢀe and low ꢀpuriouꢀ content poꢀꢀible in an integrated
ꢀyntheꢀizer. spuriouꢀ ꢀignalꢀ in a ꢀyntheꢀizer can occur in any mode of operation and can come from a number of
ꢀourceꢀ.
fꢁguꢉꢊ ꢆꢋ Mꢊꢉꢁꢅ, nꢆꢁꢈꢊ fꢄꢆꢆꢉ, ꢃꢇd fꢄꢁꢂkꢊꢉ nꢆꢁꢈꢊ Mꢆdꢊꢄꢈ
The phaꢀe noiꢀe of an ideal phaꢀe locked oꢀcillator iꢀ dependent upon a number of factorꢀ:
a. Frequency of the VCO, and the Phaꢀe detector
b. VCO senꢀitivity, kvco, VCO and Reference Oꢀcillator phaꢀe noiꢀe profileꢀ
c. Charge Pump current, Loop Filter and Loop Bandwidth
d. Mode of Operation: Integer, Fractional modulator ꢀtyle
The contributionꢀ of the PLL to the output phaꢀe noiꢀe can be characterized in termꢀ of a Figure of Merit (FOM) for both
the PLL noiꢀe floor and the PLL flicker (1/f) noiꢀe regionꢀ, aꢀ followꢀ:
where:
2
Фp
fo
Phaꢀe Noiꢀe Contribution of the PLL (radꢀ2/Hz)
Frequency of the VCO (Hz)
fpd
fm
Fpo
Frequency of the Phaꢀe Detector (Hz)
Frequency offꢀet from the carrier (Hz)
Figure of Merit (FOM) for the phaꢀe noiꢀe floor
Fp1
Figure of Merit (FOM) for the flicker noiꢀe region
Fp1f02 Fp0f02
(eQ 1)
2
p
PLL Phase Noise
Contribution
�
f0,fm,fpd
=
+
fm
fpd
Figure 27. Figure of Merit Noise Models for the PLL
If the free running phaꢀe noiꢀe of the VCO iꢀ known, it may alꢀo be repreꢀented by a figure of merit for both 1/f2 , Fv2,
and the 1/f3, Fv3, regionꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 15
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
F
3f02
fm3
F
n 2f02
fm2
n
(eQ 2)
VCO Phase Noise
Contribution
2
n
�
f0,fm
=
+
The Figureꢀ of Merit are eꢀꢀentially normalized noiꢀe parameterꢀ for both the PLL and VCO that can allow quick eꢀti-
mateꢀ of the performance levelꢀ of the PLL at the required VCO, offꢀet and phaꢀe detector frequency. Normally, the PLL
IC noiꢀe dominateꢀ inꢀide the cloꢀed loop bandwidth of the ꢀyntheꢀizer, and the VCO dominateꢀ outꢀide the loop band-
width at offꢀetꢀ far from the carrier. Hence a quick eꢀtimate of the cloꢀed loop performance of the PLL can be made by
ꢀetting the loop bandwidth equal to the frequency where the PLL and free running phaꢀe noiꢀe are equal.
The Figure of Merit iꢀ alꢀo uꢀeful in eꢀtimating the noiꢀe parameterꢀ to be entered into a cloꢀed loop deꢀign tool ꢀuch aꢀ
Hittite PLL Deꢀign, which can give a much more accurate eꢀtimate of the cloꢀed loop phaꢀe noiꢀe and PLL loop filter
component valueꢀ.
Given an optimum loop deꢀign, the approximate cloꢀed loop performance iꢀ ꢀimply given by the minimum of the PLL
and VCO noiꢀe contributionꢀ.
(eQ 3)
Pll-Vco nꢆꢁꢈꢊ
� 2 = min � 2p,�n2
An example of the uꢀe of the FOM valueꢀ to make a quick eꢀtimate of PLL performance: Eꢀtimate the phaꢀe noiꢀe of an
8 GHz cloꢀed loop PLL with a 100 MHz reference operating in Fractional Mode B with the VCO operating at 8 GHz and
the VCO divide by 2 port driving the PLL at 4 GHz. Aꢀꢀume an HMC509 VCO haꢀ free running phaꢀe noiꢀe in the 1/f2
region at 1 MHz offꢀet of -135 dBc/Hz and phaꢀe noiꢀe in the 1/f3 region at 1 kHz offꢀet of -60 dBc/Hz.
Fv1_dB
=
-135
Free Running VCO PN at 1MHz offꢀet
PNoiꢀe normalized to 1Hz offꢀet
Pnoiꢀe normalized to 1Hz carrier
VCO FOM
+20*log10(1e6)
-20*log10(8e9)
= -213.1 dBc/Hz at 1Hz
Fv3
=
-60
Free Running VCO PN at 1kHz offꢀet
PNoiꢀe normalized to 1Hz offꢀet
Pnoiꢀe normalized to 1Hz carrier
VCO Flicker FOM
_dB
+30*log10(1e3)
-20*log10(8e9)
= -168 dBc/Hz at 1Hz
We can ꢀee from Figure 3 and Figure 4 reꢀpectively that the PLL FOM floor and FOM flicker parameterꢀ in fractional
Mode A:
Fpo_dB = -227 dBc/Hz at 1Hz
Fp1_dB = -266 dBc/Hz at 1Hz
Each of the Figure of Merit equationꢀ reꢀult in ꢀtraight lineꢀ on a log-frequency plot. We can ꢀee in the example below
the reꢀulting
PLL floor at 8 GHz = Fpo_dB +20log10(fvco) -10log10(fpd) = -227+198 -80 = -109 dBc/Hz
PLL Flicker at 1 kHz = Fp1_dB+20log10(fvco)-10log10(fm) = -266 +198-30 = -98 dBc/Hz
VCO at 1 MHz = Fv1_dB+20log10(fvco)-20log10(fm)= -213 +198-120
= -135 dBc/Hz
VCO flicker at 1 kHz = Fv3_dB+20log10(fvco)-30log10(fm)= -168 +198-90 = -60 dBc/Hz
Theꢀe four valueꢀ help to viꢀualize the main contributorꢀ to phaꢀe noiꢀe in the cloꢀed loop PLL. Each fallꢀ on a linear
line on the log-frequency phaꢀe noiꢀe plot ꢀhown in Figure 27.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
-20
-40
VCO at 1 kHz
-60
-80
-100
-120
-140
-160
-180
PLL Floor
PLL at 1 kHz
VCO at 1 MHz
100
1000
104
105
106
107
108
FREQUENCY OFFSET (Hz)
Figure 28. Figure of Merit Example
It ꢀhould be noted that actual phaꢀe noiꢀe near the corner frequency of the loop bandwidth iꢀ affected by loop parame-
terꢀ and one ꢀhould uꢀe a more complete deꢀign tool ꢀuch aꢀ Hittite PLL Deꢀign for better eꢀtimateꢀ of the phaꢀe noiꢀe
performance. Noiꢀe modelꢀ for each of the componentꢀ in Hittite PLL Deꢀign can be derived from the FOM equationꢀ
or can be provided by Hittite applicationꢀ engineering.
spuꢉꢁꢆuꢈ Pꢊꢉꢋꢆꢉmꢃꢇꢂꢊ
iꢇꢅꢊgꢊꢉ opꢊꢉꢃꢅꢁꢆꢇ
The VCO alwayꢀ operateꢀ at an integer multiple of the PD frequency in an integer ꢀyntheꢀizer. In general, ꢀpuriouꢀ
ꢀignalꢀ originating from an integer ꢀyntheꢀizer can only occur at multipleꢀ of the PD frequency. Theꢀe unwanted outputꢀ
are often ꢀimply referred to aꢀ reference ꢀidebandꢀ.
spurꢀ unrelated to the reference frequency muꢀt originate from outꢀide ꢀourceꢀ. External ꢀpuriouꢀ ꢀourceꢀ can
modulate the VCO indirectly through power ꢀupplieꢀ, ground, or output portꢀ, or bypaꢀꢀ the loop filter due to poor
iꢀolation of the filter. It can alꢀo ꢀimply add to the output of the ꢀyntheꢀizer.
The HMC703LP4E haꢀ been deꢀigned and teꢀted for ultra-low ꢀpuriouꢀ performance. Reference ꢀpuriouꢀ levelꢀ are
typically below -100 dBc with a well deꢀigned board layout. A regulator with low noiꢀe and high power ꢀupply rejection,
ꢀuch aꢀ the HMC860LP3E, iꢀ recommended to minimize external ꢀpuriouꢀ ꢀourceꢀ.
Reference ꢀpuriouꢀ levelꢀ of below -100 dBc require ꢀuperb board iꢀolation of power ꢀupplieꢀ, iꢀolation of the VCO
from the digital ꢀwitching of the ꢀyntheꢀizer and iꢀolation of the VCO load from the ꢀyntheꢀizer. Typical board layout,
regulator deꢀign, demo boardꢀ and application information are available for very low ꢀpuriouꢀ operation. Operation
with lower levelꢀ of iꢀolation in the application circuit board, from thoꢀe recommended by Hittite, can reꢀult in higher
ꢀpuriouꢀ levelꢀ.
Of courꢀe, if the application environment containꢀ other interfering frequencieꢀ unrelated to the PD frequency, and if
the application iꢀolation from the board layout and regulation are inꢀufficient, then the unwanted interfering frequencieꢀ
will mix with the deꢀired ꢀyntheꢀizer output and cauꢀe additional ꢀpurꢀ. The level of theꢀe ꢀpurꢀ iꢀ dependant upon
iꢀolation and ꢀupply regulation or rejection (PsRR).
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 17
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
fꢉꢃꢂꢅꢁꢆꢇꢃꢄ opꢊꢉꢃꢅꢁꢆꢇ
Unlike an integer ꢀyntheꢀizer, ꢀpuriouꢀ ꢀignalꢀ in a fractional ꢀyntheꢀizer can occur due to the fact that the VCO
operateꢀ at frequencieꢀ unrelated to the PD frequency. Hence intermodulation of the VCO and the PD harmonicꢀ can
cauꢀe ꢀpuriouꢀ ꢀidebandꢀ. spuriouꢀ emiꢀꢀionꢀ are largeꢀt when the VCO operateꢀ very cloꢀe to an integer multiple of
the PD. When the VCO operateꢀ exactly at a harmonic of the PD then, no in-cloꢀe mixing productꢀ are preꢀent.
Interference iꢀ alwayꢀ preꢀent at multipleꢀ of the PD frequency, fpd, and the VCO frequency, fvco. If the fractional mode
of operation iꢀ uꢀed, the difference, Δ, between the VCO frequency and the neareꢀt harmonic of the reference, will
create what are referred to aꢀ integer boundary ꢀpurꢀ. Depending upon the mode of operation of the ꢀyntheꢀizer, higher
order, lower power ꢀpurꢀ may alꢀo occur at multipleꢀ of integer fractionꢀ (ꢀub-harmonicꢀ) of the PD frequency. That iꢀ,
fractional VCO frequencieꢀ which are near nfpd + fpdd/m, where n, d and m are all integerꢀ and d≤m (mathematicianꢀ
refer to d/m aꢀ a rational number). We will refer to fpdd/m aꢀ an integer fraction. The denominator, m, iꢀ the order of the
ꢀpuriouꢀ product. Higher valueꢀ of m produce ꢀmaller amplitude ꢀpuriouꢀ at offꢀetꢀ of mΔ and uꢀually when m>4 ꢀpurꢀ
are very ꢀmall or unmeaꢀurable.
The worꢀt caꢀe, in fractional mode, iꢀ when d=1, and the VCO frequency iꢀ offꢀet from nfpd by leꢀꢀ than the loop
bandwidth. Thiꢀ iꢀ the “in-band fractional boundary” caꢀe.
Figure 29. Fractional Spurious Example
Characterization of the levelꢀ and orderꢀ of theꢀe productꢀ iꢀ not unlike a mixer ꢀpur chart. Exact levelꢀ of the productꢀ
are dependent upon iꢀolation of the variouꢀ ꢀyntheꢀizer partꢀ. Hittite can offer guidance about expected levelꢀ of
ꢀpuriouꢀ with our PLL and VCO application boardꢀ. Regulatorꢀ with high power ꢀupply rejection ratioꢀ (PsRR) are
recommended, eꢀpecially in noiꢀy applicationꢀ.
When operating in fractional mode, charge pump and phaꢀe detector linearity iꢀ of paramount importance. Any non-
linearity degradeꢀ phaꢀe noiꢀe and ꢀpuriouꢀ performance. Phaꢀe detector linearity degradeꢀ when the phaꢀe error iꢀ
very ꢀmall and iꢀ operating back and forth between reference lead and VCO lead. To mitigate theꢀe non-linearitieꢀ in
fractional mode it iꢀ critical to operate the phaꢀe detector with ꢀome finite phaꢀe offꢀet ꢀuch that either the reference or
VCO alwayꢀ leadꢀ. To provide a finite phaꢀe error, extra current ꢀourceꢀ can be enabled which provide a conꢀtant DC
current path to VDD (VCO leadꢀ alwayꢀ) or ground (reference leadꢀ alwayꢀ). Theꢀe current ꢀourceꢀ are called charge
pump offꢀet and they are controlled via Reg 09h. The time offꢀet at the phaꢀe detector ꢀhould be ~2.5 nꢀ + 4 Tpꢀ, where
Tpꢀ iꢀ the RF period at the fractional preꢀcaler input in nanoꢀecondꢀ (ie. after the optional fixed divide by 2). The ꢀpecific
level of charge pump offꢀet current iꢀ determined by thiꢀ time offꢀet, the compariꢀon frequency and the charge pump
current and can be calculated from:
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
-9+ 4TPS
(eQ 4)
Required CP Offꢀet = (2.5 ∙ 10
: is the RF period at the fractional prescaler input
) ∙ (F
) ∙ I where:
comparison CP
TPS
: is the full scale current setting of the switching charge pump
ICP
Note that thiꢀ calculation can be performed for the center frequency of the VCO, and doeꢀ not need refinement for ꢀmall
differenceꢀ (<25%) in center frequencieꢀ. Alꢀo, operation with unreaꢀonably large charge pump offꢀet may cauꢀe Lock
Detect to incorrectly indicate an unlocked condition. To correct, reduce the offꢀet to recommended levelꢀ.
Another factor in Fractional ꢀpectral performance iꢀ the choice of the Delta-sigma Modulator mode. Mode B iꢀ normally
recommended, aꢀ it allowꢀ higher PD frequencieꢀ and makeꢀ it eaꢀier to filter the fractional quantization noiꢀe. For low
preꢀcaler frequencieꢀ (<1.5GHz), however, mode A can offer better in-band ꢀpectral performance. see Reg 06h[0] for
DsM mode ꢀelection. Finally, all fractional ꢀyntheꢀizerꢀ create fractional ꢀpurꢀ at ꢀome level. Hittite offerꢀ the loweꢀt
level fractional ꢀpuriouꢀ in the induꢀtry in an integrated ꢀolution.
opꢊꢉꢃꢅꢁꢆꢇꢃꢄ Mꢆdꢊꢈ
The HMC703LP4E can operate in a eight of different modeꢀ (Reg 06h[7:5]), and ꢀupportꢀ “Triggering” from 3 different
ꢀourceꢀ. The modeꢀ of operation include:
“Integer Mode”
“Fractional Mode”
“Exact Frequency Mode”
Frequency Modulation “FM Mode”
Phaꢀe Modulation “PM Mode”
“Frequency sweep Mode” (3 typeꢀ)
All modeꢀ require Fractional mode to be enabled except for Integer mode. Fractional mode allowꢀ fine frequency
ꢀtepꢀ. Exact Frequency mode allowꢀ preciꢀe fractional frequency ꢀtepꢀ with zero frequency error. FM and PM modeꢀ
can be uꢀed for ꢀimple communicationꢀ linkꢀ, with data rate limitationꢀ ꢀet by the loop filter bandwidth. The PM mode
alꢀo allowꢀ for preciꢀe incremental phaꢀe adjuꢀtmentꢀ, which can be important in phaꢀed arrayꢀ and other ꢀyꢀtemꢀ.
Frequency ꢀweep ꢀupportꢀ built-in one-way, two-way, or uꢀer defined frequency ꢀweepꢀ, uꢀeful in FMCW radar
applicationꢀ.
Depending on the mode, the auxiliary regiꢀterꢀ Reg 0Ah, Reg 0Ch and Reg 0Dh are uꢀed for different functionꢀ, aꢀ
ꢀhown in Table 6.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 6. opꢊꢉꢃꢅꢁꢆꢇꢃꢄ Mꢆdꢊꢈ
PLL Operating Mode (SD_MODE = Reg 06h[7:5])
0
1
2
3
4
5 to 7
Register
Register Name
Number
Exact
Frequency
Mode
FM (Frequency
Modulation)
Mode
PM (Phase
Modulation)
Mode
Fractional
Mode
Integer Mode
Ramp Mode
Function of
Reg 03h
N Integer Part
Nint
N
Nint
Freq 1: Nint
Nint
Nfrac
start Nint
Function of
Reg 04h
N Fractional
Part
Nfrac
Nfrac
Freq 1: Nfrac
start Nfrac
Function of
Reg 0Ah
Frequency ꢀtep
/ reference clock
Aux Regiꢀter
Phaꢀe step
Function of
Reg 0Ch
Alternate
Integer
Freq 2: Nint
sTOP Nint
Function of
Reg 0Dh
Alternate
Fractional
Channelꢀ / PD
frequency
Freq 2: Nfrac
sTOP Nfrac
Additional Functionality
Double Buffer
YEs
NO
YEs
YEs
YEs
YEs
Updateꢀ
frequency,
optionally
Updateꢀ
frequency,
optionally
Toggleꢀ
frequency (level
ꢀenꢀitive)
Incrementꢀ /
decrementꢀ
phaꢀe
Proceedꢀ to
next ꢀtage of
ramp
On Trigger
initiateꢀ phaꢀe
initiateꢀ phaꢀe
Thoꢀe regiꢀterꢀ which are unuꢀed in a particular mode can take on any value, and are ignored.
tꢉꢁggꢊꢉꢁꢇg
Depending on the operating mode, a trigger event iꢀ uꢀed to change frequency, FM modulate the frequency, modulate
the phaꢀe, or advance the frequency ramp profile to itꢀ next ꢀtate. In general the HMC703LP4E can be triggered via
one of three methodꢀ. Not all modeꢀ ꢀupport all trigger methodꢀ.
1. An external hardware trigger pin-6 (TRIG)
2. sPI write to TRIG BIT in Reg 0Eh[0]
3. sPI write to fractional regiꢀter Reg 04h (frequency hopping triggerꢀ only).
Depending on the mode, the part iꢀ ꢀenꢀitive to either the riꢀing edge, or the level of the trigger. The sPI’ꢀ TRIG bit
emulateꢀ the external TRIG pin, and ꢀo it muꢀt typically be written to 1 for a trigger, and then back to 0 in preparation
for another trigger cycle. To uꢀe the external TRIG pin, it muꢀt be enabled via EXTTRIG_EN (Reg 06h[9]).
fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ ꢆꢉ exꢃꢂꢅ fꢉꢊquꢊꢇꢂꢀ Mꢆdꢊ fꢉꢊquꢊꢇꢂꢀ Updꢃꢅꢊꢈ
In non-modulated fractional modeꢀ (Reg 06h[7:5] = 0 or 2), if the external trigger iꢀ enabled, writeꢀ to NINT and Nfrac
(Reg 03h and Reg 04h) are internally buffered and wait for an explicit trigger via either the TRIG pin or the sPI’ꢀ TRIG
bit before taking effect. If EXTTRIG_EN = 0, the write to NINT iꢀ double-buffered, and waitꢀ for a fractional write to
Reg 04h ꢀo that both NINT and Nfrac are internally recognized together. see the “Fractional Mode” ꢀection for more
information on calculating the fractional multiplier for your application.
iꢇꢁꢅꢁꢃꢄ Phꢃꢈꢊ cꢆꢇꢅꢉꢆꢄ
On the HMC703LP4E, the uꢀer haꢀ control of the initial phaꢀe of the VCO via the 24-bit sEED Reg 05h. Thiꢀ ꢀeed
phaꢀe iꢀ loaded on the 1ꢀt clock cycle following a trigger event, provided that autoꢀeed (Reg 06h [8] = 1) iꢀ enabled.
The value in Reg 05h repreꢀentꢀ the phaꢀe of the VCO. For example, if two ꢀyntheꢀizerꢀ are triggered in parallel, but
one haꢀ a sEED of 0.2 (0.2x224) and the other haꢀ a sEED of 0.7 (0.7x224), the ꢀteady ꢀtate outputꢀ of the two VCOꢀ
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
(not accounting for any miꢀmatch) will be 180° out of phaꢀe = ((0.7-0.2) x 360°). The uꢀer can take advantage of thiꢀ
for phaꢀe control of the outputꢀ of multiple ꢀyntheꢀizerꢀ.
If phaꢀe control iꢀ not needed, the beꢀt ꢀpuriouꢀ operation iꢀ achieved with the sEED ꢀet to a buꢀy binary number,
for example 50F1CDh, or B29D08h.
Note that in Exact Frequency mode with an exact ꢀtep of fstep, if autoꢀeed iꢀ off, there can be a delay of up to 1/fstep
after a trigger before a new fractional frequency iꢀ recognized.
fꢉꢊquꢊꢇꢂꢀ tuꢇꢁꢇg
iꢇꢅꢊgꢊꢉ Mꢆdꢊ
In integer mode the VCO ꢀtep ꢀize iꢀ fixed to that of the PD frequency, fpd. Integer mode typically haꢀ lower phaꢀe
noiꢀe than fractional mode for a given PD operating frequency. The advantage iꢀ uꢀually of the order of 2 to 3 dB.
Integer mode, however, often requireꢀ a lower PD frequency to meet channel ꢀtep ꢀize requirementꢀ. The fractional
mode advantage iꢀ that higher PD frequencieꢀ can be uꢀed, hence lower phaꢀe noiꢀe can often be realized. “Charge
Pump Offꢀet” ꢀhould be diꢀabled in integer mode. In integer mode the Δ∑ modulator iꢀ ꢀhut off and the N divider (Reg
03h) may be programmed to any integer value in the range 16 to 216-1. To uꢀe the HMC703LP4E in integer mode
program Reg 06h[7:5] = 1, then program the integer portion of the frequency (aꢀ per (EQ 5)), ignoring the fractional
part.
There iꢀ no double buffering in integer mode, i.e. write data then trigger the frequency change later. A write to the
N
INT regiꢀter (Reg 03h) immediately ꢀtartꢀ the RF frequency hop. There iꢀ no external trigger available in thiꢀ mode.
If double buffering iꢀ required, uꢀe fractional mode (Reg 06h[7:5] = 0), with Nfrac (Reg 04h ) = 0, and sEED (Reg 05h)
= 0.
fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ
The HMC703LP4E iꢀ placed into fractional mode by ꢀetting sD_MODE (Reg 06h[7:5] ) = 0
The frequency of a locked VCO controlled by the HMC703LP4E, fvco, iꢀ given by
fxtal
fps
=
(Nint + Nfrac) = fint + ffrac
(eQ 5)
(eQ 6)
R
fvco = k fps
Where:
fps
iꢀ the frequency at the preꢀcalar input after any potential RF divide by 2
iꢀ the frequency at the HMC703LP4E’ꢀ RF port
fvco
k
iꢀ 1 if the RF Divide by 2 iꢀ bypaꢀꢀed, 2 if on (Reg 08h[17])
iꢀ the integer diviꢀion ratio, Reg 03h, an integer between 20 and 216- 1
iꢀ the fractional part, from 0.0 to 0.99999...,Nfrac=Reg 04h/224
iꢀ the reference path diviꢀion ratio, Reg 02h
Nint
Nfrac
R
fxtal
fpd
iꢀ the frequency of the reference oꢀcillator input
iꢀ the PD operating frequency, fxtal/R
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Aꢀ an example, ꢀuppoꢀe we want to tune a VCO to 7910 MHz. since the input frequency iꢀ > 4 GHz, the
RF divide-by-2 muꢀt be engaged, ꢀo k=2:
fvco
k
7,910 MHz
2
fps
3,955 MHz
fxtal
R
= 50 MHz
= 1
fpd
= 50 MHz
Nint
Nfrac
Reg 04h
= 79
= 0.1
= round(0.1 x 224) = round(1677721.6) = 1677722
50e6
1
1677722
fps
=
(79 +
) = 3955 MHz + 1.2 Hz error
(eQ 7)
(eQ 8)
224
fvco = 2 (3955 +1.2 Hz) = 7910 MHz + 2.4 Hz error
In thiꢀ example the output frequency of 7910 MHz iꢀ achieved by programming the 16-bit binary value of 79d = 4Fh =
0000 0000 0100 1111 into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah = 0001 1001 1001
1001 1001 1010 into frac_reg in Reg 04h. The 2.4 Hz quantization error can be eliminated uꢀing the exact frequency
mode if required.
exꢃꢂꢅ fꢉꢊquꢊꢇꢂꢀ Mꢆdꢊ
The abꢀolute frequency preciꢀion of a fractional PLL iꢀ normally limited by the number of bitꢀ in the fractional modulator.
For example a 24 bit fractional modulator haꢀ frequency reꢀolution ꢀet by the phaꢀe detector (PD ) compariꢀon rate
divided by 224. In the caꢀe of a 50 MHz PD rate, thiꢀ would be approximately 2.98 Hz, or 0.0596 ppm.
In ꢀome applicationꢀ it iꢀ neceꢀꢀary to have exact frequency ꢀtepꢀ, and even an error of 3 Hz cannot be tolerated. In
ꢀome fractional ꢀyntheꢀizerꢀ it iꢀ neceꢀꢀary to ꢀhorten the length of the accumulator (the denominator or the moduluꢀ)
to accommodate the exact period of the ꢀtep ꢀize. The ꢀhortened accumulator often leadꢀ to very high ꢀpuriouꢀ levelꢀ
at multipleꢀ of the channel ꢀpacing, fꢀtep = fPD/Moduluꢀ. For example 200 kHz channel ꢀtepꢀ with a 10 MHz PD rate
requireꢀ a moduluꢀ of juꢀt 50. The Hittite method achieveꢀ the exact frequency ꢀtep ꢀize while uꢀing the full 24 bit
moduluꢀ, thuꢀ achieving exact frequency ꢀtepꢀ with very low ꢀpuriouꢀ and a high compariꢀon rate, which maintainꢀ
excellent phaꢀe noiꢀe.
Fractional PLLꢀ are able to generate exact frequencieꢀ (with zero frequency error) if N can be exactly repreꢀented in
binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, ꢀome common frequencieꢀ cannot be exactly repreꢀented.
For example, Nfrac = 0.1 = 1/10 muꢀt be approximated aꢀ round((0.1 x 224)/ 224 ) ≈ 0.100000024. At fPD = 50 MHz thiꢀ
tranꢀlateꢀ to 1.2 Hz error. HMC703LP4E exact frequency mode addreꢀꢀeꢀ thiꢀ iꢀꢀue, and can eliminate quantization
error by programming the Nchannelꢀ (Reg 0Dh) to 10 (in thiꢀ example). More generally, thiꢀ feature can be uꢀed whenever
the preꢀcaler frequency, fpꢀ, can be exactly repreꢀented on a ꢀtep plan where there are an integer number (Nchannelꢀ
)
of frequency ꢀtepꢀ acroꢀꢀ integer-N boundarieꢀ. Aꢀꢀuming the RF divide by 2 iꢀ diꢀabled ꢀo that fps=fvco, thiꢀ holdꢀ
when the VCO frequency, fvco ꢀatiꢀfieꢀ (EQ 9), ꢀhown graphically in Figure 30.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
fvco mod��fgcd ÷�= 0, where fgcd = gcd(fvco,fPD
)
(eQ 9)
�
�
N
channels = fPD / fgcd, and Nchannels < 224
Where:
f
f
PD = frequency of the Phaꢀe Detector
VCO iꢀ the deꢀired output frequency
fN , fN+1 are integer multipleꢀ of the Phaꢀe Detector
f
gcd ꢀtandꢀ for Greateꢀt Common Diviꢀor
eg. gcd (4000.200MHz, 50MHz)
= 200kHz
therefore Nchannelꢀ = 50 MHz/200 kHz = 250
f
f
VCOn are other VCO frequencieꢀ we can exactly tune to, given thiꢀ fgcd ꢀpacing
Figure 30. Exact Frequency Tuning
In the previouꢀ paragraph, it waꢀ aꢀꢀumed that a ꢀingle frequency waꢀ to be achieved with zero error. Exact frequency
mode alꢀo applieꢀ to caꢀeꢀ where many exact frequencieꢀ are required, all of which fit on a particular channel ꢀpacing.
Example: To achieve exactly 50 kHz channel ꢀtepꢀ with a 61.44 MHz reference, calculate fgcd and Nchannelꢀ
:
f
f
PD = 61.44 MHz
step = 50 kHz
fgcd (61.44 MHz, 50 kHz)
Uꢀing the Euclidean algorithm to find the greateꢀt common denominator:
61.440 MHz = 50 kHz x 1228 + 50 kHz
50 kHz = 40 kHz x 1 + 10 kHz
40 kHz = 10 kHz x 4 + 0 (0 remainder, algorithm complete)
fgcd (61.44 MHz, 50 kHz) = 10 kHz
N
channelꢀ = 61.44 MHz / 10 kHz = 6144
For improved ꢀpectral performance (to keep ꢀpurꢀ low and further out of band), it iꢀ beꢀt to keep fgcd aꢀ high aꢀ poꢀ-
ꢀible (Nchannelꢀ aꢀ low poꢀꢀible) for a given application.
Uꢈꢁꢇg Hꢁꢅꢅꢁꢅꢊ exꢃꢂꢅ fꢉꢊquꢊꢇꢂꢀ Mꢆdꢊ
To uꢀe Exact Frequency Mode, we recommend the following procedure:
1. Calculate the required fgcd aꢀ either gcd(fVCO, fPD) or gcd(fPD, fstep) depending on your application
2. Calculate the number of channelꢀ per integer boundary, Nchannels= fPD / fgcd and program into Reg 0Dh
3. set the modulator mode to Exact Frequency (sD_MODE in Reg 06h[7:5] = 2)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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8 GHz fractional syntHesizer
Then, for each frequency of intereꢀt, fVCO
:
4
Calculate the approximate value of N that iꢀ required: N = fVCO/fPD = NINT + Nfrac
5. Program NINT into integer regiꢀter Reg 03h
Note: There iꢀ no need to re-program NINT if it haꢀ not changed from the previouꢀ ꢀet-point.
6. Program the fractional regiꢀter, Reg 04h = Ceiling(Nfrac*224
)
where the ceiling function meanꢀ “round up to the neareꢀt integer.”
Example: To configure HMC703LP4E for exact frequency mode with channel spacing of 50 kHz, VCO frequency =
2000.200 MHz and fPD =61.44 MHz:
1.
fgcd(61.44 MHz, 50 kHz) = 10 kHz (aꢀ above)
2. Calculate Nchannels=fPD / fgcd = 6144. Program into Reg 0Dh (6144 dec = 1800 hex)
3. set the modulator mode to Exact Frequency (sD_MODE in Reg 06h[7:5] = 2)
4. Calculate N = 2000.2 MHz / 61.44 MHz = 32.55533854 = 32 + 0.55533854
5. Program integer diviꢀor NINT (Reg 03h) = 32d = 20h
6. Program fractional diviꢀor Reg 04h= CEILING(0.55533854 x 224) = 9,317,035 = 8E2AABh
In the above example, without exact frequency mode, there would have been a -1.2 Hz error due to quantization.
fM Mꢆdꢊ
The HMC703LP4E PM mode ꢀupportꢀ ꢀimple FsK modulation via a level ꢀenꢀitive trigger. FM mode can be uꢀed for
ꢀimple communicationꢀ linkꢀ, with data rate limitationꢀ ꢀet by the loop filter bandwidth.
The HMC703LP4E iꢀ configured to operate in FM mode by writing Reg 06h[7:5] = 3.
The FM mode allowꢀ the uꢀer to toggle between two frequencieꢀ F0 = N1*fPD and F1 = N2*fPD baꢀed on the level of
the TRIG.
The following procedure iꢀ recommended to configure HMC703LP4E to FM mode:
1. Lock in fractional mode (Reg 06h[7:5]= 0) to F0 = fPD x (Reg 03h.Reg 04h).
2. Program (Reg 0Ch.Reg 0Dh) for F1.
3. Change mode to FM (Reg 06h[7:5] = 3).
4. select the trigger ꢀource Reg 06h[9] = 1, TRIG (pin-6), or Reg 06h[9] = 0 - trigger from sPI bit Reg 0Eh[0]
5. switch between F0 and F1 on a trigger ꢀtate 0/1 = F0/F1.
It iꢀ poꢀꢀible to change the next frequency ꢀtate between trigger eventꢀ, without affecting the output - ie. write the F0
value while on F1, or F1 while on F0 .
PM Mꢆdꢊ
The HMC703LP4E PM mode ꢀupportꢀ ꢀimple bi-phaꢀe modulation via a level ꢀenꢀitive trigger. PM mode alꢀo ꢀupportꢀ
programmable phaꢀe ꢀtepꢀ via an edge ꢀenꢀitive trigger. PM modeꢀ can be uꢀed for ꢀimple communicationꢀ linkꢀ,
with data rate limitationꢀ ꢀet by the loop filter bandwidth.
The HMC703LP4E iꢀ configured to operate in all PM mode by writing Reg 06h[7:5] = 4. In general the modulation
phaꢀe ꢀtep, Δq, in either PM mode iꢀ given by
x �360
224
�� =
(deg)
where x = Reg 0Ah.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
Bꢁ-Phꢃꢈꢊ Mꢆduꢄꢃꢅꢁꢆꢇ
Phaꢀe ꢀtep iꢀ programmed in Reg 0Ah aꢀ a fraction of 2π, where 224 = 2π. For example, for bi-phaꢀe modulation a
phaꢀe ꢀtep of 180°, program Reg 0Ah= round( (180/360) x 224 = 8388608d = 800000h).
Phaꢀe modulation data iꢀ input via a “trigger” ꢀource, where the trigger iꢀ level dependent (Reg 06h[8] = 0), high
trigger advanceꢀ the phaꢀe and low trigger returnꢀ the phaꢀe.
Phꢃꢈꢊ sꢅꢊp cꢆꢇꢅꢉꢆꢄ
Phaꢀe may alꢀo be advanced on the riꢀing edge of the trigger only. Phaꢀe ꢀtep iꢀ programmed in Reg 0Ah aꢀ a fraction
of 360°, where 224 = 2π. For example, for a 1° phaꢀe ꢀtep, program Reg 0Ah= round( (1/360) x 224 = 46603d =B60Bh)
In ꢀummary the following procedure iꢀ recommended to configure HMC703LP4E for PM mode:
1. Lock in fractional mode (Reg 06h[7:5] = 0) to F = fPD x (Reg 03h.Reg 04h).
2. Program (Reg 0Ah) to the intended phaꢀe ꢀtep.
3. Change mode to PM (Reg 06h[7:5] = 4).
4. Change trigger option to edge or level (Reg 06h[8])
5. select the trigger ꢀource Reg 06h[9] = 1, TRIG (pin-6), or Reg 06h[9] = 0 - trigger from sPI write to
Reg 0Eh).
fꢉꢊquꢊꢇꢂꢀ swꢊꢊp Mꢆdꢊ
The HMC703LP4E featureꢀ a built-in ꢀweeper mode, that ꢀupportꢀ external or automatic triggered ꢀweepꢀ. The
maximum ꢀweep range iꢀ only limited by the VCO dynamicꢀ and range.
sweeper Mode includeꢀ:
a. Automatic 2-Way sweep Mode
INITIAL trigger, ramp, ramp back, ramp, ramp back, ...
selected by writing Reg 06h[7:5] = 7
b. Triggered 2-Way sweep Mode
INITIAL trigger, ramp, wait for trigger, ramp back, wait for trigger, ramp, ...
selected by writing Reg 06h[7:5] = 6
c. Triggered 1-Way sweep Mode -
INITIAL trigger, ramp, wait for trigger, hop back to initial frequency, wait for trigger, ramp, ...
selected by writing Reg 06h[7:5] = 5
Applicationꢀ include teꢀt inꢀtrumentation, FMCW ꢀenꢀorꢀ, automotive radarꢀ and otherꢀ.
The parameterꢀ of the ꢀweep function are illuꢀtrated in Figure 31. The HMC703LP4E generateꢀ a ꢀweep by
implementing miniature frequency ꢀtepꢀ in time. A ꢀmooth and continuouꢀ ꢀweep iꢀ then generated, at the output of
the VCO, after the ꢀtepped ꢀignal iꢀ filtered by the loop filter, aꢀ ꢀhown in Figure 31. The ꢀtepped ꢀweep approach
enableꢀ the HMC703LP4E to be in lock for entire duration of the ꢀweep. Thiꢀ giveꢀ the HMC703LP4E a number of
advantageꢀ over conventional methodꢀ including:
•
•
•
•
The ability to generate a linear ꢀweep.
The ability to have phaꢀe coherence between different rampꢀ, ꢀo that the phaꢀe profile of each ꢀweep iꢀ identical.
The ability to generate ꢀweepꢀ with identical phaꢀe and phaꢀe noiꢀe performance.
The ability to generate uꢀer defined ꢀweepꢀ in ꢀingle-ꢀtep ramp mode.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
The HMC703LP4E ꢀweep function cycleꢀ through a ꢀerieꢀ of diꢀcrete frequency valueꢀ which may be
a. stepped by an automatic ꢀequencer or,
b. single ꢀtepped by individual triggerꢀ in single step Mode.
Triggering of each ꢀweep, or ꢀtep, may be configured to operate:
a. Via a ꢀerial port write of 1 to Reg 0Eh[0] (it ꢀhould then be returned to 0)
b. Automatically generated internally
c. Triggered via TRIG pin-6
Figure 31. HMC703LP4E Sweep Function
2-Wꢃꢀ swꢊꢊpꢈ
The HMC703LP4E can be configured to operate in 2-Way sweep mode by programming Reg 06h [7:5] = 6 or 7. A
2-way ꢀweep iꢀ ꢀhown in Figure 32. The ꢀtart of the ꢀweep can be triggered by external TRIG pin-6 if EXTTRIG_EN
= 1, or the sPI_TRIG (Reg 0Eh). In automatic 2-Way ꢀweep (Reg 06h [7:5] = 7), the ramp reꢀtartꢀ immediately, without
waiting for an external trigger.
Figure 32. 2-Way Triggered Sweep
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
1-Wꢃꢀ swꢊꢊpꢈ
The HMC703LP4E can be configured to operate in Triggered 1-Way sweep mode by programming Reg 06h [7:5] =
6. Triggered 1-way ꢀweepꢀ are ꢀhown in Figure 33. Unlike 2-Way ꢀweepꢀ, Triggered 1-Way ꢀweepꢀ force the VCO to
hop back to the ꢀtart frequency upon the next trigger. Triggered 1-Way ꢀweepꢀ alꢀo require a 3rd trigger to ꢀtart the
new ꢀweep. The 3rd trigger ꢀhould be timed appropriately to allow the VCO to ꢀettle after the large frequency hop back
to the ꢀtart frequency. subꢀequent odd numbered triggerꢀ will ꢀtart the 1-Way ꢀweep and repeat the proceꢀꢀ. 1-way
ꢀweep can be triggered by external TRIG pin-6 if EXTTRIG_EN = 1, or the sPI_TRIG (Reg 0Eh).
Figure 33. 1-Way Sweep Control
sꢁꢇgꢄꢊ sꢅꢊp rꢃmp Mꢆdꢊ
With any of the ꢀweeper profileꢀ, the HMC703LP4E can be configured to operate in ꢀingle ꢀtep mode. Thiꢀ cauꢀeꢀ
it to wait for an explicit trigger before every change in the frequency ꢀetpoint. A single step 1-Way Ramp iꢀ ꢀhown in
Figure 34. In thiꢀ mode, a trigger iꢀ required for each ꢀtep of the ramp. similar to autoꢀweep, the ramp_buꢀy flag will
go high on the firꢀt trigger, and will ꢀtay high until the nth trigger. The n+1 trigger will cauꢀe the ramp to jump to the ꢀtart
frequency in 1-way ramp mode. The n+2 trigger will reꢀtart the 1-way ramp. single ꢀtep ramp mode can be triggered
by external TRIG pin-6 if EXTTRIG_EN = 1, or the sPI_TRIG (Reg 0Eh).
In ꢀingle-ꢀtep mode (Reg 06h[23] = 1), the HMC703LP4E haꢀ the capability to generate arbitrarily ꢀhaped profileꢀ
defined by the timing denꢀity of the trigger pulꢀeꢀ. On each trigger event the frequency iꢀ ꢀtepped by the ꢀtep value
programmed in Reg 0Ah. In addition, the HMC703LP4E allowꢀ the flexibility to change the ꢀtep ꢀize (Reg 0Ah) during
the ramp, between ꢀtepꢀ, adding another degree of freedom to ramp profile generation. Note that the maximum trigger
rate where operation can be guaranteed iꢀ fPD/5. In addition, the ꢀtep regiꢀter (Reg 0Ah) ꢀhould not be updated via
the sPI during the firꢀt two reference clock cycleꢀ after the trigger. The diꢀcrete nature of the frequency updateꢀ iꢀ
ꢀmoothed by the loop filter, and ꢀhould not poꢀe a problem provided that update rate iꢀ > 10 x the loop bandwidth.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
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Figure 34. Single Step Ramp Mode
The uꢀer ꢀhould be aware that the ꢀyntheꢀized ramp iꢀ ꢀubject to normal phaꢀe locked loop dynamicꢀ. If the loop
bandwidth in uꢀe iꢀ much wider than the rate of the ꢀtepꢀ then the locking will be faꢀt and the ramp will have a
ꢀtaircaꢀe ꢀhape. If the update rate iꢀ higher than the loop bandwidth, aꢀ iꢀ normally the caꢀe, then the loop will not
fully ꢀettle before a new frequency ꢀtep iꢀ received. Hence the ꢀwept output will have a ꢀmall lag and will ꢀweep in a
near continuouꢀ faꢀhion.
Dꢊꢅꢃꢁꢄꢊd swꢊꢊpꢊꢉ cꢆꢇꢋꢁguꢉꢃꢅꢁꢆꢇ
The Following procedure iꢀ recommended to configure the frequency ꢀweep in HMC703LP4E:
1. Lock in fractional mode (Reg 06h[7:5] = 0) to the ꢀtart frequency (f0).
2. Program frequency ꢀtep Reg 0Ah and ꢀtop N (Reg 0Ch,Reg 0Dh). Note that ꢀtop N muꢀt be exactly equal
to ꢀtart N pluꢀ an integer number of ꢀtepꢀ (Reg 0Ah). If it iꢀ not, the ꢀweeper function will not terminate
properly. Thiꢀ normally meanꢀ rounding the ꢀtop N up or down ꢀlightly to enꢀure it fallꢀ on a ꢀtep boundary.
3. Change Mode to Reg 06h[7:5] = 5,6, or 7 - depending on the deꢀired profile.
Note that the ramp ꢀtep Reg 0Ah iꢀ ꢀigned two’ꢀ complement. If negative, the firꢀt ramp haꢀ a negative ꢀlope, and
vice-verꢀa.
setting autoꢀeed (Reg 06h[8] = 1) enꢀureꢀ that different ꢀweepꢀ have identical phaꢀe profile. Thiꢀ iꢀ achieved by
loading the ꢀeed (Reg 05h) into the phaꢀe accumulator at the beginning of each ramp
setting Reg 06h[22] = 1 enꢀureꢀ identical phaꢀe AND quantization noiꢀe performance on each ꢀweep by reꢀetting the
entire delta-ꢀigma modulator at the beginning of each ramp.
Note that, while the HMC703LP4E can enforce phaꢀe coherence between different frequency ꢀweepꢀ, there will be a
phaꢀe diꢀcontinuity if the ꢀtart phaꢀe that iꢀ programmed in sEED (Reg 05h) iꢀ different from the phaꢀe ꢀtate that the
PLL findꢀ itꢀelf in at the end of the ramp. Thiꢀ diꢀcontinuity can be prevented by tailoring the ꢀweep profile ꢀuch that
the phaꢀe of the PLL at the ꢀtart of the ramp iꢀ equal to phaꢀe at the end of the ramp.
Example: Configure a sweep from f0 = 3000 MHz to ff = 3105 MHz in Tramp ≈ 2 ms, with fPD = 50 MHz:
1. Start in fractional mode (Program Reg 06h[7:5] = 0)
1. Calculate Start N and Stop N, Program Start N (Reg 03h,Reg 04h)
Start N = 3000.0 MHz / 50.0 MHz = 60.0
Stop N = 3105.0 MHz / 50.0 MHz = 62.1
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
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8 GHz fractional syntHesizer
Program Reg 03h = 60, Reg 04h = 0
2. Calculate how many reference cycles will occur in 2 ms. Given that Tref = 1 / fPD = 20ns,
Nbr of Steps = Tramp/Tref = 2ms/20ns = 100,000
3. Calculate the desired N step size, given Start N, Stop N and Nbr of Steps
N_Step_Size_desired = (62.1 - 60.0) / 100,000 = 21u [fractions of N]
4. Quantize the fractional N step into the 24 bit step size
Program Reg 0Ah = 21u x 224 = round(352.32) = 352
5. Readjust the stop frequency slightly to ensure it falls exactly on a step boundary
Due to step quantization,there will be some finite error in either the sweep time or sweep span.
We have 3 choices:
a) Target an accurate sweep time, sacrifice resolution on stop frequency
Sweep time = 100k cycles = 2 ms
Stop N = Start N + 100,000 x 352/224 (Keep 100k cycles)
Stop N = 60.000 + 35,200,000 / 224 ≈ 62.09808
Program Reg 0Ch= 62, Reg 0Dh = 35,200,000 MOD 224 = 1,645,568 ≈ 0.09808
ff ≈ 3104.904 (96 kHz lower stop frequency then desired)
b) Target an accurate stop frequency, at the expense of sweep time accuracy
Given step size of 352/224, how many cycles to get from 60.0 to 62.1
Nbr of Steps = (62.1 - 60.0) / (352/224) = 100,091.345
Must round to 100,091 steps.
Sweep time = Tref * 100,091 = 2.00182ms (1.82 us longer than desired)
Stop N = 60.0 + 100,091 x 352/224 ≈ 62.0999927
Program Reg 0Ch= 62, Reg 0Dh = 35,232,032 MOD 224 = 1,677,600 ≈ 0.0999927
ff = 3104.99964 MHz (362 Hz lower stop frequency then desired)
c) A combination of situation a and b
6. Program SD_Mode based on desired trigger and ramp/hop profile (Reg 06h[7:5] = 5,6, or 7)
7. Trigger via either the external pin or SPI TRIG bit.
Continue to issue triggers to advance the ramp profile to the next stage...
swꢊꢊpꢊꢉ cꢆꢇfiguꢉꢃꢅꢁꢆꢇ ꢋꢆꢉ Uꢄꢅꢉꢃ fꢁꢇꢊ sꢅꢊp sꢁꢌꢊꢈ
In caꢀeꢀ where finer ꢀtep ꢀize reꢀolution iꢀ deꢀired, it iꢀ poꢀꢀible to reduce the fPD, along with performance implicationꢀ
it haꢀ, or uꢀe a ꢀingle-ꢀtep mode (Reg 06h[23] = 1) and provide a lower frequency clock on the external trigger pin
to reduce the update rate. The HMC703LP4E can generate a lower frequency clock by programming the R divider
appropriately, and not uꢀing it for the PD (Reg 06h[21] = 1), but rather routing it out of the HMC703LP4E via the GPO.
The R divider output can then be looped back to the TRIG pin of the HMC703LP4E to uꢀe aꢀ a low rate trigger. see
“Ref Path ’R’ Divider” for more detailꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ sꢅꢃgꢊ
Figure 35. Reference Path Input Stage
The reference buffer provideꢀ the path from an external reference ꢀource (generally cryꢀtal baꢀed) to the R divider, and
eventually to the phaꢀe detector. The buffer haꢀ two modeꢀ of operation. High Gain (recommended below 200 MHz),
and High frequency, for 200 to 350 MHz operation. The buffer iꢀ internally DC biaꢀed, with 100 Ω internal termination.
For 50 Ω match, an external 100 Ω reꢀiꢀtance to AC ground ꢀhould be added, followed by an AC coupling capacitance
(impedance < 1 Ohm), then to the XREFP pin of the part.
At low frequencieꢀ, a relatively ꢀquare reference iꢀ recommended to keep the input ꢀlew rate high. At higher frequencieꢀ,
a ꢀquare or ꢀinuꢀoid can be uꢀed. The following table ꢀhowꢀ the recommended operating regionꢀ for different reference
frequencieꢀ. If operating outꢀide theꢀe regionꢀ the part will normally ꢀtill operate, but with degraded performance.
Minimum pulꢀe width at the reference buffer input iꢀ 2.5 nꢀ. For beꢀt ꢀpur performance when R = 1, the pulꢀe width
ꢀhould be > (2.5 nꢀ + 8 Tpꢀ), where Tpꢀ iꢀ the period of the VCO at the preꢀcaler input. When R > 1 minimum pulꢀe
width iꢀ 2.5 nꢀ.
tꢃbꢄꢊ 7. rꢊꢋꢊꢉꢊꢇꢂꢊ sꢊꢇꢈꢁꢅꢁvꢁꢅꢀ tꢃbꢄꢊ
square Input
sinuꢀoidal Input
slew > 0.5V/nꢀ
Recommended swing (Vpp)
Recommended Power Range (dBm)
Frequency
(MHz)
Recommended
Min
0.6
0.6
0.6
0.6
0.6
0.9
1.2
x
Max
2.5
2.5
2.5
2.5
2.5
2.5
2.5
x
Recommended
Min
x
Max
x
< 10
10
YEs
YEs
YEs
YEs
YEs
ok
x
x
x
x
25
ok
8
15
15
15
12
8
50
YEs
YEs
YEs
YEs
6
100
5
150
4
200
ok
3
1
200 to 350
x
YEs
5
10
Note: For greater than 200 MHz operation, uꢀe buffer in High Frequency Mode. Reg 08h[18] = 1
Input referred phaꢀe noiꢀe of the PLL when operating at 50 MHz iꢀ between -150 and -156 dBc/Hz at 10 kHz offꢀet
depending upon the mode of operation. The input reference ꢀignal ꢀhould be 10dB better than thiꢀ floor to avoid deg-
radation of the PLL noiꢀe contribution. It ꢀhould be noted that ꢀuch low levelꢀ are only neceꢀꢀary if the PLL iꢀ the
dominant noiꢀe contributor and theꢀe levelꢀ are required for the ꢀyꢀtem goalꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
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8 GHz fractional syntHesizer
rꢊꢋ Pꢃꢅh ’r’ Dꢁvꢁdꢊꢉ
The reference path “R” divider iꢀ baꢀed on a 14 bit counter and can divide input ꢀignalꢀ of up to 350 MHz input by valueꢀ
from 1 to 16,383 and iꢀ controlled by Reg 02h[13:0]. The reference divider output may be viewed in teꢀt mode on the
LD_sDO pin, by ꢀetting Reg 0Fh[4:0] = 9d.
The HMC703LP4E can uꢀe the undivided reference, while exporting a divided verꢀion for auxiliary purpoꢀeꢀ (eg. ramp
triggerꢀ, FPGAꢀ etc.) on the GPO, if Reg 06h[21] = 1.
rf Pꢃꢅh
The RF path iꢀ ꢀhown in Figure 36. Thiꢀ path featureꢀ a low noiꢀe 8 GHz RF input buffer followed by an 8 GHz RF
divide-by-2 with a ꢀelectable bypaꢀꢀ. If the VCO input iꢀ below 4 GHz the RF divide-by-2 ꢀhould be by-paꢀꢀed for
improved performance in fractional mode. The RF divide-by-2 iꢀ followed by the N divider, a 16 bit divider that can
operate in either integer or fractional mode with up to 4 GHz inputꢀ. Finally the N divider iꢀ followed by the Phaꢀe
Detector (PD), which haꢀ two inputꢀ, the RF path from the VCO (V) and the reference path (R) from the cryꢀtal. The PD
can operate at ꢀpeedꢀ up to 100 MHz in fractional Mode B (recommended ), 80 MHz in fractional Mode A and 115 MHz
in integer mode.
Figure 36. RF Path
rf iꢇpuꢅ sꢅꢃgꢊ
The RF input ꢀtage provideꢀ the path from the external VCO to the phaꢀe detector via the RF or ’N’ divider. The RF
input path iꢀ rated to operate up to 8 GHz acroꢀꢀ all conditionꢀ. The RF input ꢀtage iꢀ a differential common emitter
ꢀtage with internal DC biaꢀ, and iꢀ protected by EsD diodeꢀ aꢀ ꢀhown in Figure 37. Thiꢀ input iꢀ not matched to 50 Ω. A
100 Ω reꢀiꢀtor placed acroꢀꢀ the inputꢀ can be uꢀed for a better match to 50 Ω. In moꢀt applicationꢀ the input iꢀ uꢀed
ꢀingle-ended into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking
capacitor. The preferred input level for beꢀt ꢀpectral performance iꢀ -10 dBm nominally.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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8 GHz fractional syntHesizer
Figure 37. RF Input Stage- shown with single ended device
rf Pꢃꢅh ’n’ Dꢁvꢁdꢊꢉ
The main RF path ’N’ divider iꢀ capable of divide ratioꢀ anywhere between 216-1 (524,287) and 16 . Thiꢀ divider for
example could divide a 4 GHz input to a PD frequency anywhere between itꢀ maximum output limit of 115 MHz to aꢀ low
aꢀ 7.6 kHz. The ’N’ divider output may be viewed in teꢀt mode on LD_sDO by ꢀetting Reg 0Fh[4:0] = 10d. When
operating in fractional mode the N divider can change by up to +/-4 from the average value. Hence the ꢀelected divide
ratio in fractional mode iꢀ reꢀtricted to valueꢀ between 216-5 (65,531) and 20.
If the VCO input iꢀ above 4 GHz then the 8 GHz fixed RF divide-by-2 ꢀhould be uꢀed, Reg 08h[17] = 1. In thiꢀ caꢀe the
integer diviꢀion range iꢀ reꢀtricted to even numberꢀ over the range 2*(216-5) (131,062) down to 40.
Pll Jꢁꢅꢅꢊꢉ
The ꢀtandard deviation of the arrival time of the VCO ꢀignal, or the jitter, may be eꢀtimated with a ꢀimple approximation
2
�
f0
, at offꢀetꢀ leꢀꢀ than the loop 3dB bandwidth and
if we aꢀꢀume that the locked VCO haꢀ a conꢀtant phaꢀe noiꢀe,
a 20dB per decade roll off at greater offꢀetꢀ. The ꢀimple locked VCO phaꢀe noiꢀe approximation iꢀ ꢀhown on the left of
Figure 38.
Figure 38. PLL Phase Noise and Jitter
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
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8 GHz fractional syntHesizer
With thiꢀ ꢀimplification the total integrated VCO phaꢀe noiꢀe, Ф2 , in radꢀ2 iꢀ given by
v
Ф2 = Ф2(f0) Вπ
(eQ 10)
v
where
Ф2 iꢀ the ꢀingle ꢀideband phaꢀe noiꢀe in radꢀ2/Hz inꢀide the loop bandwidth, and
В iꢀ the 3 dB corner frequency of the cloꢀed loop PLL
The integrated phaꢀe noiꢀe at the phaꢀe detector, Ф2pd, iꢀ juꢀt ꢀcaled by N2 ie. Ф2pd = Ф2 /N2
v
The rmꢀ phaꢀe jitter of the VCO (Фv) in radꢀ, iꢀ juꢀt the ꢀquare root of the phaꢀe noiꢀe integral.
since the ꢀimple integral of (EQ 10) iꢀ juꢀt a product of conꢀtantꢀ, we can eaꢀily do the integral in the log domain. For
example if the phaꢀe noiꢀe inꢀide the loop iꢀ -110 dBc/Hz at 10 kHz offꢀet and the loop bandwidth iꢀ 100 kHz, and the
diviꢀion ratio iꢀ 100, then the integrated phaꢀe noiꢀe at the phaꢀe detector, in dB, iꢀ given by;
� = 10�95
Ф2pd = 10log(Ф2(f0) Вπ/N2) = -110 + 5 + 50 - 40 = -95 dBradꢀ, or equivalently
= 18 µradꢀ = 1 milli-degreeꢀ
20
rmꢀ.
While the phaꢀe noiꢀe reduceꢀ by a factor of 20logN after diviꢀion to the reference, due to the increaꢀed period of the
PD reference ꢀignal, the jitter iꢀ conꢀtant.
The rmꢀ jitter from the phaꢀe noiꢀe iꢀ then given by Tjpn=Tpd Ф2pd/2π
In thiꢀ example if the PD reference waꢀ 50 MHz, Tpd = 20 nꢀec, and hence Tjpn = 56 femto-ꢀec.
chꢃꢉgꢊ Pump ꢃꢇd Phꢃꢈꢊ Dꢊꢅꢊꢂꢅꢆꢉ
The Phaꢀe Detector or PD haꢀ two inputꢀ, one from the reference path divider and one from the RF path divider. When
in lock theꢀe two inputꢀ are at the ꢀame average frequency and are fixed at a conꢀtant average phaꢀe offꢀet with
reꢀpect to each other. We refer to the frequency of operation of the PD aꢀ fpd. Moꢀt formula related to ꢀtep ꢀize, delta-
ꢀigma modulation, timerꢀ etc., are functionꢀ of the operating frequency of the PD, fpd iꢀ ꢀometimeꢀ referred to aꢀ the
compariꢀon frequency of the PD.
The PD compareꢀ the phaꢀe of the RF path ꢀignal with that of the reference path ꢀignal and controlꢀ the charge pump
output current aꢀ a linear function of the phaꢀe difference between the two ꢀignalꢀ. The output current varieꢀ in a linear
faꢀhion over nearly 2π radianꢀ ( 360) of input phaꢀe difference.
chꢃꢉgꢊ Pump ꢃꢇd Phꢃꢈꢊ Dꢊꢅꢊꢂꢅꢆꢉ fuꢇꢂꢅꢁꢆꢇꢈ
Phaꢀe detector regiꢀter Reg 0Bh allowꢀ manual acceꢀꢀ to control ꢀpecial phaꢀe detector featureꢀ.
Reg 0Bh[2:0] allowꢀ fine tuning of the PD reꢀet path delay. Thiꢀ adjuꢀtment can be uꢀed to improve performance at very
high PD rateꢀ. Moꢀt often thiꢀ regiꢀter iꢀ ꢀet to the recommended value only.
Reg 0Bh[5] and [6] enableꢀ the PD UP and DN outputꢀ reꢀpectively. Diꢀabling preventꢀ the charge pump from pumping
up or down reꢀpectively and effectively tri-ꢀtateꢀ the charge pump while leaving all other functionꢀ operating internally.
CP Force UP Reg 0Bh[7] and CP Force DN Reg 0Bh[8] allowꢀ the charge pump to be forced up or down reꢀpectively.
Thiꢀ will force the VCO to the endꢀ of the tuning range which can be uꢀeful for teꢀting of the VCO.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
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8 GHz fractional syntHesizer
PD Force Mid Reg 0Bh[9] will diꢀable the charge pump current ꢀourceꢀ and place a voltage ꢀource on the loop filter at
approximately VPPCP/2. If a paꢀꢀive filter iꢀ uꢀed thiꢀ will ꢀet the VCO to the mid-voltage tuning point which can be
uꢀeful for teꢀting of the VCO.
lꢆꢂk Dꢊꢅꢊꢂꢅ
Each PD (Phaꢀe Detector) cycle, the HMC703LP4E meaꢀureꢀ phaꢀe error at the PD. The meaꢀured phaꢀe error muꢀt
be:
•
•
< ~220 degreeꢀ if 40 MHz <= fPD <= 120 MHz, and
< ~14 nꢀ if fpd < 40 MHz,
for a number of conꢀecutive cycleꢀ (number of cycleꢀ iꢀ programmable in Reg 07h[2:0]), in order for HMC703LP4E to
declare a lock. A ꢀingle phaꢀe error outꢀide of theꢀe criteria diꢀqualifieꢀ lock, and the lock counter (maximum value of
lock counter = Reg 07h[2:0]) iꢀ reꢀtarted.
Note that in ꢀome caꢀeꢀ, the PLL may be locked with a phaꢀe error that exceedꢀ 180 degreeꢀ, or 12 nꢀ, whichever iꢀ
ꢀmaller. Thiꢀ can occur if the offꢀet current iꢀ inappropriately programmed too high. It iꢀ not recommended to operate
in thiꢀ condition becauꢀe it leadꢀ to degraded phaꢀe noiꢀe performance. In ꢀuch a caꢀe the lock detect circuit would
not declare a locked condition, even though the PLL iꢀ locked.
The HMC703LP4E lock-detect functionality iꢀ ꢀelf-calibrating relative to the reference frequency. Typically the
lock-detect training iꢀ only required once on power-up, or each time the reference frequency or the R divider value
(Reg 02h) iꢀ changed.
To train the lock-detect circuitry of the HMC703LP4E on power-up, ꢀet:
•
•
•
ꢀet Reg 07h [11] = 1 to enable lock-detect counterꢀ
ꢀet Reg 07h [14] = 1 to enable the lock-detect timer
ꢀet Reg 07h [20] = 1 to train the lock-detect timer
Theꢀe bitꢀ can all be written ꢀimultaneouꢀly.
On any change of the PD frequency (via either the external reference frequency, or the R divider ꢀetting (Reg 02h)),
the lock-detect circuit ꢀhould be retrained by toggling Reg 07h [20] Off and then back On.
The lock-detect indication can be read from the sPI via Reg 12h[1], or can be exported on the LD_sDO pin via the
GPO mux(Reg 0Fh[4:0]). see LD_sDO pin deꢀcription for more information.
cꢀꢂꢄꢊ sꢄꢁp Pꢉꢊvꢊꢇꢅꢁꢆꢇ (csP)
When changing frequency and the VCO iꢀ not yet locked to the reference, the inꢀtantaneouꢀ frequencieꢀ of the two PD
inputꢀ are different, and the phaꢀe difference of the two inputꢀ at the PD varieꢀ rapidly over a range much greater than
+/-2π radianꢀ. since the gain of the PD varieꢀ linearly with phaꢀe up to +/-2π, the gain of a conventional PD will cycle
from high gain, when the phaꢀe difference approacheꢀ a multiple of 2π, to low gain, when the phaꢀe difference iꢀ
ꢀlightly larger than 0 radianꢀ. The output current from the charge pump will cycle from maximum to minimum even
though the VCO haꢀ not yet reached itꢀ final frequency.
The charge on the loop filter ꢀmall cap may actually diꢀcharge ꢀlightly during the low gain portion of the cycle. Thiꢀ can
make the VCO frequency actually reverꢀe temporarily during locking. Thiꢀ phenomenon iꢀ known aꢀ cycle ꢀlipping.
Cycle ꢀlipping cauꢀeꢀ the pull-in rate during the locking phaꢀe to vary cyclically. Cycle slipping increaꢀeꢀ the time to
lock to a value much greater than that predicted by normal ꢀmall ꢀignal Laplace analyꢀiꢀ.
The HMC703LP4E mitigateꢀ the effectꢀ of cycle-ꢀlipꢀ by increaꢀing the charge-pump current when the phaꢀe error iꢀ
larger than ~220 degreeꢀ or ~14 nꢀ (whichever iꢀ leꢀꢀ aꢀ meaꢀured by the lock-detect circuit). The circuit iꢀ normally
moꢀt effective for PD frequencieꢀ <= 50 MHz.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
PD Pꢆꢄꢃꢉꢁꢅꢀ
Reg 0Bh[4]=0 ꢀetꢀ the PD polarity for uꢀe with a paꢀꢀive loop filter together with a VCO with a poꢀitive tuning ꢀlope
(increaꢀing tuning voltage increaꢀeꢀ VCO frequency).
Reg 0Bh[4]=1 invertꢀ the PD polarity. Thiꢀ iꢀ moꢀt often uꢀed if an inverting op-amp iꢀ uꢀed in an active loop filter
together with a VCO with a poꢀitive tuning ꢀlope.
chꢃꢉgꢊ Pump tꢉꢁ-ꢈꢅꢃꢅꢊ
Reg 0Bh[5]=Reg 0Bh[6]=0 tri-ꢀtateꢀ the charge pump. Thiꢀ effectively freezeꢀ charge on the loop filter and allowꢀ the
VCO to run open loop, provided that CP offꢀet iꢀ alꢀo diꢀabled.
chꢃꢉgꢊ Pump Gꢃꢁꢇ
Reg 09h[6:0] and Reg 09h[13:7] program current gain ꢀettingꢀ for the charge pump. Pump rangeꢀ can be ꢀet from 0 µA
to 2.54 mA in 20uA ꢀtepꢀ. Charge pump gain affectꢀ the loop bandwidth. The product of VCO gain (Kvco) and charge
pump gain (Kcp) can be held conꢀtant for VCO’ꢀ that have a wide ranging Kvco by adjuꢀting the charge pump gain. Thiꢀ
compenꢀation helpꢀ to keep the loop bandwidth conꢀtant.
In addition to the normal CP current aꢀ deꢀcribed above, there iꢀ alꢀo an extra output ꢀource of current that offerꢀ
improved noiꢀe performance. HiKcp provideꢀ an output current that iꢀ proportional to the loop filter voltage. Thiꢀ being
the caꢀe, HiKcp ꢀhould only be operated with active op-amp loop filterꢀ that define the voltage aꢀ ꢀeen by the charge
pump pin. With 2.5 V aꢀ obꢀerved at the charge pump pin, the HiKcp current iꢀ 3.5 mA.
There are ꢀeveral configurationꢀ that could be uꢀed with the HiKcp feature. For loweꢀt noiꢀe, HiKcp could be uꢀed
without the normal charge pump current (the charge pump current would be ꢀet to 0). In thiꢀ caꢀe, the loop filter would
be deꢀigned with 3.5 mA aꢀ the effective charge pump current.
Another poꢀꢀible configuration iꢀ to operate with both the HiKcp and normal charge pump current ꢀourceꢀ. In thiꢀ caꢀe
the effective charge pump current would be 3.5mA + programmed normal charge pump current which could offer a
maximum of 6 mA.
With paꢀꢀive loop filterꢀ the voltage ꢀeen by the charge pump pin will vary which would cauꢀe the HiKcp current to vary
widely. Aꢀ ꢀuch, HiKcp ꢀhould not be uꢀed on paꢀꢀive loop filter implementationꢀ.
A ꢀimplified diagram of the charge pump iꢀ ꢀhown in Figure 39. The current gain of the pump in Ampꢀ/radian iꢀ equal
to the gain ꢀetting of thiꢀ regiꢀter divided by 2π.
chꢃꢉgꢊ Pump oꢋꢋꢈꢊꢅ
Reg 09h[20:14] controlꢀ the charge pump current offꢀetꢀ. Reg 09h[21] and Reg 09h[22] enable the UP and DN offꢀet
currentꢀ reꢀpectively. Normally, only one iꢀ uꢀed at a time. Aꢀ mentioned earlier charge pump offꢀetꢀ affect fractional
mode linearity . Offꢀet polarity ꢀhould be choꢀen ꢀuch that the divided VCO lagꢀ the reference ꢀignal. Thiꢀ meanꢀ
down for non-inverting loop filterꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 35
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Figure 39. Charge Pump Gain and Offset Control - Reg09h
sꢊꢊd rꢊgꢁꢈꢅꢊꢉ ꢃꢇd auꢅꢆsꢊꢊd Mꢆdꢊ
The ꢀtart phaꢀe of the fractional modulator digital phaꢀe accumulator (DPA) may be ꢀet to any valueꢀ via the
ꢀeed regiꢀter Reg 05h. If autoꢀeed Reg 06h[8] iꢀ ꢀet, then the PLL will automatically reload the ꢀtart phaꢀe from
Reg 05h[23:0] into the DPA every time a new fractional frequency iꢀ ꢀelected. If autoꢀeed iꢀ not ꢀet, then the PLL will
ꢀtart new fractional frequencieꢀ with the value left in the DPA from the laꢀt frequency. Hence the ꢀtart phaꢀe will
effectively be random. Certain zero or binary ꢀeed valueꢀ may cauꢀe ꢀpuriouꢀ energy correlation at ꢀpecific
frequencieꢀ. Correlated ꢀpurꢀ are advantageouꢀ only in very ꢀpecial caꢀeꢀ where the ꢀpuriouꢀ are known to be far out
of band and are removed in the loop filter. For moꢀt caꢀeꢀ a pꢀeudo-random ꢀeed ꢀetting iꢀ recommended. Further,
ꢀince the autoꢀeed alwayꢀ ꢀtartꢀ the accumulatorꢀ at the ꢀame place, performance iꢀ repeatable if autoꢀeed iꢀ uꢀed.
Reg 05h’ꢀ default value typically provideꢀ good performance.
Pꢆwꢊꢉ ꢆꢇ rꢊꢈꢊꢅ
The HMC703LP4E featureꢀ a hardware Power on Reꢀet (POR) on the digital ꢀupply DVDD. All chip regiꢀterꢀ will be
reꢀet to default ꢀtateꢀ approximately 250 µꢀ after power up of DVDD. Once the ꢀupply iꢀ fully up, if the power ꢀupply
then dropꢀ below 0.5 V the digital portion will reꢀet. Note that the sPI control inputꢀ muꢀt alꢀo be 0 at power-down,
otherwiꢀe they will inadvertently power the chip via the EsD protection network.
Pꢆwꢊꢉ Dꢆwꢇ Mꢆdꢊ
Hꢃꢉdwꢃꢉꢊ Pꢆwꢊꢉ Dꢆwꢇ
Chip enable may be controlled from the hardware CEN pin 23, or it may be controlled from the ꢀerial port. Reg 01h[0] =1
aꢀꢀignꢀ control to the CEN pin. Reg 01h[0] =0 aꢀꢀignꢀ control to the ꢀerial port Reg 01h[1]. For hardware teꢀt reaꢀonꢀ or
ꢀome ꢀpecial applicationꢀ it iꢀ poꢀꢀible to force certain blockꢀ to remain on inꢀide the chip , even if the chip iꢀ diꢀabled.
see the regiꢀter Reg 01h deꢀcription for more detailꢀ.
chꢁp idꢊꢇꢅꢁfiꢂꢃꢅꢁꢆꢇ
Verꢀion information may be read from the ꢀyntheꢀizer by reading the content of chip_ID in Reg 00h.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
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8 GHz fractional syntHesizer
Gꢊꢇꢊꢉꢃꢄ Puꢉpꢆꢈꢊ ouꢅpuꢅ (GPo) Pꢁꢇ
The PLL ꢀhareꢀ the LD_sDO (Lock-Detect/serial Data Out) pin to perform variouꢀ functionꢀ. While the pin iꢀ moꢀt
commonly uꢀed to read back regiꢀterꢀ from chip via the sPI, it iꢀ alꢀo capable of exporting a variety of intereꢀting
ꢀignalꢀ and real time teꢀt waveformꢀ (including Lock Detect). It iꢀ driven by a tri-ꢀtate CMOs driver with ~200 Ω Rout.
It haꢀ logic aꢀꢀociated with it to dynamically ꢀelect whether the driver iꢀ enabled, and to decide which data to export
from the chip.
In itꢀ default configuration, after power-on-reꢀet, the output driver iꢀ diꢀabled, and only driveꢀ during appropriately
addreꢀꢀed sPI readꢀ. Thiꢀ allowꢀ it to ꢀhare the output with other deviceꢀ on the ꢀame buꢀ.
Depending on the sPI mode, the read ꢀection of sPI cycle iꢀ recognized differently
HMC sPI Mode: The driver iꢀ enabled during the laꢀt 24 bitꢀ of sPI READ cycle (not during write cycleꢀ).
Open sPI Mode: The driver iꢀ enabled if the chip iꢀ addreꢀꢀed - ie. The laꢀt 3 bitꢀ of sPI cycle = ‘000’b before the
riꢀing edge of sEN (Note A).
To conꢀiꢀtently monitor any of the GPO ꢀignalꢀ, including Lock Detect, ꢀet Reg 0Fh[7] = 1 to keep the sDO driver
alwayꢀ on. Thiꢀ ꢀtopꢀ the LDO driver from tri-ꢀtating and meanꢀ that the sDO line cannot be ꢀhared with other deviceꢀ.
The chip will naturally ꢀwitch away from the GPO data and export the sDO during an sPI read (Note B). To prevent
thiꢀ automatic data ꢀelection, and alwayꢀ ꢀelect the GPO ꢀignal, ꢀet “Prevent AutoMux of sDO” (Reg 0Fh[6] = 1). The
phaꢀe noiꢀe performance at thiꢀ output iꢀ poor and uncharacterized. Alꢀo, the GPO output ꢀhould not be toggling
during normal operation. Otherwiꢀe the ꢀpectral performance may degrade.
Note that there are additional controlꢀ available, which may be helpful if ꢀharing the buꢀ with other deviceꢀ:
•
To allow the driver to be active (ꢀubject to the conditionꢀ above) even when the chip iꢀ diꢀabled -
ꢀet Reg 01h[7] = 1.
•
•
To diꢀable the driver completely, ꢀet Reg 08h[5] = 0 (it takeꢀ precedence over all elꢀe).
To diꢀable either the pull-up or pull-down ꢀectionꢀ of the driver, Reg 0Fh[8] = 0 or Reg 0Fh[9] = 0 reꢀpectively.
Note A: If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the part will start to drive the
bus.
Note B: In Open Mode, the active portion of the read is defined between the 1st SCK rising edge after SEN, to the
next rising edge of SEN.
Example scenarioꢀ:
•
Drive sDO during readꢀ, tri-ꢀtate otherwiꢀe (to allow buꢀ-ꢀharing)
No action required.
•
•
Drive sDO during readꢀ, Lock Detect otherwiꢀe
•
•
set GPO select Reg 0Fh[4:0] = ‘00001’ (which iꢀ default)
set “Prevent GPO driver diꢀable” (Reg 0Fh[7] = 1)
•
Alwayꢀ drive Lock Detect
•
•
•
set “ Prevent AutoMux of sDO” Reg 0Fh[6] = 1
set GPO select Reg 0Fh[4:0]= 00001 (which iꢀ default)
set “Prevent GPO driver diꢀable” (Reg 0Fh[7] = 1))
The ꢀignalꢀ available on the GPO are ꢀelected by changing “GPO select”, Reg 0Fh[4:0].
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
Vco tuꢇꢁꢇg
Pꢃꢈꢈꢁvꢊ fꢁꢄꢅꢊꢉ
The HMC703LP4E iꢀ targeted for high performance applicationꢀ with an external VCO. The ꢀyntheꢀizer charge pump
haꢀ been deꢀigned to work directly with VCOꢀ that can be tuned nominally over 1.0 to 4.0 Voltꢀ on the varactor tuning
port with a +5 V charge pump ꢀupply voltage. slightly wider rangeꢀ are poꢀꢀible with a +5.2 V charge pump ꢀupply or
with ꢀlightly degraded performance. Hittite PLL Deꢀign ꢀoftware iꢀ available to deꢀign paꢀꢀive loop filterꢀ driven directly
from the PLL charge pump.
Hꢁgh Vꢆꢄꢅꢃgꢊ tuꢇꢁꢇg, aꢂꢅꢁvꢊ fꢁꢄꢅꢊꢉ
Optionally an external op-amp may be uꢀed in the loop filter to ꢀupport VCOꢀ requiring higher voltage tuning rangeꢀ.
Loop filter deꢀign iꢀ highly application ꢀpecific, and can have ꢀignificant impact on the PLL performance. Itꢀ impact on
PLL performance ꢀhould be well characterized, and optimized for beꢀt PLL performance. Hittite’ꢀ PLL Deꢀign ꢀoftware
iꢀ available to deꢀign active loop filterꢀ with external op-ampꢀ. Variouꢀ filter configurationꢀ are ꢀupported.
Figure 40. Synthesizer with Active Loop Filter and Conventional External VCO
Main serial Port
sꢊꢉꢁꢃꢄ Pꢆꢉꢅ Mꢆdꢊꢈ ꢆꢋ opꢊꢉꢃꢅꢁꢆꢇ
The HMC PLL-VCO ꢀerial port interface can operate in two different modeꢀ of operation.
a. HMC Mode (HMC Legacy Mode) - single ꢀlave per HMCsPI Buꢀ.
b. Open Mode - Up to 8 ꢀlaveꢀ per HMCsPI Buꢀ. The HMC703LP4E only uꢀeꢀ 5 bitꢀ of addreꢀꢀ ꢀpace.
Both protocolꢀ ꢀupport 5 bitꢀ of regiꢀter addreꢀꢀ ꢀpace. HMC Mode can ꢀupport up to 6 bitꢀ of regiꢀter addreꢀꢀ but, iꢀ
reꢀtricted to 5 bitꢀ when compatibility with Open Mode iꢀ offered.
rꢊgꢁꢈꢅꢊꢉ 0 Mꢆdꢊꢈ
Regiꢀter 0 haꢀ a dedicated function in each mode. Open Mode allowꢀ wider compatibility with other manufacturerꢀ sPI
protocolꢀ.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 8. rꢊgꢁꢈꢅꢊꢉ 0 cꢆmpꢃꢉꢁꢈꢆꢇ - sꢁꢇgꢄꢊ vꢈ Muꢄꢅꢁ-Uꢈꢊꢉ Mꢆdꢊꢈ
single Uꢀer
HMC Mode
single Or Multi-Uꢀer
Open Mode
Chip ID
24 Bitꢀ
Chip ID
24Bitꢀ
READ
Read Addreꢀꢀ [4:0]
soft reꢀet [5]
soft Reꢀet,
WRITE
General strobeꢀ
General strobeꢀ [24:6]
sꢊꢉꢁꢃꢄ Pꢆꢉꢅ Mꢆdꢊ Dꢊꢂꢁꢈꢁꢆꢇ ꢃꢋꢅꢊꢉ Pꢆwꢊꢉ-oꢇ rꢊꢈꢊꢅ
On power up, both typeꢀ of modeꢀ are active and liꢀtening. All digital IO muꢀt be low at power-up.
A deciꢀion to ꢀelect the deꢀired serial Port mode (protocol) iꢀ made on the firꢀt occurrence of sEN or sCK , after which
the serial Port mode iꢀ fixed and only changeable by a power down.
a. If a riꢀing edge on sEN iꢀ detected firꢀt HMC Mode iꢀ ꢀelected.
b. If a riꢀing edge on sCK iꢀ detected firꢀt Open mode iꢀ ꢀelected.
sꢊꢉꢁꢃꢄ Pꢆꢉꢅ HMc Mꢆdꢊ - sꢁꢇgꢄꢊ Pll
HMC Mode (Legacy Mode) ꢀerial port operation can only addreꢀꢀ and communicate with a ꢀingle PLL, and iꢀ compat-
ible with moꢀt HMC PLLꢀ and PLLꢀ with integrated VCOꢀ.
The HMC Mode protocol for the ꢀerial port iꢀ deꢀigned for a 4 wire interface with a fixed protocol featuring
a. 1 Read/Write bit
b. 6 Addreꢀꢀ bitꢀ
c. 24 data bitꢀ
sꢊꢉꢁꢃꢄ Pꢆꢉꢅ opꢊꢇ Mꢆdꢊ
The serial Port Open Mode featureꢀ:
a. Compatibility with general ꢀerial port protocolꢀ that uꢀe a ꢀhift and ꢀtrobe approach to
communication.
b. Compatible with HMC multi-Chip ꢀolutionꢀ, uꢀeful to addreꢀꢀ multiple chipꢀ of variouꢀ typeꢀ from a
ꢀingle ꢀerial port buꢀ.
The HMC Open Mode protocol haꢀ the following general featureꢀ:
a. 3 bit chip addreꢀꢀ, can addreꢀꢀ up to 8 deviceꢀ connected to the ꢀerial buꢀ ( = 000 on
HMC703LP4E)
b. Wide compatibility with multiple protocolꢀ from multiple vendorꢀ
c. simultaneouꢀ Write/Read during the sPI cycle
d. 5 bit regiꢀter addreꢀꢀ ꢀpace
e. 3 wire for Write Only capability, 4 wire for Read/Write capability.
HMC RF PLLꢀ with integrated VCOꢀ alꢀo ꢀupport HMC Open Mode. HMC700, HMC701, HMC702 and ꢀome genera-
tionꢀ of microwave PLLꢀ with integrated VCOꢀ do not ꢀupport Open Mode.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC703LP4E
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8 GHz fractional syntHesizer
Typical HMC Open Mode ꢀerial port operation can be run with sCK at ꢀpeedꢀ up to 50 MHz.
sꢊꢉꢁꢃꢄ Pꢆꢉꢅ HMc Mꢆdꢊ Dꢊꢅꢃꢁꢄꢈ
Typical ꢀerial port HMC Mode operation can be run with sCK at ꢀpeedꢀ up to 50MHz.
HMc Mꢆdꢊ - sꢊꢉꢁꢃꢄ Pꢆꢉꢅ Write opꢊꢉꢃꢅꢁꢆꢇ
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
tꢃbꢄꢊ 9. sPi HMc Mꢆdꢊ - Wꢉꢁꢅꢊ tꢁmꢁꢇg chꢃꢉꢃꢂꢅꢊꢉꢁꢈꢅꢁꢂꢈ
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sEN to sCK ꢀetup time
sDI to sCK ꢀetup time
sCK to sDI hold time
sEN low duration
8
3
nꢀec
nꢀec
nꢀec
nꢀec
nꢀec
MHz
1
t2
t3
t4
t5
3
20
10
sCK to sEN fall
Max sPI Clock Frequency
50
A typical HMC Mode WRITE cycle iꢀ ꢀhown in Figure 41.
a. The Maꢀter (hoꢀt) both aꢀꢀertꢀ sEN (serial Port Enable) and clearꢀ sDI to indicate a WRITE cycle,
followed by a riꢀing edge of sCK.
b. The ꢀlave (ꢀyntheꢀizer) readꢀ sDI on the 1ꢀt riꢀing edge of sCK after sEN. sDI low indicateꢀ a Write
cycle (/WR).
c. Hoꢀt placeꢀ the ꢀix addreꢀꢀ bitꢀ on the next ꢀix falling edgeꢀ of sCK, MsB firꢀt.
d. slave ꢀhiftꢀ the addreꢀꢀ bitꢀ in the next ꢀix riꢀing edgeꢀ of sCK (2-7).
e. Hoꢀt placeꢀ the 24 data bitꢀ on the next 24 falling edgeꢀ of sCK, MsB firꢀt.
f. slave ꢀhiftꢀ the data bitꢀ on the next 24 riꢀing edgeꢀ of sCK (8-31).
g. The data iꢀ regiꢀtered into the chip on the 32nd riꢀing edge of sCK.
h. sEN iꢀ cleared after a minimum delay of t5. Thiꢀ completeꢀ the write cycle.
Figure 41. Serial Port Timing Diagram - HMC Mode WRITE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
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8 GHz fractional syntHesizer
HMc Mꢆdꢊ - sꢊꢉꢁꢃꢄ Pꢆꢉꢅ reaD opꢊꢉꢃꢅꢁꢆꢇ
A typical HMC Mode READ cycle iꢀ ꢀhown in Figure 42.
a. The Maꢀter (hoꢀt) aꢀꢀertꢀ both sEN (serial Port Enable) and sDI to indicate a READ cycle, followed
by a riꢀing edge sCK. Note: The Lock Detect (LD) function iꢀ uꢀually multiplexed onto the LD_sDO
pin. It iꢀ ꢀuggeꢀted that LD only be conꢀidered valid when sEN iꢀ low. In fact LD will not toggle until
the firꢀt active data bit toggleꢀ on LD_sDO, and will be reꢀtored immediately after the trailing edge
of the LsB of ꢀerial data out aꢀ ꢀhown in Figure 42.
b. The ꢀlave (ꢀyntheꢀizer) readꢀ sDI on the 1ꢀt riꢀing edge of sCK after sEN. sDI high initiateꢀ the
READ cycle (RD)
c. Hoꢀt placeꢀ the ꢀix addreꢀꢀ bitꢀ on the next ꢀix falling edgeꢀ of sCK, MsB firꢀt.
d. slave regiꢀterꢀ the addreꢀꢀ bitꢀ on the next ꢀix riꢀing edgeꢀ of sCK (2-7).
e. slave ꢀwitcheꢀ from Lock Detect and placeꢀ the requeꢀted 24 data bitꢀ on sD_LDO on the next 24
riꢀing edgeꢀ of sCK (8-31), MsB firꢀt .
f. Hoꢀt regiꢀterꢀ the data bitꢀ on the next 24 falling edgeꢀ of sCK (8-31).
g. slave reꢀtoreꢀ Lock Detect on the 32nd riꢀing edge of sCK.
h. sEN iꢀ cleared after a minimum delay of t6. Thiꢀ completeꢀ the cycle.
tꢃbꢄꢊ 10. sPi HMc Mꢆdꢊ - rꢊꢃd tꢁmꢁꢇg chꢃꢉꢃꢂꢅꢊꢉꢁꢈꢅꢁꢂꢈ
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sEN to sCK ꢀetup time
sDI ꢀetup to sCK time
sCK to sDI hold time
sEN low duration
8
3
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
1
t2
t3
t4
t5
t6
3
20
sCK to sDO delay
sCK to sEN fall
8.2nꢀ+0.2nꢀ/pF
10
Figure 42. HMC Mode Serial Port Timing Diagram - READ
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
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HMC703LP4E
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8 GHz fractional syntHesizer
sꢊꢉꢁꢃꢄ Pꢆꢉꢅ opꢊꢇ Mꢆdꢊ Dꢊꢅꢃꢁꢄꢈ
opꢊꢇ Mꢆdꢊ - sꢊꢉꢁꢃꢄ Pꢆꢉꢅ Write opꢊꢉꢃꢅꢁꢆꢇ
tꢃbꢄꢊ 11. sPi opꢊꢇ Mꢆdꢊ - Wꢉꢁꢅꢊ tꢁmꢁꢇg chꢃꢉꢃꢂꢅꢊꢉꢁꢈꢅꢁꢂꢈ
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sDI ꢀetup time
sDI hold time
3
3
nꢀ
nꢀ
1
t2
t3
t4
t5
sEN low duration
sEN high duration
10
10
10
DC
10
nꢀ
nꢀ
sCK 32 Riꢀing Edge to sEN Riꢀing Edge
serial port Clock speed
nꢀ
50
MHz
nꢀ
t
sEN to sCK Recovery Time
6
A typical WRITE cycle iꢀ ꢀhown in Figure 43.
a. The Maꢀter (hoꢀt) placeꢀ 24 bit data, d23:d0, MsB firꢀt, on sDI on the firꢀt 24 falling edgeꢀ of sCK.
b. the ꢀlave (ꢀyntheꢀizer) ꢀhiftꢀ in data on sDI on the firꢀt 24 riꢀing edgeꢀ of sCK
c. Maꢀter placeꢀ 5 bit regiꢀter addreꢀꢀ to be written to, r4:r0, MsB firꢀt, on the next 5 falling edgeꢀ of
sCK (25-29)
d. slave ꢀhiftꢀ the regiꢀter bitꢀ on the next 5 riꢀing edgeꢀ of sCK (25-29).
e. Maꢀter placeꢀ 3 bit chip addreꢀꢀ, a2:a0, MsB firꢀt, on the next 3 falling edgeꢀ of sCK (30-32). The
HMC703LP4E chip addreꢀꢀ iꢀ fixed at 000.
f. slave ꢀhiftꢀ the chip addreꢀꢀ bitꢀ on the next 3 riꢀing edgeꢀ of sCK (30-32).
g. Maꢀter aꢀꢀertꢀ sEN after the 32nd riꢀing edge of sCK.
h. slave regiꢀterꢀ the sDI data on the riꢀing edge of sEN.
Figure 43. Open Mode - Serial Port Timing Diagram - WRITE
opꢊꢇ Mꢆdꢊ - sꢊꢉꢁꢃꢄ Pꢆꢉꢅ reaD opꢊꢉꢃꢅꢁꢆꢇ
A typical READ cycle iꢀ ꢀhown in Figure 44.
In general, in Open Mode the LD_sDO line iꢀ alwayꢀ active during the WRITE cycle. During any Open Mode sPI cycle
LD_sDO will contain the data from the addreꢀꢀ pointed to by Reg 00h[4:0]. If Reg 00h[4:0] iꢀ not changed then the ꢀame
data will alwayꢀ be preꢀent on LD_sDO when an Open Mode cycle iꢀ in progreꢀꢀ. If it iꢀ deꢀired to READ from a ꢀpe-
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
6 - 42
Application Support: Phone: 1-800-ANALOG-D
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
cific addreꢀꢀ, it iꢀ neceꢀꢀary in the firꢀt sPI cycle to write the deꢀired addreꢀꢀ to Reg 00h[4:0], then in the next sPI cycle
the deꢀired data will be available on LD_sDO.
An example of the Open Mode two cycle procedure to read from any random addreꢀꢀ iꢀ aꢀ followꢀ:
a. The Maꢀter (hoꢀt), on the firꢀt 24 falling edgeꢀ of sCK placeꢀ 24 bit data, d23:d0, MsB firꢀt, on sDI
aꢀ ꢀhown in Figure 44. d23:d5 ꢀhould be ꢀet to zero. d4:d0 = addreꢀꢀ of the regiꢀter to be READ on
the next cycle.
b. the ꢀlave (ꢀyntheꢀizer) ꢀhiftꢀ in data on sDI on the firꢀt 24 riꢀing edgeꢀ of sCK
c. Maꢀter placeꢀ 5 bit regiꢀter addreꢀꢀ , r4:r0, ( the addreꢀꢀ the WRITE ADDREss regiꢀter), MsB firꢀt,
on the next 5 falling edgeꢀ of sCK (25-29). r4:r0=00000.
d. slave ꢀhiftꢀ the regiꢀter bitꢀ on the next 5 riꢀing edgeꢀ of sCK (25-29).
e. Maꢀter placeꢀ 3 bit chip addreꢀꢀ, a2:a0, MsB firꢀt, on the next 3 falling edgeꢀ of sCK (30-32).The
HMC703LP4E chip addreꢀꢀ iꢀ fixed at 000.
f. slave ꢀhiftꢀ the chip addreꢀꢀ bitꢀ on the next 3 riꢀing edgeꢀ of sCK (30-32).
g. Maꢀter aꢀꢀertꢀ sEN after the 32nd riꢀing edge of sCK.
h. slave regiꢀterꢀ the sDI data on the riꢀing edge of sEN.
i. Maꢀter clearꢀ sEN to complete the addreꢀꢀ tranꢀfer of the two part READ cycle.
j. If we do not wiꢀh to write data to the chip at the ꢀame time aꢀ we do the ꢀecond cycle , then it iꢀ
recommended to ꢀimply rewrite the ꢀame contentꢀ on sDI to Regiꢀter zero on the READ back part
of the cycle.
k. Maꢀter placeꢀ the ꢀame sDI data aꢀ the previouꢀ cycle on the next 32 falling edgeꢀ of sCK.
l. slave (ꢀyntheꢀizer) ꢀhiftꢀ the sDI data on the next 32 riꢀing edgeꢀ of sCK.
m. slave placeꢀ the deꢀired data (i.e. data from addreꢀꢀ in Reg 00h[4:0 ]) on LD_sDO on the next 32
riꢀing edgeꢀ of sCK. Lock Detect iꢀ diꢀabled.
n. Maꢀter aꢀꢀertꢀ sEN after the 32nd riꢀing edge of sCK to complete the cycle and revert back to Lock
Detect on LD_sDO.
Note that if the chip addreꢀꢀ bitꢀ are unrecognized (a2:a0), the ꢀlave will tri-ꢀtate the LD_sDO output to prevent a poꢀ-
ꢀible buꢀ contention iꢀꢀue.
tꢃbꢄꢊ 12. sPi opꢊꢇ Mꢆdꢊ - rꢊꢃd tꢁmꢁꢇg chꢃꢉꢃꢂꢅꢊꢉꢁꢈꢅꢁꢂꢈ
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sDI ꢀetup time
sDI hold time
3
3
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
1
t2
t3
t4
t5
t6
t7
sEN low duration
sEN high duration
10
10
sCK Riꢀing Edge to sDO time
sEN to sCK Recovery Time
8.2+0.2nꢀ/pF
10
10
sCK 32 Riꢀing Edge to sEN Riꢀing Edge
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 43
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Figure 44. Open Mode - Serial Port Timing Diagram - READ Operation 2-Cycles
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 44
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
reGister MaP
tꢃbꢄꢊ 13. rꢊg 00h iD rꢊgꢁꢈꢅꢊꢉ (rꢊꢃd oꢇꢄꢀ)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[23:0]
RO
chip_ID
24
97370h
PLL ID
tꢃbꢄꢊ 13. rꢊg 00h opꢊꢇ Mꢆdꢊ rꢊꢃd addꢉꢊꢈꢈ/rst sꢅꢉꢆbꢊ rꢊgꢁꢈꢅꢊꢉ (Wꢉꢁꢅꢊ oꢇꢄꢀ) (Continued)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[4:0]
WO
ReadAddr
5
0
Write the intended read addreꢀꢀ to thiꢀ regiꢀter for Open Mode
regiꢀter readꢀ. On the 1ꢀt sPI clock of the next cycle the data iꢀ
read and the ꢀhift-out beginꢀ.
tꢃbꢄꢊ 13. rꢊg 00h opꢊꢇ Mꢆdꢊ rꢊꢃd addꢉꢊꢈꢈ rꢊgꢁꢈꢅꢊꢉ (Wꢉꢁꢅꢊ oꢇꢄꢀ) (Continued)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
5
WO
softRꢀt
1
0
soft-reꢀet. When 1, it Reꢀetꢀ the regiꢀterꢀ to POR ꢀtate, and iꢀ-
ꢀueꢀ POR to analog.
tꢃbꢄꢊ 14. rꢊg 01h rst rꢊgꢁꢈꢅꢊꢉ
BIT
0
TYPE
R/W
NAME
W
0
DEFLT
0
DEsCRIPTION
EnPinsel
If 1, the maꢀter chip enable iꢀ taken from the pin rather than from
the sPI.
1
R/W
R/W
EnFromsPI
EnKeepOnꢀ
1
8
1
0
The maꢀter Enable from the sPI. Write a 0 to power-down the chip.
[9:2]
While the chip iꢀ diꢀabled, the uꢀer haꢀ the option to keep the
following ꢀub-circuitꢀ active by writing a 1 to the appropriate bitꢀ.
[2] Biaꢀ, [3] PFD, [4] CHP, [5] RefBuf, [6] VCOBuf, [7] GPO, [8]
VCODIVA, [9] VCODIVB
10
R/W
EnsyncChpDiꢀ
1
0
If 1, then following a diꢀable event, the charge-pump iꢀ diꢀabled
ꢀynchronouꢀly on the falling edge of the divided reference to tri-
ꢀtate the charge pump without tranꢀient.
tꢃbꢄꢊ 15. rꢊg 02h refDiV rꢊgꢁꢈꢅꢊꢉ
BIT
TYPE
R/W
NAME
rdiv
W
DEFLT
1
DEsCRIPTION
[13:0]
14
Reference Divider ’R’ Value
Divider uꢀe alꢀo requireꢀ refBufEn Reg08[3]=1
min 1d
max 16383d
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 45
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 16. rꢊg 03h fꢉꢊquꢊꢇꢂꢀ rꢊgꢁꢈꢅꢊꢉ - iꢇꢅꢊgꢊꢉ Pꢃꢉꢅ
BIT
TYPE
R/W
NAME
intg
W
DEFLT
25d
DEsCRIPTION
[15:0]
16
The (baꢀe) integer portion of the preꢀcaler divide ratio. In any of
the fractional modeꢀ of operation, thiꢀ value iꢀ double buffered, and
doeꢀ not take effect until a ‘Trigger’ event. see ‘Operation Modeꢀ’
for more information. In integer mode, thiꢀ value can range from
16 to 65535. In fractional mode it ꢀhould be reꢀtricted between 20
and 65531.
tꢃbꢄꢊ 17. rꢊg 04h fꢉꢊquꢊꢇꢂꢀ rꢊgꢁꢈꢅꢊꢉ - fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Pꢃꢉꢅ
BIT
TYPE
R/W
NAME
frac
W
DEFLT
0
DEsCRIPTION
[23:0]
24
VCO Divider Fractional part (24 bit unꢀigned) ꢀee Fractional
Frequency Tuning
24
N
= Reg 04h/2
FRAC
Uꢀed in Fractional Modeꢀ only
min 0d
max 2^24-1 = FFFFFFh = 16,777,215d
tꢃbꢄꢊ 18. rꢊg 05h sꢊꢊd
BIT
TYPE
R/W
NAME
sEED
W
DEFLT
DEsCRIPTION
[23:0]
24
654321h
The initial ꢀtarting point for the fractional modulator at the “Trigger”
poꢀition. Thiꢀ value effectꢀ the phaꢀe of the output, and can effect
ꢀome typeꢀ of ꢀpuriouꢀ content. During ꢀweepꢀ, the modulator can
optionally be reloaded with thiꢀ value at the ꢀtart of each ramp.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 46
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 19. rꢊg 06h sD cfG rꢊgꢁꢈꢅꢊꢉ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
Modulator Type A (1) or Type B(0)
[0]
R/W
R/W
Modulator Type
Reꢀerved 1
1
4
1
Type B iꢀ eaꢀier to filter out of band, but can have reduced in-band
ꢀpectral performance at preꢀcaler frequencieꢀ <1.5GHz.
[4:1]
15
Program 15
see “Operational Modeꢀ” for mode information.
0 - Fractional
1 - Integer
2 - Exact Freq Fractional (Program Reg 0Dh appropriately)
3 - FM mode (Program Reg 0Ch/Reg 0Dh for F2)
4 - PM mode (Program phaꢀe ꢀtep in Reg 0Ah)
5 - sweep - 1 way - Ramp then Hop (Triggered)
6 - sweep - 2 way - Ramp Both directionꢀ (Triggered)
7 - sweep - 2 way Auto - Ramp Both directionꢀ Continuouꢀly
[7:5]
R/W
sD Mode
3
0
Non PM Mode
1: the modulator phaꢀe iꢀ initialized on trigger eventꢀ or at the ꢀtart
of a frequency ramp.
0: the modulator iꢀ not re-initialized
In PM mode (Reg06h[7:5]=4)
1: Trigger on riꢀing edge only
0: Bi-phaꢀe modulation, level dependent
autoꢀeed (Frac modeꢀ)
unidirectional phaꢀe (PM)
[8]
[9]
R/W
R/W
1
1
1
1
Chooꢀeꢀ to uꢀe the external TRIG pin for trigger eventꢀ (frequency
hopꢀ, ramp movement, phaꢀe or FM modulation). The function of
thiꢀ bit and the trigger ꢀyꢀtem vary depending on sD Mode. see
“Operational Modeꢀ” for more information.
External Trigger Enable
(EXTTRIG_EN)
[12:10]
[13]
R/W
R/W
Reꢀerved 7
3
1
7
0
Program to 7
Forceꢀ the modulator clock on, deꢀpite being in integer mode. Thiꢀ
iꢀ uꢀeful to teꢀt coupling from digital to analog.
Force DsM Clock on
[14]
R/W
R/W
BIsT Enable
1
2
0
0
Internal Uꢀe only - Program to 0
Internal Uꢀe only
[16:15]
Number of Biꢀt Cycleꢀ
0 - sD Clock from Mcounter (Recommended > 50MHz)
1 - VDIV PFD Clock
2 - RDIV PFD Clock - Uꢀe for Phaꢀe Coherence
3 - XTAL (Uꢀe for BIsT)
[18:17]
R/W
DsM Clock source
2
0
[19]
[20]
R/W
R/W
Invert DsM Clock
Reꢀerved 0
1
1
0
0
Teꢀt/BIsT only
Program to 0
If 1, the Rdivider can be uꢀed (and exported on GPO), but the PFD
ꢀtill uꢀeꢀ the undivided XTAL
[21]
R/W
Force RDIV bypaꢀꢀ
1
0
The Autoꢀeed bit determineꢀ if the phaꢀe accumulator of the DsM
iꢀ reꢀet at the ꢀtart of a frequency ramp. Normally the other accu-
mulatorꢀ are alꢀo reꢀet - allowing for exact repeatability from cycle-
to-cycle. Thiꢀ extra initialization iꢀ avoided if thiꢀ bit iꢀ ꢀet - which
can lead to more graceful tranꢀientꢀ at the ꢀtart of a ramp.
Diꢀable Reꢀet of
extra accumulatorꢀ on ramp
[22]
R/W
1
0
single ꢀtep ramp mode. Advanceꢀ the ramp one ꢀtep per trigger.
Can be uꢀed to generate arbitrary ꢀweep profileꢀ with an external
trigger. Can alꢀo be uꢀed for ꢀweep ꢀynchronization with the
ꢀyꢀtem.
[23]
R/W
single step Ramp Mode
1
0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 47
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 20. rꢊg 07h lꢆꢂk Dꢊꢅꢊꢂꢅ rꢊgꢁꢈꢅꢊꢉ
BIT
TYPE
NAME
W
DEFLT
5
DEsCRIPTION
[2:0]
R/W
LKDCountꢀ
3
Lock Detect window
ꢀetꢀ the number of conꢀecutive countꢀ of divided VCO that muꢀt
land inꢀide the Lock Detect Window to declare LOCK
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
[10:3]
[11]
R/W
R/W
R/W
R/W
R/W
Reꢀerved
8
1
2
1
1
12d
1
Program 12d
LockDetect Counterꢀ Enable
Reꢀerved
Enable Lock Detect Counterꢀ (R07[14] ꢀhould alꢀo = 1)
Program 0
[13:12]
[14]
0
Lock Detect Timer Enable
Cycle slip Prevention Enable
1
Enable Lock Detect Timer (R07[11] ꢀhould alꢀo = 1)
[15]
0
Increaꢀeꢀ Charge Pump gain for phaꢀe errorꢀ larger than lock-
detect timer.
[19:16]
[20]
R/W
R/W
Reꢀerved 0
4
1
0
0
Reꢀerved
Train Lock Detect Timer
Thiꢀ bit muꢀt be programmed from 0 to 1 after a change of PD
reference clock frequency (via either the external reference or a
change to the Rdivider).
[21]
R/W
Reꢀerved
1
0
Reꢀerved - Program to 1
tꢃbꢄꢊ 21. rꢊg 08h aꢇꢃꢄꢆg en rꢊgꢁꢈꢅꢊꢉ
BIT
[0]
[1]
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
NAME
EnBiaꢀ
EnCP
W
1
1
1
1
1
1
DEFLT
DEsCRIPTION
1
1
1
1
1
1
Biaꢀ
Charge-Pump
PFD
[2]
[3]
[4]
[5]
EnPFD
EnXtal
EnVCO
EnGPO
Reference Buffer
VCO Buffer
GPO Output Buffer Enable (If 0 the buffer iꢀ HiZ, if 1 the buffer MAY
be HiZ depending on GPOsel and sPI activity)
[6]
[7]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EnMcnt
EnPs
1
1
1
1
3
3
1
1
1
1
1
1
1
1
3
3
1
0
0
0
Mcounter
Preꢀcaler
[8]
EnVCOBiaꢀ
EnOpAmp
VCOOutBiaꢀA
VCOOutBiaꢀB
VCOBWsel
RFDiv2sel
XtalLowGain
XtalDiꢀsat
VCO Divider Related Biaꢀeꢀ
Charge-Pump Amplifier
RF Divider Biaꢀ A sel
[9]
[12:10]
[15:13]
[16]
RF Divider Biaꢀ B sel
RF Buffer Biaꢀ sel
[17]
Enableꢀ RF Divide/2
Lowerꢀ the gain (and extendꢀ BW) of the XTAL buffer
Diꢀableꢀ ꢀaturation protection on the XTAL buffer
[18]
[19]
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 48
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 22. rꢊg 09h chꢃꢉgꢊ Pump rꢊgꢁꢈꢅꢊꢉ
BIT
TYPE
R/W
R/W
R/W
NAME
W
DEFLT
100
100
0
DEsCRIPTION
Main sink Current (20uA ꢀtepꢀ)
[6:0]
CPIdn
7
[13:7]
[20:14]
CPIup
7
Main source Current (20uA ꢀtepꢀ)
CPOffꢀet
7
Offꢀet current (5uA ꢀtepꢀ) - see "Charge-Pump Phaꢀe offꢀet" for
more information.
[21]
[22]
[23]
R/W
R/W
R/W
CPsrcEn
CPsnkEn
CPHiK
1
1
1
0
1
0
Offꢀet current polarity (source Offꢀet current)
Recommended 0 in integer mode , PFDInv in FRAC modeꢀ.
Offꢀet current polarity (sink Offꢀet current)
Recommended 0 in integer mode ,NOT PFDInv in FRAC modeꢀ.
Hi Gain Mode (~4mA CP I booꢀt depending on Vcp) - Uꢀe only
with active loop filter configurationꢀ, where Vcp iꢀ controlled to
offer better phaꢀe-noiꢀe.
tꢃbꢄꢊ 23. rꢊg 0ah Mꢆduꢄꢃꢅꢁꢆꢇ sꢅꢊp rꢊgꢁꢈꢅꢊꢉ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[23:0]
R/W
MODsTEP
24
0
Fractional Modulation step ꢀize for Ramp/Phaꢀe Modulation modeꢀ
(Ignored in Integer, Normal Fractional, FM, or Exact Freq modeꢀ)
Thiꢀ value iꢀ ꢀigned two’ꢀ complement. Poꢀitive valueꢀ rampꢀ up,
negative valueꢀ ramp down.
tꢃbꢄꢊ 24. rꢊg 0Bh PD rꢊgꢁꢈꢅꢊꢉ
BIT
[2:0]
[3]
TYPE
R/W
R/W
R/W
NAME
PFDDly
PFDshort
PFDInv
W
3
DEFLT
DEsCRIPTION
1
0
0
Dead-zone avoidance delay (0~1 nꢀ, 3~3 nꢀ. > 3 iꢀ unuꢀed)
Tie both PD inputꢀ to Ref or Div baꢀed on phaꢀe ꢀelect.
1
[4]
1
swap PD inputꢀ for uꢀe in inverting loop configurationꢀ.
0- Uꢀe with a poꢀitive tuning ꢀlope VCO and paꢀꢀive loop filter
(default)
1- Uꢀe with a negative tuning ꢀlope, or with an inverting active loop
filter with a poꢀitive tuning ꢀlope VCO
[5]
[6]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFDUpEn
PFDDnEN
1
1
1
1
1
3
2
2
1
1
0
0
0
0
3
3
0 will diꢀable up pulꢀeꢀ from propagating to the CP
0 will diꢀable dn pulꢀeꢀ from propagating to the CP
1 will force to the top rail.
[7]
PFDForceUp
PFDForceDn
PFDForceMid
PsBiaꢀsel
[8]
1 will force to the bottom rail.
1 will force to mid-rail
[9]
[12:10]
[14:13]
[16:15]
Ps Biaꢀ Current
OpAmpBiaꢀsel
McntClkGatesel
OpAmp Biaꢀ Current
If the quantized divide ratio iꢀ guaranteed to be within a certain
range, thiꢀ feature can be enabled to reduce toggle activity and
power conꢀumption ꢀlightly. (0: 16 to 31, 1: 16 to 127, 2: 16 to 1023,
3: 16 to max)
[17]
[18]
R/W
R/W
VDIVExt
1
1
0
0
Extend VCO Divider Output Pulꢀe width
LKDProcTeꢀttoCP
Muxeꢀ the lock-detect oꢀcillator to the CP force up/dn for obꢀerva-
tion.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 49
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 25. rꢊg 0ch altint
BIT
TYPE
NAME
W
DEFLT
25d
DEsCRIPTION
[15:0]
R/W
ALTINT
16
stop freq for Ramp mode, Alternate freq for FM mode. see “Opera-
tion Modeꢀ” for more information.
tꢃbꢄꢊ 26. rꢊg 0Dh altfrac
BIT
TYPE
NAME
W
DEFLT
0
DEsCRIPTION
[23:0]
R/W
ALTFRAC
24
stop freq for Ramp mode, Alternate freq for FM mode, number of
channelꢀ/boundary for Exact frequency mode. see “Operation
Modeꢀ” for more information.
tꢃbꢄꢊ 27. rꢊg 0eh sPi triG
BIT
TYPE
NAME
W
1
DEFLT
0
DEsCRIPTION
[0]
R/W
sPITRIG
Thiꢀ bit can be uꢀed aꢀ an alternative to the external TRIG pin.
If Reg06h[9] (EXTTRIG_EN)= 0 then thiꢀ bit iꢀ uꢀed to trigger
ꢀweep, FM, or PM modeꢀ,
Trigger requireꢀ initial ꢀtate of 0 followed by a write of 1. Regiꢀter
muꢀt be reꢀet to 0 before ꢀubꢀequent triggerꢀ.
If Reg06[8] = 0, then in PM mode thiꢀ regiꢀter iꢀ level ꢀenꢀitive and
modulateꢀ the phaꢀe.
see “Operating Modeꢀ” for more information.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 50
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 28. rꢊg 0fh GPo rꢊgꢁꢈꢅꢊꢉ
BIT
TYPE
NAME
W
5
DEFLT
1
DEsCRIPTION
[4:0]
R/W
GPOsel
0: static teꢀt voltage - aꢀ defined by Reg 0Fh[5]
1: lock detect
2: lkd trigger
3: lkd window
4: proceꢀꢀ oꢀc teꢀt
5: CsP UP control
6: CsP DN control
7: rdiv core
8: xtal
9: rdiv_pfd
10: vdiv_pfd
11: mcnt_ꢀd
12: ramp_buꢀy
13: ramp_ꢀtarted
14: ramp_trig_pulꢀe
15:biꢀt_buꢀy
16: dn
17: up
18: biꢀt_clk
19: ramp_clk
20: intg ꢀtrobe
21: frac ꢀtrobe
22: ꢀpi ꢀtrobe
23: sPI ꢀle
24: ꢀd reload
25: ꢀd full-reload
29 lkd training
30 outbuf en
[5]
[6]
[7]
R/W
R/W
R/W
GPOTeꢀt
GPOAlwayꢀ
GPOOn
1
1
1
0
0
0
static teꢀt ꢀignal for output when GPOsel=0
Preventꢀ auto-muxing the GPO with sDO. It alwayꢀ ꢀtayꢀ GPO.
Keepꢀ the GPO Driver in output mode (rather than ꢀelective drive
baꢀed on ChipAddr), unleꢀꢀ EnGPO=0.
[8]
[9]
R/W
R/W
GPOPullUpDiꢀ
GPOPullDnDiꢀ
1
1
0
0
Diꢀableꢀ the GPO pull-up tranꢀiꢀtor (ꢀuitable for wired or with exter-
nal pull-up or analog lock-detect methodꢀ)
Diꢀableꢀ the GPO pull-dn tranꢀiꢀtor (ꢀuitable for wired or with exter-
nal pull-dn or analog lock-detect methodꢀ)
tꢃbꢄꢊ 29. rꢊg 10h rꢊꢈꢊꢉvꢊ rꢊgꢁꢈꢅꢊꢉ (rꢊꢃd oꢇꢄꢀ)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[8:0]
RO
Reꢀerved
9
0
Reꢀerved
tꢃbꢄꢊ 30. rꢊg 11h rꢊꢈꢊꢉvꢊ rꢊgꢁꢈꢅꢊꢉ (rꢊꢃd oꢇꢄꢀ)
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
[18:0]
RO
Reserved
19
0
Reserved
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 51
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 31. rꢊg 12h GPo2 rꢊgꢁꢈꢅꢊꢉ (rꢊꢃd oꢇꢄꢀ)
BIT
[0]
[1]
TYPE
NAME
W
DEFLT
DEsCRIPTION
RO
GPO
1
0
0
0
GPO
RO
Lock Detect
Ramp Buꢀy
1
Lock Detect
Ramp Buꢀy
[2]
RO
1
tꢃbꢄꢊ 32. rꢊg 13h Bist sꢅꢃꢅuꢈ (rꢊꢃd oꢇꢄꢀ)
BIT
[15:0]
[16]
TYPE
NAME
W
16
1
DEFLT
DEsCRIPTION
Internal Uꢀe Only
RO
BIsT signature
BIsT Buꢀy
RO
Internal Uꢀe Only
tꢃbꢄꢊ 33. rꢊg 14h lꢆꢂk Dꢊꢅꢊꢂꢅ tꢁmꢊꢉ sꢅꢃꢅuꢈ (rꢊꢃd oꢇꢄꢀ)
BIT
[2:0]
[3]
TYPE
NAME
W
DEFLT
DEsCRIPTION
Lock Detect Timer Trained speed
Lock Detect Timer iꢀ buꢀy training
RO
Lkdspeed
LkdTraining
3
0
0
RO
1
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 52
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
toc
tꢀpꢁꢂꢃꢄ appꢄꢁꢂꢃꢅꢁꢆꢇꢈ1
fuꢇꢂꢅꢁꢆꢇꢃꢄ Dꢁꢃgꢉꢃm 1
fꢊꢃꢅuꢉꢊꢈ
Gꢊꢇꢊꢉꢃꢄ Dꢊꢈꢂꢉꢁpꢅꢁꢆꢇ 1
tꢃbꢄꢊ 1. eꢄꢊꢂꢅꢉꢁꢂꢃꢄ spꢊꢂꢁfiꢂꢃꢅꢁꢆꢇꢈ
tyPical PerforMance cHaracteristics
fꢁguꢉꢊ 1. fꢄꢆꢆꢉ foM
2.5 ma cP cuꢉꢉꢊꢇꢅ
fꢁguꢉꢊ 3. fꢄꢆꢆꢉ foM vꢈ. ouꢅpuꢅ fꢉꢊquꢊꢇꢂꢀ ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
1
2
4
vꢈ.
Mꢆdꢊ
ꢃꢇd
tꢊmp,
4
4
4
[1]
fꢁguꢉꢊ 5. fꢄꢆꢆꢉ foM vꢈ. rꢊꢋꢊꢉꢊꢇꢂꢊ Pꢆwꢊꢉ ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
fꢁguꢉꢊ 2. fꢄꢁꢂkꢊꢉ foM vꢈ. Mꢆdꢊ ꢃꢇd tꢊmp, 2.5 ma cP cuꢉꢉꢊꢇꢅ 4
fꢁguꢉꢊ 4. fꢄꢁꢂkꢊꢉ foM vꢈ. ouꢅpuꢅ fꢉꢊquꢊꢇꢂꢀ ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
4
4
[1]
fꢁguꢉꢊ 6. fꢄꢁꢂkꢊꢉ foM vꢈ. rꢊꢋꢊꢉꢊꢇꢂꢊ Pꢆwꢊꢉ ꢃꢇd Mꢆdꢊ, 2.5 ma cP cuꢉꢉꢊꢇꢅ
fꢁguꢉꢊ 7. fꢄꢁꢂkꢊꢉ foM vꢈ. cP cuꢉꢉꢊꢇꢅ, fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ B, 2.5 ma cP cuꢉꢉꢊꢇꢅ 5
[1]
fꢁguꢉꢊ 9. fꢄꢁꢂkꢊꢉ foM vꢈ. cP Vꢆꢄꢅꢃgꢊ, cP cuꢉꢉꢊꢇꢅ = 2.5 ma
5
[2]
fꢁguꢉꢊ 11. fꢄꢁꢂkꢊꢉ foM vꢈ. cP Vꢆꢄꢅꢃgꢊ, HꢁKꢂp + cP cuꢉꢉꢊꢇꢅ = 6 ma
5
fꢁguꢉꢊ 8. fꢄꢆꢆꢉ foM vꢈ. cP cuꢉꢉꢊꢇꢅ, fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ B, 2.5 ma cP cuꢉꢉꢊꢇꢅ
5
6
fꢁguꢉꢊ
cP cuꢉꢉꢊꢇꢅ = 2.5 ma
fꢁguꢉꢊ 12.
HꢁKꢂp + cP cuꢉꢉꢊꢇꢅ = 6 ma
10.
fꢄꢆꢆꢉ
5
foM
foM
vꢈ.
vꢈ.
cP
cP
Vꢆꢄꢅꢃgꢊ,
Vꢆꢄꢅꢃgꢊ,
[1]
fꢄꢆꢆꢉ
[2]
5
[3]
fꢁguꢉꢊ 13. tꢀpꢁꢂꢃꢄ Phꢃꢈꢊ nꢆꢁꢈꢊ & spuꢉ Pꢊꢉꢋꢆꢉmꢃꢇꢂꢊ ꢃꢅ 8 GHꢌ + 200 kHꢌ
fꢁguꢉꢊ 15. iꢇꢅꢊgꢊꢉ Bꢆuꢇdꢃꢉꢀ
8 GHꢌ + 20 kHꢌ vꢈ. chꢃꢉgꢊ Pump oꢋꢋꢈꢊꢅ
fꢁguꢉꢊ 17. Mꢆdꢊꢄꢄꢊd vꢈ. Mꢊꢃꢈuꢉꢊd Phꢃꢈꢊ nꢆꢁꢈꢊ, iꢇꢅꢊgꢊꢉ Mꢆdꢊ HꢁK ꢃꢅ 8 GHꢌ [7] 6
spuꢉ
ꢃꢅ
[5]
6
[4]
fꢁguꢉꢊ 14. fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Pꢊꢉꢋꢆꢉmꢃꢇꢂꢊ, exꢃꢂꢅ fꢉꢊquꢊꢇꢂꢀ Mꢆdꢊ oꢇ ꢃꢅ 8013.6 MHꢌ
6
fꢁguꢉꢊ 16. rf iꢇpuꢅ lꢁmꢁꢅꢈ [6]6
[8]
fꢁguꢉꢊ 18. Mꢆdꢊꢄꢄꢊd vꢈ. Mꢊꢃꢈuꢉꢊd Phꢃꢈꢊ nꢆꢁꢈꢊ, fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Mꢆdꢊ B, HꢁK ꢃꢅ ~ 8 GHꢌ
6
fꢁguꢉꢊ 19. fꢄꢆꢆꢉ foM nꢊꢃꢉ 8 GHꢌ vꢈ rf iꢇpuꢅ Pꢆwꢊꢉ ꢃꢇd Mꢆdꢊ 7
[9]
fꢁguꢉꢊ 21. rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ sꢊꢇꢈꢁꢅꢁvꢁꢅꢀ, squꢃꢉꢊ Wꢃvꢊ, 50 Ω
7
[10]
fꢁguꢉꢊ 23. rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ rꢊꢅuꢉꢇ lꢆꢈꢈ
7
fꢁguꢉꢊ 20. fꢄꢁꢂkꢊꢉ foM nꢊꢃꢉ 8 GHꢌ vꢈ. rf iꢇpuꢅ Pꢆwꢊꢉ ꢃꢇd Mꢆdꢊ
7
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 53
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
[9]
fꢁguꢉꢊ 22. rꢊꢋꢊꢉꢊꢇꢂꢊ iꢇpuꢅ sꢊꢇꢈꢁꢅꢁvꢁꢅꢀ sꢁꢇuꢈꢆꢁd Wꢃvꢊ, 50 Ω
7
fꢁguꢉꢊ 24. rf iꢇpuꢅ rꢊꢅuꢉꢇ lꢆꢈꢈ [11] 7
fꢁguꢉꢊ 25. 2-Wꢃꢀ auꢅꢆ swꢊꢊp
tꢃbꢄꢊ 2. Pꢁꢇ Dꢊꢈꢂꢉꢁpꢅꢁꢆꢇꢈ
tꢃbꢄꢊ 3. abꢈꢆꢄuꢅꢊ Mꢃxꢁmum rꢃꢅꢁꢇgꢈ
ouꢅꢄꢁꢇꢊ Dꢉꢃwꢁꢇg
8
9
10
11
Table 4. Package Information
12
11
evꢃꢄuꢃꢅꢁꢆꢇ PcB
Table 5. Evaluation Order Information
evꢃꢄuꢃꢅꢁꢆꢇ PcB Bꢄꢆꢂk Dꢁꢃgꢉꢃm
evꢃꢄuꢃꢅꢁꢆꢇ PcB sꢂhꢊmꢃꢅꢁꢂ 13
12
13
Theory Of Operation
PLL Baꢀicꢀ 14
High Performance Low spuriouꢀ Operation 15
Figure of Merit, Noiꢀe Floor, and Flicker Noiꢀe Modelꢀ
14
15
spuriouꢀ Performance
Integer Operation17
Fractional Operation
Operational Modeꢀ
17
18
19
Triggering
20
Fractional Mode or Exact Frequency Mode Frequency Updateꢀ
20
Initial Phaꢀe Control
Frequency Tuning
20
21
Integer Mode
21
Fractional Mode 21
Exact Frequency Mode
22
Uꢀing Hittite Exact Frequency Mode
23
FM Mode
PM Mode
24
24
Bi-Phaꢀe Modulation
Phaꢀe step Control
25
25
Frequency sweep Mode 25
2-Way sweepꢀ 26
1-Way sweepꢀ 27
sꢁꢇgꢄꢊ sꢅꢊp rꢃmp Mꢆdꢊ
Detailed sweeper Configuration
27
28
sweeper Configuration for Ultra Fine step sizeꢀ
29
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 54
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Reference Input stage
Ref Path ’R’ Divider
RF Path 31
30
31
RF Input stage 31
RF Path ’N’ Divider
32
PLL Jitter
Charge Pump and Phaꢀe Detector 33
Charge Pump and Phaꢀe Detector Functionꢀ
Lock Detect 34
Cycle slip Prevention (CsP)
PD Polarity 35
32
33
34
Charge Pump Tri-ꢀtate
Charge Pump Gain
Charge Pump Offꢀet
35
35
35
seed Regiꢀter and Autoseed Mode36
Power on Reꢀet 36
Power Down Mode
Hardware Power Down
Chip Identification
36
36
36
General Purpoꢀe Output (GPO) Pin 37
VCO Tuning
38
38
Paꢀꢀive Filter
High Voltage Tuning, Active Filter 38
MAIN sERIAL PORT 38
serial Port Modeꢀ of Operation
Regiꢀter 0 Modeꢀ38
38
serial Port Mode Deciꢀion after Power-On Reꢀet
serial Port HMC Mode - single PLL39
39
serial Port Open Mode
39
serial Port HMC Mode Detailꢀ
40
HMC Mode - serial Port WRITE Operation 40
HMC Mode - serial Port READ Operation 41
serial Port Open Mode Detailꢀ
42
Open Mode - serial Port WRITE Operation 42
Open Mode - serial Port READ Operation 42
reGister MaP
tꢃbꢄꢊ 13. rꢊg 00h iD rꢊgꢁꢈꢅꢊꢉ (rꢊꢃd oꢇꢄꢀ)
tꢃbꢄꢊ 14. rꢊg 01h rst rꢊgꢁꢈꢅꢊꢉ
tꢃbꢄꢊ 15. rꢊg 02h refDiV rꢊgꢁꢈꢅꢊꢉ45
45
45
45
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 55
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
tꢃbꢄꢊ 16. rꢊg 03h fꢉꢊquꢊꢇꢂꢀ rꢊgꢁꢈꢅꢊꢉ - iꢇꢅꢊgꢊꢉ Pꢃꢉꢅ
tꢃbꢄꢊ 17. rꢊg 04h fꢉꢊquꢊꢇꢂꢀ rꢊgꢁꢈꢅꢊꢉ - fꢉꢃꢂꢅꢁꢆꢇꢃꢄ Pꢃꢉꢅ 46
tꢃbꢄꢊ 18. rꢊg 05h sꢊꢊd
tꢃbꢄꢊ 19. rꢊg 06h sD cfG rꢊgꢁꢈꢅꢊꢉ
tꢃbꢄꢊ 20. rꢊg 07h lꢆꢂk Dꢊꢅꢊꢂꢅ rꢊgꢁꢈꢅꢊꢉ 48
tꢃbꢄꢊ 21. rꢊg 08h aꢇꢃꢄꢆg en rꢊgꢁꢈꢅꢊꢉ
46
46
47
48
tꢃbꢄꢊ 22. rꢊg 09h chꢃꢉgꢊ Pump rꢊgꢁꢈꢅꢊꢉ 49
tꢃbꢄꢊ 23. rꢊg 0ah Mꢆduꢄꢃꢅꢁꢆꢇ sꢅꢊp rꢊgꢁꢈꢅꢊꢉ
49
Table 24. Reg 0Bh PD Regiꢀter
Table 25. Reg 0Ch ALTINT
Table 26. Reg 0Dh ALTFRAC
Table 27. Reg 0Eh sPI TRIG
49
50
50
50
Table 28. Reg 0Fh GPO Regiꢀter 51
Table 29. Reg 10h Reꢀerve Regiꢀter (Read Only)
Table 30. Reg 11h Reꢀerve Regiꢀter (Read Only)
Table 31. Reg 12h GPO2 Regiꢀter (Read Only)
Table 32. Reg 13h BIsT statuꢀ (Read Only) 52
51
51
52
Table 33. Reg 14h Lock Detect Timer statuꢀ (Read Only)
52
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 56
Trademarks and registered trademarks are the property of their respective owners.
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6 - 57
Trademarks and registered trademarks are the property of theirrespectiveowners. ApplicationSupport: Phone: 1-800-ANALOG-D
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent orpatent rightsof Analog Devices.
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
6 - 58
Trademarks and registered trademarks are the property of their respective owners.
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