HMC7950LS6TR [ADI]
2 GHz to 28 GHz, GaAs pHEMT MMIC Low Noise Amplifier;
| 型号： | HMC7950LS6TR |
| 厂家： | 
ADI |
| 描述： | 2 GHz to 28 GHz, GaAs pHEMT MMIC Low Noise Amplifier 射频 微波 |
| 文件： | 总16页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 GHz to 28 GHz, GaAs
pHEMT MMIC Low Noise Amplifier
Data Sheet
HMC7950
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Output power for 1 dB compression (P1dB): 16 dBm typical
Saturated output power (PSAT): 19.5 dBm typical
Gain: 15 dB typical
Noise figure: 2.0 dB typical
Output third-order intercept (IP3): 26 dBm typical
Supply voltage: 5 V at 64 mA
50 Ω matched input/output
NIC
NIC
NIC
1
2
3
11
10
9
NIC
NIC
HMC7950
APPLICATIONS
Test instrumentation
Military and space
V
DD
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The HMC7950 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic microwave
integrated circuit (MMIC). The HMC7950 is a wideband low
noise amplifier that operates between 2 GHz and 28 GHz. The
amplifier typically provides 15 dB of gain, 2.0 dB of noise figure,
26 dBm of output IP3, and 16 dBm of output power for 1 dB gain
compression, requiring 64 mA from a 5 V supply. The HMC7950
is self biased with only a single positive supply needed to
achieve a drain current, IDD, of 64 mA. The HMC7950 also has a
gain control option, VGG2. The HMC7950 amplifier input/outputs
are internally matched to 50 Ω and dc blocked. It comes in a
6 mm × 6 mm, 16-terminal LCC SMT ceramic package that is
easy to handle and assemble.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC7950
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Evaluation Board ............................................................................ 14
Evaluation Board Schematic..................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
2 GHz to 5 GHz Frequency Range............................................. 3
5 GHz to 18 GHz Frequency Range........................................... 3
18 GHz to 28 GHz Frequency Range......................................... 4
DC Specifications ......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
REVISION HISTORY
9/2017—Rev. 0 to Rev. A
Added Figure 37; Renumbered Sequentially .............................. 11
1/2017—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
HMC7950
SPECIFICATIONS
2 GHz TO 5 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to +2.6 V.
OUT is output power.
P
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
2
5
13.5 15.5
0.004
dB/°C
Input
Output
12
13
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
13
16.5
20.5
26.5
3.0
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 4 dBm
NF
4.5
5 GHz TO 18 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to +2.6 V.
OUT is output power.
P
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
5
18
13.3 15
0.007
dB/°C
Input
Output
18
14
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
13
16
19.5
26
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 4 dBm
NF
2.0
3.5
Rev. A | Page 3 of 16
HMC7950
Data Sheet
18 GHz TO 28 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to +2.6 V. POUT
is output power.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
18
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
28
13
16.5
Gain Variation over Temperature
RETURN LOSS
0.012
dB/°C
Input
Output
19
16
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
10
14.5
17
24
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 4 dBm
NF
2.8
5
DC SPECIFICATIONS
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
IDD = 58 mA
IDD
64
100
mA
3
4
5
6
7
5
V
V
V
V
V
V
V
IDD = 61 mA
IDD = 64 mA
IDD = 66 mA
IDD = 69 mA
SUPPLY VOLTAGE
VGG2 PIN
VDD
3
7
VGG2
Normal condition is VGG2 = open
−2.0
2.6
Rev. A | Page 4 of 16
Data Sheet
HMC7950
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage (VDD)
8 V
Second Gate Bias Voltage (VGG2)
Radio Frequency Input Power (RFIN)
Channel Temperature
−2.5 V to +3 V
20 dBm
175°C
θ
JC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package Type
EP-16-21
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 17.2 mW/°C Above 85°C)
1.55 W
θJC
Unit
Maximum Peak Reflow Temperature (MSL3)1 260°C
58
°C/W
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
−65°C to +150°C
−40°C to +85°C
250 V (Class 1A)
1 Channel to ground pad. See JEDEC Standard JESD51-2 for additional
information on optimizing the thermal impedance
1 See the Ordering Guide section for more information.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 5 of 16
HMC7950
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
11
10
9
NIC
NIC
NIC
NIC
NIC
HMC7950
TOP VIEW
(Not to Scale)
V
DD
NOTES
1. NIC = NO INTERNAL CONNECTION. NOTE THAT DATA
SHOWN HEREIN WAS MEASURED WITH THESE PINS
EXTERNALLY CONNECTED TO RF/DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin
Mnemonic Description
1, 2, 8, 9, 10,
11, 12, 16
NIC
No Internal Connection. Note that data shown herein was measured with these pins externally connected
to RF/dc ground. See Figure 3 for the interface schematic.
3
VDD
Power Supply Voltage for the Amplifier. Connect a dc bias to provide drain current (IDD). See Figure 4 for the
interface schematic.
4
VGG2
Gain Control. This pin is dc-coupled and accomplishes gain control by reducing the internal voltage and
becoming more negative. See Figure 5 for the interface schematic.
5, 7, 13, 15
6
GND
RFIN
These pins must be connected to RF/dc ground. See Figure 3 for the interface schematic.
Radio Frequency (RF) Input. This pin is ac-coupled, but has a large resistor to GND for ESD protection, and
matched to 50 Ω. See Figure 6 for the interface schematic.
14
RFOUT
RF Output. This pin is ac-coupled, but has a large resistor to GND for ESD protection, and matched to 50 Ω. See
Figure 7 for the interface schematic.
EPAD (GND) Exposed Pad (Ground). The exposed pad must be connected to RF/dc ground. See Figure 3 for the interface
schematic.
INTERFACE SCHEMATICS
GND
RFIN
Figure 3. GND Interface Schematic
V
DD
Figure 6. RFIN Interface Schematic
Figure 4. VDD Interface Schematic
RFOUT
Figure 7. RFOUT Interface Schematic
V
2
GG
Figure 5. VGG2 Interface Schematic
Rev. A | Page 6 of 16
Data Sheet
HMC7950
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
18
16
14
12
10
8
–40°C
+25°C
+85°C
15
10
5
0
–5
–10
–15
S21
–20
S11
S22
–25
0
5
10
15
20
25
30
35
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Response (Gain and Return Loss) vs. Frequency
Figure 11. Gain vs. Frequency at Various Temperatures
0
–5
0
–5
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–10
–15
–20
–25
–10
–15
–20
–25
2
6
10
14
18
22
26
30
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
6
18
–40°C
+25°C
+85°C
–40°C
+25°C
17
+85°C
5
4
3
2
1
0
16
15
14
13
12
11
10
9
8
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
Figure 10. Noise Figure vs. Frequency at Various Temperatures
Figure 13. P1dB vs. Frequency at Various Temperatures
Rev. A | Page 7 of 16
HMC7950
Data Sheet
22
21
20
19
18
17
16
15
14
13
12
11
19
18
17
16
15
14
13
12
11
10
9
–40°C
+25°C
+85°C
4V
5V
6V
8
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
Figure 14. PSAT vs. Frequency at Various Temperatures
Figure 17. P1dB vs. Frequency at Various Supply Voltages
23
22
21
20
19
18
17
16
15
14
13
12
30
28
26
24
22
20
18
–40°C
+25°C
+85°C
4V
5V
6V
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (dBm)
Figure 15. PSAT vs. Frequency at Various Supply Voltages
Figure 18. Output IP3 vs. Frequency at Various Temperatures,
OUT/Tone = 4 dBm
P
30
28
26
24
22
20
18
60
50
40
30
20
4V
5V
6V
4GHz
10GHz
16GHz
22GHz
28GHz
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (dBm)
0
1
2
3
4
5
6
7
8
P
/TONE (dBm)
OUT
Figure 16. Output IP3 vs. Frequency at Various Supply Voltages
OUT/Tone = 4 dBm
Figure 19. Output Third-Order Intermodulation Distortion (IMD3) vs.
OUT/Tone at Various Frequencies, VDD = 4 V
P
P
Rev. A | Page 8 of 16
Data Sheet
HMC7950
0.40
0.36
0.32
0.28
0.24
76
60
4GHz
4 GHz
10GHz
16GHz
22GHz
28GHz
10GHz
16GHz
22GHz
28GHz
72
68
64
60
I
AT 16GHz
50
40
30
20
DD
–10
–8
–6
–4
–2
0
2
4
6
8
0
1
2
3
4
5
6
7
8
INPUT POWER (dBm)
P
/TONE (dBm)
OUT
Figure 23. Power Dissipation and IDD vs. Input Power at Various Frequencies,
16 GHz, TA = 85°C
Figure 20. Output IMD3 vs. POUT/Tone at Various Frequencies, VDD = 5 V
76
60
4GHz
4GHz
10GHz
16GHz
22GHz
28GHz
72
10GHz
16GHz
22GHz
28GHz
50
68
64
60
40
30
20
–10
–8
–6
–4
–2
0
2
4
6
8
0
1
2
3
4
5
6
7
8
INPUT POWER (dBm)
P
/TONE (dBm)
OUT
Figure 21. Output IMD3 vs. POUT/Tone at Various Frequencies, VDD = 6 V
Figure 24. IDD vs. Input Power at Various Frequencies
0
1
0
70
65
60
55
50
45
40
35
–40°C
I
I
2
GG
DD
+25°C
+85°C
–10
–20
–30
–40
–50
–60
–70
–1
–2
–3
–4
–5
–6
2
6
10
14
18
22
26
30
–1.5 –1.1 –0.7 –0.3 0.1
0.5
2 (V)
0.9
1.3
1.7
2.1
2.5
FREQUENCY (GHz)
V
GG
Figure 22. Reverse Isolation vs. Frequency at Various Temperatures
Figure 25. IGG2 and IDD vs. VGG2 at 14 GHz, Input Power (PIN) = 0 dBm
Rev. A | Page 9 of 16
HMC7950
Data Sheet
22
20
18
16
14
12
10
8
20
–1.2V
–0.8V
–0.6V
–0.4V
–0.2V
0V
0.4V
0.8V
1.2V
1.6V
2V
10
2.4V
0
–10
–20
–30
6
0V
–2V
0.4V
1V
–1.6V
–1.4V
–1.2V
–1V
4
1.6V
2.2V
2.6V
2
–0.8V
–0.4V
0
–40
0
2
6
10
14
18
22
26
30
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 29. P1dB vs. Frequency at Various VGG2 Voltage Levels
Figure 26. Gain vs. Frequency at Various VGG2 Voltage Levels
22
20
18
16
14
12
10
8
0
–1.2V
–0.8V
–0.6V
–0.4V
–0.2V
0V
0.4V
0.8V
1.2V
1.6V
2V
0V
–2V
–1.6V
–1.4V
–1.2V
–1V
0.4V
1V
1.6V
2.2V
2.6V
–5
–10
–15
–20
–25
–0.8V
–0.4V
2.4V
6
4
2
0
2
6
10
14
18
22
26
30
0
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 30. PSAT vs. Frequency at Various VGG2 Voltage Levels
Figure 27. Input Return Loss vs. Frequency at Various VGG2 Voltage Levels
30
0
–2V
0V
0.4V
1V
–1.6V
–1.4V
–1.2V
–1V
1.6V
2.2V
2.6V
25
20
15
10
5
–5
–10
–15
–20
–25
–0.8V
–0.4V
–1.2V
–0.8V
–0.6V
–0.4V
0V
0.8V
1.2V
1.6V
2V
2.4V
0.4V
0
2
6
10
14
18
22
26
30
0
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. Output Return Loss vs. Frequency at Various VGG2 Voltage Levels
Figure 31. Output IP3 vs. Frequency at Various VGG2 Voltage Levels,
OUT/Tone = 4 dBm
P
Rev. A | Page 10 of 16
Data Sheet
HMC7950
45
40
35
30
25
20
15
10
5
20
15
10
5
0
–5
–10
–15
–20
–25
–40°C
+25°C
+85°C
0
2
4
6
8
10
12
14
16
18
20
22
24
2.4 2.0 1.6 1.2 0.8 0.4
0
–0.4 –0.8 –1.2 –1.6 –2.0
FREQUENCY (GHz)
V
2 (V)
GG
Figure 32. Gain vs. VGG2 at 14 GHz
Figure 35. Second Harmonic vs. Frequency at Various Temperatures,
POUT = 0 dBm
28
26
24
22
20
18
16
14
12
10
45
0dBm
5dBm
40
35
30
25
20
15
10
5
0
2.4
2.0
1.6
1.2
0.8
V
0.4
0
–0.4 –0.8 –1.2
2
4
6
8
10
12
14
16
18
20
22
24
2 (V)
FREQUENCY (GHz)
GG
Figure 36. Second Harmonic vs. Frequency at Various Output Powers
Figure 33. Output IP3 vs. VGG2 at 14 GHz
–70
–80
37
–40°C
+25°C
+85°C
35
33
31
29
27
25
23
21
19
17
–90
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
2
4
6
8
10
12
14
16
18
20
22
24
OFFSET FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 37. Additive Phase Noise vs. Offset Frequency, RF Frequency = 8 GHz,
RF Input Power = 2.5 dBm (P1dB)
Figure 34. Output IP2 vs. Frequency at Various Temperatures,
POUT/Tone = 4 dBm
Rev. A | Page 11 of 16
HMC7950
Data Sheet
THEORY OF OPERATION
The HMC7950 is a GaAs, pHEMT, MMIC low noise amplifier.
Its basic architecture is that of a single-supply, biased cascode
distributed amplifier with an integrated RF choke for the drain.
The cascode distributed architecture uses a fundamental cell
consisting of a stack of two field effect transistors (FETs) with
the source of the upper FET connected to the drain of the lower
FET. The fundamental cell is then duplicated several times, with
a transmission line feeding the RFIN signal to the gates of the
lower FETs and a separate transmission line interconnecting the
drains of the upper FETs and routing the amplified signal to the
RFOUT pin. Additional circuit design techniques around each
cell optimize the overall performance for broadband operation.
The major benefit of this architecture is that high performance
is maintained across a bandwidth far greater than a single
instance of the fundamental cell can provide. A simplified
schematic of this architecture is shown in Figure 38.
Although the gate bias voltages of the upper FETs are set internally
by a resistive voltage divider connected to VDD, the VGG2 pin
provides the user with an optional means of changing the gate
bias of the upper FETs. Application of a voltage to VGG2 allows
the user to change the voltage output by the resistive divider,
altering the gate bias of the upper FETs and thus changing the
gain. Application of VGG2 voltages across the range of −2.0 V to
+2.6 V affects gain changes of approximately 30 dB, depending
on the frequency. Increasing the voltage applied to VGG2 increases
the gain, whereas decreasing the voltage decreases the gain. For
VDD = 5.0 V (nominal), the resulting VGG2 open circuit voltage
is approximately 2.2 V.
V
DD
TRANSMISSION
LINE
RFOUT
V
2
GG
TRANSMISSION
LINE
RFIN
Figure 38. Architecture and Simplified Schematic
Rev. A | Page 12 of 16
Data Sheet
HMC7950
APPLICATIONS INFORMATION
Capacitive bypassing is recommended for VDD, as shown in the
typical application circuit in Figure 39. Gain control is possible
through the application of a dc voltage to VGG2. If gain control is
used, capacitive bypassing of VGG2 is recommended as shown in
the typical application circuit. If gain control is not used, VGG2
can be either left open or capacitively bypassed as shown in
Figure 39.
The recommended bias sequence during power-down is as
follows:
1. Turn off the RF input signal.
2. Remove the VGG2 voltage, or set it to 0 V.
3. Set VDD to 0 V.
Power-up and power-down sequences can differ from the ones
described, although care must always be taken to ensure adherence
to the values shown in the Absolute Maximum Ratings section.
The recommended bias sequence during power-up is as follows:
1. Set VDD to 5.0 V (this results in an IDD near its specified
typical value).
2. If the gain control function is to be used, apply a voltage
within the range of −2.0 V to +2.6 V to VGG2 until the
desired gain setting is achieved.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit as configured on the
HMC7950 evaluation board. The bias conditions shown in the
Specifications section are recommended to optimize the overall
performance. Operation using other bias conditions may result
in performance that differs from the data shown in this data sheet.
3. Apply the RF input signal.
V
DD
4.7µF
10nF
100pF
3
2
1
V
2
GG
4
5
16
+
4.7µF
10nF
100pF
RFIN
15
14
13
RFOUT
6
7
8
12
9
10
11
PACKAGE
BASE
GND
Figure 39. Typical Application Circuit
Rev. A | Page 13 of 16
HMC7950
Data Sheet
EVALUATION BOARD
The HMC7950 evaluation board is a 2-layer board fabricated
using Rogers 4350 and using best practices for high frequency
RF design. The RF input and RF output traces have a 50 Ω
characteristic impedance.
The evaluation board and populated components are designed
to operate over the ambient temperature range of −40°C to
+85°C. For the proper bias sequence, see the Applications
Information section.
C5
C3
C1
C9
The evaluation board schematic is shown in Figure 41. A fully
populated and tested evaluation board, shown in Figure 40, is
available from Analog Devices, Inc., upon request.
C2
C4
C6
Figure 40. Evaluation PCB
Table 8. Bill of Materials for Evaluation PCB EV1HMC7950LS6
Item
Description
RFIN, RFOUT
C1, C7
C3, C8
C5, C9
U1
PCB mount, K connector, SRI Part Number 21-146-1000-92
100 pF capacitor, 5%, 50 V, C0G, 0402 package
10 nF capacitor, 10%, 16 V, X7R, 0402 package
4.7 µF tantalum capacitor, 10%, 20 V, 1206 package
Amplifier, HMC7950LS6
PCB
Evaluation PCB; circuit board material: Rogers 4350
DC pins, Molex Part Number 87759-0414
Do not install (DNI)
VDD, VGG2
C2, C4, C6, J3, J4, VGG
Rev. A | Page 14 of 16
Data Sheet
HMC7950
EVALUATION BOARD SCHEMATIC
VGG2
1
VDD
1
2
3
4
2
3
4
GND
GND
+
C9
4.7µF
C3
10nF
C5
4.7µF
C1
100pF
C8
10nF
C7
100pF
3
2
1
16
15
4
5
V
2
NIC
GND
GG
GND
RFIN
GND
NIC
HMC7950LS6
RFOUT
RFIN
6
7
14
13
RFOUT
GND
EPAD
12
8
NIC
9
10
11
VGG
DNI
1
2
3
4
GND
C4
DNI
C2
DNI
C6
DNI
+
THRU_CAL
J3
DNI
J4
DNI
Figure 41. Evaluation Board Schematic
Rev. A | Page 15 of 16
HMC7950
Data Sheet
OUTLINE DIMENSIONS
3.45
1.65
6.10
6.00 SQ
5.90
0.31
0.25
0.19
0.35
0.80
PIN 1
INDICATOR
1.05
12
16
1.00 BSC
11
9
1
3
2.06
2.00
1.94
3.46
3.40
3.34
3.55
SQ
0.56
8
4
0.50
0.44
0.90
TOP VIEW
BOTTOM VIEW
0.63
0.57
0.51
1.21
1.15
5.90 BSC
SIDE VIEW
1.444
1.317
1.190
1.09
4.70
4.65
4.60
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.44 BSC
0.50 MAX
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
Figure 42. 16-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS]
(EP-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
MSL Rating2
Lead Finish
Package Description
Package Option
Branding3
HMC7950LS6
−40°C to +85°C
MSL3
Au
16-Terminal LCC_HS
EP-16-2
H7950
XXXX
H7950
XXXX
HMC7950LS6TR
−40°C to +85°C
MSL3
Au
16-Terminal LCC_HS
EP-16-2
EV1HMC7950LS6
Evaluation PCB
1 The HMC7950LS6 and HMC7950LS6TR are RoHS compliant parts, made of low stress injection molded plastic.
2 See the Absolute Maximum Ratings section for further information on the moisture sensitivity level (MSL) rating.
3 XXXX is the four-digit lot number.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15412-0-9/17(A)
Rev. A | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明