HMC8400-SX [ADI]
MMIC Low Noise Amplifier;
| 型号： | HMC8400-SX |
| 厂家： | 
ADI |
| 描述： | MMIC Low Noise Amplifier |
| 文件： | 总15页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 GHz to 30 GHz, GaAs
pHEMT MMIC Low Noise Amplifier
Data Sheet
HMC8400
FEATURES
GENERAL DESCRIPTION
Output power for 1 dB compression (P1dB): 14.5 dBm typical
Saturated output power (PSAT): 17 dBm typical
Gain: 13.5 dB typical
Noise figure: 2 dB
Output third-order intercept (IP3): 26.5 dBm typical
Supply voltage: 5 V at 67 mA
The HMC8400 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic microwave
integrated circuit (MMIC). The HMC8400 is a wideband low
noise amplifier that operates between 2 GHz and 30 GHz. The
amplifier provides 13.5 dB of gain, a 2 dB noise figure, 26.5 dBm
output IP3, and 14.5 dBm of output power at 1 dB gain compres-
sion, requiring 67 mA from a 5 V supply. The HMC8400 is self
biased with only a single positive supply needed to achieve a
drain current IDD of 67 mA. The HMC8400 also has a gain control
option, VGG2. The HMC8400 amplifier input/outputs are internally
matched to 50 Ω and dc blocked, facilitating integration into
multichip modules (MCMs). All data is taken with the chip
connected via two 0.025 mm (1 mil) wire bonds of minimal
length 0.31 mm (12 mils).
50 Ω matched input/output
Die size: 2.7 mm × 1.35 mm × 0.05 mm
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military and space
Telecommunications infrastructure
Fiber optics
FUNCTIONAL BLOCK DIAGRAM
3
HMC8400
V
DD
4
RFOUT
V
2
GG
2
1
RFIN
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarks and registered trademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC8400
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Biasing Procedures..................................................................... 13
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
2 GHz to 6 GHz Frequency Range............................................. 3
6 GHz to 20 GHz Frequency Range........................................... 3
20 GHz to 30 GHz Frequency Range......................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs......................................................................................... 13
Typical Application Circuit....................................................... 14
Assembly Diagram ..................................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
5/2017—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Added Figure 32 and Figure 33; Renumbered Sequentially............11
9/2016—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 14
2/2016—Revision 0: Initial Version
Rev. B | Page 2 of 15
Data Sheet
HMC8400
SPECIFICATIONS
2 GHz TO 6 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, IDD = 67 mA, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to
+2.6 V.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
FREQUENCY RANGE
GAIN
2
6
GHz
dB
12
14
Gain Variation Over Temperature
RETURN LOSS
0.005
dB/°C
Input
Output
13
15
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
13
16
19
26.5
3
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 10 dBm
NF
5
7
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
IDD = 64 mA
IDD
67
mA
4
5
6
5
V
V
V
V
IDD = 67 mA
IDD = 70 mA
SUPPLY VOLTAGE
VDD
3
6 GHz TO 20 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, IDD = 67 mA, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to
+2.6 V.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min Typ
6
Max Unit
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
20
GHz
dB
11.5 13.5
0.006
dB/°C
Input
Output
18
15
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
12.5 14.5
dBm
dBm
dBm
dB
17
25
2
Measurement taken at POUT/tone = 10 dBm
NF
3.5
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
IDD = 64 mA
IDD
67
mA
4
5
6
V
V
V
V
IDD = 67 mA
IDD = 70 mA
SUPPLY VOLTAGE
VDD
3
5
7
Rev. B | Page 3 of 15
HMC8400
Data Sheet
20 GHz TO 30 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, IDD = 67 mA, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to
+2.6 V.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min Typ
20
Max Unit
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
30
GHz
dB
11.5 13.5
0.008
dB/°C
Input
Output
15
13
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
10.5 13.5
dBm
dBm
dBm
dB
15.5
24
Measurement taken at POUT/tone = 10 dBm
NF
2.5
4.5
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
IDD = 64 mA
IDD
67
mA
4
5
6
V
V
V
V
IDD = 67 mA
IDD = 70 mA
SUPPLY VOLTAGE
VDD
3
5
7
Rev. B | Page 4 of 15
Data Sheet
HMC8400
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Drain Bias Voltage (VDD)
Second Gate Bias Voltage (VGG2)
RF Input Power (RFIN)
Channel Temperature
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 17.2 mW/°C Above 85°C)
8 V
−2.5 V to +3 V
23 dBm
175°C
1.55 W
ESD CAUTION
Thermal Resistance, θJA (Channel to
Bottom Die)
58°C/W
Storage Temperature Range
Operating Temperature Range
−65°C to +150°C
−55°C to +85°C
ESD Sensitivity, Human Body Model (HBM) 250 V (Class 1A)
Rev. B | Page 5 of 15
HMC8400
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
3
V
DD
HMC8400
RFOUT
4
2
1
V
2
GG
RFIN
NOTES
1. DIE BOTTOM MUST BE CONNECTED TO RF/DC GROUND.
Figure 2. Pad Configuration
Table 5. Pad Function Descriptions
Pad No.
Mnemonic
Description
1
RFIN
Radio Frequency (RF) Input. This pad is ac-coupled, but has a large resistor to GND for ESD protection,
and matched to 50 Ω. See Figure 3 for the interface schematic.
2
3
4
VGG2
VDD
Gain Control. This pad is dc-coupled and accomplishes gain control by bringing this voltage lower and
becoming more negative. See Figure 4 for the interface schematic.
Power Supply Voltage for the Amplifier. Connect a dc bias to provide drain current (IDD). See Figure 5 for
the interface schematic.
RF Output. This pad is ac-coupled, but has a large resistor to GND for ESD protection, and matched to 50 Ω.
See Figure 6 for the interface schematic.
RFOUT
Die Bottom GND
Die bottom must be connected to RF/dc ground. See Figure 7 for the interface schematic.
INTERFACE SCHEMATICS
RFIN
RFOUT
Figure 3. RFIN Interface Schematic
Figure 6. RFOUT Interface Schematic
V
2
GG
GND
Figure 4. VGG2 Interface Schematic
Figure 7. GND Interface Schematic
V
DD
Figure 5. VDD Interface Schematic
Rev. B | Page 6 of 15
Data Sheet
HMC8400
TYPICAL PERFORMANCE CHARACTERISTICS
20
16
14
12
10
8
15
10
S11
S21
S22
5
0
+85°C
+25°C
–55°C
–5
–10
–15
–20
–25
–30
6
0
4
8
12
16
20
24
28
32
36
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Response Gain and Return Loss vs. Frequency
Figure 11. Gain vs. Frequency at Various Temperatures
0
–5
0
–5
+85°C
+25°C
–55°C
+85°C
+25°C
–55°C
–10
–15
–20
–25
–30
–10
–15
–20
–25
2
6
10
14
18
22
26
30
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
5
18
+85°C
+25°C
–55°C
17
16
15
14
13
12
11
10
9
+85°C
+25°C
–55°C
4
3
2
1
0
8
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
Figure 10. Noise Figure vs. Frequency at Various Temperatures
Figure 13. P1dB vs. Frequency at Various Temperatures
Rev. B | Page 7 of 15
HMC8400
Data Sheet
21
20
19
18
17
16
15
14
13
12
11
10
18
17
16
15
14
13
12
11
10
9
4V
5V
6V
+85°C
+25°C
–55°C
8
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
Figure 14. PSAT vs. Frequency at Various Temperatures
Figure 17. P1dB vs. Frequency at Various Supply Voltages
21
20
19
18
17
16
15
14
13
12
11
10
30
4V
5V
6V
+85°C
+25°C
–55°C
28
26
24
22
20
18
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
Figure 18. Output IP3 vs. Frequency for Various Temperatures at
OUT = 0 dBm/Tone
Figure 15. PSAT vs. Frequency at Various Supply Voltages
P
60
50
40
30
20
30
28
26
24
22
20
18
4V
5V
6V
4GHz
10GHz
16GHz
22GHz
28GHz
0
1
2
3
4
5
6
7
8
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
P
/TONE (dBm)
OUT
Figure 16. Output IP3 vs. Frequency at Various Supply Voltages
Figure 19. Output Third-Order Intermodulation (IMD3) vs. POUT/Tone for
Various Frequencies at VDD = 4 V
Rev. B | Page 8 of 15
Data Sheet
HMC8400
60
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
4GHz
4GHz
10GHz
16GHz
22GHz
28GHz
10GHz
16GHz
22GHz
28GHz
50
40
30
20
0
1
2
3
4
5
6
7
8
–6
–4
–2
0
2
4
6
8
P
/TONE (dBm)
INPUT POWER (dBm)
OUT
Figure 20. IMD3 vs. POUT/Tone for Various Frequencies at VDD = 5 V
Figure 23. Power Dissipation vs. Input Power at Various Frequencies, TA = 85°C
60
20
10
4GHz
10GHz
16GHz
50
40
30
20
22GHz
28GHz
0
–10
–20
–2.0V
–1.6V
–1.4V
–1.2V
–1.0V
–0.8V
–0.4V
0V
+0.4V
+1.0V
+1.6V
+2.2V
+2.6V
–30
–40
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
P
/TONE (dBm)
FREQUENCY (GHz)
OUT
Figure 21. IMD3 vs. POUT/Tone for Various Frequencies at VDD = 6 V
Figure 24. Gain vs. Frequency at Various VGG2 Voltage Levels
0
0
+85°C
–5
–10
+25°C
–55°C
–10
–20
–15
–20
–25
–30
–35
–40
–30
–40
–50
–60
–70
–2.0V
–1.6V
–1.4V
–1.2V
–1.0V
–0.8V
–0.4V
0V
+0.4V
+1.0V
+1.6V
+2.2V
+2.6V
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 25. Input Return Loss vs. Frequency at Various VGG2 Voltage Levels
Figure 22. Reverse Isolation vs. Frequency at Various Temperatures
Rev. B | Page 9 of 15
HMC8400
Data Sheet
0
30
28
26
24
22
20
18
16
14
12
10
–5
–10
–15
–20
–25
–30
–35
–2.0V
–1.6V
–1.4V
–1.2V
–1.0V
–0.8V
–0.4V
0V
+0.4V
+1.0V
+1.6V
+2.2V
+2.6V
–1.2V
–0.8V
–0.6V
–0.4V
–0.2V
0V
+0.4V
+0.8V
+1.2V
+1.6V
+2.0V
+2.4V
–40
0
5
10
15
20
25
30
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Output Return Loss vs. Frequency at Various VGG2 Voltage Levels
Figure 29. Output IP3 vs. Frequency at Various VGG2 Voltage Levels
22
16
12
8
–1.2V
–0.8V
–0.6V
–0.4V
–0.2V
0V
+0.4V
+0.8V
+1.2V
+1.6V
+2.0V
+2.4V
20
18
16
14
12
10
8
4
0
–4
–8
–12
–16
–20
–24
6
4
2
0
2
6
10
14
18
22
26
30
2.4 2.0 1.6 1.2 0.8 0.4
0
–0.4 –0.8 –1.2 –1.6 2.0
FREQUENCY (GHz)
V
2 (V)
GG
Figure 27. P1dB vs. Frequency at Various VGG2 Voltage Levels
Figure 30. Gain vs. VGG2 at 10 GHz
22
20
18
16
14
12
10
8
30
26
22
18
14
10
6
–1.2V
–0.8V
–0.6V
–0.4V
–0.2V
0V
+0.4V
+0.8V
+1.2V
+1.6V
+2.0V
+2.4V
4
2
0
2
6
10
14
18
22
26
30
2.4
2.0
1.6
1.2
0.8
0.4
0
–0.4 –0.8 –1.2
FREQUENCY (GHz)
V
2 (V)
GG
Figure 28. PSAT vs. Frequency at Various VGG2 Voltage Levels
Figure 31. Output IP3 vs. VGG2 at 10 GHz
Rev. B | Page 10 of 15
Data Sheet
HMC8400
36
34
32
30
28
26
24
22
20
18
16
14
12
10
36
34
32
30
28
26
24
22
20
18
16
14
12
10
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–55°C
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 32. Output IP2 (OIP2) vs. Frequency for Various Temperatures at
OUT = 0 dBm/Tone
Figure 33. OIP2 vs. Frequency for Various POUT/Tone Levels
P
Rev. B | Page 11 of 15
HMC8400
Data Sheet
THEORY OF OPERATION
The HMC8400 is a GaAs, pHEMT, MMIC low noise amplifier.
The basic architecture is that of a self biased cascode distributed
amplifier with an integrated RF choke for the drain. The cascode
distributed architecture uses a fundamental cell consisting of a
stack of two field effect transistors (FETs) connected from source to
drain. The fundamental cell is then duplicated several times, with
transmission lines interconnecting the drains of the top devices
and the gates of the bottom devices, respectively.
Though gate bias voltages are set internally via resistor connections
and/or a resistive voltage divider tap off of VDD, the VGG2 pad is
provided to allow the user a means of changing the gate bias of
the upper FETs. Application of a voltage to VGG2 changes the
voltage output by a resistive divider, thus altering the gate bias
of the upper FETs. Adjustment of the bias in this manner allows
the user a 30 dB gain control function. For gain control, VGG2
voltages within the range of −2 V through +2.6 V can be applied.
For VDD = 5.0 V dc, the VGG2 open-circuit voltage is
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth and noise figure. The major
benefit of this architecture is that a low noise figure is maintained
across a bandwidth far greater than what a single instance of the
fundamental cell provides. A simplified schematic of this
architecture is shown in Figure 34.
approximately 2.0 V.
V
DD
T-LINE
RFOUT
V
2
GG
T-LINE
RFIN
Figure 34. Architecture and Simplified Schematic
Rev. B | Page 12 of 15
Data Sheet
HMC8400
APPLICATIONS INFORMATION
To minimize bond wire length, place microstrip substrates as
close to the die as possible. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
BIASING PROCEDURES
Capacitive bypassing is required for VDD, as shown in the typical
application circuit in Figure 36. Gain control is possible through
the application of a dc voltage to VGG2. If gain control is used,
VGG2 must be bypassed by 100 pF, 0.01 µF, and 4.7 µF capacitors. If
gain control is not used, VGG2 can be either left open or
capacitively bypassed as described.
Handling Precautions
To avoid permanent damage, adhere to the following precautions:
•
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After the sealed
ESD protective bag is opened, store all die in a dry nitrogen
environment.
The recommended bias sequence during power-up is as follows:
1. Set VDD to 5 V (this results in an IDD near the specified
typical value).
2. If the gain control function is to be used, apply to VGG2 a
voltage within the range of −2 V to +2.6 V until the desired
gain is achieved.
•
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
•
•
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. To minimize inductive pickup, use shielded
signal and bias cables.
3. Apply the RF input signal.
The recommended bias sequence during power-down is as follows:
•
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
can have fragile air bridges and must not be touched with
vacuum collet, tweezers, or fingers.
1. Turn off the RF input signal.
2. Remove the VGG2 voltage or set it to 0 V.
3. Set VDD to 0 V.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 36), configured
as shown on the assembly diagram (see Figure 37) and biased
per the conditions in the Specifications section. The bias conditions
shown in the Specifications section are the operating points
recommended to optimize the overall performance. Operation
using other bias conditions can provide performance that differs
from what is shown in this data sheet. To obtain the best
performance while not damaging the device, follow the
recommended biasing sequence outlined in this section.
Mounting
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
Eutectic Die Attach
It is best to use an 80% gold/20% tin preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When
hot 90% nitrogen/10% hydrogen gas is applied, maintain tool tip
temperature at 290°C. Do not expose the chip to a temperature
greater than 320°C for more than 20 sec. No more than 3 sec of
scrubbing is required for attachment.
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICs
Attach the die directly to the ground plane eutectically or with
conductive epoxy. To bring RF to and from the chip, use 50 Ω
microstrip transmission lines on 0.127 mm (5 mil) thick alumina
thin film substrates (see Figure 35).
Epoxy Die Attach
ABLETHERM 2600BT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the schedule
provided by the manufacturer.
0.05mm (0.002") THICK GaAs MMIC
Wire Bonding
RIBBON BOND
0.076mm
(0.003")
RF bonds made with 0.003 in. × 0.0005 in. gold ribbon are recom-
mended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 1 mil (0.025 mm)
diameter, thermosonically bonded, are recommended. Create ball
bonds with a force of 40 g to 50 g and wedge bonds with a force
of 18 g to 22 g. Create all bonds with a nominal stage temperature
of 150°C. Apply a minimum amount of ultrasonic energy to
achieve reliable bonds. Keep all bonds as short as possible, less
than 12 mil (0.31 mm).
RF GROUND PLANE
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
Figure 35. Routing RF Signals
Rev. B | Page 13 of 15
HMC8400
Data Sheet
TYPICAL APPLICATION CIRCUIT
V
2
V
DD
GG
4.7µF
0.01µF
100pF
100pF
0.01µF
4.7µF
2
3
RFIN
RFOUT
1
4
Figure 36. Typical Application Circuit
ASSEMBLY DIAGRAM
4.7µF
4.7µF
TO V SUPPLY
DD
0.01µF
ALL BOND WIRES ARE
1mil DIAMETER
TO V 2 SUPPLY
0.01µF
GG
3mil NOMINAL GAP
100pF
100pF
50Ω TRANSMISSION LINE
Figure 37. Assembly Diagram
Rev. B | Page 14 of 15
Data Sheet
HMC8400
OUTLINE DIMENSIONS
2.699
0.05
0.043
0.175
3
0.187
0.708
4
1.349
0.187
0.098
2
0.187
0.557
1
ADI2014
0.187
0.085
SIDE VIEW
0.010
0.010
2.219
0.1310.160
0.085
Figure 38. 4-Pad Bare Die [CHIP]
(C-4-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
HMC8400
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
4-Pad Bare Die [CHIP]
4-Pad Bare Die [CHIP]
Package Option
C-4-1
C-4-1
HMC8400-SX
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13852-0-5/17(B)
Rev. B | Page 15 of 15
相关型号：
©2020 ICPDF网 联系我们和版权申明