APT50M50L2FLL [ADPOW]
Power MOS 7TM is a new generation of low loss, high voltage, N-Channel enhancement mode power MOSFETS.; 功率MOS 7TM是新一代低损耗,高电压,N沟道增强型功率MOSFET 。![APT50M50L2FLL](http://pdffile.icpdf.com/pdf1/p00051/img/icpdf/APT50M50L2_266936_icpdf.jpg)
型号: | APT50M50L2FLL |
厂家: | ![]() |
描述: | Power MOS 7TM is a new generation of low loss, high voltage, N-Channel enhancement mode power MOSFETS. |
文件: | 总2页 (文件大小:69K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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APT50M50L2FLL
500V 89A 0.050W
TM
FREDFET
POWER MOS 7
Power MOS 7TM is a new generation of low loss, high voltage, N-Channel
enhancement mode power MOSFETS. Both conduction and switching
losses are addressed with Power MOS 7TM by significantly lowering RDS(ON)
and Qg. Power MOS 7TM combines lower conduction and switching losses
along with exceptionally fast switching speeds inherent with APT's
patented metal gate structure.
TO-264
Max
D
S
• Lower Input Capacitance
• Increased Power Dissipation
• Lower Miller Capacitance • Easier To Drive
G
• Lower Gate Charge, Qg
MAXIMUM RATINGS
• Popular TO-264 MAX Package
All Ratings: T = 25°C unless otherwise specified.
C
APT50M50L2FLL
UNIT
Symbol Parameter
VDSS
ID
Drain-Source Voltage
Volts
500
89
Continuous Drain Current @ TC = 25°C
Amps
Volts
1
IDM
Pulsed Drain Current
356
VGS
VGSM
Gate-Source Voltage Continuous
Gate-Source Voltage Transient
±30
±40
Total Power Dissipation @ TC = 25°C
Linear Derating Factor
890
Watts
W/°C
PD
7.12
-55 to 150
300
TJ,TSTG
TL
Operating and Storage Junction Temperature Range
°C
Amps
mJ
Lead Temperature: 0.063" from Case for 10 Sec.
1
IAR
Avalanche Current
(Repetitive and Non-Repetitive)
89
1
EAR
EAS
50
Repetitive Avalanche Energy
Single Pulse Avalanche Energy
4
3200
STATIC ELECTRICAL CHARACTERISTICS
Symbol Characteristic / Test Conditions
MIN
TYP
MAX
UNIT
BVDSS
ID(on)
Drain-Source Breakdown Voltage (VGS = 0V, ID = 250µA)
Volts
500
89
2
On State Drain Current
(VDS > ID(on) x RDS(on) Max, VGS = 10V)
Amps
2
RDS(on)
Drain-Source On-State Resistance
(VGS = 10V, 0.5 ID[Cont.])
Ohms
µA
0.050
250
Zero Gate Voltage Drain Current (VDS = VDSS, VGS = 0V)
IDSS
Zero Gate Voltage Drain Current (VDS = 0.8 VDSS, VGS = 0V, TC = 125°C)
Gate-Source Leakage Current (VGS = ±30V, VDS = 0V)
Gate Threshold Voltage (VDS = VGS, ID = 5mA)
1000
±100
5
IGSS
nA
VGS(th)
Volts
3
CAUTION: These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed.
APT Website - http://www.advancedpower.com
USA
405 S.W. Columbia Street
Chemin de Magret
Bend, Oregon 97702-1035
F-33700 Merignac - France
Phone: (541) 382-8028
Phone: (33) 5 57 92 15 15
FAX: (541) 388-0364
FAX: (33) 5 56 47 97 61
EUROPE
DYNAMIC CHARACTERISTICS
Symbol Characteristic
APT50M50L2FLL
Test Conditions
GS = 0V
MIN
MIN
MIN
TYP
9840
2030
153
246
65
MAX
UNIT
Ciss
Coss
Crss
Qg
Input Capacitance
V
Output Capacitance
pF
VDS = 25V
f = 1 MHz
Reverse Transfer Capacitance
3
VGS = 10V
VDD = 0.5 VDSS
Total Gate Charge
Qgs
Qgd
td(on)
t r
nC
ns
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time
Rise Time
ID = ID [Cont.] @ 25°C
112
24
VGS = 15V
VDD = 0.5 VDSS
ID = ID [Cont.] @ 25°C
RG =0.6W
22
td(off)
tf
Turn-off Delay Time
Fall Time
56
8
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Symbol Characteristic / Test Conditions
TYP
MAX
89
UNIT
Continuous Source Current (Body Diode)
IS
Amps
1
ISM
VSD
Pulsed Source Current (Body Diode)
356
1.3
15
2
Diode Forward Voltage
Peak Diode Recovery dv
Reverse Recovery Time
(VGS = 0V, IS = -ID [Cont.])
Volts
V/ns
5
dv
/
/
dt
dt
Tj = 25°C
Tj = 125°C
Tj = 25°C
Tj = 125°C
Tj = 25°C
Tj = 125°C
300
600
ns
µC
trr
(IS = -ID [Cont.], di/dt = 100A/µs)
Reverse Recovery Charge
(IS = -ID [Cont.], di/dt = 100A/µs)
2.6
10
17
34
Qrr
Peak Recovery Current
(IS = -ID [Cont.], di/dt = 100A/µs)
IRRM
Amps
THERMAL CHARACTERISTICS
Symbol Characteristic
TYP
MAX
0.14
40
UNIT
Junction to Case
RqJC
RqJA
°C/W
Junction to Ambient
1
2
3
4
5
Repetitive Rating: Pulse width limited by maximum junction
temperature.
See MIL-STD-750 Method 3471
Starting T = +25°C, L = 0.81mH, R = 25W, Peak I = 89A
j
G
L
dv
Pulse Test: Pulse width < 380 µs, Duty Cycle < 2%
/
numbers reflect the limitations of the test circuit rather than the
di
dt
device itself.
I
S £ -I
/
£ 700A/µs
V
R £ V
T £ 150°C
J
dt
D Cont.
[
DSS
]
TO-264 MAXTM(L2) Package Outline
APT Reserves the right to change,
without notice, the specifications
and information contained herein.
4.60 (.181)
5.21 (.205)
19.51 (.768)
20.50 (.807)
1.80 (.071)
2.01 (.079)
5.79 (.228)
6.20 (.244)
25.48 (1.003)
26.49 (1.043)
2.29 (.090)
2.69 (.106)
2.29 (.090)
2.69 (.106)
19.81 (.780)
21.39 (.842)
Gate
Drain
Source
0.48 (.019)
0.84 (.033)
2.59 (.102)
3.00 (.118)
0.76 (.030)
1.30 (.051)
2.79 (.110)
3.18 (.125)
5.45 (.215) BSC
2-Plcs.
Dimensions in Millimeters and (Inches)
APT's devices are covered by one or more of the following U.S.patents: 4,895,810
5,256,583
5,045,903
4,748,103
5,089,434
5,283,202
5,182,234
5,231,474
5,019,522 5,262,336
5,434,095 5,528,058
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