AD7175-2BRUZ-RL_技术文档

24-Bit, 250 kSPS, Sigma-Delta ADC with

20 µs Settling and True Rail-to-Rail Buffers

Data Sheet

AD7175-2

FEATURES

GENERAL DESCRIPTION

Fast and flexible output rate: 5 SPS to 250 kSPS

Channel scan data rate of 50 kSPS/channel (20 µs settling)

Performance specifications

The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-

channel (fully/pseudo differential) Σ-Δ analog-to-digital converter

(ADC) for low bandwidth inputs. It has a maximum channel

scan rate of 50 kSPS (20 µs) for fully settled data. The output

data rates range from 5 SPS to 250 kSPS.

17.2 noise free bits at 250 kSPS

20 noise free bits at 2.5 kSPS

24 noise free bits at 20 SPS

The AD7175-2 integrates key analog and digital signal condition-

ing blocks to allow users to configure an individual setup for

each analog input channel in use. Each feature can be user selected

on a per channel basis. Integrated true rail-to-rail buffers on the

analog inputs and external reference inputs provide easy to drive

high impedance inputs. The precision 2.5 V low drift (2 ppm/°C)

band gap internal reference (with output reference buffer) adds

embedded functionality to reduce external component count.

INL: 1 ppm of FSR

85 dB rejection of 50 Hz and 60 Hz with 50 ms settling

User configurable input channels

2 fully differential channels or 4 single-ended channels

Crosspoint multiplexer

On-chip 2.5 V reference ( 2 ppm/°C drift)

True rail-to-rail analog and reference input buffers

Internal or external clock

The digital filter allows simultaneous 50 Hz/60 Hz rejection at

27.27 SPS output data rate. The user can switch between

different filter options according to the demands of each

channel in the application. The ADC automatically switches

through each selected channel. Further digital processing

functions include offset and gain calibration registers,

configurable on a per channel basis.

Power supply: AVDD1 = 5 V, AVDD2 = IOVDD = 2 V to 5 V

Split supply with AVDD1/AVSS at 2.5 V

ADC current: 8.4 mA

Temperature range: −40°C to +105°C

3- or 4-wire serial digital interface (Schmitt trigger on SCLK)

Serial port interface (SPI), QSPI, MICROWIRE, and DSP

compatible

The device operates with a 5 V AVDD1, or 2.5 V AVDD1/AVSS,

and 2 V to 5 V AVDD2 and IOVDD supplies. The specified

operating temperature range is −40°C to +105°C. The AD7175-2 is

in a 24-lead TSSOP package.

APPLICATIONS

Process control: PLC/DCS modules

Temperature and pressure measurement

Medical and scientific multichannel instrumentation

Chromatography

Note that, throughout this data sheet, the dual function pin

names are referenced by the relevant function only.

FUNCTIONAL BLOCK DIAGRAM

REF– REF+ REFOUT

AVDD1 AVDD2 REGCAPA

IOVDD REGCAPD

AVDD1

AVSS

BUFFERED

PRECISION

REFERENCE

1.8V

LDO

1.8V

LDO

CROSSPOINT

MULTIPLEXER

INT

REF

RAIL-TO-RAIL

REFERENCE

INPUT BUFFERS

AIN0

AIN1

AIN2

AIN3

AIN4

AVDD

CS

SCLK

SERIAL

INTERFACE

AND CONTROL

DIGITAL

FILTER

Ȉꢀǻꢁ$'&

DIN

DOUT/RDY

SYNC/ERROR

RAIL-TO-RAIL

ANALOG INPUT

BUFFERS

GPIO AND

MUX

I/O CONTROL

XTAL AND INTERNAL

CLOCK OSCILLATOR

CIRCUITRY

AVSS

AD7175-2

TEMPERATURE

SENSOR

AVSS

GPIO0 GPIO1

XTAL1 XTAL2/CLKIO

DGND

Figure 1.

Rev. B

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Technical Support

www.analog.com

AD7175-2* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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REFERENCE MATERIALS

Press

• Analog Devices Introduces Industry’s First 24-Bit Sigma

Delta A/D Converter with Rail-to-Rail Analog and

Reference Input Buffers On-chip

EVALUATION KITS

• AD7175-2 Evaluation Board

Technical Articles

• Fundamental Principles Behind the Sigma-Delta ADC

Topology: Part 1

DOCUMENTATION

Data Sheet

• Fundamental Principles Behind the Sigma-Delta ADC

Topology: Part 2

• AD7175-2: 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 μs

Settling and True Rail-to-Rail Buffers Data Sheet

Tutorials

Technical Books

• MT-022: ADC Architectures III: Sigma-Delta ADC Basics

• The Data Conversion Handbook, 2005

User Guides

• MT-023: ADC Architectures IV: Sigma-Delta ADC

Advanced Concepts and Applications

• UG-741: Evaluating the AD7175-2 24-Bit, 250 kSPS, Sigma-

Delta ADC with 20 μs Settling and Integrated Analog

Input Buffer

DESIGN RESOURCES

• AD7175-2 Material Declaration

• PCN-PDN Information

SOFTWARE AND SYSTEMS REQUIREMENTS

• Quality And Reliability

• Symbols and Footprints

• AD7175 Microcontroller Renesas Driver

• AD7176-2 FMC-SDP Interposer & Evaluation Board / Xilinx

KC705 Reference Design

DISCUSSIONS

View all AD7175-2 EngineerZone Discussions.

• AD717x Microcontroller No-OS

• AD717x Eval+ Software

SAMPLE AND BUY

Visit the product page to see pricing options.

TOOLS AND SIMULATIONS

• AD7175-2 Digital Filter Frequency Response Model

• AD7175-2 IBIS Model

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

REFERENCE DESIGNS

• CN0292

• CN0363

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

• CN0364

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AD7175-2

Data Sheet

TABLE OF CONTENTS

Checksum Protection ................................................................ 43

CRC Calculation......................................................................... 44

Integrated Functions ...................................................................... 46

General-Purpose Input/Output................................................ 46

External Multiplexer Control ................................................... 46

Delay ............................................................................................ 46

16-Bit/24-Bit Conversions......................................................... 46

DOUT_RESET ........................................................................... 46

Synchronization.......................................................................... 46

Error Flags................................................................................... 47

DATA_STAT ............................................................................... 47

IOSTRENGTH ........................................................................... 48

Internal Temperature Sensor .................................................... 48

Grounding and Layout .................................................................. 49

Register Summary .......................................................................... 50

Register Details ............................................................................... 51

Communications Register......................................................... 51

Status Register............................................................................. 52

ADC Mode Register................................................................... 53

Interface Mode Register ............................................................ 54

Register Check............................................................................ 55

Data Register............................................................................... 55

GPIO Configuration Register................................................... 56

ID Register................................................................................... 57

Channel Register 0 ..................................................................... 57

Channel Register 1 to Channel Register 3 .............................. 58

Setup Configuration Register 0 ................................................ 59

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Timing Characteristics ................................................................ 7

Timing Diagrams.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Noise Performance and Resolution.............................................. 19

Getting Started................................................................................ 20

Power Supplies ............................................................................ 21

Digital Communication............................................................. 21

AD7175-2 Reset.......................................................................... 22

Configuration Overview ........................................................... 22

Circuit Description......................................................................... 28

Buffered Analog Input ............................................................... 28

Crosspoint Multiplexer.............................................................. 28

AD7175-2 Reference.................................................................. 29

Buffered Reference Input........................................................... 30

Clock Source ............................................................................... 30

Digital Filters................................................................................... 31

Sinc5 + Sinc1 Filter..................................................................... 31

Sinc3 Filter................................................................................... 31

Single Cycle Settling................................................................... 32

Enhanced 50 Hz and 60 Hz Rejection Filters......................... 36

Operating Modes............................................................................ 39

Continuous Conversion Mode ................................................. 39

Continuous Read Mode............................................................. 40

Single Conversion Mode ........................................................... 41

Standby and Power-Down Modes............................................ 42

Calibration................................................................................... 42

Digital Interface .............................................................................. 43

Setup Configuration Register 1 to Setup Configuration

Register 3 ..................................................................................... 59

Filter Configuration Register 0................................................. 60

Filter Configuration Register 1 to Filter Configuration

Register 3 ..................................................................................... 61

Offset Register 0 ......................................................................... 61

Offset Register 1 to Offset Register 3....................................... 61

Gain Register 0............................................................................ 61

Gain Register 1 to Gain Register 3........................................... 61

Outline Dimensions....................................................................... 62

Ordering Guide .......................................................................... 62

Rev. B | Page 2 of 62

Data Sheet

AD7175-2

REVISION HISTORY

5/2016—Rev. A to Rev. B

9/2014—Rev. 0 to Rev. A

Changes to Figure 1...........................................................................1

Added Endnote Reference 1 to 0°C to 105°C Parameter and

−40°C to +105°C Parameter, Table 1 ..............................................4

Change to Sensitivity Parameter, Table 1.......................................5

Changes to Power Supplies Section ..............................................21

Change to Table 21..........................................................................34

Change to Table 22..........................................................................35

Changes to Internal Temperature Sensor Section.......................48

Changes to Ordering Guide...........................................................60

7/2014—Revision 0: Initial Version

Rev. B | Page 3 of 62

AD7175-2

Data Sheet

SPECIFICATIONS

AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,

MCLK = internal master clock = 16 MHz, T_A= T_MINto T_MAX(−40°C to +105°C), unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC SPEED AND PERFORMANCE

Output Data Rate (ODR)

No Missing Codes¹

Resolution

5

250,000

SPS

Bits

Excluding sinc3 filter ≥ 125 kSPS

See Table 6 and Table 7

24

Noise

See Table 6 and Table 7

ACCURACY

Integral Nonlinearity (INL)

Analog input buffers enabled

Analog input buffers disabled

Internal short

3.5

1

7.8

3.5

ppm of FSR

µV

Offset Error²

Offset Drift

Gain Error²

40

80

35

0.4

Internal short

nV/°C

85

ppm of FSR

ppm/°C

Gain Drift

0.75

REJECTION

Power Supply Rejection

Common-Mode Rejection

At DC

AVDD1, AVDD2, V_IN= 1 V

V_IN= 0.1 V

95

dB

95

dB

At 50 Hz, 60 Hz¹

20 Hz output data rate (post filter),

50 Hz 1 Hz and 60 Hz 1 Hz

120

Normal Mode Rejection¹

50 Hz 1 Hz and 60 Hz 1 Hz

Internal clock, 20 SPS ODR (postfilter)

External clock, 20 SPS ODR (postfilter)

71

85

90

dB

ANALOG INPUTS

Differential Input Range

Absolute Voltage Limits¹

Input Buffers Disabled

Input Buffers Enabled

Analog Input Current

Input Buffers Disabled

Input Current

V_REF= (REF+) − (REF−)

V_REF

V

AVSS − 0.05

AVSS

AVDD1 + 0.05

AVDD1

V

48

0.75

4

µA/V

Input Current Drift

External clock

nA/V/°C

Internal clock ( 2.5% clock)

Input Buffers Enabled

Input Current

30

75

nA

Input Current Drift

AVDD1 − 0.2 V to AVSS + 0.2 V

AVDD1 to AVSS

pA/°C

nA/°C

dB

1

Crosstalk

1 kHz input

−120

INTERNAL REFERENCE

Output Voltage

Initial Accuracy³

100 nF external capacitor to AVSS

REFOUT, with respect to AVSS

REFOUT, T_A= 25°C

2.5

V

−0.12

−10

+0.12

% of V

Temperature Coefficient

0°C to 105°C¹

−40°C to +105°C¹

Reference Load Current, I_LOAD

Power Supply Rejection

Load Regulation

2

3

5

ppm/°C

mA

10

+10

AVDD1, AVDD2, (line regulation)

∆V_OUT/∆I_LOAD

90

dB

32

ppm/mA

µV rms

nV/√Hz

Voltage Noise

e_N, 0.1 Hz to 10 Hz, 2.5 V reference

e_N, 1 kHz, 2.5 V reference

4.5

215

Voltage Noise Density

Rev. B | Page 4 of 62

Data Sheet

AD7175-2

Parameter

Test Conditions/Comments

Min

Typ

200

25

Max

Unit

µs

Turn-On Settling Time

Short-Circuit Current, I_SC

EXTERNAL REFERENCE INPUTS

Differential Input Range

Absolute Voltage Limits¹

Input Buffers Disabled

Input Buffers Enabled

REFIN Input Current

Input Buffers Disabled

Input Current

100 nF REFOUT capacitor

mA

V_REF= (REF+) − (REF−)

1

2.5

AVDD1

V

AVSS − 0.05

AVSS

AVDD1 + 0.05

AVDD1

V

72

1.2

6

µA/V

Input Current Drift

External clock

Internal clock

nA/V/°C

Input Buffers Enabled

Input Current

800

nA

Input Current Drift

Normal Mode Rejection¹

Common-Mode Rejection

TEMPERATURE SENSOR

Accuracy

1.25

nA/°C

See the Rejection parameter

After user calibration at 25°C

95

dB

2

°C

Sensitivity

470

µV/K

BURNOUT CURRENTS

Source/Sink Current

Analog input buffers must be enabled

With respect to AVSS

10

µA

GENERAL-PURPOSE INPUT/

OUTPUT (GPIO0, GPIO1)

Input Mode Leakage Current¹

−10

+10

µA

pF

Floating State Output

Capacitance

5

1

Output High Voltage, V_OH

I_SOURCE= 200 µA

I_SINK= 800 µA

AVSS + 4

AVSS + 3

V

1

Output Low Voltage, V_OL

AVSS + 0.4

AVSS + 0.7

1

Input High Voltage, V_IH

1

Input Low Voltage, V_IL

CLOCK

Internal Clock

Frequency

16

50

MHz

%

Accuracy

−2.5%

+2.5%

0.4

Duty Cycle

%

Output Low Voltage, V_OL

Output High Voltage, V_OH

Crystal

V

0.8 × IOVDD

14

V

Frequency

16

10

16

50

16.384

MHz

µs

Startup Time

External Clock (CLKIO)

Duty Cycle¹

16.384

70

MHz

%

30

Rev. B | Page 5 of 62

AD7175-2

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

1

Input High Voltage, V_INH

2 V ≤ IOVDD < 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

2 V ≤ IOVDD < 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

IOVDD ≥ 2.7 V

0.65 × IOVDD

0.7 × IOVDD

V

1

Input Low Voltage, V_INL

0.35 × IOVDD

V

0.7

V

Hysteresis¹

0.08

0.04

−10

0.25

0.2

V

IOVDD < 2.7 V

V

Leakage Currents

+10

µA

LOGIC OUTPUT (DOUT/RDY)

1

Output High Voltage, V_OH

IOVDD ≥ 4.5 V, I_SOURCE= 1 mA

2.7 V ≤ IOVDD < 4.5 V, I_SOURCE= 500 µA

IOVDD < 2.7 V, I_SOURCE= 200 µA

IOVDD ≥ 4.5 V, I_SINK= 2 mA

2.7 V ≤ IOVDD < 4.5 V, I_SINK= 1 mA

IOVDD < 2.7 V, I_SINK= 400 µA

Floating state

0.8 × IOVDD

V

1

Output Low Voltage, V_OL

0.4

+10

V

Leakage Current

Output Capacitance

SYSTEM CALIBRATION¹

Full-Scale (FS) Calibration Limit

Zero-Scale Calibration Limit

Input Span

−10

µA

pF

Floating state

10

1.05 × FS

2.1 × FS

V

−1.05 × FS

0.8 × FS

POWER REQUIREMENTS

Power Supply Voltage

AVDD1 to AVSS

4.5

5.5

0

V

AVDD2 to AVSS

2

AVSS to DGND

−2.75

2

IOVDD to DGND

5.5

6.35

IOVDD to AVSS

For AVSS < DGND

POWER SUPPLY CURRENTS⁴

All outputs unloaded, digital inputs

connected to IOVDD or DGND

Full Operating Mode

AVDD1 Current

Analog input and reference input

buffers disabled, external reference

1.4

1.75

13

1.65

2

mA

Analog input and reference input

buffers disabled, internal reference

Analog input and reference input

buffers enabled, external reference

16

Each buffer: AIN+, AIN−, REF+, REF−

External reference

Internal reference

External clock

2.9

4.5

4.75

2.5

2.75

3

mA

µA

AVDD2 Current

IOVDD Current

5

5.2

2.8

3.1

Internal clock

External crystal

Standby Mode (LDO On)

Power-Down Mode

Internal reference off, total current

consumption

25

Internal reference on, total current

consumption

425

5

µA

Full power-down (including LDO and

internal reference)

10

Rev. B | Page 6 of 62

Data Sheet

AD7175-2

Parameter

POWER DISSIPATION⁴

Full Operating Mode

Test Conditions/Comments

Min

Typ

Max

Unit

All buffers disabled, external clock and

reference, AVDD2 = 2 V, IOVDD = 2 V

21

42

mW

All buffers disabled, external clock and

reference, all supplies = 5 V

All buffers disabled, external clock and

reference, all supplies = 5.5 V

52

All buffers enabled, internal clock and

reference, AVDD2 = 2 V, IOVDD = 2 V

82

All buffers enabled, internal clock and

reference, all supplies = 5 V

105

All buffers enabled, internal clock and

reference, all supplies = 5.5 V

136

50

Standby Mode

Internal reference off, all supplies = 5 V

Internal reference on, all supplies = 5 V

Full power-down, all supplies = 5 V

125

2.2

25

µW

mW

µW

Power-Down Mode

¹Specification is not production tested but is supported by characterization data at initial product release.

²Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale

calibration reduces the gain error to the order of the noise for the programmed output data rate.

³This specification includes moisture sensitivity level (MSL) preconditioning effects.

⁴This specification is with no load on the REFOUT and digital output pins.

TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, C_LOAD= 20 pF, unless otherwise noted.

Table 2.

Parameter

Limit at T_MIN, T_MAX

Unit

Test Conditions/Comments^{1, 2}

SCLK

t₃

25

ns min

SCLK high pulse width

SCLK low pulse width

t₄

READ OPERATION

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT/RDY active time

IOVDD = 4.75 V to 5.5 V

15

40

0

IOVDD = 2 V to 3.6 V

SCLK active edge to data valid delay⁴

3

t₂

12.5

25

2.5

20

0

IOVDD = 4.75 V to 5.5 V

IOVDD = 2 V to 3.6 V

5

t₅

Bus relinquish time after CS inactive edge

t₆

t₇

SCLK inactive edge to CS inactive edge

10

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

t₈

0

8

5

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

t₉

t₁₀

t₁₁

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

¹Sample tested during initial release to ensure compliance.

²See Figure 2 and Figure 3.

³This parameter is defined as the time required for the output to cross the V_OLor V_OHlimits.

⁴The SCLK active edge is the falling edge of SCLK.

5

RDY

DOUT/

while DOUT/

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required,

RDY

is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is

enabled, the digital word can be read only once.

Rev. B | Page 7 of 62

AD7175-2

Data Sheet

TIMING DIAGRAMS

CS (I)

t₆

t₁

t₅

MSB

LSB

DOUT/RDY (O)

t₇

t₂

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

Figure 2. Read Cycle Timing Diagram

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

I = INPUT, O = OUTPUT

Figure 3. Write Cycle Timing Diagram

Rev. B | Page 8 of 62

Data Sheet

AD7175-2

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

θ_JAis specified for a device soldered on a JEDEC test board for

surface-mount packages.

Table 3.

Parameter

Rating

AVDD1, AVDD2 to AVSS

AVDD1 to DGND

−0.3 V to +6.5 V

−0.3 V to +7.5 V

−3.25 V to +0.3 V

−0.3 V to AVDD1 + 0.3 V

−0.3 V to IOVDD + 0.3 V

10 mA

Table 4. Thermal Resistance

Package Type

θ_JA

Unit

IOVDD to DGND

24-Lead TSSOP

IOVDD to AVSS

JEDEC 1-Layer Board

JEDEC 2-Layer Board

149

81

°C/W

AVSS to DGND

Analog Input Voltage to AVSS

Reference Input Voltage to AVSS

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Analog Input/Digital Input Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Lead Soldering, Reflow Temperature

ESD Rating (HBM)

ESD CAUTION

−40°C to +105°C

−65°C to +150°C

150°C

260°C

4 kV

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. B | Page 9 of 62

AD7175-2

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

23

22

21

20

19

1

2

3

4

5

6

7

8

AIN4

AIN3

REF–

AIN2

REF+

AIN1

REFOUT

REGCAPA

AVSS

AIN0

GPIO1

GPIO0

REGCAPD

DGND

IOVDD

SYNC/ERROR

CS

AD7175-2

TOP VIEW

(Not to Scale) 18

AVDD1

17

16

15

14

13

AVDD2

9

XTAL1

10

11

12

XTAL2/CLKIO

DOUT/RDY

DIN

SCLK

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Type¹

Pin No.

Mnemonic

AIN4

Description

1

2

3

AI

Analog Input 4. Selectable through crosspoint multiplexer.

REF−

AI

Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V.

REF+

AI

Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+

can span from AVSS + 1 V to AVDD1.The device functions with a reference magnitude from 1 V to

AVDD1.

4

REFOUT

REGCAPA

AVSS

AO

P

Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.

Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF and a 0.1 µF capacitor.

Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V.

Analog Supply Voltage 1. This voltage is 5 V 10% with respect to AVSS.

Analog Supply Voltage 2. This voltage ranges from 2 V to 5 V with respect to AVSS.

Input 1 for Crystal.

5

6

7

AVDD1

P

8

AVDD2

P

9

XTAL1

AI

10

XTAL2/CLKIO

AI/DI

Input 2 for Crystal/Clock Input or Output. Based on the CLOCKSEL bits in the ADCMODE register. There

are four options available for selecting the MCLK source:

Internal oscillator: no output.

Internal oscillator: output to XTAL2/CLKIO. Operates at IOVDD logic level.

External clock: input to XTAL2/CLKIO. Input must be at IOVDD logic level.

External crystal: connected between XTAL1 and XTAL2/CLKIO.

11

DOUT/RDY

DO

Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data

from any of the on-chip data or control registers. The data-word/control word information is placed on

the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the

DOUT/RDY output is three-stated. When CS is low, DOUT/RDY operates as a data ready pin, going low

to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes

high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a

processor, indicating that valid data is available.

12

DIN

DI

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register address (RA) bits of the communications register

identifying the appropriate register. Data is clocked in on the rising edge of SCLK.

13

14

SCLK

CS

DI

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a

Schmitt triggered input, making the interface suitable for opto-isolated applications.

Chip Select Input. This is an active low logic input selects the ADC. CS can select the ADC in systems

with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-

wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the

DOUT/RDY output is three-stated.

Rev. B | Page 10 of 62

Data Sheet

AD7175-2

Pin No.

Mnemonic

SYNC/ERROR

Type¹

Description

15

DI/O

Synchronization Input/Error Input/Output. This pin can be switched between a logic input and a logic

output in the GPIOCON register. When synchronization input (SYNC) is enabled, this pin allows

synchronization of the digital filters and analog modulators when using multiple AD7175-2 devices.

For more information, see the Synchronization section. When the synchronization input is disabled,

this pin can be used in one of three modes:

Active low error input mode: this mode sets the ADC_ERROR bit in the status register.

Active low, open-drain error output mode: the status register error bits are mapped to the ERROR

output. The SYNC/ERROR pins of multiple devices can be wired together to a common pull-up resistor

so that an error on any device can be observed.

General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON

register. The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels

used by the GPIOx pins. The pin has an active pull-up in this case.

16

IOVDD

P

Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent

of AVDD2. For example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice versa. If AVSS is

set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.

17

18

DGND

P

Digital Ground.

REGCAPD

AO

Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND

using a 1 µF and a 0.1 µF capacitor.

19

20

21

22

23

24

GPIO0

GPIO1

AIN0

AIN1

AIN2

AIN3

DI/O

AI

General-Purpose Input/Output 0. The pin is referenced between AVDD1 and AVSS levels.

General-Purpose Input/Output 1. The pin is referenced between AVDD1 and AVSS levels.

Analog Input 0. Selectable through the crosspoint multiplexer.

AI

Analog Input 1. Selectable through the crosspoint multiplexer.

AI

Analog Input 2. Selectable through the crosspoint multiplexer.

AI

Analog Input 3. Selectable through the crosspoint multiplexer.

¹AI is analog input, AO is analog output, DI/O is bidirectional digital input/output, DO is digital output, DI is digital input, and P is power supply.

Rev. B | Page 11 of 62

AD7175-2

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, T_A= 25°C, unless otherwise noted.

8390000

8389500

8389000

8388500

8388000

8387500

8387000

8386500

8386000

1000

900

800

700

600

500

400

300

200

100

0

100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

8388460 8388461 8388462 8388463 8388464 8388465 8388466

ADC CODE

Figure 5. Noise (Analog Input Buffers Disabled, V_REF= 5 V,

Output Data Rate = 5 SPS)

Figure 8. Histogram (Analog Input Buffers Disabled, V_REF= 5 V,

Output Data Rate = 5 SPS)

120

100

80

60

40

20

0

8388480

8388475

8388470

8388465

8388460

8388455

8388450

8388445

0

100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

ADC CODE

Figure 6. Noise (Analog Input Buffers Disabled, V_REF= 5 V,

Output Data Rate = 10 kSPS)

Figure 9. Histogram (Analog Input Buffers Disabled, V_REF= 5 V,

Output Data Rate = 10 kSPS)

8388520

45

40

35

30

25

20

15

10

5

8388500

8388480

8388460

8388440

8388420

8388400

0

100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

ADC CODE

Figure 7. Noise (Analog Input Buffers Disabled, V_REF= 5 V,

Output Data Rate = 250 kSPS)

Figure 10. Histogram (Analog Input Buffers Disabled, V_REF= 5 V,

Output Data Rate = 250 kSPS)

Rev. B | Page 12 of 62

Data Sheet

AD7175-2

1000

900

800

700

600

500

400

300

200

100

0

8390000

8389500

8389000

8388500

8388000

8387500

8387000

8386500

8386000

8385500

8385000

8388490 8388491 8388492 8388493 8388494 8388495 8388496

ADC CODE

0

100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

Figure 14. Histogram (Analog Input Buffers Enabled, V_REF= 5 V,

Output Data Rate = 5 SPS)

Figure 11. Noise (Analog Input Buffers Enabled, V_REF= 5 V,

Output Data Rate = 5 SPS)

100

90

80

70

60

50

40

30

20

10

0

8388520

8388515

8388510

8388505

8388500

8388495

8388490

8388485

8388480

0

100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

ADC CODE

Figure 15. Histogram (Analog Input Buffers Enabled, V_REF= 5 V,

Output Data Rate = 10 kSPS)

Figure 12. Noise (Analog Input Buffers Enabled, V_REF= 5 V,

Output Data Rate = 10 kSPS)

35

30

25

20

15

10

5

8388580

8388560

8388540

8388520

8388500

8388480

8388460

8388440

0

100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

ADC CODE

Figure 13. Noise (Analog Input Buffers Enabled, V_REF= 5 V,

Output Data Rate = 250 kSPS)

Figure 16. Histogram (Analog Input Buffers Enabled, V_REF= 5 V,

Output Data Rate = 250 kSPS)

Rev. B | Page 13 of 62

AD7175-2

Data Sheet

0

–20

0.000016

0.000014

0.000012

0.000010

0.000008

0.000006

0.000004

0.000002

0

BUFFER ON

BUFFER OFF

–40

–60

–80

–100

–120

1

10

100

V

1k

10k

100k

1M

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

FREQUENCY (Hz)

INPUT COMMON-MODE VOLTAGE (V)

IN

Figure 20. Common-Mode Rejection Ratio (CMRR) vs. V_INFrequency

(V_IN= 0.1 V, Output Data Rate = 250 kSPS)

Figure 17. Noise vs. Input Common-Mode Voltage, Analog Input Buffers

On and Off

–80

–90

20

ANALOG INPUT BUFFERS OFF

ANALOG INPUT BUFFERS ON

18

–100

–110

–120

–130

–140

–150

–160

–170

–180

16

14

12

10

8

6

4

2

0

10

20

30

V

40

50

60

70

0

2

4

6

8

10

12

14

16

FREQUENCY (Hz)

FREQUENCY (MHz)

IN

Figure 18. Noise vs. External Master Clock Frequency,

Analog Input Buffers On and Off

Figure 21. Common-Mode Rejection Ratio (CMRR) vs. V_INFrequency

(V_IN= 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS Enhanced Filter)

16800000

16780000

16760000

16740000

16720000

16700000

16680000

16660000

CONTINUOUS CONVERSION—REFERENCE DISABLED

STANDBY—REFERENCE DISABLED

STANDBY—REFERENCE ENABLED

–60

AVDD1—EXTERNAL 2.5V REFERENCE

AVDD1—INTERNAL 2.5V REFERENCE

–70

–80

–90

–100

–110

–120

–130

1

10

100

1k

10k

1

10

100

1k

10k

100k

1M

10M

100M

SAMPLE NUMBER

V

FREQUENCY (Hz)

IN

Figure 19. Internal Reference Settling Time

Figure 22. Power Supply Rejection Ratio (PSRR) vs. V_INFrequency

Rev. B | Page 14 of 62

Data Sheet

AD7175-2

20

30

25

20

15

10

5

INTERNAL 2.5V REF,

ANALOG INPUT BUFFERS OFF

INTERNAL 2.5V REF,

ANALOG INPUT BUFFERS ON

EXTERNAL 2.5V REF,

ANALOG INPUT BUFFERS OFF

EXTERNAL 2.5V REF,

ANALOG INPUT BUFFERS ON

EXTERNAL 5V REF,

ANALOG INPUT BUFFERS OFF

15

10

5

EXTERNAL 5V REF,

ANALOG INPUT BUFFERS ON

0

–5

–10

–15

–20

0

–5

–4

–3

–2

–1

0

1

2

3

4

5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

V

(V)

INL ERROR (ppm)

IN

Figure 23. Integral Nonlinearity (INL) vs. V_IN

(Differential Input)

Figure 26. Integral Nonlinearity (INL) Distribution Histogram (Analog Input

Buffers Enabled, Differential Input, V_REF= 5 V External, 100 Units)

30

25

20

15

10

5

30

25

20

15

10

5

0

2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00

INL ERROR (ppm)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

INL ERROR (ppm)

Figure 24. Integral Nonlinearity (INL) Distribution Histogram (Differential

Input, Analog Input Buffers Enabled, V_REF= 2.5 V External, 100 Units)

Figure 27. Integral Nonlinearity (INL) Distribution Histogram (Analog Input

Buffers Disabled, Differential Input, V_REF= 5 V External, 100 Units)

30

25

20

15

10

5

5.0

BUFFER DISABLED

BUFFER ENABLED

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

–40

–20

0

20

40

60

80

100

INL ERROR (ppm)

TEMPERATURE (°C)

Figure 25. Integral Nonlinearity (INL) Distribution Histogram (Differential

Input, Analog Input Buffers Disabled, V_REF= 2.5 V External, 100 Units)

Figure 28. Integral Nonlinearity (INL) vs. Temperature

(Differential Input, V_REF= 2.5 V External)

Rev. B | Page 15 of 62

AD7175-2

Data Sheet

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

0

15.98 15.99 16.00 16.01 16.02 16.03 16.04 16.05

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

OFFSET ERROR (µV)

FREQUENCY (MHz)

Figure 29. Internal Oscillator Frequency/Accuracy Distribution Histogram

(100 Units)

Figure 32. Offset Error Distribution Histogram (Internal Short)

(248 Units)

16400000

16300000

16200000

16100000

16000000

15900000

15800000

15700000

15600000

35

30

25

20

15

10

5

0

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

OFFSET DRIFT ERROR (nV/°C)

Figure 30. Internal Oscillator Frequency vs. Temperature

Figure 33. Offset Error Drift Distribution Histogram (Internal Short)

(248 Units)

0.0010

40

35

30

25

20

15

10

5

0.0005

0

–0.0005

–0.0010

0

–40

–20

0

20

40

60

80

100

–4

–3

–2

–1

0

1

2

3

4

TEMPERATURE (°C)

GAIN ERROR (ppm/FSR)

Figure 31. Absolute Reference Error vs. Temperature

Figure 34. Gain Error Distribution Histogram (Analog Input Buffers Enabled)

(100 Units)

Rev. B | Page 16 of 62

Data Sheet

AD7175-2

0.025

0.020

0.015

0.010

0.005

0

30

25

20

15

10

5

BUFFERS DISABLED

BUFFERS ENABLED

0

–40

–20

0

20

40

60

80

100

34

35

36

37

38

39

40

41

42

43

GAIN ERROR (ppm/FSR)

TEMPERATURE (°C)

Figure 35. Gain Error Distribution Histogram

(Analog Input Buffers Disabled, 100 Units)

Figure 38. Current Consumption vs. Temperature

(Continuous Conversion Mode)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

25

20

15

10

5

0

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

GAIN ERROR DRIFT (ppm/FSR)

Figure 36. Gain Error Drift Distribution Histogram

(Analog Input Buffers Enabled, 100 Units)

Figure 39. Current Consumption vs. Temperature (Power-Down Mode)

40

35

30

25

20

15

10

5

18

16

14

12

10

8

6

4

2

0

0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55

GAIN ERROR DRIFT (ppm/FSR)

–1.2 –1.0 –0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8 1.0

TEMPERATURE DELTA (°C)

Figure 37. Gain Error Drift Distribution Histogram

(Analog Input Buffers Disabled, 100 Units)

Figure 40. Temperature Sensor Distribution Histogram

(Uncalibrated, 100 Units)

Rev. B | Page 17 of 62

AD7175-2

Data Sheet

35

30

25

20

15

10

5

100

80

AIN+ = AVDD1 – 0.2V

AIN– = AVSS + 0.2V

AIN+ = AVDD1

AIN– = AVSS

60

40

20

0

–20

–40

–60

–80

–100

0

–40

–20

0

20

40

60

80

100

9.60 9.65 9.70 9.75 9.80 9.85 9.90 9.95 10.00 10.05 10.10

CURRENT (µA)

TEMPERATURE (°C)

Figure 41. Burnout Current Distribution Histogram

(100 Units)

Figure 43. Analog Input Current vs. Temperature

100

80

–40°C, AIN+

–40°C, AIN–

+25°C, AIN+

+25°C, AIN–

+105°C, AIN+

+105°C, AIN–

60

40

20

0

–20

–40

–60

–80

–100

–5

–4

–3

–2

–1

0

1

2

3

4

5

INPUT VOLTAGE (V)

Figure 42. Analog Input Current vs. Input Voltage

(V_CM= 2.5 V)

Rev. B | Page 18 of 62

Data Sheet

AD7175-2

NOISE PERFORMANCE AND RESOLUTION

Table 6 and Table 7 show the rms noise, peak-to-peak noise,

effective resolution and the noise free (peak-to-peak) resolution

of the AD7175-2 for various output data rates and filters. The

numbers given are for the bipolar input range with an external

5 V reference.

These numbers are typical and are generated with a differential

input voltage of 0 V when the ADC is continuously converting

on a single channel. It is important to note that the peak-to-

peak resolution is calculated based on the peak-to-peak noise.

The peak-to-peak resolution represents the resolution for which

there is no code flicker.

Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc5 + Sinc1 Filter (Default)¹

Output Data Rate (SPS)

RMS Noise (µV rms)

Effective Resolution (Bits)

Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits)

Input Buffers Disabled

250,000

8.7

20.1

20.8

21.9

23.6

24

65

17.2

17.8

19.1

20.9

23.1

23.3

24

62,500

5.5

43

10,000

2.5

18.3

5.2

1000

0.77

0.19

0.18

0.1

59.92

1.1

49.96

24

0.95

0.45

0.34

16.66

24

5

0.07

24

Input Buffers Enabled

250,000

62,500

10,000

1000

9.8

20

85

16.8

17.5

18.7

20.7

23.0

23.3

23.9

24

6.4

20.6

21.7

23.4

24

55

3

23

0.92

0.23

0.2

5.7

1.2

1

59.98

49.96

16.66

5

24

0.13

0.07

24

0.66

0.32

24

¹Selected rates only, 1000 samples.

Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc3 Filter¹

Output Data Rate (SPS)

RMS Noise (µV rms)

Effective Resolution (Bits)

Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits)

Input Buffers Disabled

250,000

210

5.2

15.5

20.9

22.4

24

1600

40

12.6

17.9

19.4

21.3

23.6

23.8

24

62,500

10,000

1.8

14

1000

0.56

0.13

0.07

0.05

3.9

60

24

0.8

50

24

0.7

16.66

24

0.37

0.21

5

24

Input Buffers Enabled

250,000

62,500

10,000

1000

60

210

5.8

15.5

20.7

22.2

23.7

24

1600

48

12.6

17.7

19.3

21.1

23.1

23.5

24

2.1

16

0.71

0.17

0.15

0.12

0.08

4.5

1.1

50

24

0.83

0.6

16.66

5

24

0.35

24

¹Selected rates only, 1000 samples.

Rev. B | Page 19 of 62

AD7175-2

Data Sheet

GETTING STARTED

The AD7175-2 offers the user a fast settling, high resolution,

multiplexed ADC with high levels of configurability.

The AD7175-2 includes a precision 2.5 V low drift ( 2 ppm/°C)

band gap internal reference. This reference can used for the ADC

conversions, reducing the external component count. Alternatively,

the reference can be output to the REFOUT pin to be used as a

low noise biasing voltage for external circuitry. An example of

this is using the REFOUT signal to set the input common mode

for an external amplifier.

x

Two fully differential or four single-ended analog inputs.

Crosspoint multiplexer selects any analog input combina-

tion as the input signals to be converted, routing them to

the modulator positive or negative input.

x

True rail-to-rail buffered analog and reference inputs.

Fully differential input or single-ended input relative to any

analog input.

The AD7175-2 includes two separate linear regulator blocks for

both the analog and digital circuitry. The analog LDO regulates

the AVDD2 supply to 1.8 V, supplying the ADC core. The user

can tie the AVDD1 and AVDD2 supplies together for easiest

connection. If there is already a clean analog supply rail in the

system in the range of 2 V (minimum) to 5.5 V (maximum), the

user can also choose to connect this to the AVDD2 input,

allowing lower power dissipation.

x

Per channel configurability—up to four different setups can be

defined. A separate setup can be mapped to each of the

channels. Each setup allows the user to configure whether

the buffers are enabled or disabled, gain and offset correction,

filter type, output data rate, and reference source selection

(internal/external).

GENERAL-PURPOSE I/O 0 AND

GENERAL-PURPOSE I/O 1

OUTPUT HIGH = AVDDx

OUTPUT LOW = AVSS

GPIO0

GPIO1

16MHz

20

19

CX2

CX1

GPIO0

GPIO1

OPTIONAL EXTERNAL

CRYSTAL CIRCUITRY

CAPACITORS

9

XTAL1

21

AIN0

10

XTAL2/CLKI0

CLKIN

OPTIONAL

EXTERNAL

CLOCK

INPUT

DOUT/RDY 11

DOUT/RDY

DIN

22

23

AIN1

AIN2

12

DIN

13

SCLK

CS

SCLK

14

15

CS

SYNC/ERROR

IOVDD

24

1

AIN3

AIN4

AD7175-2

16

17

IOVDD

DGND

0.1µF

VIN

1

3

REGCAPD 18

2

4

7

6

V

NC

IN

0.1µF

1µF

AVDD1

4.7µF

0.1µF

ADR445BRZ

AVDD1

AVDD2

7

8

5

0.1µF

3

GND

5

V

REF+

REF–

OUT

AVDD2

0.1µF

4.7µF

0.1µF

8

2

4

0.1µF

REFOUT

REGCAPA

2.5V REFERENCE

OUTPUT

0.1µF

1µF

AVSS

6

0.1µF

Figure 44. Typical Connection Diagram

Rev. B | Page 20 of 62

AD7175-2

Data Sheet

The linear regulator for the digital IOVDD supply performs a

similar function, regulating the input voltage applied at the

IOVDD pin to 1.8 V for the internal digital filtering. The serial

interface signals always operate from the IOVDD supply seen at

the pin. This means that if 3.3 V is applied to the IOVDD pin,

the interface logic inputs and outputs operate at this level.

DRIVE EDGE

SAMPLE EDGE

Figure 45. SPI Mode 3 SCLK Edges

The AD7175-2 can be used across a wide variety of applications,

providing high resolution and accuracy. A sample of these

scenarios is as follows:

Accessing the ADC Register Map

The communications register controls access to the full register

map of the ADC. This register is an 8-bit write only register. On

power-up or after a reset, the digital interface defaults to a state

where it is expecting a write to the communications register;

therefore, all communication begins by writing to the

communications register.

x

Fast scanning of analog input channels using the internal

multiplexer

Fast scanning of analog input channels using an external

multiplexer with automatic control from the GPIOs.

High resolution at lower speeds in either channel scanning

or ADC per channel applications

The data written to the communications register determines

which register is being accessed and if the next operation is a

read or write. The register address bits (RA[5:0]) determine the

specific register to which the read or write operation applies.

Single ADC per channel: the fast low latency output allows

further application specific filtering in an external micro-

controller, DSP, or FPGA

When the read or write operation to the selected register is

complete, the interface returns to the default state, where it

expects a write operation to the communications register.

POWER SUPPLIES

The AD7175-2 has three independent power supply pins:

AVDD1, AVDD2, and IOVDD.

Figure 46 and Figure 47 illustrate writing to and reading from a

register by first writing the 8-bit command to the communications

register, followed by the data for that register.

8 BITS, 16 BITS,

AVDD1 powers the crosspoint multiplexer and integrated analog

and reference input buffers. AVDD1 is referenced to AVSS, and

AVDD1 − AVSS = 5 V only. This can be a single 5 V supply or a

2.5 V split supply. The split supply operation allows true bipolar

inputs. When using split supplies, consider the absolute maximum

ratings (see the Absolute Maximum Ratings section).

8-BIT COMMAND

OR 24 BITS OF DATA

CS

AVDD2 powers the internal 1.8 V analog LDO regulator. This

regulator powers the ADC core. AVDD2 is referenced to AVSS,

and AVDD2 − AVSS can range from 5.5 V (maximum) to 2 V

(minimum).

CMD

DATA

DIN

SCLK

IOVDD powers the internal 1.8 V digital LDO regulator. This

regulator powers the digital logic of the ADC. IOVDD sets the

voltage levels for the SPI interface of the ADC. IOVDD is refer-

enced to DGND, and IOVDD − DGND can vary from 5.5 V

(maximum) to 2 V (minimum).

Figure 46. Writing to a Register

(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;

Data Length on DIN Is Dependent on the Register Selected)

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OUTPUT

There is no specific requirement for a power supply sequence

on the AD7175-2. When all power supplies are stable, a device

reset is required; see the AD7175-2 Reset section for details on

how to reset the device.

8-BIT COMMAND

CS

CMD

DIGITAL COMMUNICATION

DIN

The AD7175-2 has a 3- or 4-wire SPI interface that is compatible

with QSPI™, MICROWIRE®, and DSPs. The interface operates

DOUT/RDY

DATA

CS

in SPI Mode 3 and can be operated with

tied low. In SPI

Mode 3, the SCLK idles high, the falling edge of SCLK is the

drive edge, and the rising edge of SCLK is the sample edge. This

means that data is clocked out on the falling/drive edge and data

is clocked in on the rising/sample edge.

SCLK

Figure 47. Reading from a Register

(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;

Data Length on DOUT Is Dependent on the Register Selected)

Rev. B | Page 21 of 62

AD7175-2

Data Sheet

Reading the ID register is the recommended method for verifying

correct communication with the device. The ID register is a

read only register and contains the value 0x0CDX for the

AD7175-2. The communications register and the ID register

details are described in Table 8 and Table 9.

Figure 48 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

x

Channel configuration (see Box A in Figure 48)

Setup configuration (see Box B in Figure 48)

ADC mode and interface mode configuration (see Box C

in Figure 48)

AD7175-2 RESET

In situations where interface synchronization is lost, a write

operation of at least 64 serial clock cycles with DIN high returns the

ADC to the default state by resetting the entire device, including

Channel Configuration

The AD7175-2 has four independent channels and four independ-

ent setups. The user can select any of the analog input pairs on

any channel, as well as any of the four setups for any channel,

giving the user full flexibility in the channel configuration. This

also allows per channel configuration when using differential

inputs and single-ended inputs because each channel can have a

dedicated setup.

CS

the register contents. Alternatively, if

is being used with the

high sets the digital interface to

CS

digital interface, returning

the default state and halts any serial interface operation.

CONFIGURATION OVERVIEW

After power-on or reset, the AD7175-2 default configuration is

as follows:

Channel Registers

x

Channel configuration. CH0 is enabled, AIN0 is selected

as the positive input, and AIN1 is selected as the negative

input. Setup 0 is selected.

The channel registers select which of the five analog input pins

(AIN0 to AIN4) are used as either the positive analog input (AIN+)

or the negative analog input (AIN−) for that channel. This register

also contains a channel enable/disable bit and the setup selection

bits, which pick which of the four available setups to use for this

channel.

x

Setup configuration. The internal reference and the analog

input buffers are enabled. The reference input buffers are

disabled.

x

Filter configuration. The sinc5 + sinc 1 filter is selected and

the maximum output data rate of 250 kSPS is selected.

ADC mode. Continuous conversion mode and the internal

oscillator are enabled.

When the AD7175-2 is operating with more than one channel

enabled, the channel sequencer cycles through the enabled

channels in sequential order, from Channel 0 to Channel 3. If a

channel is disabled, it is skipped by the sequencer. Details of the

channel register for Channel 0 are shown in Table 10.

Interface mode. CRC and data + status output are disabled.

Note that only a few of the register setting options are shown;

this list is just an example. For full register information, see the

Register Details section.

A

B

C

CHANNEL CONFIGURATION

SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL

SELECT ONE OF 4 SETUPS FOR ADC CHANNEL

SETUP CONFIGURATION

4 POSSIBLE ADC SETUPS

SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE

ADC MODE AND INTERFACE MODE CONFIGURATION

SELECT ADC OPERATING MODE, CLOCK SOURCE,

ENABLE CRC, DATA + STATUS, AND MORE

Figure 48. Suggested ADC Configuration Flow

Table 8. Communications Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x00

COMMS [7:0]

RA

0x00

W

WEN

R/W

Table 9. ID Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 3

Reset

RW

0x07

ID

[15:8]

[7:0]

ID[15:8]

ID[7:0]

0x0CDX

R

Rev. B | Page 22 of 62

Data Sheet

AD7175-2

Table 10. Channel 0 Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Reserved

AINNEG0

Bit 1

Bit 0

Reset

RW

0x10

CH0

[15:8] CH_EN0

[7:0]

Reserved

AINPOS0[2:0]

SETUP_SEL[2:0]

AINPOS0[4:3]

0x8001

RW

Rev. B | Page 23 of 62

AD7175-2

Data Sheet

ADC Setups

Setup Configuration Registers

The AD7175-2 has four independent setups. Each setup consists

of the following four registers:

The setup configuration registers allow the user to select the output

coding of the ADC by selecting between bipolar and unipolar. In

bipolar mode, the ADC accepts negative differential input voltages,

and the output coding is offset binary. In unipolar mode, the ADC

accepts only positive differential voltages, and the coding is straight

binary. In either case, the input voltage must be within the AVDD1/

AVSS supply voltages. The user can select the reference source

using this register. Three options are available: an internal 2.5 V

reference, an external reference connected between the REF+

and REF− pins, or AVDD1 − AVSS. The analog input and

reference input buffers can also be enabled or disabled using

this register.

x

Setup configuration register

Filter configuration register

Offset register

Gain register

For example, Setup 0 consists of Setup Configuration Register 0,

Filter Configuration Register 0, Gain Register 0, and Offset

Register 0. Figure 49 shows the grouping of these registers The

setup is selectable from the channel registers (see the Channel

Configuration section), which allows each channel to be assigned

to one of four separate setups. Table 11 through Table 14 show the

four registers that are associated with Setup 0. This structure is

repeated for Setup 1 to Setup 3.

Filter Configuration Registers

The filter configuration register selects which digital filter is

used at the output of the ADC modulator. The order of the filter

and the output data rate is selected by setting the bits in this

register. For more information, see the Digital Filters section.

SETUP CONFIG

REGISTERS

FILTER CONFIG

REGISTERS

GAIN REGISTERS*

OFFSET REGISTERS

SETUPCON0

SETUPCON1

SETUPCON2

SETUPCON3

FILTCON0

FILTCON1

FILTCON2

FILTCON3

GAIN0

GAIN1

GAIN2

GAIN3

OFFSET0

0x30

0x20

0x21

0x22

0x23

0x28

0x29

0x2A

0x2B

0x38

0x39

0x3A

0x3B

OFFSET1

0x31

OFFSET2

0x32

OFFSET3

0x33

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

AND OUTPUT DATA RATE

PROGRAMMED

PER SETUP AS REQUIRED

(*FACTORY CALIBRATED)

DATA OUTPUT CODING

REFERENCE SOURCE

INPUT BUFFERS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50Hz AND 60Hz

Figure 49. ADC Setup Register Grouping

Table 11. Setup Configuration 0 Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x20 SETUPCON0 [15:8]

[7:0]

Reserved

BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1320

RW

BURNOUT_EN0 Reserved

REF_SEL0

Reserved

Table 12. Filter Configuration 0 Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Reserved

ORDER0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x28 FILTCON0 [15:8] SINC3_MAP0

[7:0] Reserved

ENHFILTEN0

ENHFILT0

0x0500

RW

ODR0

Table 13. Gain Configuration 0 Register

Reg. Name

Bits

Bit[23:0]

Reset

RW

0x38 GAIN0

[23:0]

GAIN0[23:0]

0x5XXXX0 RW

Table 14. Offset Configuration 0 Register

Reg. Name

Bits

Bit[23:0]

Reset

RW

0x30 OFFSET0

[23:0]

OFFSET0[23:0]

0x800000 RW

Rev. B | Page 24 of 62

Data Sheet

AD7175-2

ADC Mode and Interface Mode Configuration

Gain Registers

The ADC mode register and the interface mode register configure

the core peripherals for use by the AD7175-2 and the mode for

the digital interface.

The gain register is a 24-bit register that holds the gain

calibration coefficient for the ADC. The gain registers are

read/write registers. These registers are configured at power-on

with factory calibrated coefficients. Therefore, every device has

different default coefficients. The default value is automatically

overwritten if a system full-scale calibration is initiated by the

user or if the gain register is written to by the user. For more

information on calibration, see the Operating Modes section.

ADC Mode Register

The ADC mode register is used primarily to set the conversion

mode of the ADC to either continuous or single conversion.

The user can also select the standby and power-down modes,

as well as any of the calibration modes. In addition, this register

contains the clock source select bits and the internal reference

enable bits. The reference select bits are contained in the setup

configuration registers (see the ADC Setups section for more

information).

Offset Registers

The offset register holds the offset calibration coefficient for the

ADC. The power-on reset value of the offset register is 0x800000.

The offset register is a 24-bit read/write register. The power-on

reset value is automatically overwritten if an internal or system

zero-scale calibration is initiated by the user or if the offset register

is written to by the user.

Interface Mode Register

The interface mode register configures the digital interface

operation. This register allows the user to control data-word

length, CRC enable, data plus status read, and continuous read

mode. The details of both registers are shown in Table 15 and

Table 16. For more information, see the Digital Interface section.

Table 15. ADC Mode Register

Reg. Name

0x01 ADCMODE [15:8] REF_EN

[7:0] Reserved

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Reserved

Bit 2

CLOCKSEL

Bit 1

Delay

Reserved

Bit 0

Reset

RW

HIDE_DELAY SING_CYC

Mode

0x8000 RW

Table 16. Interface Mode Register

Reg.

Name

Bits

Bit 7

Bit 6

Reserved

CONTREAD DATA_STAT

Bit 5

Bit 4

ALT_SYNC IOSTRENGTH

Reserved CRC_EN

Bit 3

Bit 2

Bit 1

Reserved

Bit 0

Reset

RW

0x02 IFMODE [15:8]

[7:0]

DOUT_RESET

WL16

0x0000 RW

REG_CHECK

Rev. B | Page 25 of 62

AD7175-2

Data Sheet

Understanding Configuration Flexibility

Programming the gain and offset registers is optional for any use

case, as indicated by the dashed lines between the register blocks.

The most straightforward implementation of the AD7175-2 is

to use two differential inputs with adjacent analog inputs and

run both of them with the same setup, gain correction, and offset

correction register. In this case, the user selects the following

differential inputs: AIN0/AIN1 and AIN2/AIN3. In Figure 50,

the registers shown in black font must be programmed for such

a configuration. The registers that are shown in gray font are

redundant in this configuration.

An alternative way to implement these two fully differential

inputs is by taking advantage of the four available setups.

Motivation for doing this includes having a different speed/noise

requirement on each of the differential inputs, or there may be a

specific offset or gain correction for each channel. Figure 51

shows how each of the differential inputs can use a separate

setup, allowing full flexibility in the configuration of each channel.

CHANNEL

REGISTERS

SETUP CONFIG

REGISTERS

FILTER CONFIG

REGISTERS

GAIN REGISTERS*

OFFSET REGISTERS

AIN0

AIN1

AIN2

AIN3

AIN4

CH0

SETUPCON0

FILTCON0

GAIN0

0x38

OFFSET0

0x30

0x10

0x20

0x28

0x29

0x2A

0x2B

CH1

CH2

CH3

SETUPCON1

SETUPCON2

SETUPCON3

FILTCON1

FILTCON2

FILTCON3

GAIN1

GAIN2

GAIN3

OFFSET1

0x31

0x21

0x22

0x23

0x39

0x3A

0x3B

0x11

0x12

0x13

OFFSET2

0x32

OFFSET3

0x33

SELECT ANALOG INPUT PAIRS

ENABLE THE CHANNEL

SELECT SETUP 0

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

PROGRAMMED

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

(*FACTORY CALIBRATED)

DATA OUTPUT CODING

REFERENCE SOURCE

INPUT BUFFERS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50Hz AND 60Hz

Figure 50. Two Fully Differential Inputs, Both Using a Single Setup (SETUPCON0; FILTCON0; GAIN0; OFFSET0)

CHANNEL

REGISTERS

SETUP CONFIG

REGISTERS

FILTER CONFIG

REGISTERS

GAIN REGISTERS*

OFFSET REGISTERS

AIN0

AIN1

AIN2

AIN3

AIN4

CH0

SETUPCON0

FILTCON0

0x28

GAIN0

0x38

OFFSET0

0x30

0x10

0x20

CH1

CH2

CH3

SETUPCON1

SETUPCON2

SETUPCON3

FILTCON1

FILTCON2

FILTCON3

GAIN1

GAIN2

GAIN3

OFFSET1

0x31

0x21

0x22

0x23

0x29

0x2A

0x2B

0x39

0x3A

0x3B

0x11

0x12

0x13

OFFSET2

0x32

OFFSET3

0x33

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

PROGRAMMED

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

(*FACTORY CALIBRATED)

DATA OUTPUT CODING

REFERENCE SOURCE

INPUT BUFFERS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50Hz AND 60Hz

Figure 51. Two Fully Differential Inputs with a Setup per Channel

Rev. B | Page 26 of 62

Data Sheet

AD7175-2

Figure 52 shows an example of how the channel registers span

between the analog input pins and the setup configurations

downstream. In this example, one differential input and two single-

ended inputs are required. The single-ended inputs are the AIN2/

AIN4 and AIN3/AIN4 combinations. The differential input pairs

is AIN0/AIN1and uses Setup 0. The two single-ended input pairs

are set up as diagnostics; therefore, use a separate setup from the

differential input but share a setup between them, Setup 1.

Given that two setups are selected for use, the SETUPCON0

and SETUPCON1 registers are programmed as required, and the

FILTCON0 and FILTCON1 registers are also programmed as

desired. Optional gain and offset correction can be employed

on a per setup basis by programming the GAIN0 and GAIN1

registers and the OFFSET0 and OFFSET1 registers.

In the example shown in Figure 52, the CH0 to CH2 registers

are used. Setting the MSB in each of these registers, the CH_EN0

to CH_EN2 bits enable the three combinations via the crosspoint

mux. When the AD7175-2 converts, the sequencer transitions

in ascending sequential order from CH0 to CH1 to CH2 before

looping back to CH0 to repeat the sequence.

CHANNEL

REGISTERS

SETUP CONFIG

REGISTERS

FILTER CONFIG

REGISTERS

GAIN REGISTERS*

OFFSET REGISTERS

AIN0

AIN1

AIN2

AIN3

AIN4

CH0

SETUPCON0

FILTCON0

GAIN0

0x38

OFFSET0

0x30

0x10

0x20

0x28

0x29

0x2A

0x2B

CH1

CH2

CH3

SETUPCON1

SETUPCON2

SETUPCON3

FILTCON1

FILTCON2

FILTCON3

GAIN1

GAIN2

GAIN3

OFFSET1

0x31

0x21

0x22

0x23

0x39

0x3A

0x3B

0x11

0x12

0x13

OFFSET2

0x32

OFFSET3

0x33

SELECT ANALOG INPUT PARTS

ENABLE THE CHANNEL

SELECT SETUP

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

PROGRAMMED

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

(*FACTORY CALIBRATED)

DATA OUTPUT CODING

REFERENCE SOURCE

INPUT BUFFERS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50Hz AND 60Hz

Figure 52. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups

Rev. B | Page 27 of 62

AD7175-2

Data Sheet

CIRCUIT DESCRIPTION

BUFFERED ANALOG INPUT

AVDD1

AIN0

AIN1

The AD7175-2 has true rail-to-rail, integrated, precision unity

gain buffers on both ADC analog inputs. The buffers provide

the benefit of giving the user high input impedance with only

30 nA typical input current, allowing high impedance sources

to be connected directly to the analog inputs. The buffers fully

drive the internal ADC switch capacitor sampling network,

simplifying the analog front-end circuit requirements while

consuming a very efficient 2.9 mA typical per buffer. Each analog

input buffer amplifier is fully chopped, meaning that it minimizes

the offset error drift and 1/f noise of the buffer. The 1/f noise

profile of the ADC and buffer combined is shown in Figure 53.

0

AVSS

AVDD1

Ø1

+IN

CS1

CS2

AVSS

Ø2

AVDD1

AIN2

AVSS

–IN

AVDD1

Ø1

AIN3

AIN4

AVSS

AVDD1

–50

–100

–150

–200

–250

AVSS

Figure 54. Simplified Analog Input Circuit

The CS1 and CS2 capacitors have a magnitude in the order of a

number of picofarads each. This capacitance is the combination

of both the sampling capacitance and the parasitic capacitance.

Fully Differential Inputs

Because the AIN0 to AIN4 analog inputs are connected to a

crosspoint multiplexer, any combination of signals can create an

analog input pair. This allows the user to select two fully

differential inputs or four single-ended inputs.

0.1

1

10

100

1k

10k

FREQUENCY (Hz)

Figure 53. Shorted Input FFT (Analog Input Buffers Enabled)

The analog input buffers do not suffer from linearity

degradation when operating at the rails, unlike many discrete

amplifiers. When operating at or close to the AVDD1 and AVSS

supply rails, there is an increase in input current. This increase

is most notable at higher temperatures. Figure 42 and Figure 43

show the input current for various conditions. With the analog

input buffers disabled, the average input current to the AD7175-2

changes linearly with the differential input voltage at a rate of

48 µA/V.

If two fully differential input paths are connected to the AD7175-2,

using AIN0/AIN1 as one differential input pair and AIN2/AIN3

as the second differential input pair is recommended. This is

due to the relative locations of these pins to each other. Decouple all

analog inputs to AVSS.

Single-Ended Inputs

The user can also choose to measure four different single-ended

analog inputs. In this case, each of the analog inputs is converted

as the difference between the single-ended input to be

CROSSPOINT MULTIPLEXER

measured and a set analog input common pin. Because there is

a crosspoint multiplexer, the user can set any of the analog inputs

as the common pin. An example of such a scenario is to connect

the AIN4 pin to AVSS or to the REFOUT voltage (that is, AVSS

+ 2.5 V) and select this input when configuring the crosspoint

multiplexer. When using the AD7175-2 with single-ended

inputs, the INL specification is degraded.

There are five analog input pins: AIN0, AIN1, AIN2, AIN3, and

AIN4. Each of these pins connects to the internal crosspoint

multiplexer. The crosspoint multiplexer enables any of these inputs

to be configured as an input pair, either single-ended or fully

differential. The AD7175-2 can have up to four active channels.

When more than one channel is enabled, the channels are

automatically sequenced in order from the lowest enabled channel

number to the highest enabled channel number. The output of

the multiplexer is connected to the input of the integrated true

rail-to-rail buffers. These can be bypassed and the multiplexer

output can be directly connected to the switched-capacitor input

of the ADC. The simplified analog input circuit is shown in

Figure 54.

Rev. B | Page 28 of 62

Data Sheet

AD7175-2

The output is then connected to a 4.7 µF capacitor, which acts

as a reservoir for any dynamic charge required by the ADC, and

followed by a 0.1 µF decoupling capacitor at the REF+ input.

This capacitor is placed as close as possible to the REF+ and

REF− pins. The REF− pin is connected directly to the AVSS

potential. On power-up of the AD7175-2, the internal reference

is enabled by default and is output on the REFOUT pin. When

an external reference is used instead of the internal reference to

supply the AD7175-2, attention must be paid to the output of

the REFOUT pin. If the internal reference is not being used

elsewhere in the application, ensure that the REFOUT pin is not

hardwired to AVSS because this draws a large current on power-

up. On power-up, if the internal reference is not being used,

write to the ADC mode register, disabling the internal

AD7175-2 REFERENCE

The AD7175-2 offers the user the option of either supplying an

external reference to the REF+ and REF− pins of the device or

allowing the use of the internal 2.5 V, low noise, low drift reference.

Select the reference source to be used by the analog input by setting

the REF_SELx bits (Bits[5:4]) in the setup configuration registers

appropriately. The structure of the Setup Configuration 0 register

is shown in Table 17. The AD7175-2 defaults on power-up to

use the internal 2.5 V reference.

External Reference

The AD7175-2 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR445, ADR444, and ADR441,

are recommended for use. Apply the external reference to the

AD7175-2 reference pins as shown in Figure 55. Decouple the

output of any external reference to AVSS. As shown in Figure 55,

the ADR445 output is decoupled with a 0.1 µF capacitor at the

output for stability purposes.

reference. This is controlled by the REF_EN bit (Bit 15) in the

ADC mode register, which is shown in Table 18.

AD7175-2

5.5V TO 18V

ADR445²

3

2

REF+

REF–

0.1µF

1

5V VREF

1

0.1µF

4.7µF

0.1µF

1

2

ALL DECOUPLING IS TO AVSS.

ANY OF THE ADR44x FAMILY OF REFERENCES CAN BE USED.

THE ADR444 AND ADR441 BOTH ENABLE REUSE OF THE 5V ANALOG SUPPLY

NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN.

Figure 55. External Reference ADR445 Connected to AD7175-2 Reference Pins

Table 17. Setup Configuration 0 Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1320 RW

REF_SEL0 Reserved

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x20 SETUPCON0 [15:8]

[7:0]

Reserved

BURNOUT_EN0 Reserved

Table 18. ADC Mode Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

CLOCKSEL

Bit 1

Delay

Reserved

Bit 0

Reset

RW

0x01 ADCMODE [15:8]

[7:0]

REF_EN

Reserved

HIDE_DELAY

SING_CYC

Mode

Reserved

0x8000

RW

Rev. B | Page 29 of 62

AD7175-2

Data Sheet

Internal Reference

the IOVDD logic level. Use of this option can affect the dc

performance of the AD7175-2 due to the disturbance introduced

by the output driver. The extent to which the performance is

affected depends on the IOVDD voltage supply. Higher IOVDD

voltages create a wider logic output swing from the driver and

affect performance to a greater extent. This effect is further

exaggerated if the IOSTRENGTH bit is set at higher IOVDD

levels (see Table 28 for more information).

The AD7175-2 includes a low noise, low drift voltage reference.

The internal reference has a 2.5 V output. The internal reference is

output on the REFOUT pin after the REF_EN bit in the ADC

mode register is set and is decoupled to AVSS with a 0.1 µF

capacitor. The AD7175-2 internal reference is enabled by default on

power-up and is selected as the reference source for the ADC.

When using the internal reference, the INL performance is

degraded as shown in Figure 23.

External Crystal

The REFOUT signal is buffered before being output to the pin.

The signal can be used externally in the circuit as a common-mode

source for external amplifier configurations.

If higher precision, lower jitter clock sources are required, the

AD7175-2 can use an external crystal to generate the master

clock. The crystal is connected to the XTAL1 and

XTAL2/CLKIO pins. A recommended crystal for use is the FA-

20H—a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom—

which is available in a surface-mount package. As shown in

Figure 56, insert two capacitors from the traces connecting the

crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors

allow for circuit tuning. Connect these capacitors to the DGND

pin. The value for these capacitors depends on the length and

capacitance of the trace connections between the crystal and the

XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these

capacitors differ depending on the printed circuit board (PCB)

layout and the crystal employed.

BUFFERED REFERENCE INPUT

The AD7175-2 has true rail-to-rail, integrated, precision unity

gain buffers on both ADC reference inputs. The buffers provide

the benefit of giving the user high input impedance and allow

high impedance external sources to be directly connected to the

reference inputs. The integrated reference buffers can fully drive

the internal reference switch capacitor sampling network,

simplifying the reference circuit requirements while consuming

a very efficient 2.9 mA typical per buffer. Each reference input

buffer amplifier is fully chopped, meaning that it minimizes the

offset error drift and 1/f noise of the buffer. When using an

external reference, such as the ADR445, ADR444, and ADR441,

these buffers are not required because these references, with

proper decoupling, can drive the reference inputs directly.

AD7175-2

Cx1

*

9

XTAL1

XTAL2/CLKIO 10

CLOCK SOURCE

Cx2

The AD7175-2 uses a nominal master clock of 16 MHz. The

AD7175-2 can source the sampling clock from one of three

sources:

*

*DECOUPLE TO DGND.

Figure 56. External Crystal Connections

x

Internal oscillator

External crystal

The external crystal circuitry can be sensitive to the SCLK

edges, depending on SCLK frequency, IOVDD voltage, crystal

circuitry layout, and the crystal used. During crystal startup, any

disturbances caused by the SCLK edges may cause double edges

on the crystal input, resulting in invalid conversions until the

crystal voltage has reached a high enough level such that any

interference from the SCLK edges is insufficient to cause double

clocking. This double clocking can be avoided by ensuring that

the crystal circuitry has reached a sufficient voltage level after

startup before applying any SCLK.

External clock source

All output data rates listed in the data sheet relate to a master

clock rate of 16 MHz. Using a lower clock frequency from, for

instance, an external source scales any listed data rate

proportionally. To achieve the specified data rates, particularly

rates for rejection of 50 Hz and 60 Hz, use a 16 MHz clock. The

source of the master clock is selected by setting the CLOCKSEL

bits (Bits[3:2]) in the ADC mode register as shown in Table 18.

The default operation on power-up and reset of the AD7175-2

is to operate with the internal oscillator. It is possible to fine

tune the output data rate and filter notch at low output data

rates using the SINC3_MAPx bit. See the Sinc3 Filter section

for more information.

Due to the nature of the crystal circuitry, it is therefore

recommended that empirical testing of the circuit b performed

under the required conditions, with the final PCB layout and

crystal, to ensure correct operation.

External Clock

Internal Oscillator

The AD7175-2 can also use an externally supplied clock. In

systems where this is desirable, the external clock is routed to

the XTAL2/CLKIO pin. In this configuration, the

The internal oscillator runs at 16 MHz and can be used as the

ADC master clock. It is the default clock source for the AD7175-2

and is specified with an accuracy of 2.5%.

XTAL2/CLKIO pin accepts the externally sourced clock and

routes it to the modulator. The logic level of this clock input is

defined by the voltage applied to the IOVDD pin.

There is an option to allow the internal clock oscillator to be

output on the XTAL2/CLKIO pin. The clock output is driven to

Rev. B | Page 30 of 62

Data Sheet

AD7175-2

DIGITAL FILTERS

The AD7175-2 has three flexible filter options to allow

SINC3 FILTER

optimization of noise, settling time, and rejection:

The sinc3 filter achieves the best single-channel noise performance

at lower rates and is, therefore, most suitable for single-channel

applications. The sinc3 filter always has a settling time equal to

x

Sinc5 + sinc1 filter

Sinc3 filter

Enhanced 50 Hz and 60 Hz rejection filters

t_SETTLE= 3/Output Data Rate

Figure 59 shows the frequency domain filter response for the

sinc3 filter. The sinc3 filter has good roll-off over frequency and

has wide notches for good notch frequency rejection.

50Hz AND 60Hz

POSTFILTER

SINC1

SINC5

SINC3

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

Figure 57. Digital Filter Block Diagram

The filter and output data rate are configured by setting the

appropriate bits in the filter configuration register for the

selected setup. Each channel can use a different setup and

therefore, a different filter and output data rate. See the Register

Details section for more information.

SINC5 + SINC1 FILTER

The sinc5 + sinc1 filter is targeted at multiplexed applications and

achieves single cycle settling at output data rates of 10 kSPS and

lower. The sinc5 block output is fixed at the maximum rate of

250 kSPS, and the sinc1 block output data rate can be varied to

control the final ADC output data rate. Figure 58 shows the

frequency domain response of the sinc5 + sinc1 filter at a 50 SPS

output data rate. The sinc5 + sinc1 filter has a slow roll-off over

frequency and narrow notches.

–120

0

50

100

FREQUENCY (Hz)

150

Figure 59. Sinc3 Filter Response

The output data rates with the accompanying settling time and

rms noise for the sinc3 filter are shown in Table 21 and Table 22. It

is possible to finely tune the output data rate for the sinc3 filter by

setting the SINC3_MAPx bit in the filter configuration registers.

If this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the sinc3 filter. All other options

are eliminated. The data rate when on a single channel can be

calculated using the following equation:

0

–20

–40

f _MOD

Output Data Rate

–60

32uFILTCONx[14:0]

–80

where:

f_MODis the modulator rate (MCLK/2) and is 8 MHz for a

16 MHz MCLK.

–100

–120

FILTCONx[14:0] are the contents on the filter configuration

registers excluding the MSB.

0

50

100

FREQUENCY (Hz)

150

For example, an output data rate of 50 SPS can be achieved with

SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a

value of 5000.

Figure 58. Sinc5 + Sinc1 Filter Response at 50 SPS ODR

The output data rates with the accompanying settling time and

rms noise for the sinc5 + sinc1 filter are shown in Table 19 and

Table 20.

Rev. B | Page 31 of 62

AD7175-2

Data Sheet

Figure 61 shows the same step on the analog input but with

SINGLE CYCLE SETTLING

single cycle settling enabled. The analog input requires at least a

single cycle for the output to be fully settled. The output data

The AD7175-2 can be configured by setting the SING_CYC bit

in the ADC mode register so that only fully settled data is output,

thus effectively putting the ADC into a single cycle settling mode.

This mode achieves single cycle settling by reducing the output

data rate to be equal to the settling time of the ADC for the selected

output data rate. This bit has no effect with the sinc5 + sinc1

filter at output data rates of 10 kSPS and lower.

RDY

rate, as indicated by the

signal, is now reduced to equal the

settling time of the filter at the selected output data rate.

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

Figure 60 shows a step on the analog input with this mode

disabled and the sinc3 filter selected. The analog input requires

at least three cycles after the step change for the output to reach

the final settled value.

t_SETTLE

Figure 61. Step Input with Single Cycle Settling

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

1/ODR

Figure 60. Step Input Without Single Cycle Settling

Table 19. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Disabled

Output Data Rate

(SPS/Channel);

SING_CYC = 1 or with

Multiple Channels

Enabled¹

Default Output

Data Rate (SPS);

SING_CYC = 0 and

Single Channel

Enabled¹

Effective

Peak-to-Peak

Resolution with

5 V Reference

(Bits)

Notch

Frequency

(Hz)

Resolution with

5 V Reference

(Bits)

Settling

Time¹

Noise

(µV rms)

Noise

(µV p-p)²

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

50,000

41,667

31,250

27,778

20,833

17,857

12,500

10,000

5000

20 µs

250,000

125,000

62,500

50,000

31,250

25,000

15,625

11,905

5435

8.7

20.1

20.4

20.8

20.9

21.3

21.4

21.7

21.9

22.5

23.0

23.6

24

65

17.2

17.3

17.8

17.9

18.3

18.4

18.8

19.1

19.7

20.2

20.9

21.6

21.7

22.3

22.9

23.1

23.3

24

24 µs

7.2

60

32 µs

5.5

43

36 µs

5

41

48 µs

4

32

56 µs

3.6

29

80 µs

2.9

22

100 µs

200 µs

400 µs

1.0 ms

2.0 ms

2.516 ms

5.0 ms

10 ms

2.5

18.3

12

1.7

2500

2604

1.2

8.2

5.2

3.2

3

1000

1016

0.77

0.57

0.5

500.0

397.5

200.0

100

504

397.5

200

400.00

200.64

100.16

59.98

24

0.36

0.25

0.19

0.18

0.11

0.1

24

2

100

24

1.3

1.1

0.95

0.6

0.45

0.4

0.34

59.92

49.96

20

59.92

49.96

20.00

16.66

10.00

5.00

16.67 ms

20.016 ms

50.0 ms

60.02 ms

100 ms

200 ms

24

50.00

24

20.01

24

16.66

10

16.66

24

10.00

0.08

0.07

24

5

5.00

24

¹The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate =1 ÷ settling time.

²1000 samples.

Rev. B | Page 32 of 62

Data Sheet

AD7175-2

Table 20. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Enabled

Output Data Rate

(SPS/Channel);

SING_CYC = 1 or

with Multiple

Default Output Data

Rate (SPS);

SING_CYC = 0 and

Single Channel

Enabled¹

Effective

Peak-to-Peak

Resolution with

5 V Reference

(Bits)

Notch

Frequency

(Hz)

Resolution with

5 V Reference

(Bits)

Settling

Time¹

Noise

(µV rms)

Noise

(µV p-p)²

Channels Enabled¹

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

50,000

41,667

31,250

27,778

20,833

17,857

12,500

10,000

5000

20 µs

250,000

125,000

62,500

50,000

31,250

25,000

15,625

11,905

5435

9.8

20

85

16.8

17.2

17.5

17.6

18.0

18.2

18.6

18.7

19.3

19.9

20.7

21.3

21.4

22.1

22.5

23

24 µs

8.4

20.2

20.6

20.7

21

66

32 µs

6.4

55

36 µs

5.9

49

48 µs

4.8

39

56 µs

4.3

21.1

21.5

21.7

22.2

22.7

23.4

23.8

24

33

80 µs

3.4

26

100 µs

200 µs

400 µs

1.0 ms

2.0 ms

2.516 ms

5.0 ms

10 ms

16.67 ms

3

23

2.1

16

2500

2604

1.5

10

1000

1016

0.92

0.68

0.6

5.7

3.9

3.7

2.2

1.7

1.2

1

500.0

397.5

200.0

100

504

397.5

200

400.00

200.64

100.16

59.98

0.43

0.32

0.23

0.2

24

100

24

59.92

49.96

20

59.92

49.96

20.00

16.66

10.00

5.00

24

20.016 ms 50.00

24

23.3

23.7

23.9

24

50.0 ms

60.02 ms

100 ms

200 ms

20.01

16.66

10.00

5.00

0.14

0.13

0.1

24

0.75

0.66

0.47

0.32

16.66

10

24

5

0.07

24

¹The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²1000 samples.

Rev. B | Page 33 of 62

AD7175-2

Data Sheet

Table 21. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Disabled

Output Data Rate

(SPS/Channel);

SING_CYC = 1 or with

Multiple Channels

Enabled¹

Default Output

Data Rate (SPS);

SING_CYC = 0 and

Single Channel

Enabled¹

Effective

Peak-to-Peak

Resolution with

5 V Reference

(Bits)

Notch

Frequency

(Hz)

Resolution with

5 V Reference

(Bits)

Settling

Time¹

Noise

(µV rms)

Noise

(µV p-p)²

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

83,333

41,667

20,833

16,667

10,417

8333

5208

3333

1667

833

12 µs

24 µs

48 µs

60 µs

96 µs

120 µs

192 µs

300 µs

600 µs

1.2 ms

3 ms

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

210

28

15.5

18.4

20.9

21.2

21.6

21.7

22.1

22.4

22.9

23.4

24

1600

200

40

12.6

15.6

17.9

18.2

18.6

18.7

19.2

19.4

20

5.2

4.2

34

3.2

26

2.9

23

2.2

17

1.8

14

1.3

9.5

6

2500

0.91

0.56

0.44

0.4

20.7

21.3

21.9

22.1

22.8

23.3

23.6

23.8

24

333.3

166.7

133.3

66.7

1000

3.9

2.5

2.3

1.4

1

6 ms

500

24

400

7.5 ms

15 ms

30 ms

400

24

200

0.25

0.2

24

100

33.33

19.99

16.67

6.67

100

24

60

50.02 ms 59.98

0.13

0.08

0.07

0.06

0.05

24

0.8

0.7

0.42

0.37

0.28

0.21

50

60 ms

50

24

20

150 ms

180 ms

300 ms

600 ms

20

24

16.67

10

5.56

16.67

10

24

3.33

24

5

1.67

5

24

¹The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate =1 ÷ settling time.

²1000 samples.

Rev. B | Page 34 of 62

Data Sheet

AD7175-2

Table 22. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Enabled

Output Data Rate

(SPS/Channel);

SING_CYC = 1 or with

Multiple Channels

Enabled¹

Default Output

Data Rate (SPS);

SING_CYC = 0 and

Single Channel

Enabled¹

Effective

Peak-to-Peak

Resolution with

5 V Reference

(Bits)

Notch

Frequency

(Hz)

Resolution with

5 V Reference

(Bits)

Settling

Time¹

Noise

(µV rms)

Noise

(µV p-p)²

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

83,333

41,667

20,833

16,667

10,417

8333

5208

3333

1667

833

12 µs

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

210

28

15.5

18.4

20.7

21

1600

210

48

12.6

15.5

17.7

17.9

18.3

18.6

19.1

19.3

19.8

20.4

21.1

21.7

21.8

22.4

23

24 µs

48 µs

5.8

60 µs

4.9

41

96 µs

3.8

21.3

21.5

21.9

22.2

22.7

23.1

23.7

24

30

120 µs

192 µs

300 µs

600 µs

1.2 ms

3 ms

3.4

26

2.6

18

2.1

16

1.5

11

1.1

7

333.3

166.7

133.3

66.7

0.71

0.52

0.41

0.32

0.2

4.5

3

6 ms

400

7.5 ms

15 ms

30 ms

50.02ms

60 ms

150 ms

180 ms

300 ms

600 ms

400

24

2.7

1.8

1.2

1.1

0.83

0.61

0.6

0.55

0.35

200

24

100

33.33

19.99

16.67

6.67

100

24

60

59.98

50

0.17

0.15

0.13

0.12

0.1

24

23.1

23.5

24

50

24

20

24

16.67

10

5.56

16.67

10

24

3.33

24

5

1.67

5

0.08

24

¹The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate =1 ÷ settling time.

²1000 samples.

Rev. B | Page 35 of 62

AD7175-2

Data Sheet

sinc1 filter must be selected when using the enhanced filters to

achieve the specified settling time and noise performance. Table 23

shows the output data rates with the accompanying settling

time, rejection, and rms noise. Figure 62 to Figure 69 show the

frequency domain plots of the responses from the enhanced filters.

ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS

The enhanced filters are designed to provide rejection of 50 Hz

and 60 Hz simultaneously and to allow the user to trade off

settling time and rejection. These filters can operate up to

27.27 SPS or can reject up to 90 dB of 50 Hz 1 Hz and 60 Hz

1 Hz interference. These filters are realized by postfiltering

the output of the sinc5 + sinc1 filter. For this reason, the sinc5 +

Table 23. Enhanced Filters Output Data Rate, Noise, Settling Time, and Rejection Using the Enhanced Filters

Output Data Rate

(SPS)

Settling

Simultaneous Rejection of

Noise

Peak-to-Peak

Time (ms) 50 Hz 1 Hz and 60 Hz 1 Hz(dB)¹(µV rms) Resolution (Bits) Comments

Input Buffers Disabled

27.27

36.67

40.0

50.0

60.0

47

62

85

90

0.22

0.2

22.7

22.9

23

See Figure 62 and Figure 65

See Figure 63 and Figure 66

See Figure 64 and Figure 67

See Figure 68 and Figure 69

25

20

0.2

16.667

0.17

Input Buffers Enabled

27.27

25

36.67

40.0

50.0

60.0

47

62

85

90

0.22

0.21

22.7

22.8

See Figure 62 and Figure 65

See Figure 63 and Figure 66

See Figure 64 and Figure 67

See Figure 68 and Figure 69

20

16.667

¹Master clock = 16.00 MHz.

Rev. B | Page 36 of 62

Data Sheet

AD7175-2

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

70

0

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 65. 27.27 SPS ODR, 36.67 ms Settling Time

Figure 62. 27.27 SPS ODR, 36.67 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

100

200

300

400

500

FREQUENCY (Hz)

Figure 66. 25 SPS ODR, 40 ms Settling Time

Figure 63. 25 SPS ODR, 40 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

100

200

300

400

500

FREQUENCY (Hz)

Figure 67. 20 SPS ODR, 50 ms Settling Time

Figure 64. 20 SPS ODR, 50 ms Settling Time

Rev. B | Page 37 of 62

AD7175-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 68. 16.667 SPS ODR, 60 ms Settling Time

Figure 69. 16.667 SPS ODR, 60 ms Settling Time

Rev. B | Page 38 of 62

Data Sheet

AD7175-2

OPERATING MODES

The AD7175-2 has a number of operating modes that can be set

from the ADC mode register and interface mode register (see

Table 27 and Table 28). These modes are as follows and are

described in the following paragraphs:

When the data-word has been read from the data register, the

RDY

DOUT/

pin goes high. The user can read this register

additional times, if required. However, the user must ensure that

the data register is not being accessed at the completion of the

next conversion; otherwise, the new conversion word is lost.

x

Continuous conversion mode

Continuous read mode

Single conversion mode

Standby mode

When several channels are enabled, the ADC automatically

sequences through the enabled channels, performing one

conversion on each channel. When all channels have been

converted, the sequence starts again with the first channel. The

channels are converted in order from lowest enabled channel to

highest enabled channel. The data register is updated as soon as

Power-down mode

Calibration modes (three)

CONTINUOUS CONVERSION MODE

RDY

each conversion is available. The

output pulses low each

time a conversion is available. The user can then read the

conversion while the ADC converts the next enabled channel.

Continuous conversion is the default power-up mode. The

RDY

AD7175-2 converts continuously, and the

register goes low each time a conversion is complete. If

RDY

bit in the status

CS

is low,

output also goes low when a conversion is complete. To

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register, along with the conversion data,

are output each time the data register is read. The status register

indicates the channel to which the conversion corresponds.

the

read a conversion, the user writes to the communications

register, indicating that the next operation is a read of the data

register.

CS

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 70. Continuous Conversion Mode

Rev. B | Page 39 of 62

AD7175-2

Data Sheet

To enable continuous read mode, set the CONTREAD bit in the

interface mode register. When this bit is set, the only serial interface

operations possible are reads from the data register. To exit con-

tinuous read mode, issue a dummy read of the ADC data register

CONTINUOUS READ MODE

In continuous read mode, it is not required to write to the

communications register before reading ADC data; apply only

RDY

the required number of SCLKs after

goes low to indicate

RDY

command (0x44) while the

output is low. Alternatively, apply

CS

the end of a conversion. When the conversion is read,

a software reset, that is, 64 SCLKs with

= 0 and DIN = 1.

returns high until the next conversion is available. In this mode,

the data can be read only once. The user must also ensure that

the data-word is read before the next conversion is complete. If

the user has not read the conversion before the completion of

the next conversion or if insufficient serial clocks are applied to

the AD7175-2 to read the data word, the serial output register is

reset shortly before the next conversion is complete, and the

new conversion is placed in the output serial register. The ADC

must be configured for continuous conversion mode to use

continuous read mode.

This resets the ADC and all register contents. These are the only

commands that the interface recognizes after it is placed in

continuous read mode. Hold DIN low in continuous read mode

until an instruction is to be written to the device.

If multiple ADC channels are enabled, each channel is output

in turn, with the status bits being appended to the data if

DATA_STAT is set in the interface mode register. The status

register indicates the channel to which the conversion corresponds.

CS

0x02

0x0080

DIN

DATA

DOUT/RDY

SCLK

Figure 71. Continuous Read Mode

Rev. B | Page 40 of 62

Data Sheet

AD7175-2

RDY

As soon as the conversion is available, the

output goes low.

SINGLE CONVERSION MODE

The ADC then selects the next channel and begins a conversion.

The user can read the present conversion while the next

conversion is being performed. As soon as the next conversion is

complete, the data register is updated; therefore, the user has a

limited period in which to read the conversion. When the ADC

has performed a single conversion on each of the selected

channels, it returns to standby mode.

In single conversion mode, the AD7175-2 performs a single

conversion and is placed in standby mode after the conversion

RDY

is complete. The

of a conversion. When the data-word has been read from the

RDY

output goes low to indicate the completion

data register, DOUT/

pin goes high. The data register can

RDY

be read several times, if required, even when DOUT/

pin has

gone high.

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register, along with the conversion, are

output each time the data register is read. The two LSBs of the

status register indicate the channel to which the conversion

corresponds.

If several channels are enabled, the ADC automatically

sequences through the enabled channels and performs a

conversion on each channel. When a conversion is started, the

RDY

DOUT/

pin goes high and remains high until a valid

CS

conversion is available and is low.

CS

0x01

0x8010

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 72. Single Conversion Mode

Rev. B | Page 41 of 62

AD7175-2

Data Sheet

STANDBY AND POWER-DOWN MODES

ª

«

º

0.75uV_IN

Gain

»

Data

u2 ²³ꢀ( Offset ꢀ 0x800000) u

ꢁ 0x800000

In standby mode, most blocks are powered down. The LDOs

remain active so that registers maintain their contents. The

internal reference remains active if enabled, and the crystal

oscillator remains active if selected. To power down the

reference in standby mode, set the REF_EN bit in the ADC

mode regsiter to 0. To power down the clock in standby mode,

set the CLOCKSEL bits in the ADC mode register to 00

(internal oscillator).

«

»

V_REF

0x 400000

¬

¼

To start a calibration, write the relevant value to the mode bits

RDY RDY

in the ADC mode register. The DOUT/

pin and the

bit in the status register go high when the calibration initiates.

When the calibration is complete, the contents of the corre-

RDY

sponding offset or gain register are updated, the

bit in the

CS

output pin returns low (if

RDY

status register is reset and the

is low), and the AD7175-2 reverts to standby mode.

In power-down mode, all blocks are powered down, including

the LDOs. All registers lose their contents, and the GPIO outputs

are placed in three-state. To prevent accidental entry to power-

down mode, the ADC must first be placed in standby mode.

During an internal offset calibration, the selected positive analog

input pin is disconnected, and both modulator inputs are

connected internally to the selected negative analog input pin.

For this reason, it is necessary to ensure that the voltage on the

selected negative analog input pin does not exceed the allowed

limits and is free from excessive noise and interference.

CS

Exiting power-down mode requires 64 SCLKs with

= 0 and

DIN = 1, that is, a serial interface reset. A delay of 500 µs is

recommended before issuing a subsequent serial interface

command to allow the LDO to power up.

System calibrations, however, expect the system zero-scale

(offset) and system full-scale (gain) voltages to be applied to the

ADC pins before initiating the calibration modes. As a result,

errors external to the ADC are removed.

Figure 19 shows the internal reference settling time after

returning from standby mode (setting REF_EN = 0 and then 1)

and returning from power down.

From an operational point of view, treat a calibration like

another ADC conversion. An offset calibration, if required,

must always be performed before a full-scale calibration. Set the

CALIBRATION

The AD7175-2 allows a two-point calibration to be performed

to eliminate any offset and gain errors. Three calibration modes

eliminate these offset and gain errors on a per setup basis:

RDY

system software to monitor the

bit in the status register or

output to determine the end of a calibration via a

RDY

the

x

Internal zero-scale calibration mode

System zero-scale calibration mode

System full-scale calibration mode

polling sequence or an interrupt-driven routine. All calibrations

require a time equal to the settling time of the selected filter and

output data rate to be completed.

There is no internal full-scale calibration mode bcause this is

calibrated in the factory at the time of production.

An internal offset calibration, system zero-scale calibration, and

system full-scale calibration can be performed at any output data

rate. Using lower output data rates results in better calibration

accuracy and is accurate for all output data rates. A new offset

calibration is required for a given channel if the reference source

for that channel is changed.

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

The default value of the offset register is 0x800000, and the

nominal value of the gain register is 0x555555. The calibration

range of the ADC gain is from 0.4 × V_REFto 1.05 × V_REF. The

following equations show the calculations that are used. In

unipolar mode, the ideal relationship—that is, not taking into

account the ADC gain error and offset error—is as follows:

The offset error is typically 40 µV and an offset calibration

reduces the offset error to the order of the noise. The gain error

is factory calibrated at ambient temperature. Following this

calibration, the gain error is typically 35 ppm of FSR.

The AD7175-2 provides the user with access to the on-chip

calibration registers, allowing the microprocessor to read the

calibration coefficients of the device and to write a calibration

coefficients. A read or write of the offset and gain registers can be

performed at any time except during an internal or self calibration.

ª

«

º

0.75uV _IN

Gain

»

Data

u 2 ²³ꢀ (Offset ꢀ 0x800000 ) u

u 2

«

»

V _REF

0x 400000

¬

¼

In bipolar mode, the ideal relationship—that is, not taking into

account the ADC gain error and offset error—is as follows:

Rev. B | Page 42 of 62

Data Sheet

AD7175-2

DIGITAL INTERFACE

The programmable functions of the AD7175-2 are controlled via

the SPI serial interface. The serial interface of the AD7175-2

For CRC checksum calculations during a write operation, the

following polynomial is always used:

CS

consists of four signals: , DIN, SCLK, and DOUT/

RDY

. The

x⁸+ x²+ x + 1

DIN input transfers data into the on-chip registers, and DOUT

output accesses data from the on-chip registers. SCLK is the serial

clock input for the device, and all data transfers (either on DIN

input or on DOUT output) occur with respect to the SCLK

signal.

During read operations, the user can select between this

polynomial and a simpler XOR function. The XOR function

requires less time to process on the host microcontroller than

the polynomial-based checksum. The CRC_EN bits in the

interface mode register enable and disable the checksum and

allow the user to select between the polynomial check and the

simple XOR check.

RDY

The DOUT/

the output going low if

available in the data register. The

a read operation from the data register is complete. The

pin also functions as a data ready signal, with

CS

is low when a new data-word is

RDY

output is reset high when

RDY

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8-bit to

24-bit data. For a read transaction, the checksum is calculated

using the command word and the 8-bit to 32-bit data output.

Figure 73 and Figure 74 show SPI write and read transactions,

respectively.

output also goes high before updating the data register to

indicate when not to read from the device to ensure that a data

read is not attempted while the register is being updated. Take

RDY

care to avoid reading from the data register when the

output is about to go low. The best method to ensure that no data

RDY

read occurs is to always monitor the

output; start reading

output goes low; and

ensure a sufficient SCLK rate, such that the read is completed

8-BIT COMMAND

UP TO 24-BIT INPUT

8-BIT CRC

RDY

the data register as soon as the

CS

before the next conversion result. selects a device. It can decode

CS

DATA

CRC

DIN

the AD7175-2 in systems where several components are

connected to the serial bus.

SCLK

Figure 2 and Figure 3 show timing diagrams for interfacing to

CS

the AD7175-2 using

to decode the device. Figure 2 shows

Figure 73. SPI Write Transaction with CRC

the timing for a read operation from the AD7175-2, and Figure 3

shows the timing for a write operation to the AD7175-2. It is

possible to read from the data register several times even though

8-BIT COMMAND

UP TO 32-BIT INPUT

8-BIT CRC

CS

RDY

the

output returns high after the first read operation.

However, care must be taken to ensure that the read operations are

completed before the next output update occurs. In continuous

read mode, the data register can be read only once.

CMD

DIN

DOUT/

RDY

DATA

CRC

CS

The serial interface can operate in 3-wire mode by tying

low.

RDY

In this case, the SCLK, DIN, and DOUT/

with the AD7175-2. The end of the conversion can also be

RDY

pins communicate

SCLK

monitored using the

bit in the status register.

Figure 74. SPI Read Transaction with CRC

CS

The AD7175-2 can be reset by writing 64 SCLKs with

= 0

and DIN = 1. A reset returns the interface to the state in which it

expects a write to the communications register. This operation

resets the contents of all registers to their power-on values.

Following a reset, allow a period of 500 µs before addressing the

serial interface.

If checksum protection is enabled when continuous read mode

is active, an implied read data command of 0x44 before every

data transmission must be accounted for when calculating the

checksum value. This implied read data command ensures a

nonzero checksum value even if the ADC data equals 0x000000.

CHECKSUM PROTECTION

The AD7175-2 has a checksum mode that can improve

interface robustness. Using the checksum ensures that only

valid data is written to a register and allows data read from a

register to be validated. If an error occurs during a register

write, the CRC_ERROR bit is set in the status register. However,

to ensure that the register write was successful, read back the

register and verify the checksum.

Rev. B | Page 43 of 62

AD7175-2

Data Sheet

An XOR (exclusive OR) function is applied to the data to

CRC CALCULATION

produce a new, shorter number. The polynomial is again aligned

so that the MSB is adjacent to the leftmost Logic 1 of the new result,

and the procedure is repeated. This process repeats until the

original data is reduced to a value less than the polynomial.

This is the 8-bit checksum.

Polynomial

The checksum, which is eight bits wide, is generated using the

polynomial

x⁸+ x²+ x + 1

To generate the checksum, the data is left shifted by eight bits to

create a number ending in eight Logic 0s. The polynomial is

aligned so that the MSB is adjacent to the leftmost Logic 1 of the

data.

Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)

An example of generating the 8-bit checksum using the polynomial based checksum is as follows:

Initial value

011001010100001100100001

01100101010000110010000100000000

left shifted eight bits

polynomial

x⁸+ x²+ x + 1

=

100000111

100100100000110010000100000000

100000111

XOR result

polynomial

XOR result

polynomial

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

checksum = 0x86

100011000110010000100000000

100000111

11111110010000100000000

100000111

1111101110000100000000

100000111

111100000000100000000

100000111

11100111000100000000

100000111

1100100100100000000

100000111

100101010100000000

100000111

101101100000000

100000111

1101011000000

100000111

101010110000

100000111

1010001000

100000111

10000110

Rev. B | Page 44 of 62

Data Sheet

AD7175-2

XOR Calculation

The checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes.

Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)

Using the previous example, divide into three bytes: 0x65, 0x43, and 0x21

01100101

01000011

00100110

00100001

00000111

0x65

0x43

XOR result

0x21

CRC

Rev. B | Page 45 of 62

AD7175-2

Data Sheet

INTEGRATED FUNCTIONS

The AD7175-2 has integrated functions that improve the

usefulness of a number of applications as well as serve

diagnostic purposes in safety conscious applications.

The effect on the noise performance depends on the delay time

compared to the conversion time. It is possible to absorb the delay

only for output data rates less than 10 kSPS with the exception

of the following four rates, which cannot absorb any delay:

397.5 SPS, 59.92 SPS, 49.96 SPS, and 16.66 SPS.

GENERAL-PURPOSE INPUT/OUTPUT

The AD7175-2 has two general-purpose digital input/output pins:

GPIO0 and GPIO1. They are enabled using the IP_EN0/IP_EN1

bits or the OP_EN0/OP_EN1 bits in the GPIOCON register. When

the GPIO0 or GPIO1 pin is enabled as an input, the logic level at

the pin is contained in the GP_DATA0 or GP_DATA1 bit,

respectively. When the GPIO0 or GPIO1 pin is enabled as an

output, the GP_ DATA0 or GP_DATA1 bits, respectively,

determine the logic level output at the pin. The logic levels for

these pins are referenced to AVDD1 and AVSS; therefore, outputs

have an amplitude of 5 V.

16-BIT/24-BIT CONVERSIONS

By default, the AD7175-2 generates 24-bit conversions.

However, the width of the conversions can be reduced to 16 bits.

Setting the WL16 bit in the interface mode register to 1 rounds

all data conversions to 16 bits. Clearing this bit sets the width of

the data conversions to 24 bits.

DOUT_RESET

RDY

The serial interface uses a shared DOUT/

pin. By default,

signal. During a data read, this pin

outputs the data from the register being read. After the read is

RDY

this pin outputs the

SYNC ERROR

pin can also be used as a general-purpose

The

output. When ERR_EN bits in the GPIOCON register are set to

SYNC ERROR

pin operates as a general-purpose output.

/

complete, the pin reverts to outputting the

signal after a

11, the

/

short fixed period of time (t₇). However, this time may be too

short for some microcontrollers and can be extended until the

In this configuration, the ERR_DAT bit in the GPIOCON register

determines the logic level output at the pin. The logic level for the

pin is referenced to IOVDD and DGND.

CS

pin is brought high by setting the DOUT_RESET bit in the

CS

interface mode register to 1. This means that

must frame

SYNC ERROR

pin, when set as general-

Both GPIOs and the

/

each read operation and compete the serial interface transaction.

purpose outputs, have an active pull-up.

SYNCHRONIZATION

EXTERNAL MULTIPLEXER CONTROL

Normal Synchronization

If an external multiplexer increases the channel count, the

multiplexer logic pins can be controlled via the AD7175-2

GPIOx pins. With the MUX_IO bit, the GPIOx timing is

controlled by the ADC; therefore, the channel change is

synchronized with the ADC, eliminating any need for external

synchronization.

When the SYNC_EN bit in the GPIOCON register is set to 1,

SYNC ERROR

/

the

pin functions as a synchronization input.

SYNC

The

input lets the user reset the modulator and the

digital filter without affecting any of the setup conditions on the

device. This feature lets the user start to gather samples of the

SYNC

analog input from a known point, the rising edge of the

SYNC

DELAY

input. The

input must be low for at least one master

It is possible to insert a programmable delay before the AD7175-2

begins to take samples. This delay allows an external amplifier

or multiplexer to settle and can also alleviate the specification

requirements for the external amplifier or multiplexer. Eight

programmable settings, ranging from 0 µs to 1 ms, can be set

using the delay bits in the ADC mode register (Register 0x01,

Bits[10:8]).

clock cycle to ensure that synchronization occurs.

If multiple AD7175-2 devices are operated from a common

master clock, they can be synchronized so that their analog

inputs are sampled simultaneously. This synchronization is

normally done after each AD7175-2 device performs a calibration

or has calibration coefficients loaded into the calibration registers.

SYNC

A falling edge on the

analog modulator and places the AD7175-2 into a consistent

SYNC

input resets the digital filter and the

If a delay greater than 0 µs is selected and the HIDE_DELAY bit

in the ADC mode register is set to 0, this delay is added to the

conversion time, regardless of selected output data rate.

known state. While the

input is low, the AD7175-2 is

SYNC

maintained in this known state. On the

input rising edge,

the modulator and filter are taken out of this reset state, and on

the next master clock edge, the device starts to gather input

samples again.

When using the sinc5 + sinc1 filter, it is possible to hide this

delay such that the output data rate remains the same as the output

data rate without the delay enabled. If the HIDE_DELAY bit is

set to 1 and the selected delay is less than half of the conversion

time, the delay can be absorbed by reducing the number of

averages the digital filter performs, which keeps the conversion

time the same but can affect the noise performance.

Rev. B | Page 46 of 62

Data Sheet

AD7175-2

The device is taken out of reset on the master clock falling edge

CRC_ERROR

SYNC

following the

input low to high transition. Therefore,

SYNC

If the CRC value that accompanies a write operation does not

correspond with the information sent, the CRC_ERROR flag is

set. The flag is reset as soon as the status register is explicitly read.

when multiple devices are being synchronized, take the

input high on the master clock rising edge to ensure that all

devices are released on the master clock falling edge. If the

REG_ERROR

SYNC

input is not taken high in sufficient time, a difference of

The RE_ERROR flag is used in conjunction with the

one master clock cycle between the devices is possible; that is,

the instant at which conversions are available differs from

device to device by a maximum of one master clock cycle.

REG_CHECK bit in the interface mode register. When the

REG_CHECK bit is set, the AD7175-2 monitors the values in

the on-chip registers. If a bit changes, the REG_ERROR bit is

set. Therefore, for writes to the on-chip registers, set REG_CHECK

to 0. When the registers have been updated, the REG_CHECK

bit can be set to 1. The AD7175-2 calculates a checksum of the

on-chip registers. If one of the register values has changed, the

REG_ERROR bit is set. If an error is flagged, the REG_CHECK

bit must be set to 0 to clear the REG_ERROR bit in the status

register. The register check function does not monitor the data

register, status register, or interface mode register.

SYNC

The

input can also be used as a start conversion

command for a single channel when in normal synchronization

SYNC

mode. In this mode, the rising edge of

input starts a

RDY

conversion, and the falling edge of the

output indicates when

the conversion is complete. The settling time of the filter is

required for each data register update. After the conversion is

SYNC

complete, bring the

input low in preparation for the next

conversion start signal.

ERROR

Alternate Synchronization

Input/Output

When the SYNC_EN bit in the GPIOCON register is set to 0,

SYNC ERROR

pin functions as an error input/output pin or

SYNC

In alternate synchronization mode, the

input operates as

a start conversion command when several channels of the

AD7175-2 are enabled. Setting the ALT_SYNC bit in the interface

mode register to 1 enables an alternate synchronization scheme.

the

/

a general-purpose output pin. The ERR_EN bits in the GPIOCON

register determine the function of the pin.

SYNC

When the

input is taken low, the ADC completes the

SYNC ERROR

/

With ERR_EN is set to 10,the

pin functions as

conversion on the current channel, selects the next channel in

ERROR

an open-drain error output,

. The three error bits in the

SYNC

the sequence, and then waits until the

to commence the conversion. The

input is taken high

status register (ADC_ERROR, CRC_ERROR, and REG_ERROR)

ERROR

RDY

output goes low when

are OR’ed, inverted, and mapped to the

output. Therefore,

output indicates that an error has occurred. The

status register must be read to identify the error source.

SYNC ERROR

the conversion is complete on the current channel, and the data

register is updated with the corresponding conversion.

ERROR

the

SYNC

Therefore, the

input does not interfere with the sampling

When ERR_EN is set to 01, the

/

pin functions as

. The error output of another component

ERROR

on the currently selected channel but allows the user to control

the instant at which the conversion begins on the next channel

in the sequence.

ERROR

an error input,

can be connected to the AD7175-2

AD7175-2 indicates when an error occurs on either itself or the

ERROR

input so that the

Alternate synchronization mode can be used only when several

channels are enabled. It is not recommended to use this mode

when a single channel is enabled.

external component. The value on the

input is inverted

and OR’ed with the errors from the ADC conversion, and the

result is indicated via the ADC_ERROR bit in the status register.

ERROR FLAGS

ERROR

The value of the

input is reflected in the ERR_DAT bit

The status register contains three error bits—ADC_ERROR,

CRC_ERROR, and REG_ERROR—that flag errors with the

ADC conversion, errors with the CRC check, and errors caused

in the status register.

ERROR

The

input/output is disabled when ERR_EN is set to 00.

SYNC ERROR

When the ERR_EN bits are set to 11, the

operates as a general-purpose output.

/

ERROR

by changes in the registers, respectively. In addition, the

output can indicate that an error has occurred.

DATA_STAT

ADC_ERROR

The contents of the status register can be appended to each con-

version on the AD7175-2. This function is useful if several

channels are enabled. Each time a conversion is output, the

contents of the status register are appended. The two LSBs of

the status register indicate to which channel the conversion

corresponds. In addition, the user can determine if any errors

are being flagged by the error bits.

The ADC_ERROR bit in the status register flags any errors that

occur during the conversion process. The flag is set when an over-

range or underrange result is output from the ADC. The ADC

also outputs all 0s or all 1s when an undervoltage or overvoltage

occurs. This flag is reset only when the overvoltage or undervoltage

is removed. It is not reset by a read of the data register.

Rev. B | Page 47 of 62

AD7175-2

Data Sheet

The temperature sensor requires the analog input buffers be

enabled on both analog inputs. It is recommend that the input

buffers are enabled, but this is not necessary for the

measurement.

IOSTRENGTH

The serial interface can operate with a power supply as low as

RDY

2 V. However, at this low voltage, the DOUT/

pin may not

have sufficient drive strength if there is moderate parasitic

capacitance on the board or the SCLK frequency is high. The

IOSTRENGTH bit in the interface mode register increases the

To use the temperature sensor, the first step is to calibrate the

device in a known temperature (25°C) and take a conversion as

a reference point. The temperature sensor has a nominal

sensitivity of 470 µV/K; the difference in this ideal slope and the

slope measured can calibrate the temperature sensor. The

temperature sensor is specified with a 2°C typical accuracy

after calibration at 25°C. The temperature can be calculated as

follows:

RDY

drive strength of the DOUT/

pin.

INTERNAL TEMPERATURE SENSOR

The AD7175-2 has an integrated temperature sensor. The

temperature sensor can be used as a guide for the ambient

temperature at which the part is operating. This can be used for

diagnostic purposes or as an indicator of when the application

circuit must rerun a calibration routine to take into account a

shift in operating temperature. The temperature sensor is

selected using the crosspoint multiplexer and is selected the

same as an analog input channel.

§

¨

©

·

¸

¹

Conversion Result

Temperature(qC )

– 273.15

477 ȝ9

Rev. B | Page 48 of 62

Data Sheet

AD7175-2

GROUNDING AND LAYOUT

The analog inputs and reference inputs are differential and,

therefore, most of the voltages in the analog modulator are

common-mode voltages. The high common-mode rejection of

the device removes common-mode noise on these inputs. The

analog and digital supplies to the AD7175-2 are independent

and connected to separate pins to minimize coupling between the

analog and digital sections of the device. The digital filter provides

rejection of broadband noise on the power supplies, except at

integer multiples of the master clock frequency.

possible to provide low impedance paths and reduce glitches on

the power supply line. Shield fast switching signals like clocks

with digital ground to prevent radiating noise to other sections

of the board and never run clock signals near the analog inputs.

Avoid crossover of digital and analog signals. Run traces on

opposite sides of the board at right angles to each other. This

technique reduces the effects of feed through on the board. A

microstrip technique is by far the best but is not always possible

with a double-sided board.

The digital filter also removes noise from the analog and

reference inputs, provided that these noise sources do not

saturate the analog modulator. As a result, the AD7175-2 is

more immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD7175-2 is high and the noise levels from the converter are so

low, take care with regard to grounding and layout.

Good decoupling is important when using high resolution ADCs.

The AD7175-2 has three power supply pins—AVDD1, AVDD2,

and IOVDD. The AVDD1 and AVDD2 pins are referenced to

AVSS, and the IOVDD pin is referenced to DGND. Decouple

AVDD1 and AVDD2 with a 10 µF capacitor in parallel with a

0.1 µF capacitor to AVSS on each pin. Place the 0.1 µF capacitor

as close as possible to the device on each supply, ideally right up

against the device. Decouple IOVDD with a 10 µF capacitor in

parallel with a 0.1 µF capacitor to DGND. Decouple all analog

inputs to AVSS. If an external reference is used, decouple the

REF+ and REF− pins to AVSS.

The PCB that houses the ADC must be designed such that the

analog and digital sections are separated and confined to

certain areas of the board. A minimum etch technique is

generally best for ground planes because it results in the best

shielding.

The AD7175-2 also has two on-board LDO regulators—one

that regulates the AVDD2 supply and one that regulates the

IOVDD supply. For the REGCAPA pin, it is recommended that

1 µF and 0.1 µF capacitors to AVSS be used. Similarly, for the

REGCAPD pin, it is recommended that 1 µF and 0.1 µF

capacitors to DGND be used.

In any layout, the user must consider the flow of currents in the

system, ensuring that the paths for all return currents are as close as

possible to the paths the currents took to reach their destinations.

Avoid running digital lines under the device because this

couples noise onto the die and allow the analog ground plane to

run under the AD7175-2 to prevent noise coupling. The power

supply lines to the AD7175-2 must use as wide a trace as

If using the AD7175-2 for split supply operation, a separate

plane must be used for AVSS.

Rev. B | Page 49 of 62

AD7175-2

Data Sheet

REGISTER SUMMARY

Table 24. Register Summary

Reg. Name

0x00 COMMS

0x00 STATUS

Bits

[7:0]

Bit 7

WEN

RDY

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

RA

Bit 1

Bit 0

Reset

0x00

0x80

RW

W

R/

ADC_ERROR

HIDE_DELAY

CRC_ERROR

REG_ERROR

RESERVED

CHANNEL

R

0x01 ADCMODE

[15:8]

[7:0]

REF_EN

SING_CYC

MODE

RESERVED

DELAY

RESERVED

0x8000

RW

R

RESERVED

CLOCKSEL

0x02 IFMODE

[15:8]

[7:0]

RESERVED

ALT_SYNC

REG_CHECK RESERVED

REGISTER_CHECK[23:16]

IOSTRENGTH

RESERVED

DOUT_RESET 0x0000

WL16

CONTREAD

DATA_STAT

CRC_EN

RESERVED

0x03 REGCHECK

[23:16]

[15:8]

[7:0]

0x000000

REGISTER_CHECK[15:8]

REGISTER_CHECK[7:0]

DATA[23:16]

0x04 DATA

[23:16]

[15:8]

[7:0]

0x000000

R

DATA[15:8]

DATA[7:0]

0x06 GPIOCON

0x07 ID

[15:8]

[7:0]

RESERVED

MUX_IO

SYNC_EN

OP_EN1

ERR_EN

GP_DATA1

ERR_DAT

0x0800

0x0CDX

0x8001

0x0001

RW

R

RESERVED

IP_EN1

IP_EN0

OP_EN0

GP_DATA0

[15:8]

[7:0]

ID[15:8]

ID[7:0]

0x10 CH0

[15:8]

[7:0]

CH_EN0

CH_EN1

CH_EN2

CH_EN3

RESERVED

AINPOS0[2:0]

RESERVED

AINPOS1[2:0]

RESERVED

AINPOS2[2:0]

RESERVED

AINPOS3[2:0]

RESERVED

SETUP_SEL0

SETUP_SEL1

SETUP_SEL2

SETUP_SEL3

RESERVED

AINNEG0

RESERVED

AINNEG1

RESERVED

AINNEG2

RESERVED

AINNEG3

REFBUF0-

RESERVED

REFBUF1− AINBUF1+

RESERVED

REFBUF2− AINBUF2+

RESERVED

REFBUF3− AINBUF3+

RESERVED

ENHFILT0

AINPOS0[4:3]

RW

0x11 CH1

[15:8]

[7:0]

AINPOS1[4:3]

AINPOS2[4:3]

AINPOS3[4:3]

0x12 CH2

[15:8]

[7:0]

0x13 CH3

[15:8]

[7:0]

0x20 SETUPCON0

0x21 SETUPCON1

0x22 SETUPCON2

0x23 SETUPCON3

0x28 FILTCON0

0x29 FILTCON1

0x2A FILTCON2

0x2B FILTCON3

[15:8]

[7:0]

BI_UNIPOLAR0

REF_SEL0

BI_UNIPOLAR1

REF_SEL1

BI_UNIPOLAR2

REF_SEL2

BI_UNIPOLAR3

REF_SEL3

RESERVED

REFBUF0+

REFBUF1+

REFBUF2+

REFBUF3+

AINBUF0+

AINBUF0− 0x1320

AINBUF1− 0x1320

AINBUF2− 0x1320

AINBUF3− 0x1320

0x0500

BURNOUT_EN0

BURNOUT_EN1

BURNOUT_EN2

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

BURNOUT_EN3

SINC3_MAP0

RESERVED

[15:8]

[7:0]

ENHFILTEN0

ENHFILTEN1

ENHFILTEN2

ENHFILTEN3

ORDER0

ODR0

ODR1

ODR2

ODR3

[15:8]

[7:0]

SINC3_MAP1

RESERVED

ENHFILT1

ENHFILT2

ENHFILT3

0x0500

ORDER1

ORDER2

ORDER3

[15:8]

[7:0]

SINC3_MAP2

RESERVED

0x0500

[15:8]

[7:0]

SINC3_MAP3

RESERVED

0x0500

0x30 OFFSET0

0x31 OFFSET1

0x32 OFFSET2

0x33 OFFSET3

0x38 GAIN0

0x39 GAIN1

0x3A GAIN2

0x3B GAIN3

[23:0]

OFFSET0[23:0]

0x800000 RW

0x5XXXX0 RW

OFFSET1[23:0]

OFFSET2[23:0]

OFFSET3[23:0]

GAIN0[23:0]

GAIN1[23:0]

GAIN2[23:0]

GAIN3[23:0]

Rev. B | Page 50 of 62

Data Sheet

AD7175-2

REGISTER DETAILS

COMMUNICATIONS REGISTER

Address: 0x00, Reset: 0x00, Name: COMMS

All access to the on-chip registers must start with a write to the communications register. This write determines what register is next

accessed and whether that operation is a write or a read.

Table 25. Bit Descriptions for COMMS

Bits

7

Bit Name

WEN

Settings

Description

Reset

0x0

Access

W

This bit must be low to begin communications with the ADC.

6

R/W

This bit determines if the command is a read or write operation.

0x0

W

0

1

Write command.

Read command.

[5:0]

RA

The register address bits determine which register is to be read from or

written to as part of the current communication.

0x00

W

000000 Status register.

000001 ADC mode register.

000010 Interface mode register.

000011 Register checksum register.

000100 Data register.

000110 GPIO configuration register.

000111 ID register.

010000 Channel 0 register.

010001 Channel 1 register.

010010 Channel 2 register.

010011 Channel 3 register.

100000 Setup Configuration 0 register.

100001 Setup Configuration 1 register.

100010 Setup Configuration 2 register.

100011 Setup Configuration 3 register.

101000 Filter Configuration 0 register.

101001 Filter Configuration 1 register.

101010 Filter Configuration 2 register.

101011 Filter Configuration 3 register.

110000 Offset 0 register.

110001 Offset 1 register.

110010 Offset 2 register.

110011 Offset 3 register.

111000 Gain 0 register.

111001 Gain 1 register.

111010 Gain 2 register.

111011 Gain 3 register.

Rev. B | Page 51 of 62

AD7175-2

Data Sheet

STATUS REGISTER

Address: 0x00, Reset: 0x80, Name: STATUS

The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data

register by setting the DATA_STAT bit in the interface mode register.

Table 26. Bit Descriptions for STATUS

Bits

Bit Name

Settings

Description

Reset

Access

7

RDY

The status of RDY is output to the DOUT/RDYpin whenever CS is low and a 0x1

register is not being read. This bit goes low when the ADC has written a

new result to the data register. In ADC calibration modes, this bit goes low

when the ADC has written the calibration result. RDY is brought high

automatically by a read of the data register.

R

0

1

New data result available.

Awaiting new data result.

6

ADC_ERROR

This bit by default indicates if an ADC overrange or underrange has

occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and

0x000000 for underrange errors. This bit is updated when the ADC result is

written and is cleared at the next update after removing the overrange or

underrange condition.

0x0

R

0

1

No error.

Error.

5

4

CRC_ERROR

REG_ERROR

This bit indicates if a CRC error has taken place during a register write. For

register reads, the host microcontroller determines if a CRC error has

occurred. This bit is cleared by a read of this register.

0x0

R

0

1

No error.

CRC error.

This bit indicates if the content of one of the internal registers has

changed from the value calculated when the register integrity check was

activated. The check is activated by setting the REG_CHECK bit in the

interface mode register. This bit is cleared by clearing the REG_CHECK bit.

0

1

No error.

Error.

[3:2]

[1:0]

RESERVED

CHANNEL

These bits are reserved.

0x0

R

These bits indicate which channel was active for the ADC conversion

whose result is currently in the data register. This may be different from

the channel currently being converted. The mapping is a direct map from

the channel register; therefore, Channel 0 results in 0x0 and Channel 3

results in 0x3.

00 Channel 0.

01 Channel 1.

10 Channel 2.

11 Channel 3.

Rev. B | Page 52 of 62

Data Sheet

AD7175-2

ADC MODE REGISTER

Address: 0x01, Reset: 0x8000, Name: ADCMODE

The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets

the filter and the bits and starts a new conversion or calibration.

RDY

Table 27. Bit Descriptions for ADCMODE

Bits

Bit Name

Settings

Description

Reset

Access

15

REF_EN

Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. 0x1

RW

0

1

Disabled.

Enabled.

14

13

HIDE_DELAY

SING_CYC

If a programmable delay has been set using the DELAY bits, this bit allows

the delay to be hidden by absorbing the delay into the conversion time

for selected data rates with the sinc5 + sinc1 filter. See the Delay section

for more information.

0x0

RW

0

1

Enabled.

Disabled.

This bit can be used when only a single channel is active to set the ADC to 0x0

only output at the settled filter data rate.

0

1

Disabled.

Enabled.

[12:11] RESERVED

These bits are reserved; set these bits to 0.

0x0

R

[10:8]

DELAY

These bits allow a programmable delay to be added after a channel switch 0x0

to allow settling of external circuitry before the ADC starts processing the

input.

RW

000 0 µs.

001 4 µs.

010 16 µs.

011 40 µs.

100 100 µs.

101 200 µs.

110 500 µs.

111 1 ms.

7

RESERVED

MODE

This bit is reserved; set this bit to 0.

0x0

R

[6:4]

These bits control the operating mode of the ADC. See the Operating

Modes section for more information.

RW

000 Continuous conversion mode.

001 Single conversion mode.

010 Standby mode.

011 Power-down mode.

100 Internal offset calibration.

110 System offset calibration.

111 System gain calibration.

[3:2]

[1:0]

CLOCKSEL

RESERVED

This bit selects the ADC clock source. Selecting internal oscillator also

enables the internal oscillator.

0x0

RW

00 Internal oscillator.

01 Internal oscillator output on XTAL2/CLKIO pin.

10 External clock input on XTAL2/CLKIO pin.

11 External crystal on XTAL1 and XTAL2/CLKIO pins.

These bits are reserved; set these bits to 0.

R

Rev. B | Page 53 of 62

AD7175-2

Data Sheet

INTERFACE MODE REGISTER

Address: 0x02, Reset: 0x0000, Name: IFMODE

The interface mode register configures various serial interface options.

Table 28. Bit Descriptions for IFMODE

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] RESERVED

These bits are reserved; set these bits to 0.

12

11

ALT_SYNC

This bit enables a different behavior of the SYNC/ERROR pin to allow the

use of SYNC/ERROR as a control for conversions when cycling channels

(see the description of the SYNC_EN bit in the GPIO Configuration Register

section for details).

0x0

RW

0

1

Disabled.

Enabled.

IOSTRENGTH

This bit controls the drive strength of the DOUT/RDY pin. Set this bit when 0x0

reading from the serial interface at high speed with a low IOVDD supply

and moderate capacitance.

RW

0

1

Disabled (default).

Enabled.

[10:9]

8

RESERVED

These bits are reserved; set these bits to 0.

0x0

R

DOUT_RESET

See DOUT_RESET section for more information.

RW

0

1

Disabled.

Enabled.

7

6

CONTREAD

DATA_STAT

This enables continuous read of the ADC data register. The ADC must be

configured in continuous conversion mode to use continuous read. For

more details, see the Operating Modes section.

0x0

RW

0

1

Disabled.

Enabled.

This enables the status register to be appended to the data register when

read so that channel and status information are transmitted with the data.

This is the only way to be sure that the channel bits read from the status

register correspond to the data in the data register.

0

1

Disabled.

Enabled.

5

REG_CHECK

This bit enables a register integrity checker, which can monitor any

change in the value of the user registers. To use this feature, configure all

other registers as desired, with this bit cleared.Then write to this register to set

the REG_CHECK bit to 1. If the contents of any of the registers change, the

REG_ERROR bit is set in the status register. To clear the error, set the

REG_CHECK bit to 0. Neither the interface mode register nor the ADC data

or status registers are included in the registers that are checked. If a

register must have a new value written, this bit must first be cleared;

otherwise, an error is flagged when the new register contents are written.

0x0

RW

0

1

Disabled.

Enabled.

4

RESERVED

CRC_EN

This bit is reserved; set this bit to 0.

0x0

R

[3:2]

Enables CRC protection of register reads/writes. CRC increases the

number of bytes in a serial interface transfer by one. See the CRC

Calculation section for more details.

0x00

RW

00 Disabled.

01 XOR checksum enabled for register read transactions; register writes still

use CRC with these bits set.

10 CRC checksum enabled for read and write transactions.

This bit is reserved; set this bit to 0.

1

RESERVED

0x0

R

Rev. B | Page 54 of 62

Data Sheet

AD7175-2

Bits

Bit Name

Settings

Description

Reset

0x0

Access

0

WL16

Changes the ADC data register to 16 bits. The ADC is not reset by a write

to the interface mode register; therefore, the ADC result is not rounded to

the correct word length immediately after writing to these bits. The first

new ADC result is correct.

RW

0

1

24-bit data.

16-bit data.

REGISTER CHECK

Address: 0x03, Reset: 0x000000, Name: REGCHECK

The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit

in the interface mode register must be set for this to operate; otherwise, the register reads 0.

Table 29. Bit Descriptions for REGCHECK

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

REGISTER_CHECK

This register contains the 24-bit checksum of user registers when the

REG_CHECK bit is set in the interface mode register.

0x000000

R

DATA REGISTER

Address: 0x04, Reset: 0x000000, Name: DATA

The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the

RDY RDY

output high if it had

BI_UNIPOLARx bit in the setup configuration registers. Reading the data register brings the

bit and the

output has been brought high, it is not possible to know

RDY

been low. The ADC result can be read multiple times; however, because the

if another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the

data register.

Table 30. Bit Descriptions for DATA

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

DATA

This register contains the ADC conversion result. If DATA_STAT is set in

the interface mode register, the status register is appended to this

register when read, making this a 32-bit register. If WL16 is set in the

interface mode register, this register is reduced to 16 bits.

0x000000

R

Rev. B | Page 55 of 62

AD7175-2

Data Sheet

GPIO CONFIGURATION REGISTER

Address: 0x06, Reset: 0x0800, Name: GPIOCON

The GPIO configuration register controls the general-purpose input/output pins of the ADC.

Table 31. Bit Descriptions for GPIOCON

Bits

Bit Name

Settings Description

These bits are reserved; set these bits to 0.

Reset

0x0

Access

R

[15:13] RESERVED

12

11

MUX_IO

This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1 in sync

with the internal channel sequencing. The analog input pins used for a channel

can still be selected on a per channel basis. Therefore, it is possible to have a

4-channel multiplexer in front of AIN0/AIN1 and another in front of AIN2/AIN3, giving a

total of eight differential channels with the AD7175-2. However, only four channels at a

time can be automatically sequenced. A delay can be inserted after switching an

external multiplexer (see the DELAY bits in the ADC Mode Register section).

0x0

RW

SYNC_EN

This bit enables the SYNC/ERROR pin as a sync input. When the pin is low, this

holds the ADC and filter in reset until SYNC/ERROR pin goes high. An alternative

operation of the SYNC/ERROR pin is available when the ALT_SYNC bit in the

interface mode register is set. This mode only works when multiple channels are

enabled. In this case, a low on the SYNC/ERROR pin does not immediately reset the

filter/modulator. Instead, if the SYNC/ERROR pin is low when the channel is due to

be switched, the modulator and filter are prevented from starting a new

conversion. Bringing SYNC/ERROR high begins the next conversion. This

alternative sync mode allows SYNC/ERROR to be used while cycling through channels.

0x1

RW

0

1

Disabled.

Enabled.

[10:9]

ERR_EN

These bits enable the SYNC/ERROR pin as an error input/output.

0x0

RW

00 Disabled.

01 SYNC/ERROR is an error input. The (inverted) readback state is OR'ed with other

error sources and is available in the ADC_ERROR bit in the status register. The SYNC/

ERROR pin state can also be read from the ERR_DAT bit in this register.

10 SYNC/ERROR is an open-drain error output. The status register error bits are OR'ed,

inverted, and mapped to the SYNC/ERROR pin. The SYNC/ERROR pins of multiple

devices can be wired together to a common pull-up resistor so that an error on

any device can be observed.

11 SYNC/ERROR is a general-purpose output. The status of the pin is controlled by the

ERR_DAT bit in this register. This output is referenced between IOVDD and DGND,

as opposed to the AVDD1 and AVSS levels used by the general-purpose input/

output pins. The SYNC/ERROR pin has an active pull-up in this case.

8

ERR_DAT

This bit determines the logic level at the SYNC/ERROR pin if the pin is enabled as a

general-purpose output. This bit reflects the readback status of the pin if the pin is

enabled as an input.

0x0

RW

[7:6]

5

RESERVED

IP_EN1

These bits are reserved; set these bits to 0.

0x0

R

This bit turns GPIO1 into an input. Inputs are referenced to AVDD1 or AVSS.

RW

0

1

Disabled.

Enabled.

4

3

2

IP_EN0

This bit turns GPIO0 into an input. Inputs are referenced to AVDD1 or AVSS.

0x0

RW

0

1

Disabled.

Enabled.

OP_EN1

OP_EN0

This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS. 0x0

0

1

Disabled.

Enabled.

This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS. 0x0

0

1

Disabled.

Enabled.

1

0

GP_DATA1

GP_DATA0

This bit is the readback or write data for GPIO1.

This bit is the readback or write data for GPIO0.

0x0

RW

Rev. B | Page 56 of 62

Data Sheet

AD7175-2

ID REGISTER

Address: 0x07, Reset: 0x0CDX, Name: ID

The ID register returns a 16-bit ID. For the AD7175-2, this must be 0x0CDX.

Table 32. Bit Descriptions for ID

Bits

Bit Name

Settings

Description

Reset

0x0CDX

Access

[15:0]

ID

The ID register returns a 16-bit ID code that is specific to the ADC.

R

0x0CDX AD7175-2.

CHANNEL REGISTER 0

Address: 0x10, Reset: 0x8001, Name: CH0

The channel registers are 16-bit registers that select which channels are currently active, which inputs are selected for each channel, and

which setup configures the ADC for that channel.

Table 33. Bit Descriptions for CH0

Bits

Bit Name

Settings

Description

Reset

Access

15

CH_EN0

This bit enables Channel 0. If more than one channel is enabled, the ADC

automatically sequences between them.

0x1

RW

0

1

Disabled.

Enabled (default).

14

RESERVED

This bit is reserved; set this bit to 0.

0x0

R

[13:12] SETUP_SEL0

These bits identify which of the four setups configure the ADC for this

channel. A setup comprises a set of four registers: setup configuration register,

filter configuration register, offset register, and gain register. All channels

can use the same setup, in which case the same 2-bit value must be written

to these bits on all active channels, or up to four channels can be

configured differently.

RW

00 Setup 0.

01 Setup 1.

10 Setup 2.

11 Setup 3.

[11:10] RESERVED

[9:5] AINPOS0

These bits are reserved; set these bits to 0.

0x0

R

These bits select which input is connected to the positive input of the

ADC for this channel.

RW

00000 AIN0 (default).

00001 AIN1.

00010 AIN2.

00011 AIN3.

00100 AIN4.

10001 Temperature sensor+.

10010 Temperature sensor−.

10011 ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled).

10100 ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled).

10101 REF+.

10110 REF−.

Rev. B | Page 57 of 62

AD7175-2

Data Sheet

Bits

Bit Name

AINNEG0

Settings

Description

Reset

Access

[4:0]

These bits select which input is connected to the negative input of the

ADC for this channel.

0x1

RW

00000 AIN0.

00001 AIN1 (default).

00010 AIN2.

00011 AIN3.

00100 AIN4.

10001 Temperature sensor+.

10010 Temperature sensor−.

10011 ((AVDD1 − AVSS)/5)+.

10100 ((AVDD1 − AVSS)/5)−.

10101 REF+.

10110 REF−.

CHANNEL REGISTER 1 TO CHANNEL REGISTER 3

Address: 0x11 to 0x13, Reset: 0x0001, Name: CH1 to CH3

The remaining three channel registers share the same layout as Channel Register 0.

Table 34. CH1 to CH3 Register Map

Bits

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x11

CH1

[15:8]

[7:0]

CH_EN1

RESERVED

AINPOS1[2:0]

SETUP_SEL1

RESERVED

AINPOS1[4:3]

0x0001

RW

AINNEG1

RESERVED

AINNEG2

RESERVED

AINNEG3

0x12

0x13

CH2

CH3

[15:8]

[7:0]

CH_EN2

CH_EN3

RESERVED

SETUP_SEL2

SETUP_SEL3

AINPOS2[4:3]

AINPOS3[4:3]

RW

AINPOS2[2:0]

[15:8]

[7:0]

RESERVED

AINPOS3[2:0]

Rev. B | Page 58 of 62

Data Sheet

AD7175-2

SETUP CONFIGURATION REGISTER 0

Address: 0x20, Reset: 0x1320, Name: SETUPCON0

óhe setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.

Table 35. Bit Descriptions for SETUPCON0

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] RESERVED

These bits are reserved; set these bits to 0.

This bit sets the output coding of the ADC for Setup 0.

Unipolar coded output.

12

11

10

9

BI_UNIPOLAR0

0x1

RW

0

1

Bipolar coded output (offset binary).

This bit enables or disables the REF+ input buffer.

REF+ buffer disabled.

REFBUF0+

REFBUF0−

AINBUF0+

0x0

0x1

RW

0

1

REF+ buffer enabled.

This bit enables or disables the REF− input buffer.

REF− buffer disabled.

0

1

REF− buffer enabled.

This bit enables or disables the AIN+ input buffer.

AIN+ buffer disabled.

0

1

AIN+ buffer enabled.

8

7

AINBUF0−

This bit enables or disables the AIN− input buffer.

AIN− buffer disabled.

0x1

RW

R

0

1

AIN− buffer enabled.

BURNOUT_EN0

This bit enables a 10 µA current source on the positive analog input

selected and a 10 µA current sink on the negative analog input selected.

The burnout currents are useful in diagnosis of an open wire, whereby the

ADC result goes to full scale. Enabling the burnout currents during

measurement results in an offset voltage on the ADC. This means the

strategy for diagnosing an open wire operates best by turning on the

burnout currents at intervals, before or after precision measurements.

0x00

6

RESERVED

REF_SEL0

These bits are reserved; set these bits to 0.

0x00

0x2

R

[5:4]

These bits allow you to select the reference source for ADC conversion on

Setup 0.

RW

00 External Reference.

10 Internal 2.5 V Reference. This must also be enabled in the ADC mode register.

11 AVDD1 − AVSS. This can be used as a diagnostic to validate other

reference values.

[3:0]

RESERVED

These bits are reserved; set these bits to 0.

0x0

R

SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3

Address: 0x21 to 0x23, Reset: 0x1320, Name: SETUPCON1 to SETUPCON3

The remaining three setup configuration registers share the same layout as Setup Configuration Register 0.

Table 36. SETUPCON1 to SETUPCON3 Register Map

Bits

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x21

SETUPCON1

[15:8]

[7:0]

RESERVED

BI_UNIPOLAR1

REFBUF1+

REFBUF1−

AINBUF1+

AINBUF1−

AINBUF2−

AINBUF3−

0x1320

RW

BURNOUT_EN1

BURNOUT_EN2

BURNOUT_EN3

REF_SEL1

BI_UNIPOLAR2

REF_SEL2

BI_UNIPOLAR3

REF_SEL3

RESERVED

0x22

0x23

SETUPCON2

SETUPCON3

[15:8]

[7:0]

REFBUF2+

REFBUF3+

REFBUF2−

AINBUF2+

RW

RESERVED

[15:8]

[7:0]

REFBUF3−

AINBUF3+

RESERVED

Rev. B | Page 59 of 62

AD7175-2

Data Sheet

FILTER CONFIGURATION REGISTER 0

Address: 0x28, Reset: 0x0500, Name: FILTCON0

The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers

resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 37. Bit Descriptions for FILTCON0

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAP0

If this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the sinc3 filter for Setup 0. All other

options are eliminated. This allows fine tuning of the output data rate and

filter notch for rejection of specific frequencies. The data rate when on a

single channel equals f_MOD/(32 × FILTCON0[14:0]).

0x0

RW

[14:12] RESERVED

These bits are reserved; set these bits to 0.

0x0

R

11

ENHFILTEN0

This bit enables various postfilters for enhanced 50 Hz/60 Hz rejection for

Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1

filter for this to work.

RW

0

1

Disabled.

Enabled.

[10:8]

ENHFILT0

These bits select between various postfilters for enhanced 50 Hz/60 Hz

rejection for Setup 0.

0x5

RW

010 27 SPS, 47 dB rejection, 36.7 ms settling.

011 25 SPS, 62 dB rejection, 40 ms settling.

101 20 SPS, 86 dB rejection, 50 ms settling.

110 16.67 SPS, 92 dB rejection, 60 ms settling.

This bit is reserved; set this bit to 0.

7

RESERVED

ORDER0

0x0

R

[6:5]

These bits control the order of the digital filter that processes the

modulator data for Setup 0.

RW

00 Sinc5 + sinc1 (default).

11 Sinc3.

[4:0]

ODR0

These bits control the output data rate of the ADC and, therefore, the

settling time and noise for Setup 0. Rates shown as for sinc5 + sinc 1 filter.

See Table 19 to Table 22.

0x0

RW

00000 250,000.

00001 125,000.

00010 62,500.

00011 50,000.

00100 31,250.

00101 25,000.

00110 15,625.

00111 10,000.

01000 5000.

01001 2500.

01010 1000.

01011 500.

01100 397.5.

01101 200.

01110 100.

01111 59.92.

10000 49.96.

10001 20.

10010 16.66.

10011 10.

10100 5.

Rev. B | Page 60 of 62

Data Sheet

AD7175-2

FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3

Address: 0x29 to 0x2B, Reset: 0x0500, Name: FILTCON1 to FILTCON3

The remaining three filter configuration registers share the same layout as Filter Configuration Register 0.

Table 38. FILTCON1 to FILTCON3 Register Map

Bits

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ENHFILT1

Bit 0

Reset

RW

0x29

FILTCON1

[15:8]

[7:0]

SINC3_MAP1

RESERVED

ENHFILTEN1

0x0500

RW

ORDER1

RESERVED

ORDER2

RESERVED

ORDER3

ODR1

0x2A

0x2B

FILTCON2

FILTCON3

[15:8]

[7:0]

SINC3_MAP2

RESERVED

ENHFILTEN2

ENHFILTEN3

ENHFILT2

ENHFILT3

0x0500

RW

ODR2

ODR3

[15:8]

[7:0]

SINC3_MAP3

RESERVED

OFFSET REGISTER 0

Address: 0x30, Reset: 0x800000, Name: OFFSET0

The offset (zero-scale) registers are 24-bit registers that can compensate for any offset error in the ADC or in the system.

Table 39. Bit Descriptions for OFFSET0

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSET0

Offset calibration coefficient for Setup 0.

0x800000 RW

OFFSET REGISTER 1 TO OFFSET REGISTER 3

Address: 0x31 to 0x33, Reset: 0x800000, Name: OFFSET1 to OFFSET3

The remaining three offset registers share the same layout as Offset Register 0.

Table 40. OFFSET1 to OFFSET3 Register Map

Reg. Name

Bits

Reset

RW

0x31 OFFSET1 [23:0]

0x32 OFFSET2 [23:0]

0x33 OFFSET3 [23:0]

OFFSET1[23:0]

OFFSET2[23:0]

OFFSET3[23:0]

0x800000 RW

GAIN REGISTER 0

Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0

The gain (full-scale) registers are 24-bit registers that can compensate for any gain error in the ADC or in the system.

Table 41. Bit Descriptions for GAIN0

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

GAIN0

Gain calibration coefficient for Setup 0.

0x5XXXX0 RW

GAIN REGISTER 1 TO GAIN REGISTER 3

Address: 0x39 to 0x3B, Reset: 0x5XXXX0, Name: GAIN1 to GAIN3

The remaining three gain registers share the same layout as Gain Register 0.

Table 42. GAIN1 to GAIN3 Register Map

Reg. Name

0x39 GAIN1

0x3A GAIN2

0x3B GAIN3

Bits

Reset

RW

[23:0]

GAIN1[23:0]

GAIN2[23:0]

GAIN3[23:0]

0x5XXXX0 RW

Rev. B | Page 61 of 62

AD7175-2

Data Sheet

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 75. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Models¹

Temperature Range

Package Description

Package Option

AD7175-2BRUZ

AD7175-2BRUZ-RL

AD7175-2BRUZ-RL7

EVAL-AD7175-2SDZ

EVAL-SDP-CB1Z

−40°C to +105°C

24-Lead Thin Shrink Small Outline Package [TSSOP]

Evaluation Board

RU-24

Evaluation Controller Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12468-0-5/16(B)

Rev. B | Page 62 of 62


型号：	AD7175-2BRUZ-RL
厂家：	ADI
描述：	24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers 光电二极管转换器
文件：	总63页 (文件大小：1115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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