ADSP-21MOD870-000_技术文档

a

Internet Gateway Processor

ADSP-21mod870

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

FEATURES

PERFORMANCE

Complete Single-Chip Internet Gateway Processor (No

External Memory Required)

Implements V.34/V.90 Data/FAX Modem Including

Controller and Datapump

CONTROL

FULL MEMORY

MODE

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

16K

؋

24 PM

8K

؋

24 OVERLAY 1 8K

؋

16 OVERLAY 1

8K

؋

16 OVERLAY 2

16K

؋

16 DM

EXTERNAL

ADDRESS

BUS

PROGRAM

SEQUENCER

I/O

AND

FLAGS

DAG 2

DAG 1

8K

؋

24 OVERLAY 2

19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained

Performance

Open Architecture Platform Extensible to Voice Over IP

and Other Applications

Low Power Dissipation, 80 mW (Typical) for Digital

Modem

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation

EXTERNAL

DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BUS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

SERIAL PORTS

SPORT 0 SPORT 1

ARITHMETIC UNITS

TIMER

INTERNAL

DMA

PORT

ALU

SHIFTER

MAC

INTEGRATION

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

160K Bytes of On-Chip RAM, Configured as 32K Words

On-Chip Program Memory RAM and 32K Words On-

Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP with 0.4 Square Inch (256 mm²) Footprint

GENERAL DESCRIPTION

The ADSP-21mod870 is a single-chip Internet gateway pro-

cessor optimized for implementation of a complete V.34/56K

modem. All data pump and controller functions can be imple-

mented on a single chip, offering the lowest power consumption

and highest possible modem port density.

The ADSP-21mod870, shown in the Functional Block Dia-

gram, combines the ADSP-2100 family base architecture (three

computational units, data address generators and a program

sequencer) with two serial ports, a 16-bit internal DMA port, a

byte DMA port, a programmable timer, Flag I/O, extensive

interrupt capabilities and on-chip program and data memory.

SYSTEM INTERFACE

The ADSP-21mod870 integrates 160K bytes of on-chip

memory configured as 32K words (24-bit) of program RAM,

and 32K words (16-bit) of data RAM. Power-down circuitry is

also provided to meet the low power needs of battery operated

portable equipment. The ADSP-21mod870 is available in

100-lead LQFP package.

16-Bit Internal DMA Port for High Speed Access to On-

Chip Memory (Mode Selectable)

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Programmable Multichannel Serial Port Supports

24/32 Channels

Automatic Booting of On-Chip Program Memory

Through Internal DMA Port

Six External Interrupts

Fabricated in a high speed, low power, CMOS process, the

ADSP-21mod870 operates with a 19 ns instruction cycle time.

Every instruction can execute in a single processor cycle.

The ADSP-21mod870’s flexible architecture and comprehen-

sive instruction set allow the processor to perform multiple

operations in parallel. In one processor cycle the ADSP-21mod870

can:

13 Programmable Flag Pins Provide Flexible System

Signaling

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

ICE-Port is a trademark of Analog Devices, Inc.

All other trademarks are the property of their respective holders.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-21mod870

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

requires fewer mechanical clearance considerations than other

ADSP-2100 Family EZ-ICEs. The ADSP-21mod870 device

need not be removed from the target system when using the EZ-

ICE, nor are any adapters needed. Due to the small footprint of

the EZ-ICE connector, emulation can be supported in final

board designs.

Modem Software

The modem software executes general modem control, com-

mand sets, error correction and data compression, data modula-

tions (for example, V.90 and V.34), and host interface functions.

The host interface allows system access to modem statistics

such as call progress, connect speed, retrain count, symbol rate

and other modulation parameters.

The EZ-ICE performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

The modem data pump and controller software reside in on-

chip SRAM and do not require external memory. You can

configure the ADSP-21mod870 dynamically by downloading

software from the host through the 16-bit DMA interface. This

SRAM-based architecture provides a software upgrade path to

future standards and applications, such as voice over IP.

See Designing An EZ-ICE-Compatible Target System in the

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as

well as the Designing an EZ-ICE Compatible System section of

this data sheet for the exact specifications of the EZ-ICE target

board connector.

The modem software is available as object code.

DEVELOPMENT SYSTEM

ADSP-21mod870 Reference Design/Evaluation Kit

The ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, sup-

ports the ADSP-21mod870. The System Builder provides a

high level method for defining the architecture of systems under

development. The Assembler has an algebraic syntax that is

easy to program and debug. The Linker combines object files

into an executable file. The Simulator provides an interactive

instruction-level simulation with a reconfigurable user interface

to display different portions of the hardware environment.

The ADSP-21mod870-EV1 is a reference design/evaluation kit

that includes an ISA bus PC card that has an ADSP-21061L

SHARC^®processor as a host, four ADSP-21mod870 Internet

gateway processors and a T1 interface. The board is shipped

with an evaluation copy of the modem software and software

that runs on the PC. The PC software provides a user interface

that lets you run a modem session “right out of the box.” When

you run the modem in keyboard mode, characters typed on the

keyboard are transmitted to the other modem and characters

sent by the other modem are displayed on the screen. Data can

also be streamed through the COM port of the PC to send and

receive files and perform automated testing.

A PROM Splitter generates PROM programmer compatible

files. The C Compiler, based on the Free Software Foundation’s

GNU C Compiler, generates ADSP-21mod870 assembly source

code. The source code debugger allows programs to be cor-

rected in the C environment. The Runtime Library includes

over 100 ANSI-standard mathematical and DSP-specific

functions.

The ADSP-218x EZ-ICE^®Emulator aids in the hardware de-

bugging of an ADSP-21mod870 system. The emulator consists

of hardware, host computer resident software, and the target

board connector. The ADSP-21mod870 integrates on-chip

emulation support with a 14-pin ICE-Port interface. This

interface provides a simpler target board connection that

The modem system contains four ADSP-21mod870s connected

to an ADSP-21061 SHARC host processor. This design is ex-

tensible to 32 ADSP-21mod870s. The ADSP-21mod870s are

connected to a T1 interface. This accommodates testing with a

digital line. A diagram of the system is shown below in Figure 1.

The SHARC processor communicates to the PC through the

ISA bus. The SHARC acts as the modem system host and con-

trols the ADSP-21mod870-based modems connected to a DMA

bus. The code, written in C, runs on the SHARC and provides

an example of how the host loads code into the ADSP-21mod870s,

HOST

MODEM POOL

LINE I/F

SPORT0

ADSP-

SPORT0

DIGITAL

TELCO

T1/ISDN

ADSP-

21mod870

MEM

I/F

IDMA

PORT

IDMA

PORT

ISA

BUS

ADSP-21061

SHARC

IDMA

PORT

IDMA

PORT

ADSP-2183

SPORT

FLASH

ADSP-

21mod870

ADSP-

21mod870

SPORT0

Figure 1. Evaluation/Reference Design Board

EZ-ICE and SHARC are registered trademarks of Analog Devices, Inc.

–2–

REV. 0

ADSP-21mod870

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

how data is passed, and how commands and status information

are communicated. You can port this C code to whatever host

processor you are using in your system. The SHARC also

controls an ADSP-2181 connected to the DMA bus. The

ADSP-2181 controls the T1 interface. The PCM serial stream

from the T1 interface is connected to the serial ports of the

ADSP-21mod870s.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. The sequencer supports conditional jumps, sub-

routine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADSP-21mod870 executes looped

code with zero overhead; no explicit jump instructions are re-

quired to maintain loops.

A debugger is provided that lets you download code and data to

the SHARC and examine register and memory contents. Moni-

tor software is also included so you can run a modem session

immediately “out of the box” without writing extra layers of

software or adding to the configuration.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four ad-

dress pointers. Whenever the pointer is used to access data (indi-

rect addressing), it is post-modified by the value of one of four

possible modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers.

Additional Information

This data sheet provides a general overview of ADSP-21mod870

functionality. For additional information on the architecture

and instruction set of the processor, refer to the ADSP-2100

Family User’s Manual, Third Edition. For more information

about the development tools, refer to the ADSP-2100 Family

Development Tools data sheet.

Efficient data transfer is achieved with the use of five internal

buses:

For more information about the modem software refer to

ADSP-21mod870-100 Modem Software data sheet.

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

ARCHITECTURE OVERVIEW

The ADSP-21mod870 instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The ADSP-21mod870 assembly language uses an

algebraic syntax for ease of coding and readability. A compre-

hensive set of development tools supports program development.

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte and I/O memory space also share the external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-21mod870 to fetch two operands in a single

cycle, one from program memory and one from data memory.

The ADSP-21mod870 can fetch an operand from program

memory and the next instruction in the same cycle.

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

DATA ADDRESS

PROGRAMMABLE

16K

؋

24 PM

16K

؋

16 DM

EXTERNAL

ADDRESS

BUS

PROGRAM

GENERATORS

I/O

SEQUENCER

8K

؋

24 OVERLAY 1 8K

؋

16 OVERLAY 1

AND

FLAGS

DAG 2

DAG 1

8K

؋

16 OVERLAY 2

8K

؋

24 OVERLAY 2

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

In lieu of the address and data bus for external memory connec-

tion, the ADSP-21mod870 may be configured for 16-bit Inter-

nal DMA port (IDMA port) connection to external systems.

The IDMA port is made up of 16 data/address pins and five

control pins. The IDMA port provides transparent, direct ac-

cess to the DSPs on-chip program and data RAM.

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

SERIAL PORTS

SPORT 0 SPORT 1

ARITHMETIC UNITS

TIMER

INTERNAL

DMA

PORT

ALU

SHIFTER

MAC

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

Figure 2. Functional Block Diagram

Figure 2 is an overall block diagram of the ADSP-21mod870.

The processor contains three independent computational units:

the ALU, the multiplier/accumulator (MAC) and the shifter.

The computational units process 16-bit data directly and have

provisions to support multiprecision computations. The ALU

performs a standard set of arithmetic and logic operations;

division primitives are also supported. The MAC performs

single-cycle multiply, multiply/add and multiply/subtract opera-

tions with 40 bits of accumulation. The shifter performs logical

and arithmetic shifts, normalization, denormalization and de-

rive exponent operations.

The byte memory and I/O memory space interface supports

slow memories and I/O memory-mapped peripherals with pro-

grammable wait state generation. External devices can gain

control of external buses with bus request/grant signals (BR,

BGH, and BG). One execution mode (Go Mode) allows the

ADSP-21mod870 to continue running from on-chip memory.

Normal execution mode requires the processor to halt while

buses are granted.

The ADSP-21mod870 can respond to eleven interrupts. There

can be up to six external interrupts (one edge-sensitive, two

level-sensitive, and three configurable) and seven internal inter-

rupts generated by the timer, the serial ports (SPORTs), the

Byte DMA port, and the power-down circuitry. There is also a

master RESET signal. The two serial ports provide a complete

The shifter can be used to efficiently implement numeric

format control including multiword and block floating-point

representations.

REV. 0

–3–

ADSP-21mod870

synchronous serial interface with optional companding in hard-

ware and a wide variety of framed or frameless data transmit

and receive modes of operation.

Common-Mode Pins

#

Input/

Out-

of

Name(s)

Pins put

Function

Each port can generate an internal programmable serial clock or

accept an external serial clock.

RESET

BR

BG

BGH

DMS

PMS

IOMS

BMS

CMS

RD

1

I

Processor Reset Input

Bus Request Input

Bus Grant Output

The ADSP-21mod870 provides up to 13 general-purpose flag

pins. The data input and output pins on SPORT1 can be alter-

natively configured as an input flag and an output flag. In addi-

tion, there are eight flags that are programmable as inputs or

outputs, and three flags that are always outputs.

O

I

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

Edge- or Level-Sensitive

Interrupt Request¹

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) decrements every n processor

cycles, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

WR

IRQ2/

Serial Ports

PF7

IRQL1/

PF6

IRQL0/

PF5

IRQE/

PF4

I/O

I

I/O

I

I/O

I

Programmable I/O Pin

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

The ADSP-21mod870 incorporates two complete synchronous

serial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

1

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Here is a brief list of the capabilities of the ADSP-21mod870

SPORTs. For additional information on Serial Ports, refer to the

ADSP-2100 Family User’s Manual, Third Edition.

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

I/O

I

Mode D/

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with one overhead cycle per data word. An interrupt is

generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24 or 32 word, time-division multiplexed,

serial bitstream.

PF3

I/O

I

Mode C/

PF2

1

I/O

I

Mode B/

PF1

I/O

I

Mode A/

PF0

I/O

Normal Operation

CLKIN, XTAL

CLKOUT

SPORT0

2

1

5

I

O

I/O

Clock or Quartz Crystal Input

Processor Clock Output

Serial Port 0 Pins (TFS0, RFS0,

DT0, DR0, SCLK0)

Serial Port 1 Pins (TFS1, RFS1,

DT1, DR1, SCLK1)

SPORT1²

5

I/O

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

or Interrupts and Flags:

IRQ0 (RFS1)

IRQ1 (TFS1)

FI (DR1)

1

I

O

I

O

I

External Interrupt Request #0

External Interrupt Request #1

Flag Input Pin

FO (DT1)

1

Flag Output Pin

PIN DESCRIPTIONS

PWD

1

Power-Down Control Input

Power-Down Control Output

Output Flags

Power and Ground

For Emulation Use

The ADSP-21mod870 is available in a 100-lead LQFP package.

To maintain maximum functionality and reduce package size

and pin count, some serial port, programmable flag, interrupt,

and external bus pins have dual, multiplexed functionality. The

external bus pins are configured during RESET, while serial

port pins are software configurable during program execution.

Flag and interrupt functionality is retained concurrently on

multiplexed pins. The following table shows the common-mode

pins. When pin functionality is configurable, the default state is

shown in plain text, alternate functionality is in italics.

PWDACK

FL0, FL1, FL2

V_DDand GND

EZ-Port

1

3

16

9

I/O

NOTES

¹Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the

corresponding interrupts, the DSP will vector to the appropriate interrupt vector address

when the pin is asserted, either by external devices or set as a programmable flag.

²SPORT configuration determined by the DSP System Control Register. Software

configurable.

–4–

REV. 0

ADSP-21mod870

Memory Interface Pins

D4 or

IS

I/O (Z)

I

I/O (Z)

**

Hi-Z

I

BR, EBR Float

High (Inactive)

BR, EBR Float

Float

The ADSP-21mod870 processor can be used in one of two

modes: Full Memory Mode, which allows BDMA operation

with full external overlay memory and I/O capability, or Host

Mode, which allows IDMA operation with limited external

addressing capabilities. The operating mode is determined by

the state of the Mode C pin during RESET and cannot be

changed while the processor is running.

D3 or

IACK

D2:0 or

IAD15:13

PMS

DMS

BMS

IOMS

CMS

RD

WR

BR

BG

BGH

IRQ2/PF7

Hi-Z

**

Hi-Z

O

I

O

I

I/O (Z)

O (Z)

I

BR, EBR Float

IS

Float

BR, EBR Float

Full Memory Mode Pins (Mode C = 0)

#

of

Input/

Pin Name Pins Output Function

High (Inactive)

Float

A13:0

D23:0

14

24

O

Address Output Pins for Pro-

gram, Data, Byte and I/O Spaces

O (Z)

I/O (Z)

EE

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High or Low,

Output = Float

I/O

Data I/O Pins for Program,

Data, Byte and I/O Spaces

(8 MSBs Are Also Used as

Byte Memory Addresses)

IRQL1/PF6 I/O (Z)

IRQL0/PF5 I/O (Z)

I

Host Mode Pins (Mode C = 1)

#

of

Input/

IRQE/PF4

I/O (Z)

I/O

Pin Name Pins Output Function

IAD15:0

A0

16

1

I/O

O

IDMA Port Address/Data Bus

Address Pin for External I/O,

Program, Data, or Byte Access

SCLK0

RFS0

DR0

TFS0

DT0

I/O

I

I/O

O

I

O

I

High or Low

Float

Input = High or Low,

Output = Float

High or Low

D23:8

16

I/O

Data I/O Pins for Program,

Data Byte and I/O Spaces

IWR

IRD

IAL

IS

1

I

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

I

SCLK1

I/O

I

RFS1/IRQ0 I/O

DR1/FI

TFS1/IRQ1 I/O

DT1/FO

EE

I

O

I

O

I

O

I

IACK

O

IDMA Port Acknowledge

Configurable in Mode D; Open

Drain

O

I

O

I

O

I

O

Float

In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS and IOMS signals.

EBR

EBG

ERESET

EMS

EINT

ECLK

ELIN

ELOUT

Terminating Unused Pin

The following table shows the recommendations for terminating

unused pins.

Pin Terminations

I

O

I/O

Hi-Z*

Caused

By

Name

3-State Reset

(Z)

Unused

Configuration

NOTES

**Hi-Z = High Impedance.

**Determined by MODE D pin:

Mode D = 0 and in host mode: IACK is an active, driven signal and cannot

be “wire ORed.”

Mode D = 1 and in host mode: IACK is an open source and requires an

external pull-down, but multiple IACK pins can be “wire ORed” together.

1. If the CLKOUT pin is not used, turn it OFF.

2. If the Interrupt/Programmable Flag pins are not used, there are two options:

Option 1: When these pins are configured as INPUTS at reset and function

as interrupts and input flag pins, pull the pins High (inactive).

Option 2: Program the unused pins as OUTPUTS, set them to 1, and let

them float.

3. All bidirectional pins have three-stated outputs. When the pins is configured

as an output, the output is Hi-Z (high impedance).

4. CLKIN, RESET, and PF3:0 are not included in the table because these pins

State

XTAL

CLKOUT

A13:1 or

IAD12:0

A0

D23:8

D7 or

IWR

D6 or

IRD

D5 or

IAL

I

O

I

O

Float

BR, EBR Float

IS Float

BR, EBR Float

High (Inactive)

BR, EBR Float

BR, EBR High (Inactive)

BR, EBR Float

O (Z)

I/O (Z)

O (Z)

I/O (Z)

I

I/O (Z)

I

I/O (Z)

I

Hi-Z

I

Hi-Z

I

Hi-Z

I

must be used.

Low (Inactive)

REV. 0

–5–

ADSP-21mod870

Interrupts

LOW POWER OPERATION

The interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

The ADSP-21mod870 provides four dedicated external inter-

rupt input pins, IRQ2, IRQL0, IRQL1, and IRQE (shared with

the PF7:4 pins). In addition, SPORT1 may be reconfigured for

IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six

external interrupts. The ADSP-21mod870 also supports internal

interrupts from the timer, the byte DMA port, the two serial

ports, software and the power-down control circuit. The inter-

rupt levels are internally prioritized and individually maskable

(except power down and reset). The IRQ2, IRQ0 and IRQ1

input pins can be programmed to be either level- or edge-

sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is

edge-sensitive. The priorities and vector addresses of all inter-

rupts are shown in Table I.

The ADSP-21mod870 has three low power modes that signifi-

cantly reduce the power dissipation when the device operates

under standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Power-Down

The ADSP-21mod870 Internet gateway processor has a low

power feature that lets the processor enter a very low power

dormant state through hardware or software control. Here is a

brief list of power-down features. Refer to the ADSP-2100 Fam-

ily User’s Manual, Third Edition, “System Interface” chapter, for

detailed information about the power-down feature.

Table I. Interrupt Priority and Interrupt Vector Addresses

• Quick recovery from power-down. The processor begins

executing instructions in as few as 400 CLKIN cycles.

Source of Interrupt

Interrupt Vector Address (Hex)

• Support for an externally generated TTL or CMOS processor

clock. The external clock can continue running during power-

down without affecting the lowest power rating and 400 CLKIN

cycle recovery.

Reset (or Power-Up with

PUCR = 1)

Power-Down (Nonmaskable) 002C

IRQ2

IRQL1

0000 (Highest Priority)

0004

0008

000C

0010

0014

0018

001C

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits approxi-

mately 4096 CLKIN cycles for the crystal oscillator to start or

stabilize), and letting the oscillator run to allow 400 CLKIN

cycle startup.

IRQL0

SPORT0 Transmit

SPORT0 Receive

IRQE

BDMA Interrupt

SPORT1 Transmit or IRQ1 0020

SPORT1 Receive or IRQ0 0024

• Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit. Interrupt support al-

lows an unlimited number of instructions to be executed

before optionally powering down. The power-down interrupt

also can be used as a nonmaskable, edge-sensitive interrupt.

Timer

0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority inter-

rupts taking precedence or processed sequentially. Interrupts can

be masked or unmasked with the IMASK register. Individual

interrupt requests are logically ANDed with the bits in IMASK;

the highest priority unmasked interrupt is then selected. The

power-down interrupt is nonmaskable.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor

has entered power-down.

The ADSP-21mod870 masks all interrupts for one instruction

cycle following the execution of an instruction that modifies the

IMASK register. This does not affect serial port autobuffering or

DMA transfers.

Idle

When the ADSP-21mod870 is in the Idle Mode, the processor

waits indefinitely in a low power state until an interrupt occurs.

When an unmasked interrupt occurs, it is serviced; execution

then continues with the instruction following the IDLE instruc-

tion. In Idle Mode IDMA, BDMA and autobuffer cycle steals

still occur.

The interrupt control register, ICNTL, controls interrupt nesting

and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be

either edge- or level-sensitive. The IRQE pin is an external edge

sensitive interrupt and can be forced and cleared. The IRQL0

and IRQL1 pins are external level-sensitive interrupts.

Slow Idle

The IDLE instruction is enhanced on the ADSP-21mod870 to

let the processor’s internal clock signal be slowed, further reduc-

ing power consumption. The reduced clock frequency, a pro-

grammable fraction of the normal clock rate, is specified by a

selectable divisor given in the IDLE instruction.

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks

are twelve levels deep to allow interrupt, loop, and subroutine

nesting. The following instructions allow global enable or disable

servicing of the interrupts (including power down), regardless of

the state of IMASK. Disabling the interrupts does not affect serial

port autobuffering or DMA.

The format of the instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the processor

fully functional, but operating at the slower clock rate. While it is

in this state, the processor’s other internal clock signals, such as

SCLK, CLKOUT and timer clock, are reduced by the same

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

–6–

REV. 0

ADSP-21mod870

ratio. The default form of the instruction, when no clock divisor

is given, is the standard IDLE instruction.

CLOCK SIGNALS

The ADSP-21mod870 can be clocked by either a crystal or a

TTL-compatible clock signal.

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts. The one-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-21mod870 will remain in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64,

or 128) before resuming normal operation.

The CLKIN input cannot be halted, changed during operation,

or operated below the specified frequency during normal opera-

tion. The only exception is while the processor is in the power-

down state. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual, Third Edition, for detailed

information on this power-down feature.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

If an external clock is used, it should be a TTL-compatible

signal running at half the instruction rate. The signal is con-

nected to the processor’s CLKIN input. When an external clock

is used, the XTAL input must be left unconnected.

The ADSP-21mod870 uses an input clock with a frequency

equal to half the instruction rate; a 26 MHz input clock yields a

19 ns processor cycle (which is equivalent to 52 MHz). Nor-

mally, instructions are executed in a single processor cycle. All

device timing is relative to the internal instruction clock rate,

which is indicated by the CLKOUT signal when enabled.

SYSTEM INTERFACE

Figure 3 shows a typical multichannel modem configuration

with the ADSP-21mod870. A line interface can be used to

connect the multichannel subscriber or client data stream to the

multichannel serial port of the ADSP-21mod870. The ADSP-

21mod870 can support 24 or 32 channels. The IDMA port of

the ADSP-21mod870 is used to give a host processor full access

to the internal memory of the ADSP-21mod870. This lets the

host dynamically configure the ADSP-21mod870 by loading code

and data into its internal memory. This configuration also lets

the host access server data directly from the ADSP-21mod870’s

internal memory. In this configuration, the ADSP-21mod870

should be put into host memory mode where Mode C = 1,

Mode B = 0 and Mode A = 1 (see Table II).

Because the ADSP-21mod870 includes an on-chip oscillator

circuit, an external crystal may be used. The crystal should be

connected across the CLKIN and XTAL pins, with two capaci-

tors connected as shown in Figure 4. Capacitor values are de-

pendent on crystal type and should be specified by the crystal

manufacturer. A parallel-resonant, fundamental frequency,

microprocessor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This is enabled and disabled by the

CLKODIS bit in the SPORT0 Autobuffer Control Register.

SP0

ADSP-

21mod870

IDMA

LINE

INTERFACE

HOST BUS

HOST

(2183)

CALL

CONTROL

IDMA

T1, E1, PRI,

xDSL, ATM

ADSP-

21mod870

LAN OR

INTERNET

SP0

ADSP-21mod870 FUNCTIONS

HOST FUNCTIONS

• V.34/56k MODEM

• V.17 FAX

DTMF DIALING

CALLER ID

• MULTI-DSP CONTROL AND OVERLAY

MANAGEMENT

• V.42, V.42bis, MNP2-5 HDLC PROTOCOL

• SERVICE 32 DSPs/HOST

• DATA PACKETIZING

Figure 3. Network Access System

XTAL

CLKIN

DSP

CLKOUT

Figure 4. External Crystal Connections

–7–

REV. 0

ADSP-21mod870

Reset

MODES OF OPERATION

The RESET signal initiates a master reset of the ADSP-

21mod870. The RESET signal must be asserted during the

power-up sequence to assure proper initialization. RESET

during initial power-up must be held long enough to allow the

internal clock to stabilize. If RESET is activated any time after

power-up, the clock continues to run and does not require

stabilization time.

Table II summarizes the ADSP-21mod870 memory modes.

Setting Memory Mode

The ADSP-21mod870 uses the Mode C pin to make a Memory

Mode selection during chip reset. This pin is multiplexed with

the processor’s PF2 pin, so exercise care when selecting a mode.

The two methods for selecting the value of Mode C are active

and passive.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis ap-

plied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum

of 2000 CLKIN cycles ensures that the PLL has locked but

does not include the crystal oscillator start-up time. During

this power-up sequence the RESET signal should be held low.

On any subsequent resets, the RESET signal must meet the

Passive configuration uses a pull-up or pull-down resistor

connected to the Mode C pin. To minimize power consump-

tion, or if the PF2 pin is used as an output in the DSP applica-

tion, use a weak pull-up or pull-down, on the order of 100 kΩ.

This value should be sufficient to pull the pin to the desired

level and still let the pin operate as a programmable flag output

without undue strain on the processor’s output driver. For mini-

mum power consumption during power-down, reconfigure PF2

as an input, as the pull-up or pull-down will hold the pin in a

known state, and will not switch.

minimum pulsewidth specification, t_RSP

.

The RESET input contains some hysteresis; however, if you use

an RC circuit to generate your RESET signal, the use of an

external Schmidt trigger is recommended.

Active configuration uses a three-statable external driver con-

nected to the Mode C pin. A driver’s output enable should be

connected to the processor’s RESET signal so it only drives the

PF2 pin when RESET is active (low). When RESET is de-as-

serted, the driver should three-state, allowing the PF2 pin to be

an input or output. To minimize power consumption during

power-down, configure the programmable flag as an output when

connected to a three-stated buffer. This ensures that the pin is

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT

register. When RESET is released, if there is no pending bus

request and the chip is configured for booting, the boot-loading

sequence is performed. The first instruction is fetched from

on-chip program memory location 0x0000 once boot loading

completes.

Table II. Modes of Operation¹

MODE D²MODE C³MODE B⁴MODE A⁵Booting Method

X

0

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Full Memory Mode.⁶

X

0

1

0

No automatic boot operations occur. Program execution starts at external

memory location 0. Chip is configured in Full Memory Mode. BDMA can

still be used but the processor does not automatically use or wait for these

operations.

0

1

0

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Host Mode. IACK has active pull-down.

(REQUIRES ADDITIONAL HARDWARE).

0

1

0

1

0

IDMA feature is used to load any internal memory as desired. Program ex-

ecution is held off until internal program memory location 0 is written to.

Chip is configured in Host Mode.⁶IACK has active pull-down.

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Host Mode; IACK requires external pull-

down. (REQUIRES ADDITIONAL HARDWARE).

1

0

1

IDMA feature is used to load any internal memory as desired. Program ex-

ecution is held off until internal program memory location 0 is written to.

Chip is configured in Host Mode. IACK requires external pull-down.⁶

NOTES

¹All mode pins are recognized while RESET is active (low).

²When Mode D = 0 and in host mode, IACK is an active, driven signal and cannot be “wire ORed.”

When Mode D = 1 and in host mode, IACK is an open source and requires an external pull-down, multiple IACK pins can be “wire ORed” together.

³When Mode C = 0, Full Memory Mode enabled. When Mode C = 1, Host Memory Mode enabled.

⁴When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.

⁵When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.

⁶Considered standard operating settings. Using these configurations allows for easier design and better memory management.

–8–

REV. 0

ADSP-21mod870

held at a constant level and will not oscillate if the three-state

driver’s level hovers around the logic switching point.

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is 16 bits wide only.

The PMOVLAY bits are defined in Table III.

MEMORY ARCHITECTURE

The ADSP-21mod870 provides a variety of memory and pe-

ripheral interface options. The key functional groups are Pro-

gram Memory, Data Memory, Byte Memory and I/O. Refer to

the following figures and tables for PM and DM memory alloca-

tions in the ADSP-21mod870.

Table III. PMOVLAY Bits

PMOVLAY

Memory A13

A12:0

0, 4, 5

1

Internal

External

Overlay 1

Not Applicable

0

Not Applicable

13 LSBs of Address

Between 0x2000

and 0x3FFF

13 LSBs of Address

Between 0x2000

and 0x3FFF

Program Memory

The Program Memory map is shown in Figure 5.

Program Memory (Full Memory Mode) is a 24-bit space for

storing both instruction op codes and data. The ADSP-21mod870

has 32K words of Program Memory RAM on chip, and the

capability of accessing up to two 8K external memory overlay

spaces using the external data bus.

2

External

Overlay 2

1

Data Memory

The Data Memory map is shown in Figure 6.

1

PM MODE B=0

PM (MODE B=1)

ALWAYS

RESERVED

ACCESSIBLE

AT ADDRESS

0x0000 – 0x1FFF

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 0

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 0

0x2000–

0x3FFF

INTERNAL

MEMORY

RESERVED

0x2000–

0x3FFF

0x0000–

0x1FFF

INTERNAL

MEMORY

ACCESSIBLE WHEN

PMOVLAY = 4

2

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 5

ACCESSIBLE WHEN

PMOVLAY = 1

2

EXTERNAL

MEMORY

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 1

RESERVED

2

EXTERNAL

ACCESSIBLE WHEN

MEMORY

1

WHEN MODE = 1, PMOVLAY MUST BE SET TO 0

SEE TABLE III FOR PMOVLAY BITS

PMOVLAY = 2

2

PROGRAM MEMORY

MODE B = 0

PROGRAM MEMORY

MODE B = 1

ADDRESS

0x3FFF

ADDRESS

0x3FFF

8K INTERNAL

PMOVLAY = 0, 4, 5

OR

8K EXTERNAL

PMOVLAY = 1, 2

8K INTERNAL

PMOVLAY = 0

0x2000

0x1FFF

0x2000

0x1FFF

8K EXTERNAL

8K INTERNAL

0x0000

Figure 5. Program Memory

DATA MEMORY

ADDRESS

0x3FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

ALWAYS

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

0

x3FE0

0x3FDF

INTERNAL

8160

WORDS

0

x2000–

0x2000

0x1FFF

ACCESSIBLE WHEN

DMOVLAY = 0

0x0000–

0x1FFF

8K INTERNAL

DMOVLAY = 0, 4, 5

OR

EXTERNAL 8K

DMOVLAY = 1, 2

0x0000–

0x1FFF

0x0000–

0x1FFF

INTERNAL

MEMORY

ACCESSIBLE WHEN

DMOVLAY = 4

ACCESSIBLE WHEN

DMOVLAY = 5

0x0000

ACCESSIBLE WHEN

DMOVLAY = 1

0x0000–

0x1FFF

EXTERNAL

MEMORY

ACCESSIBLE WHEN

DMOVLAY = 2

Figure 6. Data Memory Map

–9–

REV. 0

ADSP-21mod870

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The ADSP-21mod870 has 32K words on Data

Memory RAM on chip, consisting of 16,352 user-accessible

locations and 32 memory-mapped registers. Support also exists

for up to two 8K external memory overlay spaces through the

external data bus. All internal accesses complete in one cycle.

Accesses to external memory are timed using the wait states

specified by the DWAIT register.

The CMS pin functions like the other memory select signals with

the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at reset,

except BMS.

Boot Memory Select (BMS) Disable

The ADSP-21mod870 lets you boot the processor from one

external memory space while using a different external memory

space for BDMA transfers during normal operation. You can

use the CMS to select the first external memory space for

BDMA transfers and BMS to select the second external space

for booting. The BMS signal can be disabled by setting Bit 3 of

the system control register to 1. The system control register is

illustrated in Figure 7.

Data Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). The DMOVLAY bits are defined in Table IV.

Table IV. DMOVLAY Bits

SYSTEM CONTROL REGISTER

DMOVLAY Memory A13

A12:0

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

1

0

1

DM (0x3FFF)

0

1

0

0, 4, 5

1

Internal

External

Overlay 1

Not Applicable Not Applicable

13 LSBs of Address

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT0 ENABLE

1 = ENABLED, 0 = DISABLED

0

Between 0x2000

and 0x3FFF

SPORT1 ENABLE

1 = ENABLED, 0 = DISABLED

BMS ENABLE

0 = ENABLED, 1 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

2

External

Overlay 2

13 LSBs of Address

Between 0x2000

and 0x3FFF

1

Figure 7. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The byte memory space

consists of 256 pages, each of which is 16K × 8.

I/O Space (Full Memory Mode)

The ADSP-21mod870 supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space

supports 2048 locations of 16-bit-wide data. The lower eleven

bits of the external address bus are used; the upper 3 bits are

undefined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated three-bit wait state

registers, IOWAIT0-3, which specify up to seven wait states to

be automatically generated for each of four regions. The wait

states act on address ranges as shown in Table V.

The byte memory space on the ADSP-21mod870 supports read

and write operations as well as four different data formats. The

byte memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space

while the processor is operating normally and steals only one

processor cycle per 8-, 16- or 24-bit word transferred.

Table V. Wait States

Address Range

Wait State Register

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

BDMA CONTROL

15 14 13 12 11 10

9

8

7

6

5

0

4

0

3

1

2

0

1

0

DM (0x3FE3)

Composite Memory Select (CMS)

BTYPE

BDIR

0 = LOAD FROM BM

1 = STORE TO BM

BMPAGE

BDMA

OVERLAY

BITS

The ADSP-21mod870 has a programmable memory select

signal that is useful for generating memory select signals for

memories mapped to more than one space. The CMS signal is

generated to have the same timing as each of the individual

memory select signals (PMS, DMS, BMS, IOMS) but can com-

bine their functionality.

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Figure 8. BDMA Control Register

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory, and use either DMS or PMS as the additional

address bit.

The BDMA circuit supports four different data formats which

are selected by the BTYPE register field. The appropriate num-

ber of 8-bit accesses are done from the byte memory space to

build the word size selected. Table VI shows the data formats

supported by the BDMA circuit.

–10–

REV. 0

ADSP-21mod870

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external byte

memory space. The 8-bit BMPAGE register specifies the start-

ing page for the external byte memory space. The BDIR register

field selects the direction of the transfer. Finally the, 14-bit

BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

processor’s memory-mapped control registers. A typical IDMA

transfer process is described as follows:

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the processor is busy.

3. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection

into the processor’s IDMA control registers.

If IAD[15] = 1, the value of IAD[7:0] represents the IDMA

overlay: Bits 14:8 must be set to 0.

Table VI. Data Formats

Internal

If IAD[15] = 0, the value of IAD[13:0] represents the start-

ing address of internal memory to be accessed and IAD[14]

reflects PM or DM for access.

BTYPE

Memory Space

Word Size

Alignment

4. Host uses IS and IRD (or IWR) to read (or write) processor

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

internal memory (PM or DM).

5. Host checks IACK line to see if the processor has completed

8

LSBs

the previous IDMA operation.

6. Host ends IDMA transfer.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written to while the ADSP-

21mod870 is operating at full speed.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches zero,

the transfers have finished and a BDMA interrupt is generated.

The BMPAGE and BEAD registers must not be accessed by the

processor during BDMA operations.

The processor memory address is latched and is then automati-

cally incremented after each IDMA transaction. An external

device can therefore access a block of sequentially addressed

memory by specifying only the starting address of the block.

This increases throughput as the address does not have to be

sent for each memory access.

The source or destination of a BDMA transfer will always be

on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value,

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one processor cycle. Processor

accesses to external memory have priority over BDMA byte

memory accesses.

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location; the destination type specifies whether it is a DM or

PM access. The falling edge of the address latch signal latches

this value into the IDMAA register.

Once the address is stored, data can then be either read from, or

written to, the ADSP-21mod870’s on-chip memory. Asserting

the select line (IS) and the appropriate read or write line (IRD

and IWR respectively) signals the ADSP-21mod870 that a par-

ticular transaction is required. In either case, there is a one-

processor-cycle delay for synchronization. The memory access

consumes one additional processor cycle.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor, and start execution at address 0 when

the BDMA accesses have completed. The BDMA overlay bits

specify the OVLAY memory blocks to be accessed for internal

memory.

Once an access has occurred, the latched address is automati-

cally incremented, and another access can occur.

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

Through the IDMAA register, the processor can also specify the

starting address and data format for DMA operation. Asserting

the IDMA port select (IS) and address latch enable (IAL)

directs the ADSP-21mod870 to write the address onto the

IAD[14:0] bus into the IDMA Control Register. If IAD[15]

is set to 0, IDMA latches the address. If IAD[15] is set to 1,

IDMA latches OVLAY memory. This register, shown below, is

memory mapped at address DM (0x3FE0). Note that the latched

address (IDMAA) cannot be read back by the host.

The IDMA Port provides an efficient means of communication

between a host system and the ADSP-21mod870. The port is

used to access the on-chip program memory and data memory

of the processor with only one processor cycle per word over-

head. The IDMA port cannot be used, however, to write to the

REV. 0

–11–

ADSP-21mod870

Figure 9 shows the IDMA Control and OVLAY Registers, Fig-

ure 10 shows the bus usage during IDMA transfers, and Figure

11 shows the DMA memory maps.

Bootstrap Loading (Booting)

The ADSP-21mod870 has two mechanisms to allow automatic

loading of the internal program memory after reset. The method

for booting is controlled by the Mode A, B and C configuration

bits.

IDMA OVERLAY

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

When the MODE pins specify BDMA booting, the ADSP-

21mod870 initiates a BDMA boot sequence when reset is

released.

0

DM(0x3FE7)

RESERVED

SET TO 0

ID PMOVLAY

ID DMOVLAY

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0, the BTYPE register is

set to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at Address 0.

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

U

DM(0x3FE0)

IDMAA

ADDRESS

IDMAD

DESTINATION MEMORY TYPE:

0 = PM

1 = DM

Figure 9. IDMA Control/OVLAY Registers

The ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate boot code compatible with byte memory space.

IDMA DATA READ/OUTPUT

(IAD 15–0)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the ad-

dresses to boot memory must be constructed externally to the

ADSP-21mod870. The only memory address bit provided by

the processor is A0.

DATA

DM 16-BIT

UPPER BYTE

LOWER BYTE

1ST

TRANSFER

DATA

PM 24-BIT

UPPER BYTE

MIDDLE BYTE

2ND

TRANSFER

0

LOWER BYTE

IDMA DATA WRITE/INPUT

(IAD 15–0)

IDMA Port Booting

15 14 13 12 11 10

9

8

7

6

5

4

3

2

The ADSP-21mod870 can also boot programs through its In-

ternal DMA port. If Mode C = 1, Mode B = 0, and Mode A =

1, the ADSP-21mod870 boots from the IDMA port. IDMA

feature can load as much on-chip memory as desired. Program

execution is held off until data is written to on-chip program

memory location 0.

DATA

DM 16-BIT

PM 24-BIT

UPPER BYTE

LOWER BYTE

1ST

TRANSFER

DATA

UPPER BYTE

MIDDLE BYTE

2ND

TRANSFER

IGNORED

LOWER BYTE

PAGE AND ADDRESS LATCH

(IAD 15–0)

Bus Request and Bus Grant

15 14 13 12 11 10

9

8

7

6

5

4

3

2

PAGE

LATCH

The ADSP-21mod870 can relinquish control of the data and

address buses to an external device. When the external device

requires access to memory, it asserts the bus request (BR)

signal. If the ADSP-21mod870 is not performing an external

memory access, it responds to the active BR input in the follow-

ing processor cycle by:

1

0

DM PAGE

PM PAGE

ADDRESS

LATCH

0

ADDRESS

0 = PM

1 = DM

Figure 10. Bus Usage During IDMA Transfers

•

Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

DMA

PROGRAM MEMORY

OVLAY

DMA

DATA MEMORY

OVLAY

•

Asserting the bus grant (BG) signal and

ALWAYS

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

ACCESSIBLE

AT ADDRESS

0x0000 – 0x1FFF

Halting program execution.

0x2000–

0x3FFF

If Go Mode is enabled, the ADSP-21mod870 will not halt pro-

gram execution until it encounters an instruction that requires an

external memory access.

0x0000–

0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 0

0x2000–

0x3FFF

0x0000–

0x1FFF

0x2000–

0x3FFF

0x0000–

0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 4

ACCESSIBLE WHEN

DMOVLAY = 4

If the ADSP-21mod870 is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

processor cycle after the access completes. The instruction does

not need to be completed when the bus is granted. If a single

instruction requires two external memory accesses, the bus will

be granted between the two accesses.

ACCESSIBLE WHEN

PMOVLAY = 5

ACCESSIBLE WHEN

DMOVLAY = 5

NOTE:

IDMA AND BDMA HAVE

SEPARATE DMA CONTROL REGISTERS

Figure 11. Direct Memory Access-PM and DM Memory

Maps

–12–

REV. 0

ADSP-21mod870

the target system to the EZ-ICE. Target systems must have a

14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-

pin plug. See the ADSP-2100 Family EZ-Tools data sheet for

complete information on ICE products.

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program

execution from the point at which it stopped.

The bus request feature operates at all times, including when the

Issuing the “chip reset” command during emulation causes the

DSP processor to perform a full chip reset, including a reset of its

memory mode. Therefore, it is vital that the mode pins are set

correctly PRIOR to issuing a chip reset command from the emu-

lator user interface. As the mode pins share functionality with

PF0:2 (and PF3 on the ADSP-21mod870), it may be necessary

to reset the target hardware separately to insure the proper mode

selection state on emulator chip reset.

processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-21mod870 is ready to

execute an instruction but is stopped because the external bus is

already granted to another device. The other device can release

the bus by deasserting bus request. Once the bus is released, the

ADSP-21mod870 deasserts BG and BGH and executes the

external memory access.

Flag I/O Pins

If you are using a passive method of maintaining mode informa-

tion (as discussed in the Setting Memory Modes section), it

does not matter that mode information is latched by an emula-

tor reset. However, if you are using the RESET pin as a method

of setting the value of the mode pins, then you must consider

the effects of an emulator reset.

The ADSP-21mod870 has eight general purpose programmable

input/output flag pins. They are controlled by two memory map-

ped registers. The PFTYPE register determines the direction,

1 = output and 0 = input. The PFDATA register is used to read

and write the values on the pins. Data being read from a pin

configured as an input is synchronized to the ADSP-21mod870’s

clock. Bits that are programmed as outputs will read the value

being output. The PF pins default to input during reset.

One method of ensuring that the values located on the mode

pins is correct is to construct a circuit like the one shown below.

This circuit will force the value located on the mode A pin

to zero, regardless of whether it latched via the RESET or

ERESET pin.

In addition to the programmable flags, the ADSP-21mod870

has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1,

and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and

FLAG_OUT are available as an alternate configuration of

SPORT1.

ERESET

RESET

Note: Pins PF0, PF1, PF2 and PF3 are also used for device

configuration during reset.

Instruction Set Description

1k⍀

MODE A/PFO

The ADSP-21mod870 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of

the processor’s unique architecture, offers the following ben-

efits:

PROGRAMMABLE I/O

Figure 12. RESET, ERESET Circuit

• The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

See the ADSP-2100 Family EZ-Tools data sheet for complete

information on ICE products.

The ICE-Port interface consists of the following ADSP-21mod870

pins:

• Every instruction assembles into a single, 24-bit word that can

execute in a single instruction cycle.

EBR

EBG

ERESET

EMS

EINT

ECLK

ELIN

ELOUT

EE

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relo-

cated to utilize on-chip memory and conform to the ADSP-

21mod870’s interrupt vector and reset vector map.

These ADSP-21mod870 pins must be connected only to the EZ-

ICE connector in the target system. These pins have no function

except during emulation, and do not require pull-up or pull-

down resistors. The traces for these signals between the ADSP-

21mod870 and the connector must be kept as short as possible,

no longer that three inches.

• Sixteen condition codes are available. For conditional jump,

call, return or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

The following pins are also used by the EZ-ICE:

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

BR

BG

RESET

GND

The EZ-ICE uses the EE (emulator enable) signal to take control

of the ADSP-21mod870 in the target system. This causes the

processor to use its ERESET, EBR and EBG pins instead of the

RESET, BR and BG pins. The BG output is three-stated. These

signals do not need to be jumper-isolated in your system.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-21mod870 has on-chip emulation support and an

ICE-Port, a special set of pins that interface to the EZ-ICE.

These features allow in-circuit emulation without replacing the

target system processor by using only a 14-pin connection from

REV. 0

–13–

ADSP-21mod870

The EZ-ICE connects to your target system via a ribbon cable

and a 14-pin female plug. The ribbon cable is ten inches long

with one end fixed to the EZ-ICE. The female plug is plugged

onto the 14-pin connector (a pin strip header) on the target

board.

Note: If your target does not meet the worst case chip specifica-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. De-

pending on the severity of the specification violation, you may

have trouble manufacturing your system as processor compo-

nents statistically vary in switching characteristic and timing

requirements within published limits.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 13. You must add this connector to your target board

design if you intend to use the EZ-ICE. Be sure to allow enough

room in your system to fit the EZ-ICE probe onto the 14-pin

connector.

Restriction: All memory strobe signals on the ADSP-21mod870

(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your

target system must have 10 kΩ pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed at

your option when the EZ-ICE is not being used.

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing

should be 0.1 × 0.1 inches. The pin strip header must have at

least 0.15 inch clearance on all sides to accept the EZ-ICE probe

plug.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals changes. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

Pin strip headers are available from vendors such as 3M,

McKenzie and Samtec.

Target Memory Interface

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the processor on the

RESET signal.

For your target system to be compatible with the EZ-ICE emu-

lator, it must comply with the memory interface guidelines listed

below.

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the processor on the BR

signal.

1

3

2

4

GND

BG

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

EBG

BR

5

6

• EZ-ICE emulation ignores RESET and BR when in Emulator

Space (processor halted).

EBR

EINT

ELIN

ECLK

7

8

KEY (NO PIN)

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

processor’s external memory bus only if bus grant (BG) is

asserted by the EZ-ICE board’s processor.

9

10

12

14

ELOUT

EE

11

13

EMS

RESET

ERESET

TOP VIEW

Figure 13. Target Board Connector for EZ-ICE

PM, DM, BM, IOM and CM

Design your Program Memory (PM), Data Memory (DM), Byte

Memory (BM), I/O Memory (IOM), and Composite Memory

(CM) external interfaces to comply with worst case device tim-

ing requirements and switching characteristics as specified in

this data sheet. The performance of the EZ-ICE may approach

published worst case specification for some memory access

timing requirements and switching characteristics.

–14–

REV. 0

ADSP-21mod870

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

Parameter

Min

Max

Unit

V_DD

T_AMB

3.15

0

3.45

+70

V

°C

ELECTRICAL CHARACTERISTICS

K/B Grades

Parameter

Test Conditions

Min

Typ

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

2.0

2.2

V

0.8

V_OH

2.4

V

I

_OH= –100 µA⁶

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

@ V_DD= min

_OL= 2 mA

I

0.4

10

µA

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

I_IL

Lo-Level Input Current³

Three-State Leakage Current⁷

Supply Current (Idle)⁹

V

_IN= 0 V

@ V_DD= max

_IN= V_DDmax⁸

I_OZH

I_OZL

I_DD

V

@ V_DD= max

V_IN= 0 V⁸, t_CK= 25 ns

@ V_DD= 3.3

t

_CK= 19 ns¹⁰

10

8

7

mA

t_CK= 25 ns¹⁰

_CK= 30 ns¹⁰

t

I_DD

Supply Current (Dynamic)¹¹

@ V_DD= 3.3

T_AMB= +25°C

t

_CK= 19 ns¹⁰

_CK= 25 ns¹⁰

51

41

34

mA

t_CK= 30 ns¹⁰

C_I

Input Pin Capacitance^{3, 6, 12}

@ V_IN= 2.5 V,

f

_IN= 1.0 MHz,

8

pF

T_AMB= +25°C

@ V_IN= 2.5 V,

f

C_O

Output Pin Capacitance^{6, 7, 12, 13}

_IN= 1.0 MHz,

T_AMB= +25°C

pF

NOTES

¹Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

²Input only pins: RESET, BR, DR0, DR1, PWD.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.

⁵Although specified for TTL outputs, all ADSP-21mod870 outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7.

⁸0 V on BR.

⁹Idle refers to ADSP-21mod870 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V _DDor GND.

10

11

V

I

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

IN

DD

and type 6, and 20% are idle instructions.

¹²Applies to LQFP package type.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0

–15–

ADSP-21mod870

ABSOLUTE MAXIMUM RATINGS*

ADSP-

21mod870

Timing

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Operating Temperature Range (Ambient) . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . +280°C

Memory

Device

Specification

Timing

Parameter

Parameter Definition

Address Setup to

Write Start

t_ASWA0–A13, xMS Setup

before WR Low

Address Setup to

Write End

t_AW

t_WRA

t_DW

A0–A13, xMS Setup

before WR Deasserted

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Address Hold Time

A0–A13, xMS Hold

before WR Low

Data Setup Time

Data Setup before WR

High

TIMING PARAMETERS

Data Hold Time

t_DH

Data Hold after WR High

RD Low to Data Valid

GENERAL NOTES

OE to Data Valid

t_RDD

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

Address Access Time t_AA

A0–A13, xMS to Data

Valid

Note: xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING

SPECIFICATIONS

t_CKis defined as 0.5 t_CKI. The ADSP-21mod870 uses an input

clock with a frequency equal to half the instruction rate: a

26 MHz input clock (which is equivalent to 38 ns) yields a 19 ns

processor cycle (equivalent to 52 MHz). t_CKvalues within the

range of 0.5 t_CKIperiod should be substituted for all relevant tim-

ing parameters to obtain the specification value.

TIMING NOTES

Switching characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Example: t_CKH= 0.5 t_CK– 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the proces-

sor operates correctly with other devices.

T_AMB

T_CASE

PD

=

T_CASE– (PD × θ_CA)

Case Temperature in °C

Power Dissipation in W

θ_CA

θ_JA

θ_JC

Thermal Resistance (Case-to-Ambient)

Thermal Resistance (Junction-to-Ambient)

Thermal Resistance (Junction-to-Case)

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications

and the corresponding ADSP-21mod870 timing parameter.

Package

␪

JA

␪

JC

␪

CA

LQFP

50°C/W

2°C/W

48°C/W

ESD SENSITIVITY

The ADSP-21mod870 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges

readily accumulate on the human body and equipment and can discharge without detection.

Permanent damage may occur to devices subjected to high energy electrostatic discharges.

WARNING!

The ADSP-21mod870 features proprietary ESD protection circuitry to dissipate high energy

discharges (Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are

recommended to avoid performance degradation or loss of functionality. Unused devices must be

stored in conductive foam or shunts, and the foam should be discharged to the destination before

devices are removed.

ESD SENSITIVE DEVICE

–16–

REV. 0

ADSP-21mod870

OUTPUT DRIVE CURRENTS

1, 3, 4

21mod870 POWER, INTERNAL

250

200

Figure 14 shows typical I-V characteristics for the output driv-

ers of the ADSP-21mod870. The curves represent the current

drive capability of the output drivers as a function of output

voltage.

216mW

V

= 3.6V

= 3.3V

DD

168.3mW

132mW

144mW

150

100

50

DD

112.2mW

80

60

V

= 3.0V

DD

3.6V, –40°C

87mW

40

20

0

33.3

52

3.0V, +85°C

1/t – MHz

CK

0

3.3V, +25°C

1, 2, 3

POWER, IDLE

45

40

35

30

–20

–40

3.0V, +85°C

3.3V, +25

°

C

35mW

V

= 3.3V

V

= 3.6V

= 3.0V

DD

32mW

30mW

DD

–60

–80

3.6V, –40

°C

25mW

25

20

15

10

5

0

0.5

1.0

1.5

2.0

2.5

3.0 3.5

4.0

DD

SOURCE VOLTAGE – V

23mW

21mW

Figure 14. Typical Drive Currents

POWER DISSIPATION

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

0

33.3

52

1/f – MHz

CK

C × V_DD²× f

3

POWER, IDLE n MODES

45

40

C = load capacitance, f = output switching frequency.

Example

35

30

25

32mW

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as follows:

IDLE

Assumptions

23mW

20

• External data memory is accessed every cycle with 50% of

the address pins switching.

15

10

13mW

12mW

IDLE (16)

IDLE (128)

10mW

9mW

• External data memory writes occur every other cycle with

50% of the data pins switching.

5

0

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V_DD= 3.3 V and t_CK= 30 ns.

Total Power Dissipation = P_INT+ (C × V_DD²× f)

33.3

52

1/f – MHz

CK

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-21mod870 STATE OF OPERATION DURING EXECUTION OF

IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

P

_INT= internal power dissipation from Power vs. Frequency

DD

3

4

TYPICAL POWER DISSIPATION AT 3.3V V AND +25؇C, EXCEPT WHERE SPECIFIED.

DD

graph (Figure 15).

I

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

DD

2

(C × V_DD× f) is calculated for each output:

MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),

30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

# of

Pins

؋

C

2

؋

V_DD

؋

f

Figure 15. Power vs. Frequency

Address, DMS

Data Output, WR 9

RD

CLKOUT

8

× 10 pF × 3.3²V × 33.3²MHz = 29.0 mW

× 10 pF × 3.3²V × 16.67 MHz = 16.3 mW

× 10 pF × 3.3²V × 16.67 MHz = 1.8 mW

1

× 10 pF × 3.3²V × 33.3 MHz =

3.6 mW

50.7 mW

Total power dissipation for this example is P_INT+ 50.7 mW.

REV. 0

–17–

ADSP-21mod870

CAPACITIVE LOADING

Figures 16 and 17 show the capacitive loading characteristics of

the ADSP-21mod870.

C_L×0.5V

t_DECAY

=

i_L

from which

18

T = +85 C

t

_DIS= t_MEASURED– t_DECAY

V

= 30V

DD

16

14

12

10

8

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, see Figure

19. If multiple pins (such as the data bus) are enabled, the mea-

surement value is that of the first pin to start driving. Figure 20

shows the equivalent device loading for ac measurements.

6

4

2

0

50

100

150

– pF

200

250

C

L

Figure 16. Typical Output Rise Time vs. Load Capacitance,

C_L(at Maximum Ambient Operating Temperature)

REFERENCE

SIGNAL

t_MEASURED

t_DIS

t_ENA

10

9

V

OH

(MEASURED)

OH

(MEASURED)

8

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

7

6

5

4

OUTPUT

OL

V

OL

t_DECAY

(MEASURED)

3

2

1

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

NOMINAL

–1

Figure 19. Output Enable/Disable

–2

–3

–4

I

OL

20

40

60

80

120 140 160 180 20.0

– pF

0

100

C

L

Figure 17. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

TO

OUTPUT

+1.5V

50pF

INPUT

1.5V

OR

OUTPUT

I

OH

Figure 18. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

Figure 20. Equivalent Device Loading for AC Measure-

ments (Including All Fixtures)

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. The out-

put disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY

The time is the interval from when a reference signal reaches

a high or low voltage level to when the output voltages have

.

changed by 0.5 V from the measured output high or low voltage,

see Figure 19.

The decay time, t_DECAY, is dependent on the capacitive load, C_L,

and the current load, i_L, on the output pin. It can be approxi-

mated by the following equation:

–18–

REV. 0

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

38

15

100

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5 t_CK– 7

0

ns

20

Control Signals

Timing Requirements:

1

t_RSP

t_MS

t_MH

RESET Width Low

Mode Setup before RESET High

Mode Setup after RESET High

5 t_CK

2

5

ns

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

PF(3:0)*

t_MH

t_MS

RESET

t_RSP

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 21. Clock Signals

REV. 0

–19–

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25 t_CK+ 15

0.25 t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.25 t_CK– 7

ns

0.5 t_CK+ 6

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the

following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information

on interrupt servicing.)

²Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag outputs = PFx, FL0, FL1, FL2, Flag_out.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 22. Interrupts and Flags

–20–

REV. 0

ADSP-21mod870

Parameter

Min

Max

Unit

Bus Request–Bus Grant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25 t_CK+ 2

0.25 t_CK+ 17

ns

Switching Characteristics:

t_SD

t_SDB

t_SE

t_SEC

t_SDBH

t_SEH

CLKOUT High to xMS, RD, WR Disable

0.25 t_CK+ 10

ns

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

0.25 t_CK– 4

0

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

WR

t_SEC

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 23. Bus Request–Bus Grant

REV. 0

–21–

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0–A13, xMS to Data Valid

Data Hold from RD High

0.5 t_CK– 9 + w

0.75 t_CK– 12.5 + w

ns

0

Switching Characteristics:

t_RP

RD Pulsewidth

CLKOUT High to RD Low

A0–A13, xMS Setup before RD Low

A0–A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

0.5 t_CK– 5 + w

0.25 t_CK– 5

0.25 t_CK– 6

0.25 t_CK– 3

0.5 t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25 t_CK+ 7

w = wait states × t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0 – A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

RD

t_ASR

t_CRD

t_RP

t_RWR

D

t_RDD

t_RDH

t_AA

WR

Figure 24. Memory Read

–22–

REV. 0

ADSP-21mod870

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_WRA

t_WWR

Data Setup before WR High

Data Hold after WR High

WR Pulsewidth

WR Low to Data Enabled

A0–A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, xMS, Setup before WR Deasserted

A0–A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.5 t_CK– 7 + w

0.25 t_CK– 2

0.5 t_CK– 5 + w

0

0.25 t_CK– 6

0.25 t_CK– 7

0.25 t_CK– 5

0.75 t_CK– 9 + w

0.25 t_CK– 3

0.5 t_CK– 5

ns

0.25 t_CK+ 7

w = wait states × t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 25. Memory Write

REV. 0

–23–

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

38

4

7

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

15

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

0.25 t_CK

0

0.25 t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

14

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCSt_SCH

DR

TFS

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 26. Serial Ports

–24–

REV. 0

ADSP-21mod870

Parameter

Min

Max

Unit

IDMA Address Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

t_IKA

t_IALS

t_IALD

Duration of Address Latch^{1, 2}

10

5

2

0

3

ns

IAD15–0 Address Setup before Address Latch End²

IAD15–0 Address Hold after Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

Start of Write or Read after Address Latch End^{1, 2}

Address Latch Start after Address Latch End^{1, 2}

2

NOTES

¹Start of Address Latch = IS Low and IAL High.

²End of Address Latch = IS High or IAL Low.

³Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

t_IALD

IAL

t_IALP

IS

IAD15–0

t_IASU

t_IAH

t_IALS

IRD OR

IWR

Figure 27. IDMA Address Latch

REV. 0

–25–

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Write, Short Write Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

15

5

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristics:

t_IKHW

Start of Write to IACK High

4

15

ns

NOTES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

t_IKHW

IS

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 28. IDMA Write, Short Write Cycle

–26–

REV. 0

ADSP-21mod870

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before IACK Low^{2, 3, 4}

IAD15–0 Data Hold after IACK Low^{2, 3, 4}

0.5 t_CK+ 10

2

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5 t_CK

4

ns

15

NOTES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 29. IDMA Write, Long Write Cycle

REV. 0

–27–

ADSP-21mod870

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

Duration of Read

0

15

ns

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read¹

4

0

15

10

ns

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

0

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

IACK

IS

t_IKR

t_IKHR

t_IRP

IRD

t_IKDH

t_IRDE

IAD15–0

t_IKDD

t_IRDV

Figure 30. IDMA Read, Short Read Cycle

–28–

REV. 0

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle

Timing Requirements:

t_IKR

t_IRK

IACK Low before Start of Read¹

End of Read after IACK Low²

0

2

ns

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

4

15

ns

IAD15–0 Data Setup before IACK Low

0.5 t_CK– 7

0

IAD15–0 Data Hold after End of Read³

IAD15–0 Data Disabled after End of Read³

10

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)²

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2 t_CK– 5

t_CK– 5

NOTES

¹Start of Read = IS Low and IRD Low.

²DM read or first half of PM read.

³End of Read = IS High or IRD High.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRK

IRD

t_IKDS

t_IRDE

t_IKDH

READ

DATA

IAD15–0

t_IRDV

t_IKDD

t_IRDH

Figure 31. IDMA Read, Long Read Cycle

REV. 0

–29–

ADSP-21mod870

100-Lead LQFP Package Pinout

75 D15

74 D14

1

2

3

4

5

6

7

8

9

A4/IAD3

PIN 1

IDENTIFIER

A5/IAD4

GND

73

D13

72 D12

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

71

70

69

68

67

GND

D11

D10

D9

V

DD

66 GND

A12/IAD11 10

65

64

63

62

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

D8

A13/IAD12

GND

D7/IWR

D6/IRD

D5/IAL

ADSP-21mod870

CLKIN

XTAL

TOP VIEW

(Not to Scale)

61 D4/IS

V

DD

60 GND

CLKOUT

GND

59

V

DD

58

V

D3/IACK

DD

57 D2/IAD15

WR

RD

56

55

54

53

52

51

D1/IAD14

D0/IAD13

BG

BMS

DMS

PMS

IOMS

CMS

EBG

BR

EBR

–30–

REV. 0

ADSP-21mod870

The ADSP-21mod870 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions

when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed

in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

LQFP Pin Configurations

LQFP

Number

Name

Number

Name

Number

Name

Number

Name

1

2

3

4

5

6

7

8

A4/IAD3

A5/IAD4

GND

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

TFS0

RFS0

DR0

SCLK0

V_DD

DT1/FO

TFS1/IRQ1

RFS1/IRQ0

DR1/FI

GND

SCLK1

ERESET

RESET

EMS

EE

ECLK

ELOUT

ELIN

EINT

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

EBR

BR

EBG

BG

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D16

D17

D18

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3 [Mode D]

PF2 [Mode C]

V_DD

PWD

GND

PF1 [Mode B]

PF0 [Mode A]

BGH

PWDACK

A0

A1/IAD0

A2/IAD1

A3/IAD2

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

V_DD

CLKOUT

GND

V_DD

WR

RD

BMS

DMS

PMS

IOMS

CMS

D0/IAD13

D1/IAD14

D2/IAD15

D3/IACK

V_DD

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

V_DD

D9

D10

D11

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND

D12

D13

D14

D15

REV. 0

–31–

ADSP-21mod870

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

0.640 (16.25)

0.630 (16.00)

0.620 (15.75)

TYP SQ

0.555 (14.10)

0.551 (14.00)

0.547 (13.90)

TYP SQ

0.063 (1.60) MAX

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

100

1

76

75

12°

TYP

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.004

(0.102)

MAX LEAD

COPLANARITY

25

51

50

26

6؇ ± 4؇

0؇ – 7؇

0.020 (0.50)

0.007 (0.177)

0.005 (0.127) TYP

0.003 (0.077)

0.011 (0.27)

0.009 (0.22) TYP

0.007 (0.17)

BSC

LEAD PITCH

LEAD WIDTH

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.0032 (0.08) FROM

ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

ORDERING GUIDE

Instruction

Ambient

Temperature

Range

Rate

(MHz)

Package

Description

Package

Option

Part Number

ADSP-21mod870-000

0°C to +70°C

52.0

Plastic Thin Quad Flatpack (LQFP)

ST-100

–32–

REV. 0


型号：	ADSP-21MOD870-000
厂家：	ADI
描述：	Internet Gateway Processor 互联网网关处理器调制解调器电信集成电路电信电路栅
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