L9216A_技术文档

Preliminary Data Sheet

September 2001

L9216A/G

Short-Loop Ringing SLIC with Ground Start

Applications

Introduction

■ Voice over Internet Protocol (VoIP)

■ Cable Modems

The Agere Systems Inc. L9216 is a subscriber line

interface circuit (SLIC) that is optimized for short-

loop, power-sensitive applications. This device pro-

vides the complete set of line interface functionality,

including power ringing needed to interface to a sub-

scriber loop. This device has the capability to operate

with a V^CCsupply of 3.3 V or 5 V and is designed to

minimize external components required at all device

interfaces.

■ Terminal Adapters (TA)

■ Wireless Local Loop (WLL)

■ Telcordia Technologies™ GR-909 Access

■ Network Termination (NT)

■ Key Systems

Features

Description

■ Onboard ringing generation

This device is optimized to provide battery feed, ring-

ing, and supervision on short-loop plain old tele-

phone service (POTS) loops.

■ Three ringing input options:

— Sine wave

— PWM

— Logic level square wave

This device provides power ring to the subscriber

loop through amplification of a low-voltage input. It

provides forward and reverse battery feed states, on-

hook transmission, a low-power scan state, ground

start (tip open), and a forward disconnect state.

■ Flexible VCC options:

— 5 V or 3.3 V V^CC

— No –5 V required

■ Battery switch to minimize off-hook power

The device requires a V^CCand battery to operate.

V^CCmay be either a 5 V or a 3.3 V supply. The ring-

ing signal is derived from the high-voltage battery. A

battery switch is included to allow for use of a lower-

voltage battery in the off-hook mode, thus minimizing

short-loop off-hook power.

■ Eight operating states:

— Scan mode for minimal power dissipation

— Forward and reverse battery active

— On-hook transmission states

— Ground start (tip open)

— Ring mode

— Disconnect mode

Loop closure, ring trip, and ground start detectors are

available. The loop closure detector has a fixed

threshold with hysteresis. The ring trip detector

requires a single-pole filter, thus minimizing external

components required.

■ Ultralow on-hook power:

— 27 mW scan mode

— 41 mW active mode

■ Two SLIC gain options to minimal external compo-

nents in codec interface

The dc current limit is set and fixed by a logic control-

lable pin. Ground or open is applied to this pin set the

current limit at the low or high value.

■ Loop start, ring trip, and ground start detectors

■ Software-controllable dual current-limit option

■ 28-pin PLCC package

The device is offered with two gain options. This

allows for an optimized codec interface, with minimal

external components regardless of whether a first-

generation or a programmable third-generation

codec is used.

■ 48-pin MLCC package

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Table of Contents

Page Contents

Contents

Page

Introduction..................................................................1

Features....................................................................1

Applications...............................................................1

Description................................................................1

Features ......................................................................4

Description...................................................................4

Architecture Diagram...................................................7

Pin Information ............................................................8

Operating States .......................................................10

State Definitions ........................................................11

Forward Active........................................................11

Reverse Active........................................................11

Scan........................................................................11

On-Hook Transmission—Forward Battery..............11

On-Hook Transmission—Reverse Battery..............11

Disconnect ..............................................................11

Ring.........................................................................11

Ground Start ...........................................................11

Thermal Shutdown..................................................12

Absolute Maximum Ratings (@ T^A= 25 °C) ..............12

Electrical Characteristics ...........................................13

Test Configurations ...................................................20

Applications ...............................................................22

Power Control .........................................................22

dc Loop Current Limit..............................................23

Overhead Voltage...................................................23

Active Mode .........................................................23

Scan Mode ...........................................................23

On-Hook Transmission Mode...............................23

Ring Mode............................................................24

Loop Range ............................................................24

Battery Reversal Rate.............................................24

Supervision................................................................24

Loop Closure...........................................................24

Ring Trip .................................................................24

Tip or Ring Ground Detector...................................24

Power Ring .............................................................25

Sine Wave Input Signal and Sine Wave

ac Applications ......................................................... 32

ac Parameters........................................................ 32

Codec Types.......................................................... 32

First-Generation Codecs ..................................... 32

Third-Generation Codecs.................................... 32

ac Interface Network .............................................. 32

Design Examples................................................... 34

First-Generation Codec ac Interface

Network—Resistive Termination ...................... 34

Example 1, Real Termination.............................. 34

First-Generation Codec ac Interface

Network—Complex Termination....................... 37

Complex Termination Impedance Design

Example............................................................ 37

ac Interface Using First-Generation Codec......... 37

Transmit Gain...................................................... 38

Receive Gain....................................................... 39

Hybrid Balance.................................................... 39

Blocking Capacitors ............................................ 40

Third-Generation Codec ac Interface

Network—Complex Termination....................... 42

Outline Diagrams...................................................... 44

28-Pin PLCC .......................................................... 44

48-Pin MLCC.......................................................... 45

48-Pin MLCC, JEDEC MO-220 VKKD-2................ 46

Ordering Information ................................................ 47

Power Ring Signal Output .................................26

PWM Input Signal and Sine Wave Power

Ring Signal Output.............................................28

5 V V^CCOperation................................................29

3.3 V V^CCOperation .............................................30

Square Wave Input Signal and Trapezoidal

Power Ring Signal Output .................................30

2

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC w/ Ground Start

Table of Contents (continued)

Page Tables

Figures

Page

Figure 1. Architecture Diagram ...................................7

Figure 2. 28-Pin PLCC ...............................................8

Figure 3. 48-Pin MLCC................................................8

Figure 4. Basic Test Circuit ......................................20

Figure 5. Metallic PSRR ...........................................21

Figure 6. Longitudinal PSRR ....................................21

Figure 7. Longitudinal Balance .................................21

Figure 8. ac Gains ....................................................21

Figure 9. Ringing Waveform Crest Factor = 1.6 .......25

Figure 10. Ringing Waveform Crest Factor = 1.2 .....25

Figure 11. Ring Mode Typical Operation ..................26

Figure 12. RING^INOperation ....................................27

Figure 13. L9215/16 Ringing Input Circuit Selection

Table for Square Wave and PWM

Table 1. Pin Descriptions .......................................... 9

Table 2. Control States............................................. 10

Table 3. Supervision Coding ................................... 10

Table 4. Recommended Operating

Characteristics .......................................... 12

Table 5. Thermal Characteristics.............................. 12

Table 6. Environmental Characteristics.................... 13

Table 7. 5 V Supply Currents ................................... 13

Table 8. 5 V Powering .............................................. 13

Table 9. 3.3 V Supply Currents ............................... 14

Table 10. 3.3 V Powering ......................................... 14

Table 11. 2-Wire Port .............................................. 15

Table 12. Analog Pin Characteristics ..................... 16

Table 13. ac Feed Characteristics .......................... 17

Table 14. Logic Inputs and Outputs (V^CC= 5 V) ..... 18

Table 15. Logic Inputs and Outputs (V^CC= 3.3 V) .. 18

Table 16. Ground Start ............................................ 18

Table 17. Ringing Specifications ............................. 19

Table 18. Ring Trip .................................................. 19

Table 19. Typical Active Mode On- to Off-Hook

Tip/Ring Current-Limit Transient

Inputs .......................................................28

Figure 14. Modulation Waveforms ............................29

Figure 15. 5 V PWM Signal Amplitude .....................29

Figure 16. Ringing Output on RING, with

V^CC= 5 V .................................................29

Figure 17. 3.3 V PWM Signal Amplitude ..................30

Figure 18. Ringing Output on RING, with

V^CC= 3.1 V ..............................................30

Figure 19. Square Wave Input Signal and

Response ................................................ 23

Table 20. FB1 and FB2 Values vs. Typical Ramp

Time ......................................................... 24

Table 21. Onset of Power Ringing Clipping

V^CC= 5 V, Cinput = 0.47 µF ................... 27

Table 22. Onset of Power Ringing Clipping

V^CC= 3.1 V, Cinput = 0.47 µF ................ 27

Table 23. Signal and Component Selection Chart ... 28

Table 24. Parts List L9216; Agere T7504 First-

Generation Codec Resistive Termination;

Trapezoidal Power Ring Signal Output ...30

Figure 20. Crest Factor vs. Battery Voltage .............31

Figure 21. Crest Factor vs. R (kΩ) ...........................31

Figure 22. ac Equivalent Circuit ................................35

Figure 23. Agere T7504 First-Generation Codec

Resistive Termination ..............................35

Figure 24. Interface Circuit Using First-Generation

Codec (Blocking Capacitors Not

Shown) ....................................................38

Figure 25. ac Interface Using First-Generation Codec

(Including Blocking Capacitors) for

Nonmeter Pulse Application ................... 36

Table 25. Parts List L9216; Agere T7504 First-

Generation Codec Complex Termination;

Complex Termination Impedance ...........40

Figure 26. Agere T7504 First-Generation Codec

Complex Termination ..............................40

Meter Pulse Application ........................... 41

Table 26. Parts List L9216; Agere T8536

Third-Generation Codec ac and

Figure 27. Third-Generation Codec ac Interface

Network; Complex Termination ...............42

dc Parameters; Fully Programmable ...... 43

Agere Systems Inc.

3

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

■ Adjustable current limit:

— 25 mA or 40 mA via ground or open to control

input

Features

■ Onboard balanced ringing generation:

— No ring relay

■ Overhead voltage:

— No bulk ring generator required

— 15 Hz to 70 Hz ring frequency supported

— Sine wave input-sine wave output

— PWM input-sine wave output

— Square wave input-trapezoidal output

— Clamped typically <51 V differentially

— Clamped maximum <56.5 V single-ended

■ Thermal shutdown protection with hysteresis

■ Longitudinal balance:

— Telcordia Technologies GR-909 balance

■ Power supplies requirements:

— V^CCtalk battery and ringing battery required

— No –5 V supply required

— No high-voltage positive supply required

■ ac interface:

— Two SLIC gain options to minimize external com-

ponents required for interface to first- or third-gen-

eration codecs

■ Flexible Vcc options:

— Sufficient dynamic range for direct coupling to

codec output

— 5 V or 3.3 V V^CCoperation

— 5 V or 3.3 V V^CCinterchangeable and transparent

to users

■ 28-pin PLCC/48-pin MLCC package

■ 90 V CBIC-S technology

■ Battery switch via logic control:

— Minimize off-hook power dissipation

■ Minimal external components required

Description

■ Eight operating states:

— Forward active, V^BAT2applied

— Polarity reversal active, V^BAT2applied

— On-hook transmission, V^BAT1applied

— On-hook transmission polarity reversal, V^BAT1

applied

The L9216 is designed to provide battery feed, ringing,

and supervision functions on short plain old telephone

service (POTS) loops. This device is designed for

ultralow power in all operating states.

— Ground start

— Scan

— Forward disconnect

The L9216 offers eight operating states. The device

assumes uses of a lower-voltage talk battery, a higher-

voltage ringing battery, and a V^CCsupply.

— Ring mode

The L9216 requires only a positive V^CCsupply. No

–5 V supply is needed. The L9216 can operate with a

V^CCof either 5 V or 3.3 V, allowing for greater user flex-

ibility. The choice of V^CCvoltage is transparent to the

user; the device will function with either supply voltage

connected.

■ Unlatched parallel data control interface

■ Ultralow SLIC power:

— Scan 37 mW (V^CC= 5 V)

— Forward/reverse active 54 mW (V^CC= 5 V)

— Scan 27 mW (V^CC= 3.3 V)

— Forward/reverse active 41 mW (V^CC= 3.3 V)

Two batteries are used:

■ Supervision:

1. A high-voltage ring battery (V^BAT1).

— Loop start, fixed threshold with hysteresis

— Ring trip, single-pole ring trip filtering, fixed thresh-

old as a function of battery voltage

— Ring current for ground start applications, user-

adjustable threshold

V^BAT1is a maximum –75 V. VBAT1 is used for power

ring signal amplification and for scan, on-hook

transmission, and ground start modes. This supply

is current limited to approximately the maximum

power ringing current, typically 50 mA.

2. A lower-voltage talk battery (V^BAT2).

V^BAT2is used for active mode powering.

4

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

The device offers a ground start mode. In this mode,

the tip drive amplifier is turned off. The device presents

a high impedance (>100 kΩ) to PT and a current-lim-

ited battery (V^BAT1) to PR. VBAT1 is clamped to less than

56.5 V in this mode as PR. A ring current detector for

ring ground detection is included for ground start appli-

cations. The threshold is user programmable via exter-

nal resistors. See the Applications section of this data

sheet for more information on supervision functions.

Output pin RGDET indicates current flowing in the ring

lead.

Description (continued)

Forward and reverse battery active modes are used for

off-hook conditions. Since this device is designed for

short-loop applications, the lower-voltage V^BAT2is

applied during the forward and reverse active states.

Battery reversal is quiet, without breaking the ac path.

Rate of battery reversal may be ramped to control

switching time.

The magnitude of the overhead voltage in the forward

and reverse active modes has a typical default value of

6.0 V, allowing for an undistorted signal of 3.14 dBm

into 900 Ω. This overhead is fixed. The ring trip detec-

tor is turned off during active modes to conserve power.

Both the ring trip and loop closure supervision func-

tions are included. The loop closure has a fixed typical

10.5 mA on- to off-hook threshold in the active mode

and a fixed 11.5 mA on- to off-hook threshold from the

scan mode. In either case, there is a 2 mA hysteresis.

The ring trip detector requires only a single-pole filter at

the input, minimizing external components. The ring

trip threshold at a given battery voltage is fixed. Typical

ring trip threshold is 42.5 mA for a –70 V V^BAT1.

Because on-hook transmission is not allowed in the

scan mode, an on-hook transmission mode is defined.

This mode is functionally similar to the active mode,

except the tip ring voltage is derived from the higher

V^BAT1rather than VBAT2.

In the on-hook transmission modes with a primary

battery whose magnitude is greater than a nominal

51 V, the magnitude of the tip to ground and ring to

ground voltage is clamped at less than 56.5 V.

Upon reaching the thermal shutdown temperature, the

device will enter an all-off mode. Upon cooling, the

device will re-enter the state it was in prior to thermal

shutdown. Hysteresis is built in to prevent oscillation.

To minimize on-hook power, a low-power scan mode is

available. In this mode, all functions except off-hook

supervision are turned off to conserve power. On-hook

transmission is not allowed in the scan mode.

Longitudinal balance is consistent with North American

GR-909 requirements. Specifications are given in Table

12.

Data control is via a parallel unlatched control scheme.

In the scan mode with a primary battery whose magni-

tude is greater than a nominal 51 V, the magnitude of

the tip to ground and ring to ground voltage is clamped

at less than 56.5 V.

The dc current limit is fixed to either 25 mA or 40 mA

depending if ground or open is applied to the V^PROG

current-limit programming pin. Programming accuracy

is ±8%.

A forward disconnect mode is provided, where all cir-

cuits are turned off and power is denied to the loop.

Circuitry is added to the L9216 to minimize the inrush

of current from the V^CCsupply and to the battery supply

during an on- to off-hook transition, thus saving in

power supply design cost. See the Applications section

of this data sheet for more information.

The device offers a ring mode, in which a power ring

signal is provided to the tip/ring pair. During the ring

mode, a user-supplied low-voltage ring signal (ac-cou-

pled) is input to the device’s RING^INinput. This signal is

amplified to produce the power ring signal. This signal

may be a sine wave or filtered square wave to produce

a sine wave on trapezoidal output. Ring trip detector

and common-mode current detector are active during

the ring mode.

Overhead in the active modes (V^BAT2applied) is fixed

to approximately 6.0 V is achieved. This is adequate

for a 3.14 dBm overload into 900 Ω.

Transmit and receive gains have been chosen to mini-

mize the number of external components required in

the SLIC-codec ac interface, regardless of the choice

of codec.

This feature eliminates the need for a separate external

ring relay, associated external circuitry, and a bulk ring-

ing generator. See the Applications section of this data

sheet for more information.

Agere Systems Inc.

5

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

performance, it is best to operate the codec at a higher

gain level. If the SLIC then provides a high gain, the

SLIC output may be saturated causing clipping distor-

tion of the signal at tip and ring. To avoid this situation,

with a higher gain SLIC, external resistor dividers are

used. These external components are not necessary

with the lower gain offered by the L9216. See the Appli-

cations section of this data sheet for more information.

Description (continued)

The L9216 uses a voltage feed-current sense architec-

ture; thus, the transmit gain is a transconductance. The

L9216 transconductance is set via a single external

resistor, and this device is designed for optimal perfor-

mance with a transconductance set at 300 V/A.

The L9216 offers an option for a single-ended to differ-

ential receive gain of either 8 or 2. These options are

mask programmable at the factory and are selected by

choice of code.

The L9216 is internally referenced to 1.5 V. This refer-

ence voltage is output at the V^REFoutput of the device.

The SLIC output VITR is also referenced to 1.5 V;

therefore, it must be ac coupled to the codec input.

However, the SLIC inputs RCVP/RCVN are floating

inputs. If there is not feedback from RCVP/RCVN to

VITR, RCVP/RCVN may be directly coupled to the

codec output. If there is feedback from RCVP/RCVN to

VITR, RCVP/RCVN must be ac coupled to the codec

output.

A receive gain of 8 is more appropriate when choosing

a first-generation type codec where termination imped-

ance, hybrid balance, and overall gains are set by

external analog filters. The higher gain is typically

required for synthesization of complex termination

impedance.

A receive gain of 2 is more appropriate when choosing

a third-generation type codec. Third-generation codecs

will synthesize termination impedance and set hybrid

balance and overall gains. To accomplish these func-

tions, third-generation codecs typically have both ana-

log and digital gain filters. For optimal signal to noise

The L9216 is packaged in a 28-pin PLCC package and

an ultrasmall 48-pin MLCC package. Use L9216A for

gain of eight applications and L9216G for gain of two

applications.

6

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Architecture Diagram

AGND

V^CC

BGND VBAT2

VBAT1

VPROG

NSTAT

RTFLT DCOUT

VREF

CURRENT

LIMIT

RING

TRIP

AND

VITR

POWER

INRUSH

CONTROL

B = 20

LOOP

CLOSURE

AAC

1.5 V

BAND-GAP

COMMON-

MODE

CURRENT

DETECTOR

ICM

REFERENCE

TXI

ITR

VTX

RECTIFIER

X1

RGDET

–

(ITR/306)

OUT

AX

VTX

CF2

VREF

+

–

RFT

PT

+1

18 Ω

+

ITR

X1

CF1

VREG

TIP/RING

CURRENT

SENSE

FB2

FB1

–

RCVN

RCVP

ITR

+

–

GAIN

RFR

PR

–1

+

18 Ω

ac INTERFACE

9216A GAIN = 4

9216G GAIN = 1

VREG

PARALLEL

DATA

INTERFACE

RINGING

27.5x

RINGIN

B0 B1 B2

12-3530.E (F)

Figure 1. Architecture Diagram

Agere Systems Inc.

7

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Pin Information

4

3

2

1

28 27 26

25

RINGIN

DCOUT

VPROG

CF2

5

6

7

8

9

B0

24

23

22

21

20

19

B1

B2

L9216

PR

PT

28-PIN PLCC

CF1

RTFLT

10

11

FB1

FB2

VREF

12 13 14 15 16 17 18

12-3558.d (F)

Figure 2. 28-Pin PLCC

48 47 46 45 44 43 42 41 40 39 38 37

1

36

35

34

33

32

31

30

29

28

27

26

25

NC

B0

RINGIN

NC

2

3

B1

NC

4

B2

NC

5

NC

PR

NC

PT

NC

6

DCOUT

VPROG

NC

L9216A/G

48-PIN MLCC

7

8

9

NC

FB1

FB2

CF2

10

11

12

CF1

NC

RTFLT

13 14 15 16 17 18 19 20 21 22 23 24

Figure 3. 48-Pin MLCC

8

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Pin Information (continued)

Table 1. Pin Descriptions

28-Pin

PLCC

48-Pin

MLCC

Symbol

Type

Name/Function

1

2

3

4

5

43

45

47

48

1

NSTAT

O

Loop Closure Detector Output—Ring Trip Detector Output.

When low, this logic output indicates that an off-hook condition

exists or ringing is tripped.

VITR

RCVP

RCVN

RING^IN

O

I

Transmit ac Output Voltage. Output of internal AAC amplifier.

This output is a voltage that is directly proportional to the differen-

tial ac tip/ring current.

Receive ac Signal Input (Noninverting). This high-impedance

input controls the ac differential voltage on tip and ring. This node

is a floating input.

I

Receive ac Signal Input (Inverting). This high-impedance input

controls the ac differential voltage on tip and ring. This node is a

floating input.

I

Power Ring Signal Input. ac-couple to a sine wave or lower crest

factor low-voltage ring signal. The input here is amplified to pro-

vide the full power ring signal at tip and ring. This signal may be

applied continuously, even during nonringing states.

6

7

6

7

DCOUT

V^PROG

O

I

dc Output Voltage. This output is a voltage that is directly propor-

tional to the absolute value of the differential tip/ring current. This

is used to set ring trip threshold.

Current-Limit Program Input. Connect ground to this pin to set

current-limit to 25 mA, float to this pin to set current limit to 40 mA.

8

9

CF2

CF1

—

Filter Capacitor. Connect a capacitor from this node to ground.

Filter Capacitor. Connect a capacitor from this node to CF2.

10

12

10

RTFLT

Ring Trip Filter. Connect this lead to DCOUT via a resistor and to

AGND with a capacitor to filter the ring trip circuit to prevent spuri-

ous responses. A single-pole filter is needed.

11

13

V^REF

O

SLIC Internal Reference Voltage. Output of internal 1.5 V refer-

ence voltage.

12

13

15

16

AGND

V^CC

GND Analog Signal Ground.

PWR Analog Power Supply. User choice of 5 V or 3.3 V nominal power

or supply.

14

15

16

—

19

20

22

V^BAT1

V^BAT2

BGND

NC

PWR Battery Supply 1. High-voltage battery.

PWR Battery Supply 2. Lower-voltage battery.

GND Battery Ground. Ground return for the battery supplies.

2, 3, 4, 5, 8,

11, 14, 17,

18, 21, 27,

28, 30, 32,

36, 37, 39,

42, 44, 46

—

No Connection.

17

18

23

RGDET

ICM

O

I

Ring Ground Detect. When high, this open collector output indi-

cates the presence of a ring ground or a tip ground. This supervi-

sion output may be used in ground key, ground start or common-

mode fault detection applications.

24

Common-Mode Current Sense. To program tip or ring ground

sense threshold, connect a resistor to V^CCand connect a capacitor

to AGND to filter 50/60 Hz. If unused, the pin is connected to

ground.

Agere Systems Inc.

9

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Pin Information (continued)

Table 1. Pin Descriptions (continued)

28-Pin

PLCC

48-Pin

MLCC

Symbol

Type

Name/Function

19

20

21

22

25

26

29

31

FB2

—

Polarity Reversal Slowdown Capacitor. Connect a capacitor from

this node to ground for controlling rate of battery reversal. If ramped

battery reversal is not desired, this pin is left open.

FB1

PT

—

Polarity Reversal Slowdown Capacitor. Connect a capacitor from

this node to ground for controlling rate of battery reversal. If ramped

battery reversal is not desired, this pin is left open.

I/O Protected Tip. The output drive of the tip amplifier and input to the

loop sensing circuit. Connect to loop through overvoltage and overcur-

rent protection.

PR

I/O Protected Ring. The output drive of the ring amplifier and input to the

loop sensing circuit. Connect to loop through overvoltage and overcur-

rent protection.

23

24

25

26

33

34

35

38

B2

B1

I^d

I

State Control Input. These pins have an internal 110 kΩ pull-down.

B0

ITR

Transmit Gain. Input to AX amplifier. Connect a 4.75 kΩ resistor from

this node to VTX to set transmit gain. Gain shaping for termination

impedance with a first-generation codec is also achieved with a net-

work from this node to VTX.

27

28

40

41

VTX

TXI

O

I

ac Output Voltage. Output of internal AX amplifier. The voltage at this

pin is directly proportional to the differential tip/ring current.

ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1 µF

capacitor from this pin to VTX.

Operating States

Table 2. Control States

B0

1

B1

1

B2

0

State

Forward active

1

0

Reverse active

1

On-hook transmission forward battery

1

0

1

On-hook transmission reverse battery

0

1

Ground start

0

1

Scan

0

Disconnect, device will power up in this state

Ring

0

1

0

Table 3. Supervision Coding

NSTAT

RGDET

0 = off-hook or ring trip or TSD.

0 = no ring or tip ground.

1 = on-hook and no ring trip and no TSD or DISCONNECT state. 1 = ring or tip ground.

10

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

On-Hook Transmission—Reverse Battery

State Definitions

■ Pin PR is positive with respect to PT.

Forward Active

■ VBAT1 is applied to tip/ring drive amplifiers.

■ Pin PT is positive with respect to PR.

■ Supervision circuits, loop closure, and common-

mode detect are active.

■ VBAT2 is applied to tip/ring drive amplifiers.

■ Loop closure and common-mode detect are active.

■ Ring trip detector is turned off to conserve power.

■ On-hook transmission is allowed.

■ Overhead is set to nominal 6.0 V for undistorted

transmission of 3.14 dBm into 900 Ω.

■ The tip-to-ring on-hook differential voltage will be typ-

ically between –41 V and –49 V with a –70 V primary

battery.

Reverse Active

Disconnect

■ Pin PR is positive with respect to PT.

■ The tip/ring amplifiers and all supervision are turned

■ VBAT2 is applied to tip/ring drive amplifiers.

■ Loop closure and common-mode detect are active.

■ Ring trip detector is turned off to conserve power.

off.

■ The SLIC goes into a high-impedance state.

■ NSTAT is forced high (on-hook).

■ Overhead is set to nominal 6.0 V for undistorted

transmission of 3.14 dBm into 900 Ω.

■ Device will power up in this state.

Ring

Scan

■ Power ring signal is applied to tip and ring.

■ Input waveform at RINGIN is amplified.

■ Except for loop closure, all circuits (including ring trip

and common-mode detector) are powered down.

■ On-hook transmission is disabled.

■ Ring trip supervision and common-mode current

supervision are active; loop closure is inactive.

■ Pin PT is positive with respect to PR, and VBAT1 is

applied to tip/ring.

■ Overhead voltage is reduced to typically 4 V.

■ The tip to ring on-hook differential voltage will be typ-

icallybetween –44 V and –51 V with a –70 V primary

battery.

■ Current is limited by saturation current of the amplifi-

ers themselves, typically 100 mA at 125 °C.

Ground Start

On-Hook Transmission—Forward Battery

■ Tip drive amplifer is turned off.

■ Pin PT is positive with respect to PR.

■ Device presents a high impedance (>100 kΩ) to pin

PT.

■ VBAT1 is applied to tip/ring drive amplifiers.

■ Supervision circuits, loop closure, and common-

mode detect are active.

■ Device presents a clamped (<56.5 V) current-limited

battery (V^BAT1) to PR.

■ Ring trip detector is turned off to conserve power.

■ On-hook transmission is allowed.

■ Output pin RGDET indicates current flowing in the

ring lead.

■ The tip-to-ring on-hook differential voltage will be typ-

ically between –41 V and –49 V with a –70 V primary

battery.

Thermal Shutdown

■ Not controlled via truth table inputs.

■ NSTAT is forced low (off-hook) during this state.

■ This mode is caused by excessive heating of the

device, such as may be encountered in an extended

power cross situation.

Agere Systems Inc.

11

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Absolute Maximum Ratings (@ TA = 25 °C)

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter

Symbol

Min

–0.5

—

Typ

—

Max

7.0

Unit

V

dc Supply (V^CC)

—

Battery Supply (V^BAT1)

—

–80

V

Battery Supply (V^BAT2)

—

VBAT1

V^CC+ 0.5

125

V

Logic Input Voltage

—

–0.5

–40

V

Logic Output Voltage

—

V

Operating Temperature Range

Storage Temperature Range

Relative Humidity Range

°C

%

V

—

–40

150

—

5

95

PT or PR Fault Voltage (dc)

PT or PR Fault Voltage (10 x 1000 µs)

Ground Potential Difference (BGND to AGND)

VPT, VPR

VBAT – 5

3

VPT, VPR VBAT – 15

15

V

—

±1

V

Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when

powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the

device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.

Table 4. Recommended Operating Characteristics

Parameter

5 V dc Supplies (V^CC)

Min

—

Typ

5.0

3.3

–70

—

Max

5.25

—

Unit

V

3 V dc Supplies (V^CC)

3.13

–60

–12

–40

V

High Office Battery Supply (V^BAT1)

Auxiliary Office Battery Supply (V^BAT2)

Operating Temperature Range

–75

VBAT1

85

V

25

°C

Table 5. Thermal Characteristics

Parameter

Min

Typ

Max

Unit

Thermal Protection Shutdown (Tjc)¹

150

165

—

°C

28-pin PLCC Thermal Resistance Junction to Ambient (θ^JA)²:

Natural Convection 2S2P Board

Natural Convection 2S0P Board

Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board

Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board

—

35.5

50.5

31.5

42.5

—

°C/W

48-pin MLCC Thermal Resistance Junction to Ambient (θ^JA)^{1, 2}

—

38

—

°C/W

1. This parameter is not tested in production. It is guaranteed by design and device characterization.

2. Airflow, PCB board layers, and other factors can greatly affect this parameter.

12

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics

Table 6. Environmental Characteristics

Parameter

Min

–40

5

Typ

—

Max

85

95¹

Unit

°C

Temperature Range

Humidity Range¹

—

%RH

1. Not to exceed 26 grams of water per kilogram of dry air.

Table 7. 5 V Supply Currents

V^BAT1= –70 V, VBAT2 = –21 V, VCC = 5 V.

Parameter

Min

Typ

Max

Unit

Supply Currents (scan state; no loop current):

I^VCC

IVBAT1

IVBAT2

—

4.30

0.24

3

4.80

0.35

6

mA

µA

Supply Currents (forward/reverse active; no loop current, with or without PPM,

V^BAT2applied):

I^VCC

IVBAT1

—

5.95

25

1.2

7.0

85

1.40

mA

µA

mA

IVBAT2

Supply Currents (on-hook transmission mode; no loop current, with or without

PPM, V^BAT1applied):

I^VCC

IVBAT1

IVBAT2

—

6.0

1.5

7.0

1.9

6

mA

µA

Supply Currents (disconnect mode):

I^VCC

IVBAT1

IVBAT2

—

2.7

15

3.5

3.75

110

25

mA

µA

Supply Currents (ground start mode, no loop current):

I^VCC

IVBAT1

IVBAT2

—

4.0

0.24

2

—

mA

µA

Supply Currents (ring mode; no load):

I^VCC

IVBAT1

IVBAT2

—

5.9

1.8

2

6.5

2.2

6

mA

µA

Table 8. 5 V Powering

V^BAT1= –70 V, VBAT2 = –21 V, VCC = 5 V.

Parameter

Min

—

Typ

38

Max

46

Unit

mW

Power Dissipation (scan state; no loop current)

Power Dissipation (forward/reverse active; no loop current, V^BAT2applied)

Power Dissipation (on-hook transmission mode; no loop current, V^BAT1applied)

Power Dissipation (disconnect mode)

—

57

64

—

135

14

165

23

—

Power Dissipation (ground start mode)

—

37

—

Power Dissipation (ring mode; no load)

—

156

184

Agere Systems Inc.

13

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics (continued)

Table 9. 3.3 V Supply currents

V^BAT1= –70 V, VBAT2 = –21 V, VCC = 3.3 V.

Parameter

Min

Typ

Max

Unit

Supply Currents (scan state; no loop current):

I^VCC

IVBAT1

IVBAT2

—

3.2

0.24

3

3.6

0.35

6

mA

µA

Supply Currents (forward/reverse active; no loop current, V^BAT2applied):

I^VCC

IVBAT1

IVBAT2

—

4.8

25

1.2

5.7

85

1.4

mA

µA

mA

Supply Currents (on-hook transmission mode; no loop current, V^BAT1applied):

I^VCC

IVBAT1

IVBAT2

—

4.9

1.5

5.7

1.9

6

mA

µA

Supply Currents (disconnect mode):

I^VCC

IVBAT1

IVBAT2

—

1.8

8

2

2.5

110

25

mA

µA

Supply Currents (ground start mode, no loop current):

I^VCC

IVBAT1

IVBAT2

—

3.1

0.24

2

—

mA

µA

Supply Currents (ring mode; no load):

I^VCC

IVBAT1

IVBAT2

—

4.70

1.8

2

5.4

2.2

6

mA

µA

Table 10. 3.3 V Powering

VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.

Parameter

Min

—

Typ

27

Max

36.5

53

Unit

mW

Power Dissipation (scan state; no loop current)

Power Dissipation (forward/reverse active; no loop current, V^BAT2applied)

Power Dissipation (on-hook transmission mode; no loop current, V^BAT1applied)

Power Dissipation (disconnect mode)

—

42

—

121

6.5

27

151

15

—

Power Dissipation (ground start mode)

—

Power Dissipation (ring mode; no loop current)

—

141

172

14

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics (continued)

Table 11. 2-Wire Port

Parameter

Tip or Ring Drive Current = dc + Longitudinal + Signal Currents

Tip or Ring Drive Current = Ringing + Longitudinal

Signal Current

Min

105

65

Typ

—

Max

—

Unit

mAp

—

mAp

10

—

mArms

Longitudinal Current Capability per Wire (Longitudinal current is indepen-

dent of dc loop current.)

8.5

15

—

Ringing Current (RLOAD = 1386 Ω + 40 µF)

Ringing Current Limit (R^LOAD= 100 Ω)

29

—

mArms

mAp

50

dc Loop Current—I^LIM(VBAT2 applied, RLOOP = 100 Ω):

V^PROG= 0

V^PROG= Open

—

25

40

—

mA

dc Current Variation

—

±8

—

%

dc Feed Resistance (does not include protection resistors)

50

Ω

Open Loop Voltages:

Scan Mode:

PR to Battery Ground

PT to Battery Ground

OHT Mode:

44

—

51

—

56.5

V

PR to Battery Ground

PT to Battery Ground

Active Mode:

41

—

49

—

56.5

V

|PT – PR| – |V^BAT2|

Ring Mode:

|PT – PR| – |V^BAT1|

5.75

—

6.25

4

6.75

—

V

Agere Systems Inc.

15

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics (continued)

Table 11. 2-Wire Port (continued)

Parameter

Min

Typ

Max

Unit

Loop Closure Threshold:

Active/On-hook Transmission Modes

Scan Mode

—

10.5

11.5

—

mA

Loop Closure Threshold Hysteresis:

V^CC= 5 V Active Mode

V^CC= 3.3 V Active Mode

V^CC= 5 V Ground Start Mode

V^CC= 3.3 V Ground Start Mode

—

2

1

6

5

—

mA

Longitudinal to Metallic Balance at PT/PR

Test Method: Q552 (11/96) Section 2.1.2 and IEEE^®455:

300 Hz to 600 Hz

52

—

dB

600 Hz to 3.4 kHz

Metallic to Longitudinal (harm) Balance:

200 Hz to 1000 Hz

100 Hz to 4000 Hz

40

—

dB

PSRR 500 Hz—3000 Hz:

V^BAT1, VBAT2

VCC (5 V operation)

45

35

—

dB

Table 12. Analog Pin Characteristics

Parameter

Min

Typ

Max

Unit

TXI (input impedance)

—

100

—

kΩ

Output Offset (VTX)

Output Offset (VITR)

—

±300

±10

—

±10

100

—

mV

µA

Output Drive Current (VTX)

Output Drive Current (VITR)

Output Voltage Swing:

Maximum (VTX, VITR)

Minimum (VTX)

—

µA

AGND

AGND + 0.25

AGND + 0.35

—

20

V^CC

V^CC– 0.5

V^CC– 0.4

±50

V

mA

kΩ

pF

Minimum (VITR)

Output Short-circuit Current

Output Load Resistance

Output Load Capacitance

—

10

—

RCVN and RCVP:

Input Voltage Range (V^CC= 5 V)

Input Voltage Range (V^CC= 3.3 V)

Input Bias Current

0

—

0.05

V^CC– 0.5

V^CC– 0.3

—

V

µA

Differential PT/PR Current Sense (DCOUT):

Gain (PT/PR to DCOUT)

Offset Voltage at I^LOOP= 0

—

–20

67

—

20

V/A

mV

16

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics (continued)

Table 13. ac Feed Characteristics

Parameter

Min

Typ

Max

Unit

ac Termination Impedance¹

150

600

1400

Ω

Total Harmonic Distortion (200 Hz—4 kHz)²:

Off-hook

On-hook

—

0.3

1.0

%

Transmit Gain (f = 1004 Hz, 1020 Hz, current limit)³:

PT/PR Current to VITR

300 – 3%

300

300 + 3%

V/A

Receive Gain, f = 1004 Hz, 1020 Hz Open Loop:

RCVP or RCVN to PT—PR (gain of 8 option, L9216A)

RCVP or RCVN to PT—PR (gain of 2 option, L9216G)

7.76

1.94

8

2

8.24

2.06

—

Gain vs. Frequency (transmit and receive)²600 Ω Termination,

1004 Hz, 1020 Hz Reference:

200 Hz—300 Hz

300 Hz—3.4 kHz

3.4 kHz—20 kHz

–0.3

–0.05

–3.0

—

0

0.05

2.0

dB

20 kHz—266 kHz

—

Gain vs. Level (transmit and receive)²0 dBV Reference:

–55 dB to +3.0 dB

–0.05

0

0.05

dB

Idle-channel Noise (tip/ring) 600 Ω Termination:

Psophometric

C-Message

3 kHz Flat

—

–82

8

—

–77

13

20

dBmp

dBrnC

dBrn

Idle-channel Noise (VTX) 600 Ω Termination:

Psophometric

C-Message

3 kHz Flat

—

–82

8

—

–77

13

20

dBmp

dBrnC

dBrn

1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between

150 Ω and 1400 Ω can be synthesized.

2. This parameter is not tested in production. It is guaranteed by design and device characterization.

3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω, the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR.

Agere Systems Inc.

17

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics (continued)

Table 14. Logic Inputs and Outputs (V^CC= 5 V)

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

Low Level

High Level

V^IL

VIH

–0.5

2.0

0.4

2.4

0.7

V^CC

V

Input Current:

Low Level (V^CC= 5.25 V, VI = 0.4 V)

High Level (V^CC= 5.25 V, VI = 2.4 V)

I^IL

IIH

—

±50

µA

Output Voltages (open collector with internal pull-up resistor):

Low Level (V^CC= 4.75 V, IOL = 200 µA)

High Level (V^CC= 4.75 V, IOH = –20 µA)

V^OL

VOH

0

2.4

0.2

—

0.4

V^CC

V

Table 15. Logic Inputs and Outputs (V^CC= 3.3 V)

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

Low Level

High Level

V^IL

VIH

–0.5

2.0

0.2

2.5

0.5

V^CC

V

Input Current:

Low Level (V^CC= 3.46 V, VI = 0.4 V)

High Level (V^CC= 3.46 V, VI = 2.4 V)

I^IL

IIH

—

±50

µA

Output Voltages (open collector with internal 60 kΩ pull-up resistor):

Low Level (V^CC= 3.13 V, IOL = 200 µA)

High Level (V^CC= 3.13 V, IOH = –5 µA)

V^OL

VOH

0

2.2

0.2

—

0.5

V^CC

V

Table 16. Ground Start

Parameter

Min

Typ

Max

Unit

Tip Open Mode:

Tip Input Impedance

150

—

20

—

kΩ

%

Detector Accuracy

Detection

50

ms

18

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Electrical Characteristics (continued)

Table 17. Ringing Specifications

Parameter

Min

Typ

Max

Unit

RING^IN(This input is ac coupled through 0.47 µF.):

Input Voltage Swing

Input Impedance

0

—

100

V^CC

—

V

kΩ

Ring Signal Isolation:

PT/PR to VITR

Ring Mode

—

60

—

dB

Ring Signal Isolation:

RING^INto PT/PR

Nonring Mode

—

80

—

dB

Ringing Voltage (5 REN 1380 Ω + 40 µF load, 100 Ω loop, 2 x 50 Ω protection

resistors, –70 V battery)

40

—

Vrms

Ringing Voltage (3 REN 2310 Ω + 24 µF load, 250 Ω loop, 2 x 50 Ω protection

resistors, –70 V battery)

Ring Signal Distortion:

5 REN 1380 Ω, 40 µF Load, 100 Ω Loop

3 REN 2310 Ω, 24 µF Load, 250 Ω Loop

—

3

—

%

Differential Gain:

RING^INto PT/PR—No Load

—

55

—

Table 18. Ring Trip

Parameter

Min

Typ

Max

Unit

Ring Trip (NSTAT = 0): Loop Resistance (total) High Battery

Ring Trip (NSTAT = 1): Loop Resistance (total) High Battery

Trip Time (f = 20 Hz)

100

—

600

10

Ω

kΩ

ms

—

100

Ringing will not be tripped by the following loads:

■ 10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

■ 100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

Agere Systems Inc.

19

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Test Configurations

RTFLT

RINGIN

RING^IN

0.1 µF

0.47 µF

383 kΩ

26.7 kΩ

DCOUT

RCVP

RCVN

VITR

RCV

VITR

30 Ω

60.4 kΩ

69.8 kΩ

TIP

PR

RLOOP

0.1 µF

100 Ω/600 Ω

30 Ω

RING

PT

L9216

BASIC

TEST

0.1 µF

TXI

V^PROG

VREF

FB2

CIRCUIT

VTX

4750 Ω

ITR

FB1

B0

B1

B2

B0

B1

B2

CF1

CF2

0.1 µF

VBAT2

VBAT1

BGND VCC

AGND

ICM RGDET NSTAT

0.1 µF

114 kΩ

0.1 µF

VBAT2

VBAT1

VCC

12-3531.h (F)

Figure 4. Basic Test Circuit

20

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Test Configurations (continued)

100 µF

VBAT OR VCC

TIP

VS

100 Ω

368 Ω

+

DISCONNECT

BYPASS CAPACITOR

BASIC

TEST CIRCUIT

4.7 µF

VM

–

VS

RING

VBAT OR

VCC

100 µF

TIP

+

VT/R

–

BASIC

TEST CIRCUIT

VS

VM

LONGITUDINAL BALANCE = 20log

600 Ω

12-2584.c (F)

RING

Figure 7. Longitudinal Balance

VS

VT/R

PSRR = 20log

12-2582.c (F)

VITR

Figure 5. Metallic PSRR

PT

+

BASIC

TEST CIRCUIT

VT/R

600 Ω

VBAT OR VCC

–

RCV

DISCONNECT

BYPASS CAPACITOR

100 Ω

4.7 µF

PR

RCV

VS

VBAT OR

VCC

VXMT

VT/R

GXMT =

67.5 Ω

VT/R

VRCV

TIP

GRCV =

10 µF

BASIC

TEST CIRCUIT

12-2587.G (F)

67.5 Ω

56.3 Ω

+

Figure 8. ac Gains

RING

VM

–

10 µF

VS

VM

PSRR = 20log

12-2583.b (F)

Figure 6. Longitudinal PSRR

Agere Systems Inc.

21

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Thus, if the total power dissipated in the SLIC is less

than 1.83 W, it will not enter the thermal shutdown

state. Total SLIC power is calculated as:

Applications

Power Control

Total P^D= maximum battery • maximum current

Under normal device operating conditions, power dissi-

pation on the device must be controlled to prevent the

device temperature from rising above the thermal shut-

down and causing the device to shut down. Power dis-

sipation is highest with higher battery voltages, higher

current limit, and under shorter dc loop conditions.

Additionally, higher ambient temperature will also

reduce thermal margin.

limit + SLIC quiescent power.

For the L9216, the worst-case SLIC on-hook active

power is 75 mW. Thus,

Total off-hook power = (ILOOP)(current-limit

tolerance)*(V^BATAPPLIED) + SLIC on-hook power

Total off-hook power = (0.030 A)(1.08) * (21) +

75 mW

Total off-hook power = 755.4 mW

To support required power ringing voltages, this device

is meant to operate with a high-voltage primary battery

(–65 V to –75 V typically). Thus, power control is nor-

mally achieved by use of the battery switch and an aux-

iliary lower absolute voltage battery. Operating

temperature range, maximum current limit, maximum

battery voltage, minimum dc loop length and protection

resistor values, airflow, and number of PC board layers

will influence the overall thermal performance. The fol-

lowing example illustrates typical thermal design con-

siderations.

The power dissipated in the SLIC is the total power dis-

sipation less the power that is dissipated in the loop.

SLIC P^D= total power – loop power

Loop off-hook power = (ILOOP * 1.08)²• (RLOOP(dc)

min + 2R^HANDSET)

Loop off-hook power = (0.030 A)(1.08)²• (20 Ω +

60 Ω + 200 Ω)

Loop off-hook power = 293.9 mW

SLIC off-hook power = Total off-hook power – loop

off-hook power

The thermal resistance of the 28-pin PLCC package is

typically 35.5 °C/W, which is representative of the natu-

ral airflow as seen in a typical switch cabinet with a

multilayer board.

SLIC off-hook power = 755.4 mW – 293.9 mW

SLIC off-hook power = 461.5 mW < 1.83 W

Thus, under the operating conditions of this example,

the thermal design, using the auxiliary, is adequate to

ensure the device is not driven into thermal shutdown

under worst-case operating conditions.

The L9216 will enter thermal shutdown at a tempera-

ture of 150 °C. The thermal design should ensure that

the SLIC does not reach this temperature under normal

operating conditions.

For this example, assume a maximum ambient operat-

ing temperature of 85 °C, a maximum current limit of

30 mA, a maximum battery of –75 V, and an auxiliary

battery of –21 V. Assume a (worst-case) minimum dc

loop of 20 Ω of wire resistance, 30 Ω protection resis-

tors, and 200 Ω for the handset. Additionally, include

the effects of parameter tolerance.

1. T^TSD– TAMBIENT(max) = allowed thermal rise.

150 °C – 85 °C = 65 °C.

2. Allowed thermal rise = package thermal

impedance • SLIC power dissipation.

65 °C = 35.5 °C/W • SLIC power dissipation

SLIC power dissipation (P^D) = 1.83 W.

22

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Overhead Voltage

Active Mode

Applications (continued)

dc Loop Current Limit

Overhead is fixed to a nominal 6.0 V, which is adequate

for on-hook transmission of 3.14 dBm into 900 Ω.

Current limit may be chosen from two discrete values,

25 mA or 40 mA, depending on if V^PROGis grounded

(25 mA) or left floating (40 mA). Note that there is a

12.5 kΩ slope to the I/V characteristic in the current-

limit region; thus, once in current limit, the actual loop

current will increase slightly, as loop length decreases.

Scan Mode

If the magnitude of the primary battery is greater than

51 V, the magnitude of the open loop tip-to-ring open

loop voltage is clamped typically between 44 V and

51 V. If the magnitude of the primary battery is less

than a nominal 51 V, the overhead voltage will track the

magnitude of the battery voltage, i.e., the magnitude of

the open circuit tip-to-ring voltage will be 4 V to 6 V less

than battery. In the scan mode, overhead is unaffected

by VOVH.

The above describes the active mode steady-state cur-

rent-limit response. There will be a transient response

of the current-limit circuit upon an on- to off-hook transi-

tion. Typical active mode transient current-limit

response is given in Table 19.

Table 19. Typical Active Mode On- to Off-Hook Tip/

Ring Current-Limit Transient Response

On Hook Transmission Mode

Parameter

dc Loop Current:

Value

Unit

I^LIM+ 60

mA

If the magnitude of the primary battery is greater than

51 V, the magnitude of the open loop tip-to-ring open

loop voltage is clamped typically between 41 V and

49 V. If the magnitude of the primary battery is less

than a nominal 51 V, the overhead voltage will track the

magnitude of the battery voltage, i.e., the magnitude of

the open circuit tip-to-ring voltage will be 6 V to 8 V less

than battery. In the scan mode, overhead is unaffected

by VOVH.

Active Mode

R^LOOP= 100 Ω On- to Off-hook

Transition t < 5 ms

dc Loop Current:

Active Mode

R^LOOP= 100 Ω On- to Off-hook

Transition t < 50 ms

I^LIM+ 20

mA

dc Loop Current:

I^LIM

Active Mode

R^LOOP= 100 Ω On- to Off-hook

Transition t < 300 ms

Agere Systems Inc.

23

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Applications (continued)

Overhead Voltage (continued)

Ring Mode

Supervision

The L9216 offers the loop closure and ring trip supervi-

sion functions. Internal to the device, the outputs of

these detectors are multiplexed into a single package

output, NSTAT. Additionally, a common-mode current

detector for tip or ring ground detection is included for

ground key applications.

In the ring mode, to maximize ringing loop length, the

overhead is decreased to the saturation of the tip ring

drive amplifiers, a nominal 4 V. The tip to ground volt-

age is 1 V, and the ring to V^BAT1voltage is 3 V.

Loop Closure

During the ring mode, to conserve power, the receive

input at RCVN/RCVP is deactivated. During the ring

mode, to conserve power, the AAC amplifier in the

transmit direction at VITR is deactivated. However, if

the AX amplifier at VTX is active during the ring mode,

differential ring current may be sensed at VTX during

the ring mode.

The loop closure has a fixed typical 10.5 mA on- to off-

hook threshold in the active mode and a fixed 11.5 mA

on- to off-hook threshold from the scan mode. In either

case, there is a 2 mA hysteresis with V^CC= 5 V and a

1 mA hysteresis with V^CC= 3.3 V.

Ring Trip

Loop Range

The ring trip detector requires only a single-pole filter at

the input, minimizing external components. An R/C

combination of 383 kΩ and 0.1 µF, for a filter pole at

5.15 Hz, is recommended.

The dc loop range is calculated using:

VBAT2 – VOH

--------------------------------------

RL =

– 2RP – RDC

ILIMIT

VBAT2 is typically applied under off-hook conditions for

power conservation and SLIC thermal considerations.

The L9216 is intended for short-loop applications and,

therefore, will always be in current limit during off-hook

conditions. However, note that the ringing loop length

rather than the dc loop length, will be the factor to

determine operating loop length.

The ring trip threshold is internally fixed as a function of

battery voltage and is given by:

RT (mA) = 67 * {(0.0045 * V^BAT1) + 0.317}

where:

RT is ring trip current in mA.

V^BAT1is the magnitude of the ring battery in V.

There is a 6 mA to 8 mA hysteresis.

Battery Reversal Rate

Tip or Ring Ground Detector

The rate of battery reverse is controlled or ramped by

capacitors FB1 and FB2. Table 20 below shows FB1

and FB2 values vs. typical ramp time. Leave FB1 and

FB2 open if it is not desired to ramp the rate of battery

reversal.

In the ground key or ground start applications, a com-

mon-mode current detector is used to indicate either a

tip- or ring-ground has occurred (ground key) or an off-

hook has occurred (ground start).

Table 20. FB1 and FB2 Values vs. Typical Ramp

Time

For ground start applications detection may be seen at

the output of the common mode current detector

(RGDET) or the loop closure detector (NSTAT).

C^FB1and CFB2

Transition Time

If ICM is used, the detection threshold is set by con-

necting a resistor from ICM to V^CC.

0.01 µF

0.1 µF

0.22 µF

0.47 µF

1.0 µF

1.22 µF

1.3 µF

1.4 µF

1.6 µF

20 ms

220 ms

440 ms

900 ms

1.8 s

2.25 s

2.5 s

2.7 s

205 x V^CC/RICM (kΩ) = ITH (mA)

Additionally, a filter capacitor across RICM will set the

time constant of the detector. No hysteresis is associ-

ated with this detector. The RC filter at ICM gives

immunity to longitudinal currents.

3.2 s

24

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Supervision (continued)

80

60

Tip or Ring Ground Detector (continued)

40

Also in the ground start mode, the fixed loop current

threshold associated with the NSTAT detector output is

internally adjusted to account for common-mode cur-

rent detection in ground start mode (as opposed to dif-

ferential current in loop start mode) maintain the

detector at 10 mA. Thus, NSTAT may also be used for

loop closure detion in ground start. However, the detec-

tor at NSTAT is not filtered against longitudinal cur-

rents, which may or may not be an issue in short loop

applications. Using NSTAT will also save components

at ICM.

20

0

–20

–40

–60

–80

0.00 0.04 0.08 0.12 0.16 0.20

0.02 0.06 0.10 0.14 0.18

TIME (s)

12-3346a (F)

Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms;

period = 50 ms.

Figure 9. Ringing Waveform Crest Factor = 1.6

Power Ring

The device offers a ring mode, in which a balanced

power ring signal is provided to the tip/ring pair. During

the ring mode, a user-supplied low-voltage ring signal

is input to the device’s RING^INinput. This signal is

amplified to produce the balanced power ring signal.

The user may supply a sine wave input, PWM input, or

a square wave to produce sinusoidal or trapezoidal

ringing at tip and ring.

80

60

40

20

0

–20

–40

–60

Various crest factors are shown for illustrative pur-

poses.

–80

0.00 0.04 0.08 0.12 0.16 0.20

0.02 0.06 0.10 0.14 0.18

TIME (s)

12-3347a (F)

Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms;

period = 50 ms.

Figure 10. Ringing Waveform Crest Factor = 1.2

Voltage applied to the load may be increased by using

a filtered square wave input to produce a lower crest

factor trapezoidal power ring signal at tip and ring.

Agere Systems Inc.

25

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

on ring and from –8 V to –34 V on tip, as shown in

Figure 11. Thus, the total voltage swing is 52 V (60 V to

8 V) for a 1 V input, which is approximately the differen-

tial gain of the device. Note that the tip and ring power

ring signals will swing around V^BATTERYdivided by two.

In this case, there is a –70 V battery so tip and ring

swing around –34 V.

Supervision (continued)

Power Ring (continued)

Sine Wave Input Signal and Sine Wave Power Ring

Signal Output

The low-voltage sine wave input is applied to the L9216

at pin RING^IN. This signal should be ac-coupled

through 0.47 µF. During the ring mode, the signal at

RING^INis amplified and presented to the subscriber

loop. The differential gain from RING^INto tip and ring is

a nominal 55.

0

VRING

VTIP

–20

–40

–60

When the device enters the ring mode, the tip/ring

overhead set at OVH and the scan clamp circuit is dis-

abled, allowing the voltage magnitude of the power ring

signal to be maximized. Additionally, in the ring mode,

the loop current limit is increased 2.5X the value set by

the V^PROGvoltage.

0.60 0.62

0.64

0.66

0.68

0.70

0.72

0.74

0.76

0.78 0.80

TIME

12-3573F

1.0

VRINGIN

The magnitude of the power ring voltage will be a func-

tion of the gain of the ring amplifier, the high voltage

battery, and the input signal at RING^IN. The input range

of the signal at RING^INis 0 V to Vcc. As the input volt-

age at RING^INis increased, the magnitude of the power

ring voltage at tip and ring will increase linearly, per the

differential gain of 55, until the tip and ring drive amplifi-

ers begin to saturate. Once the tip and ring amplifiers

reach saturation, further increases of the input signal

will cause clipping distortion of the power ring signal

at tip and ring. The ring signal will appear balanced on

tip and ring. That is, the power ring signal is applied

to both tip and ring, with the signal on tip 180°

0.5

0.0

–0.5

–1.0

0.60 0.62

0.64

0.66

0.68

0.70

TIME

0.72

0.74

0.76

0.78 0.80

12-3574F

Figure 11. Ring Mode Typical Operation

(180 degrees) out of phase from the signal on ring.

Figure 11 shows typical operation of the ring mode,

prior to saturation of the tip and ring drive amplifiers. A

–70 V battery is used with a 100 Ω loop and a 1 REN

load. The input signal is 1 V through a 0.47 µF capaci-

tor at RING^IN, (the input circuit is shown in Figure 12).

This produces a voltage swing from –34 V to –60 V

26

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Supervision (continued)

Power Ring (continued)

Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)

It is recommended that the input level at RING^INbe adjusted so that the power ring signal at tip and ring is just at

the edge or slightly clipping. This gives maximum power transfer with minimal distortion of the sine wave. The tip

side will saturate at a nominal 1 V above ground. The ring side will saturate at a nominal 3 V above battery. The

input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in Figure 12.

L9216

PT

GND

+1

1 V

3 V

RING^IN

27.5x

0.47 µF

V^TIP

INPUT

71 V

VRING

–1

V^BAT

TR

100 kΩ

VBAT = –75 V

12-3532J

Figure 12. RINGIN Operation

The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the

input capacitor at RING^IN, and the input signal at RINGIN and Vcc. Typical characteristic conditions showing the

onset of clipping are given below.

Table 21. Onset of Power Ringing Clipping V^CC= 5 V, Cinput = 0.47 µF

Input

T/R

V^BAT1(V)

–70.15

–68.06

–66.00

–64.08

–62.04

–60.05

Vrms (mV)

891

Vrms (V)

46.88

45.11

Gain

52.62

52.58

52.45

52.30

52.23

52.36

858

833

43.69

42.57

41.21

39.11

814

789

747

Table 22. Onset of Power Ringing Clipping V^CC= 3.1 V, Cinput = 0.47 µF

Input T/R

V^BAT1(V)

–70.12

–68.07

–66.06

–64.01

–62.00

–60.00

Vrms (mV)

894

Vrms (V)

47.15

45.11

Gain

52.74

52.76

52.65

52.5

855

824

43.38

41.95

40.79

39.09

799

780

52.29

52.19

749

Agere Systems Inc.

27

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Supervision (continued)

Power Ring (continued)

Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)

During nonring modes, the sinusoidal ringing waveform may be left on at RING^IN. Via the state table, the ring signal

will be removed from tip and ring even if the low- voltage input is still present at RING^IN. There are certain timing

considerations that should be made with respect to state changes which are detailed in the Switching Behavior of

L9215/6 Ringing SLIC Application Note.

PWM Input Signal and Sine Wave Power Ring Signal Output

A pulse-width modulated (PWM) signal may be used to provide the ringing input to RING^IN. The signal is applied

through a low-pass filter and ac-coupled into RING^INas shown in Figure 13 below. This approach gives a sine

wave output at tip and ring.

L9215/16

R1

C2

RINGIN

INPUT

C1

12-3578bF

Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs

Table 23. Signal and Component Selection Chart

V^BAT

70 V

85 V

VCC

5 V

3 V

5 V

3 V

5 V

3 V

5 V

3 V

5 V

3 V

5 V

3 V

Input

R1

C1

C2

CF Typical 5 REN Ringing Voltage RMS

5 V Square

3 V Square

12 kΩ

7 kΩ

1 µF

0.47 µF

1.3

48 V

49 V

42 V

59 V

51 V

47 V

51 V

49 V

10 kHz PWM 5 V 10 kΩ 0.22 µF 0.47 µF sine

10 kHz PWM 3 V 10 kΩ 0.22 µF 0.47 µF sine

90 kHz PWM 5 V

90 kHz PWM 3 V

5 V Square

7 kΩ

10 kΩ

7 kΩ

0.1 µF 0.47 µF sine

1 µF

0.47 µF

1.3

3 V Square

10 kHz PWM 5 V 10 kΩ 0.22 µF 0.47 µF sine

10 kHz PWM 3 V

90 kHz PWM 5 V

90 kHz PWM 3 V

4 kΩ 0.22 µF 0.47 µF sine

4 kΩ

0.1 µF 0.47 µF sine

28

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

5 V V^CCOperation

Supervision (continued)

Power Ring (continued)

A PWM signal was generated with an HP™ 8116

Function Generator modulated with a 20 Hz signal. The

optimal frequency used was 10 kHz. The PWM signal

amplitude was 5.0 V (0 V to 5 V). This signal is shown

in Figure 15.

PWM Input Signal and Sine Wave Power Ring Sig-

nal Output (continued)

Modulation waveforms showing PWM are in Figure 14

below.

12-3575F

Figure 15. 5 V PWM Signal Amplitude

12-3381(F)

A. Upper = Pwm Signal Centered at 10 kHz

Lower = Modulation Signal

This input produced 44.96 Vrms ringing signal on

tip/ring under open-loop conditions and 42.0 Vrms was

delivered to 5 REN load. The ringing output on ring,

with V^CC= 5 V, is shown in Figure 16.

12-3380(F)

1660

B. Same as A but Expanded

Notes:

The modulating 20 Hz signal THD was measured at 1.3%.

Figure 14. Modulation Waveforms

The tip/ring 20 Hz signal THD was measured at 1%.

VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 5.019 V.

PWM input 10 kHz, 5.0 Vp-p.

R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.

Figure 16. Ringing Output on RING, with VCC = 5 V

Agere Systems Inc.

29

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

During nonring modes, the PWM waveform may be left

on at RING^IN. Via the state table, the ring signal will be

removed from tip and ring even if the low-voltage input

is still present at RING^IN. There are certain timing con-

siderations that should be made with respect to state

changes which are detailed in the Switching Behavior

of L9215/6 Ringing SLIC Application Note.

Supervision (continued)

Power Ring (continued)

3.3 V V^CCOperation

A PWM signal was generated with an HP 8116 Func-

tion Generator modulated with a 20 Hz signal. The opti-

mal frequency used was 10 kHz. The PWM signal

amplitude was 3.10 V (0 V to 3.10 V). This input signal

is shown in Figure 17.

Square Wave Input Signal and Trapezoidal Power

Ring Signal Output

A low-voltage square wave signal may be used to pro-

vide the ringing input to RING^IN. The signal is applied

through a low-pass filter and ac-coupled into RING^INas

shown in Figure 13 and Table 23. This approach gives

a trapezoidal wave output at tip and ring.

Using this approach, a trapezoidal waveform can be

achieved at tip and ring. This has the advantage of

increasing the power transfer to the load for a given

battery voltage, thus increasing the effective ringing

loop length as compared to a sine wave. The actual

crest factor achieved is a function of the magnitude of

the battery, the magnitude of the input voltage, fre-

quency, and R¹.

12-3571F

Figure 17. 3.3 V PWM Signal Amplitude

This produced 44.96 Vrms ringing signal on tip/ring

under open-loop conditions and 42.0 Vrms was deliv-

ered to 5 REN load. The ringing output on ring with V^CC

= 3.1 V is shown in Figure 18.

CH1

CH2

CH3

CH4

1660

12-3572F

Notes:

The modulating 20 Hz signal THD was measured at 1.3%.

The tip/ring 20 Hz signal THD was measured at 1%.

VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 3.10 V.

PWM input 10 kHz, 3.1 Vp-p.

CH1—CMOS Input (5 V) at RINGIN.

CH2—Filtered input at RINGIN.

CH3—Tip.

CH4—Ring.

R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.

R1 = 14 kΩ, C1 = 1.0 µF, C2 = 0.47 µF.

VBAT1 = –70 V, Vrms = 51 V, Vp-p = 67 V, frequency = 20 Hz, Crest

Factor = 1.3.

Figure 18. Ringing Output on RING, with VCC = 3.1 V

Figure 19. Square Wave Input Signal and Trapezoi-

dal Power Ring Signal Output

30

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Supervision (continued)

Power Ring (continued)

Square Wave Input Signal and Trapezoidal Power Ring Signal Output (continued)

Figure 20 and Figure 21 provide some guidance to the relationship between crest factor, battery voltage, and R¹

value.

1.36

1.35

1.34

1.33

1.32

1.31

1.3

1.29

1.28

1.27

1.26

58

60

62

64

66

68

70

72

BAT V

12-3576F

Figure 20. Crest Factor vs. Battery Voltage

1.5

1.45

1.4

1.35

1.3

1.25

10

10.5

11

11.5

12

12.5

13

13.5

14

R (kΩ)

12-3577F

Figure 21. Crest Factor vs. R (kΩ)

During nonring modes, the square wave input may be left on or removed from RING^IN. Via the state table, the ring

signal will be removed from tip and ring even if the low-voltage input is still present at RING^IN. However, removing

the waveform has certain advantages in terms of the timing of state. These advantages are detailed in the Switch-

ing Behavior of L9215/16 Ringing SLIC Application Note.

Agere Systems Inc.

31

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Third-Generation Codecs

ac Applications

This class of devices includes all ac parameters set

digitally under microprocessor control. Depending on

the device, it may or may not have data control latches.

Additional functionality sometimes offered includes

tone plant generation and reception, PPM generation,

test algorithms, and echo cancellation. Again, this type

of codec may be 3.3 V, 5 V only, or ±5 V operation, sin-

gle quad or multichannel, and µ-law/A-law or 16-bit lin-

ear coding selectable. Examples of this type of codec

are the Agere T8535/6 (5 V only, quad, standard fea-

tures), T8537/8 (3.3 V only, quad, standard features),

T8533/4 (5 V only, quad with echo cancellation), and

the T8531/32 (5 V only multichannel).

ac Parameters

There are four key ac design parameters. Termination

impedance is the impedance looking into the 2-wire

port of the line card. It is set to match the impedance of

the telephone loop in order to minimize echo return to

the telephone set. Transmit gain is measured from the

2-wire port to the PCM highway, while receive gain is

done from the PCM highway to the transmit port.

Transmit and receive gains may be specified in terms

of an actual gain, or in terms of a transmission level

point (TLP), that is the actual ac transmission level

in dBm. Finally, the hybrid balance network cancels

the unwanted amount of the receive signal that

appears at the transmit port.

ac Interface Network

The ac interface network between the L9216 and the

codec will vary depending on the codec selected. With

a first-generation codec, the interface between the

L9216 and codec actually sets the ac parameters. With

a third-generation codec, all ac parameters are set dig-

itally, internal to the codec; thus, the interface between

the L9216 and this type of codec is designed to avoid

overload at the codec input in the transmit direction

and to optimize signal to noise ratio (S/N) in the receive

direction.

Codec Types

At this point in the design, the codec needs to be

selected. The interface network between the SLIC and

codec can then be designed. Below is a brief codec

feature summary.

First-Generation Codecs

These perform the basic filtering, A/D (transmit), D/A

(receive), and µ-law/A-law companding. They all have

an op amp in front of the A/D converter for transmit

gain setting and hybrid balance (cancellation at the

summing node). Depending on the type, some have

differential analog input stages, differential analog out-

put stages, 5 V only or ±5 V operation, and µ-law/A-law

selectability. These are available in single and quad

designs. This type of codec requires continuous time

analog filtering via external resistor/capacitor networks

to set the ac design parameters. An example of this

type of codec is the Agere T7504 quad 5 V only codec.

Because the design requirements are very different

with a first- or third-generation codec, the L9216 is

offered with two different receive gains. Each receive

gain was chosen to optimize, in terms of external com-

ponents required, the ac interface between the L9216

and codec.

This type of codec tends to be the most economical in

terms of piece part price, but tends to require more

external components than a third-generation codec.

Further ac parameters are fixed by the external R/C

network so software control of ac parameters is diffi-

cult.

32

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Note also that some third-generation codecs require

the designer to provide an inherent resistive termina-

tion via external networks. The codec will then provide

gain shaping, as a function of frequency, to meet the

return loss requirements. This feedback will increase

the signal at the codec input and increase the likeli-

hood that a resistor divider is needed in the transmit

direction. Further stability issues may add external

components or excessive ground plane requirements

to the design.

ac Applications (continued)

ac Interface Network (continued)

With a first-generation codec, the termination imped-

ance is set by providing gain shaping through a feed-

back network from the SLIC VITR output to the SLIC

RCVN/RCVP inputs. The L9216 provides a transcon-

ductance from T/R to VITR in the transmit direction and

a single-ended to differential gain from either RCVN or

RCVP to T/R in the receive direction. Assuming a short

from VITR to RCVN or RCVP, the maximum imped-

ance that is seen looking into the SLIC is the product of

the SLIC transconductance multiplied by the SLIC

receive gain, plus the protection resistors. The various

specified termination impedances can range over the

voiceband as low as 300 Ω up to over 1000 Ω. Thus, if

the SLIC gains are too low, it will be impossible to syn-

thesize the higher termination impedances. Further, the

termination that is achieved will be far less than what is

calculated by assuming a short for SLIC output to SLIC

input. In the receive direction, in order to control echo,

the gain is typically a loss, which requires a loss net-

work at the SLIC RCVN/RCVP inputs, which will

reduce the amount of gain that is available for termina-

tion impedance. For this reason, a high-gain SLIC is

required with a first-generation codec.

In the receive direction, the issue is to optimize the

S/N. Again, the designer must consider all the consid-

ered TLPs. The idea, for all desired TLPs, is to run the

codec at or as close as possible to its maximum output

signal, to optimize the S/N. Remember, noise floor is

constant, so the hotter the signal from the codec, the

better the S/N. The problem is if the codec is feeding a

high gain SLIC, either an external resistor divider is

needed to knock the gain down to meet the TLP

requirements, or the codec is not operated near maxi-

mum signal levels, thus compromising the S/N.

Thus, it appears that the solution is to have a SLIC with

a low gain, especially in the receive direction. This will

allow the codec to operate near its maximum output

signal (to optimize S/N), without an external resistor

divider (to minimize cost).

To meet the unique requirements of both types of

codecs, the L9216 offers two receive gain choices.

These receive gains are mask-programmable at the

factory and are offered as two different code variations.

For interface with a first-generation codec, the L9216 is

offered with a receive gain of 8. For interface with a

third-generation codec, the L9216 is offered with a

receive gain of 2. In either case, the transconductance

in the transmit direction or the transmit gain is 300 Ω.

With a third-generation codec, the line card designer

has different concerns. To design the ac interface, the

designer must first decide upon all termination imped-

ance, hybrid balances, and transmission level point

(TLP) requirements that the line card must meet. In the

transmit direction, the only concern is that the SLIC

does not provide a signal that is too hot and overloads

the codec input. Thus, for the highest TLP that is being

designed to, given the SLIC gain, the designer, as a

function of voiceband frequency, must ensure the

codec is not overloaded. With a given TLP and a given

SLIC gain, if the signal will cause a codec overload, the

designer must insert some sort of loss, typically a resis-

tor divider, between the SLIC output and codec input.

These receive gain options afford the designer the flex-

ibility to maximize performance and minimize external

components, regardless of the type of codec chosen.

Agere Systems Inc.

33

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Receive Gain:

ac Applications (continued)

VT/R

-----------

grcv =

Design Examples

VFR

8

First-Generation Codec ac Interface Network—

Resistive Termination

grcv =

------------------------------------------------------------------

R^RCVRRCV

Z^T

1 +

+

1 +

--------

----------- -----------

RT1

RGP

ZT/R

The reference circuit in Figure 23 shows the complete

SLIC schematic for interface to the Agere T7504 first-

generation codec for a resistive termination imped-

ance. For this example, the ac interface was designed

for a 600 Ω resistive termination and hybrid balance

with transmit gain and receive gain set to 0 dBm.

Transmit Gain:

VGSX

g^tx

= ----------

VT/R

–RX 300

g^tx= -------- × --------

This is a lower feature application example and uses

single battery operation, fixed overhead, current limit,

and loop closure threshold.

RT2

Z^T/R

Hybrid Balance:

Resistor RGN is optional. It compensates for any mis-

match of input bias voltage at the RCVN/RCVP inputs.

If it is not used, there may be a slight offset at tip and

ring due to mismatch of input bias voltage at the

RCVN/RCVP inputs. It is very common to simply tie

RCVN directly to ground in this particular mode of oper-

ation. If used, to calculate RGN, the impedance from

RCVN to ac ground should equal the impedance from

RCVP to ac ground.

R^X

RHB

-----------

h^bal= 20log

– gtx × grcv

VGSX

--------------

h^bal= 20log

VFR

To optimize the hybrid balance, the sum of the currents

at the VFX input of the codec op amp should be set to

0. The expression for ZHB becomes the following:

Example 1, Real Termination

RX

RHB(kΩ) = -------------------

gtx × grcv

The following design equations refer to the circuit in

Figure 22. Use these to synthesize real termination

impedance.

Termination Impedance:

V^T/R

–IT/R

------------

zT =

2400

zT = 50 Ω + 2RP +

----------------------------------

1 +

R^T1

RT1

+

-------- -----------

RGP RRCV

34

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Applications (continued)

Design Examples (continued)

Example 1, Real Termination (continued)

RX

VGSX

–0.300 V/mA

RT2

VFXIN

VFXIP

–

+

VITR

RT1

RHB1

RCVN

RCVP

–

18 Ω

ZT/R

+2.4 V

RP

TIP

AV = 4

AV = 1

RRCV

VFR

+

IT/R

+

CURRENT

SENSE

VS

ZT

VT/R

–

RP

RGP

+

AV = –1

RING

18 Ω

–

L9216

1/4 T7504 CODEC

0586 (F)

Figure 22. ac Equivalent Circuit

V^BAT1

VBAT2 VCC

CBAT1

CBAT2

CCC

DBAT1

0.1 µF 0.1 µF

0.1 µF

VBAT1

BGND VBAT2 VCC AGND

ICM

RGDET

CRT

ITR

RTFLT

RGX

0.1 µF

4750 Ω

R^RT

RX

VTX

383 kΩ

100 kΩ

DCOUT

PR

CTX

GSX

DX

FUSIBLE OR PTC

0.1 µF

30 Ω

TXI

CC1

RT6

49.9 kΩ

AGERE

L7591

VBAT1

–

+

0.1 µF

VITR

30 Ω

VFXIN

R^HB1

100 kΩ

PT

RT3

L9216A

PCM

HIGHWAY

FUSIBLE OR PTC

69.8 kΩ

+2.4 V

CC2

0.1 µF

R^RCV

60.4 kΩ

VFRO

DR

RCVP

RCVN

VPROG

RGP

FSE

FSEP

MCLK

26.7 kΩ

SYNC

AND

VREF

CLOCK

V^REF

rate of battery

reversal not

ramped

RN2

17.65 kΩ

CONTROL

INPUTS

ASEL

CF1

CF2 FB1 FB2 NSTAT B2 B1 B0

RINGIN

1/4 T7504

CODEC

VREF

C²

0.47 µF

0.22 µF

CF2

0.1 µF

R1

12 kΩ

C1

1.0 µF

Figure 23. Agere T7504 First-Generation Codec Resistive Termination

Agere Systems Inc.

35

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Applications (continued)

Design Examples (continued)

Example 1, Real Termination (continued)

Table 24. Parts List L9216; Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse

Application

Name

Value

Tolerance

Rating

Function

Fault Protection

RPT

30 Ω

Agere L7591

1%

—

Fusible or PTC Protection resistor.

RPR

Protector

—

Secondary protection.

Power Supply

CBAT1

0.1 µF

1N4004

0.1 µF

0.22 µF

0.1 µF

20%

—

20%

100 V

50 V

—

10 V

100 V

VBAT filter capacitor.

VBAT filter capacitor. |VBAT2| < |VBAT1|.

Reverse current.

CBAT2

DBAT1

CCC

VCC filter capacitor.

Filter capacitor.

CF1

CF2

Ring/Ring Trip

C1

1.0 µF

0.47 µF

12 kΩ

0.1 µF

383 kΩ

20%

1%

20%

1%

10 V

1/16 W

10 V

Ring filter for square wave.

ac-couple input ring signal.

Ring filter for square wave.

Ring trip filter capacitor.

Ring trip filter resistor.

C2

R1

CRT

RRT

1/16 W

ac Interface

RGX

4750 Ω

0.1 µF

69.8 kΩ

1%

20%

1%

1/16 W

10 V

1/16 W

Sets T/R to VITR transconductance.

ac/dc separation.

dc blocking capacitor.

With RGP and RRCV, sets termination impedance

and receive gain.

CTX

CC1

CC2

RT3

RT6

49.9 kΩ

100 kΩ

60.4 kΩ

1%

1/16 W

With RX, sets transmit gain.

With RT6, sets transmit gain.

With RX, sets hybrid balance.

With RGP and RT3, sets termination impedance

and receive gain.

RX

RHB1

RRCV

RGP

26.7 kΩ

17.6 kΩ

1%

1/16 W

With RRCV and RT3, sets termination impedance

and receive gain.

Optional. Compensates for input offset at

RCVN/RCVP.

RGN Optional

Notes:

Termination Impedance = 600 Ω.

Hybrid Balance = 600 Ω.

Tx = 0 dBm.

Rx = 0 dBm.

36

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Interface Using First-Generation Codec

ac Applications (continued)

Design Examples (continued)

R^GX/RTGS/CGS (ZTG): these components give gain shap-

ing to get good gain flatness. These components are a

scaled version of the specified complex termination

impedance.

First-Generation Codec ac Interface Network—

Complex Termination

Note for pure (600 Ω) resistive terminations, compo-

nents R^TGSand CGS are not used. Resistor RGX is used

and is still 4750 Ω.

The reference circuit in Figure 26 shows the complete

SLIC schematic for interface to the Agere T7504 first-

generation codec for the German complex termination

impedance. For this example, the ac interface was

designed for a 220 Ω + (820 Ω || 115 nF) complex

termination and hybrid balance with transmit gain and

receive gain set to 0 dBm. For illustration purposes,

1 Vrms PPM injection was assumed in this example.

This implies the overhead voltage is increased to

7.24 V and no meter pulse rejection is required. Also,

this example illustrates the device using fixed overhead

and current limit.

R^X/RT6: with other components set, the transmit gain

(for complex and resistive terminations) R^Xand RT6 are

varied to give specified transmit gain.

R^T3/RRCV/RGP: for both complex and resistive termina-

tions, the ratio of these resistors sets the receive gain.

For resistive terminations, the ratio of these resistors

sets the return loss characteristic. For complex termi-

nations, the ratio of these resistors sets the low-fre-

quency return loss characteristic.

C^N/RN1/RN2: for complex terminations, these compo-

nents provide high-frequency compensation to the

return loss characteristic.

Complex Termination Impedance Design Example

The gain shaping necessary for a complex termination

impedance may be done by shaping across the AX

amplifier at nodes ITR and VTX.

For resistive terminations, these components are not

used and RCVN is connected to ground via a resistor.

Complex termination is specified in the form:

R^HB: sets hybrid balance for all terminations.

Set Z^TG—Gain Shaping:

R2

Z^TG= RGX || RTGS + CGS which is a scaled version of

Z^T/R(the specified termination resistance) in the

R¹´ || R2´ + C´ form.

R1

C

R^GXmust be 4750 Ω to set SLIC transconductance to

5-6396(F)

300 V/A.

To work with this application, convert termination to the

form:

R^GX= 4750 Ω

R1´

At dc, C^GSand C´ are open.

R^GX= M x R1´

where M is the scale factor.

4750

R2´ C´

--------------

M =

5-6398(F)

R¹′

where:

It can be shown:

R¹´ = R1 + R2

R1

R^TGS= M x R2´

-------

R2´ =

(R1 + R2)

and

R2

C′

M

------

C^TGS=

C´ =

²C

R2

R1 + R2

---------------------

Agere Systems Inc.

37

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Using R^EQ, calculate the desired transmit gain, taking

into account the impedance transformation:

600

ac Applications (continued)

Design Examples (continued)

Transmit Gain

T^X(dB) = TX (specified[dB]) + 20log

----------

R^EQ

T^{X (specified[dB])}is the specified transmit gain. 600 Ω is the

impedance at the PCM, and R^EQis the impedance at

Transmit gain will be specified as a gain from T/R to

PCM, T^X(dB). Since PCM is referenced to 600 Ω and

assumed to be 0 dB, and in the case of T/R being refer-

enced to some complex impedance other than 600 Ω

resistive, the effects of the impedance transformation

must be taken into account.

600

tip and ring. 20log

represents the power

----------

R^EQ

loss/gain due to the impedance transformation.

Note that in the case of a 600 Ω pure resistive termina-

tion

Again, specified complex termination impedance at T/R

is of the form:

600

R^EQ

600

= 0.

---------

at T/R 20log

= 20log

----------

600

R2

Thus, there is no power loss/gain due to impedance

transformation and T^X(dB) = TX (specified[dB]).

R1

C

Finally, convert T^X(dB) to a ratio, gTX:

T^X(dB) = 20log gTX

5-6396(F)

First, calculate the equivalent resistance of this network

at the midband frequency of 1000 Hz.

The ratio of RX/RT6 is used to set the transmit gain:

RX

RT6

318.25

20

1

M

----------

= g^TX• ----------------- • ---- with a quad Agere codec

R^EQ=

2

(2 πf) C1 R1R2²+ R1 + R2

2 πfR2 C1

-----------------------------------------------------------------------------

--------------------------------------------------

+

such as T7504:

2

1 + (2 πf) R2 C1

R^X< 200 kΩ

RTGS CGS

Rx

RGX = 4750 Ω

–IT/R

0.1 µF

318.25

RT6

–

20

+

VTX

TXI

VITR

CODEC

OP AMP

CN

RT3

RHB

RN1

RN2

RCVN

RCVP

CODEC

OUTPUT

DRIVE

AMP

RRCV

RGP

5-6400.P (F)

Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)

38

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Hybrid Balance

ac Applications (continued)

Design Examples (continued)

Receive Gain

Set the hybrid cancellation via R^HB.

RX

gRCV × gTX

------------------------------

R^HB=

If a 5 V only codec such as the Agere T7504 is used,

dc blocking capacitors must be added as shown in

Figure 25. This is because the codec is referenced to

2.5 V and the SLIC to ground—with the ac coupling, a

dc bias at T/R is eliminated and power associated with

this bias is not consumed.

Ratios of R^RCV, RT3, RGP will set both the low-frequency

termination and receive gain for the complex case. In

the complex case, additional high-frequency compen-

sation, via C^N, RN1, and RN2, is needed for the return

loss characteristic. For resistive termination, C^N, RN1,

and R^N2are not used and RCVN is tied to ground via a

resistor.

Typically, values of 0.1 µF to 0.47 µF capacitors are

used for dc blocking. The addition of blocking capaci-

tors will cause a shift in the return loss and hybrid bal-

ance frequency response toward higher frequencies,

degrading the lower-frequency response. The lower

the value of the blocking capacitor, the more pro-

nounced the effect is, but the cost of the capacitor is

lower. It may be necessary to scale resistor values

higher to compensate for the low-frequency response.

This effect is best evaluated via simulation. A PSPICE^®

model for the L9216 is available.

Determine the receive gain, g^RCV, taking into account

the impedance transformation in a manner similar to

transmit gain.

R^EQ

R^X(dB) = RX (specified[dB]) + 20log ----------

600

R^X(dB) = 20log gRCV

Then:

4

-----------------------------------------------

R^RCVRRCV

g^RCV=

--------------- ---------------

1 +

+

Design equation calculations seldom yield standard

component values. Conversion from the calculated

value to standard value may have an effect on the ac

parameters. This effect should be evaluated and opti-

mized via simulation.

RT3

RGP

and low-frequency termination

2400

--------------------------------------------

Z^TER(low)=

+ 2RP + 50 Ω

R^T3

RT3

----------- ---------------

1 +

+

RGP RRCV

Z^TER(low)is the specified termination impedance assum-

ing low frequency (C or C´ is open).

R^Pis the series protection resistor.

50 Ω is the typical internal feed resistance.

These two equations are best solved using a computer

spreadsheet.

Next, solve for the high-frequency return loss compen-

sation circuit, C^N, RN1, and RN2:

2RP

C^NRN2 = ------------ CG RTGP

2400

R^TGS

-------------

2400

2R^P

RN1 = RN2 ------------

– 1

RTGP

There is an input offset voltage associated with nodes

RCVN and RCVP. To minimize the effect of mismatch

of this voltage at T/R, the equivalent resistance to ac

ground at RCVN should be approximately equal to that

at RCVP. Refer to Figure 25 (with dc blocking capaci-

tors). To meet this requirement, R^N2= RGP || RT3.

Agere Systems Inc.

39

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Applications (continued)

Design Examples (continued)

Blocking Capacitors

RTGS

CGS

Rx

RGX = 4750 Ω

–IT/R

CB1

0.1 µF

318.25

RT6

RT3

–

+

20

VTX

TXI

VITR

CODEC

OP AMP

CN

RHB

RN1

RCVN

RCVP

CB2

RRCV

RGP

2.5 V

RN2

CODEC

OUTPUT

DRIVE

AMP

5-6401.M (F)

Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termi-

nation Impedance

V^BAT1

VBAT2 VCC

CBAT1

CBAT2

CCC

DBAT1

VBAT1

0.1 µF 0.1 µF

0.1 µF

BGND VBAT2 VCC

AGND

ICM

RGDET

ground key

not used

CRT

ITR

RTFLT

R^TGS1.74 kΩ

RGX

0.1 µF

4750 Ω

R^RT

C^GS12 nF

383 kΩ

VTX

TXI

FUSIBLE

OR PTC

DCOUT

PR

CTX

0.1 µF

RX

115 kΩ

30 Ω

GSX

AGERE

L7591

VBAT1

CC1

0.1 µF

RT6

40.6 kΩ

30 Ω

VITR

–

+

PT

L9216A

CN

VFXIN

FUSIBLE

OR PTC

DX

120 pF

RT3

49.9 kΩ

PCM

HIGHWAY

RHB1

113 kΩ

+2.4

VFRO

V^PROG

RRCV

RCVP

RCVN

DR

59.0 kΩ

C^C2

0.1 µF

R^N1

127

kΩ

FSE

SYNC

AND

CLOCK

FSEP

MCLK

V^REF

CF1

rate of battery

reversal not

ramped

RGP

54.9 kΩ

VREF

47.5 kΩ

RN2

CF2

FB1 FB2

NSTAT B2 B1 B0

FROM/TO CONTROL

RINGIN

CONTROL

INPUTS

ASEL

CF1

VREF

CRING

0.47 µF

0.22 µF

CF2

0.1 µF

1/4 T7504

CODEC

RING

Figure 26. Agere T7504 First-Generation Codec Complex Termination

40

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Applications (continued)

Design Examples (continued)

Blocking Capacitors (continued)

Table 25. Parts List L9216; Agere T7504 First-Generation Codec Complex Termination; Meter Pulse

Application

Termination impedance = 220 Ω + (820 Ω || 115 nF), hybrid balance = 220 Ω + (820 Ω || 115 nF) Tx = 0 dBm,

Rx = 0 dBm.

Name

Value Tolerance

Rating

Function

Fault Protection

RPT

RPR

Protector

30 Ω

Agere

L7591

1%

—

Fusible or PTC Protection resistor.

—

Secondary protection.

Power Supply

CBAT1

CBAT2

DBAT1

CCC

0.1 µF

20%

—

20%

100 V

50 V

—

10 V

100 V

VBAT filter capacitor.

VBAT filter capacitor. |VBAT2| < |VBAT1|.

Reverse current.

VCC filter capacitor.

Filter capacitor.

0.1 µF

1N4004

0.1 µF

0.22 µF

0.1 µF

CF1

CF2

Ring/Ring Trip

CRING

CRT

RRT

0.47 µF

0.1 µF

383 kΩ

20%

1%

10 V

1/16 W

ac-couple input ring signal.

Ring trip filter capacitor.

Ring trip filter resistor.

ac Interface

RGX

RTGS

CGS

CTX

CC1

4750 Ω

1.74 kΩ

12 nF

0.1 µF

49.9 kΩ

1%

5%

20%

1%

1/16 W

10 V

Sets T/R to VITR transconductance.

Gain shaping for complex termination.

ac/dc separation.

dc blocking capacitor.

CC2

RT3

10 V

1/16 W

With RGP and RRCV, sets termination impedance and receive

gain.

RT6

RX

RHB1

RRCV

40.2 kΩ

115 kΩ

113 kΩ

59.0 kΩ

1%

1/16 W

With RX, sets transmit gain.

With RT6, sets transmit gain.

With RX, sets hybrid balance.

With RGP and RT3, sets termination impedance and receive

gain.

RGP

54.9 kΩ

1%

1/16 W

With RRCV and RT3, sets termination impedance and receive

gain.

CN

RN1

RN2

120 pF

127 kΩ

47.5 kΩ

20%

1%

10 V

1/16 W

High frequency compensation.

High frequency compensation, compensate for dc offset at

RCVP/RCVN.

Agere Systems Inc.

41

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Applications (continued)

Design Examples (continued)

Third-Generation Codec ac Interface Network—Complex Termination

The following reference circuit, Figure 27, shows the complete SLIC schematic for interface to the Agere T8536

third-generation codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that

no external components are required in the ac interface to provide a dc termination impedance or for stability. For

illustration purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used.

Also, this example illustrates the device using programmable overhead and current limit. Please see the T8535/6

data sheet for information on coefficient programming.

VBAT1

VBAT2 VCC

CBAT1

CBAT2

CCC

DBAT1

VBAT1

0.1 µF 0.1 µF

0.1 µF

BGND VBAT2 VCC

AGND

ICM

RGDET

ground key

not used

ITR

CRT

RTFLT

RGX

4750 Ω

0.1 µF

R^RT

383 kΩ

VTX

CTX

DCOUT

PR

0.1 µF

FUSIBLE OR PTC

50 Ω

AGERE

TXI

CC1

0.1 µF

VBAT1

VFXI

DX0

DR0

VITR

L7591

RCIN

20 MΩ

L9216G

50 Ω

PT

PCM

HIGHWAY

DX1

DR1

FUSIBLE OR PTC

VFROP

VFRON

RCVP

RCVN

V^PROG

1/4

T8536/8

VREF

rate of battery

reversal not

ramped

SYNC

AND

CLOCK

FS

SLIC4a

SLIC3a

SLIC2a

SLIC0a

BCLK

B2

B1

CF1

CF2

FB1 FB2

NSTAT B2 B1 B0

RINGIN

C^RING

0.47 µF

0.22 µF

DGND

V^DD

CF2

0.1 µF

B0

FROM/TO

CONTROL

NSTAT

V^DD

Figure 27. Third-Generation Codec ac Interface Network; Complex Termination

42

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

ac Applications (continued)

Design Examples (continued)

Third-Generation Codec ac Interface Network—Complex Termination (continued)

Table 26. Parts List L9216; Agere T8536 Third-Generation Codec ac and dc Parameters; Fully

Programmable

Name

Value

Tolerance

Rating

Function

Fault Protection

RPT

RPR

50 Ω

1%

—

Fusible orPTC Protection resistor*.

Protector

Agere L7591

—

Secondary protection.

Power Supply

CBAT1

0.1 µF

1N4004

0.1 µF

0.22 µF

0.1 µF

20%

—

100 V

50 V

—

VBAT filter capacitor.

CBAT2

VBAT filter capacitor. |VBAT2| < |VBAT1|.

Reverse current.

DBAT1

CCC

20%

10 V

100 V

VCC filter capacitor.

Filter capacitor.

CF1

CF2

Filter capacitor.

Ring/Ring Trip

CRING

0.47 µF

0.1 µF

20%

1%

10 V

ac-couple input ring signal.

Ring trip filter capacitor.

Ring trip filter resistor.

CRT

RRT

383 kΩ

1/16 W

ac Interface

RGX

4750 Ω

20 MΩ

0.1 µF

1%

5%

1/16 W

10 V

Sets T/R to VITR transconductance.

dc bias.

RCIN

CTX

20%

ac/dc separation.

CC1

10 V

dc blocking capacitor.

* For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.

Agere Systems Inc.

43

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Outline Diagrams

28-Pin PLCC

Dimensions are in millimeters.

Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Agere Sales Representative.

12.446 ± 0.127

11.506 ± 0.076

PIN #1 IDENTIFIER

4

1

26

ZONE

25

5

11.506

± 0.076

12.446

± 0.127

11

19

12

18

4.572

MAX

SEATING PLANE

0.10

0.51 MIN

TYP

1.27 TYP

0.330/0.533

5-2506r.8(F)

44

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Outline Diagrams (continued)

48-Pin MLCC

Dimensions are in millimeters.

Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Agere Sales Representative.

The exposed pad on the bottom of the package will be at V^BAT1potential.

C

7.00

CL

3.50

6.75

3.375

0.50 BSC

1

2

3

DETAIL A

VIEW FOR EVEN TERMINAL/SIDE

6.75

7.00

PIN #1

IDENTIFIER ZONE

0.18/0.30

0.00/0.05

SECTION C–C

DETAIL A

0.65/0.80

1.00 MAX

12°

SEATING PLANE

0.08

0.20 REF

0.01/0.05

11 SPACES @

0.50 = 5.50

0.24/0.60

0.18/0.30

0.24/0.60

5.10

± 0.15

3

2

1

0.30/0.45

EXPOSED PAD

0.50 BSC

0195mod

Agere Systems Inc.

45

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Outline Diagrams (continued)

48-Pin MLCC, JEDEC MO-220 VKKD-2

Dimensions are in millimeters.

Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Agere Sales Representative.

The exposed pad on the bottom of the package will be at V^BAT1potential.

7.00

CL

3.50

PIN #1

IDENTIFIER ZONE

0.50 BSC

3.50

INDEX AREA

DETAIL A

VIEW FOR EVEN TERMINAL/SIDE

(7.00/2 x 7.00/2)

7.00

0.18

0.23

0.18

TOP VIEW

SIDE VIEW

0.23

1.00 MAX

SEATING PLANE

0.08

0.20 REF

DETAIL B

0.02/0.05

11 SPACES @

0.50 = 5.50

DETAIL A

0.18/0.30

0.30/0.50

2.50/2.625

5.00/5.25

3

2

1

EXPOSED PAD

0.50 BSC

DETAIL B

BOTTOM VIEW

0195a

46

Agere Systems Inc.

L9216A/G

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

Ordering Information

Device Part No.

Description

Package

Comcode

LUCL9216AGF-D

SLIC Gain = 8

28-Pin PLCC

Dry-bagged

108876723

LUCL9216AGF-DT

LUCL9216GGF-D

LUCL9216GGF-DT

LUCL9216ARG-D

LUCL9216GRG-D

SLIC Gain = 8

SLIC Gain = 2

SLIC Gain = 8

SLIC Gain = 2

28-Pin PLCC

Tape & Reel, Dry-bagged

108876731

108876780

108876798

108955477

108955469

28-Pin PLCC

Tape & Reel

28-Pin PLCC

Tape & Reel, Dry-bagged

48-Pin MLCC

Dry-bagged

48-Pin MLCC

Dry-bagged

Agere Systems Inc.

47

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

PSPICE is a registered trademark of MicroSim Corporation.

Telcordia Technologies is a trademark of Bell Communications Research, Inc.

HP is a trademark of Hewlett-Packard Company.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

http://www.agere.com

E-MAIL:

docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

Tel. (44) 7000 624624, FAX (44) 1344 488 045

EUROPE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

September 2001

DS01-301ALC (Replaces DS00-133ALC)


型号：	L9216A
厂家：	AGERE SYSTEMS
描述：	Short-Loop Ringing SLIC with Ground Start 短循环振铃SLIC与地面开始
文件：	总48页 (文件大小：1018K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9216A [AGERE]

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