AK7752VQ [AKM]
Audio/Hands Free DSP with Stereo CODEC; 音频/免提DSP与立体声编解码器
| 型号： | AK7752VQ |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Audio/Hands Free DSP with Stereo CODEC |
| 文件： | 总23页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK7752]
AK7752
Audio/Hands Free DSP with Stereo CODEC
GENERAL DESCRIPTION
The AK7752 is a digital signal processor with an integrated stereo CODEC. The digital signal processor
(DSP) can execute a high-quality hands-free algorithm, using only internal memory. Fine tuning is
available for improving voice quality of the hands-free function in actual user environments. The
AK7752 includes delay RAM, an integrated PLL, four digital audio input and eight digital audio output
ports. The AK7752 can perform pre and post processing for speech recognition, volume control
adjustment and parametric equalization, executed by programs downloaded via the microprocessor
interface.
FEATURES
[ADC Block]
Sampling rate: 8kHz ~ 48kHz
24-bit stereo
S/(N+D): 86dB
DR, S/N: 89dB (fs=8 kHz), 91dB (fs=48kHz)
Integrated DC offset canceling High Pass Filter
[DAC Block]
Sampling rate: 8kHz ~ 48kHz
18-bit stereo
S/(N+D): 90dB (fs =8kHz), 88dB (fs=48kHz)
DR, S/N: 95dB (fs =8kHz), 95dB (fs=48kHz)
[Input/Output Digital Interface]
4-channel Serial Data Input
8-channel Serial Output
[General]
Integrated PLL
EEPROM (AK6514C) Interface
Microprocessor Interface: I²C BUS or AKM original mode
Power Supply: Single 3.3V ±0.3V
Operating Temperature Range: -40°C~85°C
64pin LQFP
MS0578-E-01-PB
2007/09
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[AK7752]
BLOCK DIAGRAM
VCOM
VREFH
ANE_OUT
ALINE_OUT
ALINE_IN
ANE_IN
VREFL
pull down
2
2
AVDD
AVSS
BVSS
Hi-z
Open drain
REF
ADC
DAC
2
SDATA_DA
SDATA_AD
ctrl reg sw
5
5
DVDD
DVSS
Lch:ANE_OUT
Rch:ALINE_OUT
SELA2A
Lch:ALINE_IN / Rch:ANE_IN
SWG0
SDOUTA
GPO0
SDINA
SDIN1
DEXT3_OUT
DEXT2_OUT
DLINE_IN
SDOUT3
OUTEX2_N
SDIN2
SWG1
DEXT_IN / JX3
SDOUT2
GPO1
DEXT1_OUT
DLINE_OUT
OUTEX1_N
OUTLE_N
HF(DSP)
SDOUT1
JX3_E
JX3
WDT
CRC
STO
CRC_E
JX2_E
JX1_E
JX2
JX2
JX1
JX0
I2CSEL
JX1
JX0
MICIF
RQ_N/CAD1
SI/CAD0
JX0_E
SCL/SCLK
SDA
SO
SO
RDY
EEST/RSTO_N
EESI
EESEL
EESEL
SEL_EEST
EEST
RSTO_N
TESTI1
TESTI2
EECK
CONT
EEPIF
CLK
EECS_N
EESO
INIT_RESET_N
S_RESET_N
CK_RESET_N
XTI
CKM[3:0]
4
CKM[3:0]
(Master="L", Slave="H")
SMODE
XTO
CLKO1
CLKO1E
BE
LE
TESTO1
LFLT
SYNC_O BITCLK_O SYNC_I BITCLK_I
Figure 1. Block Diagram
* Figure 1 shows a simplified diagram of the AK7752, which isn’t the perfect same as the actual circuit diagram.
MS0578-E-01-PB
2007/09
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[AK7752]
■ Ordering Guide
AK7752VQ
AKD7752
-40 ∼ +85°C
64pin LQFP
Evaluation Board for AK7752
■ Pin Layout
TESTI2
CKM[1]
CKM[0]
TESTI1
CLKO1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CKM[2]
CKM[3]
S_RESET_N
CK_RESET_N
INIT_RESET_N
SYNC_I
BITCLK_I
DVSS
LFLT
AVSS
AVDD
ANE_IN
ALINE_IN
AVDD
64pin LQFP
(TOP VIEW)
DVDD
VREFH
JX0
JX1
VCOM
VREFL
JX2
DEXT_IN/JX3
DLINE_IN
STO
AVSS
ALINE_OUT
ANE_OUT
Input
Output
I / O
Power
Note) XXXX is internal pull-down pin. XXXX is the pin name.
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[AK7752]
PIN/FUNCTION
No. Pin Name I/O
Function
Classification
EEPIF
EEPROM Chip Select Pin
1
2
3
EECS_N
O
Connect to the C_N pin of the AK6514C (EEPROM).The output is Hi-Z when
EESEL pin= “L”.
EEPROM Serial Data Receive Pin ( Internal pull-down )
Connect to the SO pin of the AK6514C (EEPROM).
Connect to DVSS or leave open when a EEPROM is not use.
EESO
I
EEPROM Serial Data Output Clock Pin
Connect to the SCK pin of the AK6514C (EEPROM). The output is Hi-Z when
EESEL pin = “L”.
EECK
O
EEPROM Serial Data Output Pin
4
5
EESI
O
-
Connect to the SI pin of the AK6514C. The output is Hi-Z when EESEL pin=
“L”.
Silicon Substrate Potential 0V
Analog Power
Supply
BVSS
Connect to AVSS.
6
7
DVSS
DVDD
-
-
Ground Pin for Digital Section 0.0V
Power Supply Pin for Digital Section (3.3V typical)
Digital
Power Supply
Microprocessor Interface Write Request Pin (I2CSEL pin = “L”)
When initial reset state and Microcomputer interface are not in use, leave RQ_N
pin= “H”.
Microprocessor
Interface.
8
RQ_N
I
CAD1
RDY
I
I2C Bus Address Setting Pin 1 (I2CSEL pin = “H”)
I2C
Microprocessor
Interface
9
O
Data Write Ready Output Pin for Microprocessor Interface
Serial Data Output Pin for Microprocessor Interface
When RQ_N pin = “H”, SO pin= Hi-Z
Serial Data Input Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SI is not used, tie the SI pin = “L”.
I2CSEL= “H” I2C Bus Address Pin 0
10
11
SO
SI
O
I
CAD0
DVSS
DVDD
I
-
-
I2C
12
13
Ground Pin for Digital Section 0.0V
Digital
Power Supply Pin for Digital Section (3.3V typical)
Power Supply
Serial Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SCLK is not used, tie the SCLK pin = “H”.
I2C Bus Data Clock Pin (I2CSEL pin = “H”)
Microprocessor
Interface
14
SCLK
SCL
I
I
I2C
TEST
I2C
Test Pin (I2CSEL pin = “L”)
Leave open. SDA goes “L”.
I/O I2C Bus Data Clock Pin (I2CSEL pin = “H”)
15
SDA
SDA
I/O
Test Output Pin
Leave open. Normally TESTO1 goes “L”.
16 TESTO1
17 STO
O
TEST
O
Status Output Pin
Status
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[AK7752]
No.
18
Pin Name
I/O
I
Function
Classification
Digital Section
HF Serial Data Input Pin ( Internal pull-down )
Compatible with MSB / LSB justified 24, 20 and 16 bits. Normally connected Serial Input
DLINE_IN
to Bluetooth line (receiving).
Data
Digital Section
Serial Input
Data /
Conditional
Input
HF Serial Data Input Pin ( Internal pull-down )
Compatible with MSB / LSB justified 24, 20 and 16 bits. This pin changes to
a conditional jump pin (JX3) by setting control register (JX3_E) to “1”.
DEXT_IN/
JX3
19
I
Conditional Jump Pin2 (Internal pull-down)
A conditional jump pin (JX2) is available by setting control register (JX2_E)
to “1”.
Conditional
Input
20
21
JX2
JX1
I
I
Conditional Jump Pin1 (Internal pull-down)
A conditional jump pin (JX1) is available by setting control register (JX1_E)
to “1”.
Conditional Jump Pin0 (Internal pull-down)
22
JX0
I
A conditional jump pin (JX2) is available by setting control register (JX0_E)
to “1”.
23
24
DVDD
DVSS
- Power Supply for Digital Section (3.3V typical)
- Ground Pin for Digital Section 0V
Digital
Power Supply
Serial Bit Clock Input Pin
Normally connected to the Bluetooth Data Clock line (256kHz/512kHz).
SYNC Input Pin
Normally connected to the Bluetooth Sync Clock line (8kHz).
25
26
BITCLK_I
SYNC_I
I
System Clock
I
Reset Pin (for initialization)
27 INIT_RESET_N
I
I
Use to initialize the AK7752. When changing CKM [3:0] and changing XTI
or BITCLK_I input frequency, it is necessary to set this pin.
Clock Reset Pin
When changing CKM[3:0] and XTI or BITCLK_I input frequency without
using INIT_RESET_N, it is necessary to set this pin. The control register
CKRST has the same function.
Reset
28 CK_RESET_N
29 S_RESET_N
I System Reset N Pin
I Clock Mode Select Pin 3
I Clock Mode Select Pin 2
Clock Output Pin 1
30
31
CKM[3]
CKM[2]
Mode Select
Clock Output
32
CLKO1
O
The output frequency is selected by a control register.
MS0578-E-01-PB
2007/09
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[AK7752]
No.
Pin Name I/O
Function
Classification
TEST
HF Serial Data Output Pin
The data format is MSB justified.
33 DEXT3_OUT O
EES Output Pin / Internal Reset Monitor Pin
Set by control resistor SEL_EEST.
SEL_EEST bit= “0”: EEST pin
SEL_EEST bit= “1”: RSTO_N Monitor internal reset process.
RSTO_N pin =“L”: Reset mode, RSTO_N pin =“H”: Exit reset mode.
EEST
/RSTO_N
EEPIF/
Monitor
34
O
Digital Section
Serial Input
Data
HF Serial Data Output Pin
Compatible with MSB / LSB justified 24, 20 and 16 bits.
35 DEXT2_OUT O
36 DEXT1_OUT O
37 DLINE_OUT O
HF Serial Data Input Pin
Compatible with MSB / LSB justified 24, 20 and 16 bits.
HF Serial Data Output Pin
Compatible with MSB / LSB justified 24, 20 and 16 bits. Normally connected
to Bluetooth line (sending).
Serial Bit Clock Output Pin
Normally goes “L” by control register setting.
Master Mode: Outputs 64fs or 32fs clock.
Slave Mode: Outputs BITCLK_I clock.
SYNC Output Pin
Normally goes “L” by control register setting.
Master Mode: Outputs 64fs or 32fs clock.
Slave Mode: Outputs SYNC_I clock.
38 BITCLK_O
O
O
System Clock
39
SYNC_O
40
41
DVDD
DVSS
- Power Supply for Digital Section (3.3V typical)
- Ground Pin for Digital Section 0V
Crystal oscillator output pin
Digital
Power Supply
42
43
XTO
XTI
O
When a crystal oscillator is used, connect it between XTI and XTO.
When an external clock is used, leave this pin open.
Crystal oscillator input pin
Connect a crystal oscillator between this pin and the XTO pin, or input an
external CMOS clock to the XTI pin.
System Clock
I
44
45
DVSS
DVDD
- Ground Pin for Digital Section 0V
- Power Supply for Digital Section (3.3V typical)
Digital
Power Supply
Analog
Silicon Substrate Potential 0V
Connect to AVSS.
46
BVSS
-
Power Supply
Control Mode select pin (Internal pull-down)
47
EESEL
I
EESEL pin = “L” : Normal mode
EEPIF
EESEL pin = “H”: In self-boot up mode using an AKM EEPROM, AK6514C
I2C BUS Select Pin (Internal pull-down)
I2CSEL pin = “L”: Normal serial interface
48
49
I2CSEL
TESTI2
I
I
I2C Select
TEST
I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active.
I2CSEL should be connected to “L” (DVSS) or “H” (DVDD).
TEST pin (Internal pull-down)
Connect to DVSS.
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[AK7752]
No. Pin Name I/O
Function
Classification
Mode Select
50
51
CKM[1]
CKM[0]
I Clock Mode Select Pin 1
I Clock Mode Select Pin 0
TEST pin (Internal pull-down)
Connect to DVSS.
PLL RC component connect pin
Connect a series resistor and capacitor pair to this pin.
52
53
TESTI1
LFLT
I
TEST
O
Analog Output
54
55
AVSS
AVDD
- Analog ground Pin 0V (Silicon substrate potential)
- Power Supply Pin for Analog Section (3.3V typical)
Analog
Power Supply
ADC Analog Input Pin (ANE_IN)
Normally connected to the microphone amplifier.
56
ANE_IN
I
Analog Input
ADC Analog Input Pin (ALINE_IN)
Normally the receiving analog phone voice signal is input.
57 ALINE_IN
I
Analog
Power Supply
58
59
AVDD
- Analog Power Supply Pin (3.3V typical)
Analog Reference Voltage Input Pin
VREFH
I
Connect this pin to AVDD. Connect capacitors of 0.1 uF and 10 uF between this Analog Input
pin and AVSS.
Analog Common Voltage Output pin
60
VCOM
O
I
Connect capacitors of 0.1 uF and 10 uF between this pin and AVSS. No external Analog Output
circuits should be connected to this pin.
Analog Reference Voltage Input pin
Connect this pin to AVSS.
61
62
63
VREFL
AVSS
Analog Input
Analog
Power Supply
- Analog ground Pin 0V (Silicon substrate potential)
DAC Analog Output Pin (ALINE_OUT)
O
ALINE_OUT
Normally the sending analog phone voice signal is output.
DAC Analog Output Pin (ANE_OUT)
Analog Output
64 ANE_OUT
O
Normally connected to the speaker amplifier.
Note 1. Do NOT leave digital input pins open except for pins that indicate “Internal pull down”, BITCLK_I and
SYNC_I at master mode. (Internal pull down pins except TEST1 and TEST2 pins leave them open or connect
them to DVSS. Connect TEST1 and TEST2 pins to DVSS).
Note 2. When analog input pins (ALINE_IN, ANE_IN) are not used, leave them open.
Note 3. Connect I2CSEL to “L” (DVSS) or “H” (DVDD).
Relationship between I2CSEL and SDA
uP I/F
I2CSEL
INIT_RESET_N
SDA
Normal Serial
Interface
L
L
H
H
L
H
L
L
L
I2C Bus Mode
“Hi-Z” → pull-up
H
function
MS0578-E-01-PB
2007/09
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[AK7752]
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS=0V: All voltages are with respect to ground)
Parameter
Power Supply Voltage
Symbol
min
max
Units
Analog (AVDD)
Digital (DVDD)
|AVSS(BVSS) – DVSS| (Note 4)
Input Current (except for power supply pin )
Analog Input Voltage
VA
VD
ΔGND
-0.3
-0.3
4.6
4.6
0.3
±10
V
V
V
IIN
-
mA
VINA
-0.3
VA+0.3
V
ALINE_IN, ANE_IN
Digital Input Voltage
Operating Ambient Temperature
Storage Temperature
VIND
Ta
Tstg
-0.3
-40
-65
VD+0.3
85
150
V
°C
°C
Note 4. AVSS, BVSS and DVSS must be connected to the same ground plane..
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, BVSS, DVSS=0V: All voltages indicated are relative to the ground)
Parameter
Symbol
min
typ
max
Units
Power Supply Voltage
AVDD
VA
VD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
DVDD
Reference Voltage (VREF)
VREFH (Note 5)
VREFL (Note 6)
VRH
VRL
VA
0.0
V
V
Note 5. VREFH is normally connected to AVDD.
Note 6. VREFL is normally connected to AVSS
Note: The analog input voltage and output voltage are proportional to the VREFH-VREFL voltages.
When using the AK6514C, the same voltage as used for the digital section of the AK7752 is recommended.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0578-E-01-PB
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[AK7752]
ELECTRIC CHARACTERISTICS
(1) Analog Characteristics
1) fs=8kHz
(Ta = 25°C; AVDD, DVDD = 3.3V; VREFH = AVDD, VREFL = AVSS;
BITCLK = 64fs; Signal frequency 1kHz; Measurement frequency = 20Hz to 3.4 kHz; fs = 8kHz;
CKM Mode 0 (CKM[3:0]=LLLL) Unless otherwise specified.)
Parameter
min
typ
max
Units
ADC
Resolution
24
Bits
Section
Dynamic Characteristics
S/(N+D) (-1dBFS)
Dynamic Range
S/N
76
81
81
90
86
89
89
dB
dB
dB
dB
(Note 7)
Inter-Channel Isolation (f=1kHz) (Note 8.)
DC accuracy
105
Channel Gain Mismatch
Analog Input
Input Voltage
Input Impedance
Resolution
0.2
0.5
2.18
18
dB
(Note 9)
1.78
40
1.98
60
Vp-p
kΩ
Bits
DAC
Section
Dynamic Characteristics
S/(N+D) (0dB)
Dynamic Range
S/N
80
87
87
85
90
95
95
dB
dB
dB
dB
(Note 7)
Inter-Channel Isolation (f=1kHz) (Note 10)
DC accuracy
100
Channel Gain Mismatch
Analog Output
Output Voltage
Load Resistance
Load Capacitance
0.2
0.5
2.15
50
dB
(Note 11)
1.85
10
2.00
Vp-p
kΩ
pF
Note 7. S/(N+D) when -60dB signal is applied.
Note 8. Inter-channel isolation between ALINE_IN and ANE_IN at –1dB FS signal input.
Note 9. The full scale for analog input voltage is FS = (VREFH-VREFL) ∗ 0.6.
Note 10. Between ANE_OUT and ALINE_OUT.
Note 11. Full scale output voltage when VREFH = AVDD, VREFL = AVSS.
MS0578-E-01-PB
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[AK7752]
2) fs=48kHz
(Ta = 25°C; AVDD, DVDD = 3.3V; VREFH = AVDD, VREFL = AVSS;
BITCLK = 64fs; Signal frequency 1kHz; Measurement frequency = 20Hz to 3.4kHz; fs = 48kHz;
CKM Mode 0 (CKM [3:0]=LLLL) Unless otherwise specified. )
Parameter
min
typ
max
Units
ADC
Resolution
24
Bits
Section
Dynamic Characteristics
S/(N+D) (-1dBFS)
Dynamic Range (A-weighted)
S/N (A-weighted)
76
83
83
90
86
91
91
dB
dB
dB
dB
(Note 12)
Inter-Channel Isolation (f=1kHz) (Note 13)
DC accuracy
110
Channel Gain Mismatch
Analog Input
Input Voltage
Input Impedance
Resolution
0.2
0.5
2.20
18
dB
(Note 14)
1.80
35
2.00
50
Vp-p
kΩ
Bits
DAC
Section
Dynamic Characteristics
S/(N+D) (0 dB)
78
87
87
85
88
95
95
dB
dB
dB
dB
Dynamic Range (A-weighted)
S/N (A-weighted)
Inter-Channel Isolation (f=1kHz) (Note 15)
DC Accuracy
(Note 12)
100
Channel Gain Mismatch
Analog input
Output Voltage
Load Resistance
Load Capacitance
0.2
0.5
2.15
50
dB
(Note 16)
1.85
10
2.00
Vp-p
kΩ
pF
Note 12. S/(N+D) when -60dB signal is applied.
Note 13. Inter-channel isolation between ALINE_IN and ANE_IN at –1 dB FS signal input.
Note 14. The full scale for analog input voltage is FS=(VREFH-VREFL)×0.606.
Note 15. Between ANE_OUT and ALINE_OUT.
Note 16. Full scale output voltage when VREFH=AVDD, VREFL=AVSS.
MS0578-E-01-PB
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[AK7752]
(2) DC Characteristics
(Ta=-40°C ~ 85°C; AVDD, DVDD=3.0 ~ 3.6V)
Parameter
Symbol
min
typ
max
Units
High Level Input Voltage
Low Level Input Voltage
SCL, SDA High Level Input Voltage
SCL, SDA Low Level Input Voltage
High Level Output Voltage Iout=-100μA (Note 18)
Low Level Output Voltage Iout=100μA
(Note 17)
(Note 17)
VIH
VIL
VIH
VIL
VOH
VOL
80%VDD
70%VDD
VDD-0.5
V
V
V
V
V
V
20%VDD
30%VDD
0.5
SDA Low Level Output Voltage Iout=3mA
VOL
Iin
Iid
0.4
±10
V
Input Leak Current
(Note 19)
μA
μA
μA
Input Leak Current (pull-down pin) (Note 20)
Input Leak Current (XTI pin)
22
26
Iix
Note 17. SCL and SDA pins are not included. (SI, SCLK pins are included)
Note 18. SDA pin is not included.
Note 19. Pull-down pins and XTI pin are not included.
Note 20. EESO, DLINE_IN, DEXT_IN / JX3, JX2, JX1, JX0, EESEL, I2CSEL, TESTI2 and TESTI1 (Typ150kΩ)
(3) Current Consumption
(Ta=25°C; AVDD, DVDD=3.0~3.6V (typ = 3.3V, max = 3.6V)
Parameter
min
typ
max
Units
Power Supply Current (Note 21)
AVDD
DVDD
AVDD + DVDD
10
90
100
mA
mA
mA
165
Note 21. The current of DVDD changes depending on the system frequency and contents of the DSP program.
MS0578-E-01-PB
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[AK7752]
(4) Digital Filter Characteristics
1) ADC Section:
(Ta= 25°C; AVDD, DVDD=3.0 ~ 3.6V; fs = 8kHz; Note 22)
Parameter
Passband (±0.1dB) (Note 23)
Symbol
min
0
typ
max
3.15
Units
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
PB
(-1.0dB)
(-3.0dB)
3.63
3.83
Stopband
Passband Ripple
Stopband Attenuation (Note 24, Note 25)
Group Delay Distortion
Group Delay
SB
PR
SA
GD
GD
4.66
65
(Note 23)
±0.1
0
(Ts=1/fs)
16.3
Note 22. HPF response is not included.
Note 23. The passband is from DC to 3.15kHz when fs = 8kHz.
Note 24. The stopband is from 4.66kHz to 507.34kHz when fs = 8kHz.
Note 25. When fs = 8 kHz, the analog modulator samples the analog input at 512kHz
2) DAC Section:
(Ta=25°C; AVDD, DVDD=3.0~3.6V; fs=8kHz)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband (±0.1dB) (Note 26)
(-6.0dB)
PB
0
-
4.57
3.5
-
kHz
kHz
kHz
dB
dB
Ts
4.0
Stopband
(Note 26)
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay (Ts=1/fs) (Note 27)
Digital Filter + SCF
±0.01
59
-
15
Amplitude Characteristics 0~3.5kHz
±0.5
dB
Note 26. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents
PB=0.4292fs (@-0.06dB) and SB=0.571fs, respectively.
Note 27. The digital filter’s delay is calculated as the time from setting 18 Bit data into the input register until an analog
signal is output.
MS0578-E-01-PB
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[AK7752]
(5) Switching Characteristcis
1) System Clock
(Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Units
XTI
CKM Mode 0-6
a) with a Crystal Oscillator:
Frequency (CKM Mode 0/2)
fXTI
fXTI
-
-
11.2896
12.288
24.576
-
-
MHz
MHz
Frequency (CKM Mode 1/3)
b) with an External Clock
Duty Cycle
40
50
60
%
Frequency (CKM Mode 0/2)
fXTI
fXTI
11.0
12.4
MHz
Frequency (CKM Mode 1/3)
22
24.8
MHz
Clock Rise Time
Clock Fall Time
SYNC_I Frequency
tCR
tCF
Fs
6
6
48
ns
ns
kHz
(Note 28)
7.35
8
Clock rise time
Clock fall time
tLR
tLF
6
6
ns
ns
BITCLK_I Frequency
High Level Width
Low Level Width
Clock Rise Time
Clock Fall Time
tBCLKH
tBCLKL
tBR
tBF
fBCLK
120
120
ns
ns
ns
ns
fs
%
MHz
fs
6
6
64
60
3.2
-
a) CKM Mode 2/3
(Note 29)
32
40
0.23
-
Duty Cycle
Frequency (CKM Mode 2/3)
50
b) CKM Mode 4
Duty Cycle
(Note 30)
fBCLK
32
50
40
60
%
Frequency (CKM Mode 4)
fBCLK
fBCLK
230
-
256
64
258
-
kHz
fs
c) CKM Mode 5/6
(Note 31)
Duty Cycle
40
50
60
%
Frequency (CKM Mode 5)
Frequency (CKM Mode 6)
fBCLK
fBCLK
460
2.75
512
3.072
516
3.1
kHz
MHz
Note 28. SYNC_I frequency and sampling rate (fs) should be the same.
Note 29. When BITCLK_I is 32fs, I/O interface format has some limitation.
Note 30. When BITCLK_I is a source of master clock, it should be 32 times fs correctly.
Note 31. When BITCLK_I uses as a source of master clock, it should be 64 times fs correctly.
MS0578-E-01-PB
2007/09
- 13 -
[AK7752]
2) Reset
(Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V)
Parameter
INIT_RESET_N
CK_RESET_N
S_RESET_N
Symbol
tRST
tRST
tRST
min
600
600
600
typ
max
Units
(Note 32)
ns
ns
ns
Note 32. The AK7752 can be powered up when INIT_RESET_N pin = “L”. The power supply must be ON and the
master clock must be input before the INIT_RESET_N pin transitions “H”.
3) Audio interface
(Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V; CL=20pF)
Parameter
Symbol min
typ
max
Units
Slave Mode (CKM Mode 2-4)
Delay Time from BITCLK_I “↑” to SYNC_I (Note 33)
Delay Time from SYNC_I to BITCLK_I “↑” (Note 33)
Delay Time from SYNC_I,_O to Serial Data Output
Delay Time from BITCLK_I,_O to Serial Data Output
Serial Data Output Latch Setup Time
tBLRD
tLRBD
tLRD
tBSOD
tBSIDS
tBSIDH
60
60
Ns
Ns
ns
ns
ns
ns
80
80
80
80
Serial Data Input Latch Hold Time
Master Mode (CKM Mode 0-1)
BITCLK_O Frequency (BIT32FS bit = “0”)
BITCLK_O Frequency (BIT32FS bit = “1”)
BITCLK_O Duty Factor
Delay Time from BITCLK_O “↑” to SYNC_O (Note 34) tBLRD
Delay Time from SYNC_O to BITCLK_O “↑” (Note 34) tLRBD
Delay Time from SYNC_O to Serial Data Output
Delay Time from BITCLK_O to Serial Data Output
Serial Data Output Latch Setup Time
fBCLK
64
32
50
fs
fs
%
ns
ns
ns
ns
Ns
ns
60
60
tLRD
tBSOD
tBSIDS
tBSIDH
80
80
80
80
Serial Data Input Latch Hold Time
Note 33. BITCLK_I “↑“ must not occur at the same time as SYNC_I edge.
Note 34. BITCLK_O “↑“ must not occur at the same time as SYNC_O edge.
(When control register SEL_BCK bit = “0”. The edge reverses when SEL_BCK bit = “1”.)
MS0578-E-01-PB
2007/09
- 14 -
[AK7752]
4) Microprocessor Interface
(Ta=-40ºC~85ºC; AVDD, DVDD=3.0~3.6V; CL=20pF)
Parameter
Symbol
min typ
max
Units
Microprocessor Interface Signal
RQ_N Fall Time
RQ_N Rise Time
SCLK Fall Time
SCLK Rise Time
SCLK Frequency
SCLK Low Level Width
SCLK High Level Width
tWRF
tWRR
tSF
30
30
30
30
2.1
ns
ns
ns
ns
MHz
tSR
fSCLK
tSCLKL
tSCLKH
200
200
ns
ns
Microprocessor to AK7752
Time from S_RESET_N “↓” to RQ_N “↓”
Time from RQ_N “↑” to S_RESET_N “↑”
RQ_N High Level Width
Time from RQ_N “↓” to SCLK “↓”
Time from SCLK “↑” to RQ_N “↑”
SI Latch Setup Time
tREW
tWRE
tWRQH
tWSC
tSCW
tSIS
tSIH
tSOS
tSOH
500
500
500
500
800
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
SI Latch Hold Time
200
Delay Time from SCLK “↓“ to SO Output
Hold Time from SCLK “↑“ to SO Output
Time from RQ_N “↓” to SO Hi-Z Release
(Iout=±360μA)
200
tRQHR
tRQHS
600
600
ns
ns
RQ_N “↑” to SO Hi-Z set (Iout=±360μA)
MS0578-E-01-PB
2007/09
- 15 -
[AK7752]
5) I2CBUS Interface
(Ta=-40ºC~85ºC; AVDD, DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Units
I2C Timing
SCL Clock Frequency
fSCL
tBUF
tHD:STA
400
KHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first Clock pulse)
Clock Low Time
1.3
0.6
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
μs
μs
μs
μs
μs
μs
μs
μs
ns
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
By Input Filter
0.9
0.1
0.3
0.3
tF
tSU:STO
tSP
0.6
0
50
Capacitive Load on Bus
Cb
400
pF
Note 35. I2C is a registered trademark of Philips Semiconductors.
6) EEPROM Interface
(Ta=-40ºC ~ 85ºC; AVDD, DVDD=3.0 ~ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
EEPROM→AK7752
EESO Latch Setup Time (EESEL pin = “H”)
EESO Latch Hold Time (EESEL pin = “H”)
Time from EESEL “↑” to EECS_N, EECK, EESI
Hi-Z release (Iout=±360μA)
Time from EESEL “↓” to EECS_N, EECK, EESI
Hi-Z set (Iout=±360μA)
tEESOS
tEESOH
160
160
ns
ns
tESLHR
tESLHS
600
600
ns
ns
MS0578-E-01-PB
2007/09
- 16 -
[AK7752]
(6) Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
tCF
tCR
1/fs
ts=1/fs
1/fs
SYNC_I
VIH
VIL
tLR
tLF
1/fBCLK
tBCLK=1/fBCLK
1/fBCLK
VIH
VIL
BITCLK_I
tBR tBF
tBCLKL
tBCLKH
Figure 2. System Clock
INIT_RESET_N
tRST
CK_RESET_N
S_RESET_N
VIL
Figure 3. Reset
MS0578-E-01-PB
2007/09
- 17 -
[AK7752]
SYNC_I
50%DVDD
SYNC_O
tLRBD
tBLRD
tLRD
50%DVDD
50%DVDD
50%DVDD
BITCLK_I
BITCLK_O
tBSOD
DLINE_OUT
DEXT1_OUT
DEXT2_OUT
DEXT3_OUT
tBSIDS
tBSIDH
DLINE_IN
DEXT_IN
Figure 4. Audio Interface
VIH
VIL
RQ_N
tWRF
tWRR
Figure 5. Microprocessor Interface Signal 1
tSF
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
Figure 6. Microprocessor Interface Signal 2
MS0578-E-01-PB
2007/09
- 18 -
[AK7752]
VIH
VIL
tWRQH
RQ_N
SI
VIH
VIL
tSIS
tSIH
VIH
VIL
SCLK
SO
tWSC
tSCW
tWSC
tSCW
VIH
VIL
tSOH
tSOS
Figure 7. Microprocessor Æ AK7752
VIH
VIL
RQ_N
tRQHR
tRQHS
VOH
VOL
SO
Figure 8. Microprocessor Æ AK7752
MS0578-E-01-PB
2007/09
- 19 -
[AK7752]
VIH
VIL
SDA
SCL
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
tHD:STA
tHD:DAT
tSU:DAT tSU:STA
Start
tSU:STO
Stop
Stop Start
Figure 9. I2C Bus Interface
50%DVDD
50%DVDD
EECK
EESO
tEESOS
tEESOH
Figure 10. EEPROM Interface 1
VIH
VIL
EESEL
tESLHR
tESLHS
VOH
VOL
EECS_N, EECK, EESI
Figure 11. EEPROM Interface 2
MS0578-E-01-PB
2007/09
- 20 -
[AK7752]
PACKAGE
64pin LQFP
(Unit: mm)
12.0±0.3
Max 1.70
1.40
10.0
0.10±0.10
33
32
48
49
64
17
16
1
0.17±0.05
0.5
0.21±0.05
0.10
M
1.0
0°~10°
0.45 ±0.2
0.10
Material & Lead finish
Package:
Lead-frame:
Lead-finish:
Epoxy
Copper
Soldering plate (Pb free)
MS0578-E-01-PB
2007/09
- 21 -
[AK7752]
MARKING
AKM
AK7752VT
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX (7 digits)
3) Marking Code: AK7752VT
4) Asahi Kasei Logo
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of As
ahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application
or use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support,
or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the
use approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or sy
stem containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its fail
ure to function or perform may reasonably be expected to result in loss of life or in significant injur
y or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless
from any and all claims arising from the use of said product in the absence of such notification.
MS0578-E-01-PB
2007/09
22
[AK7752]
Thank you for your access to AKEMD product informations.
More detail product informations are available, please contact
our sales office or authorized distributors.
MS0578-E-01-PB
2007/09
23
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