AK7754EN [AKM]
Audio DSP with Stereo CODEC MIC/HP-AMP; 音频DSP带有立体声编解码器MIC / HP- AMP
| 型号： | AK7754EN |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Audio DSP with Stereo CODEC MIC/HP-AMP |
| 文件： | 总26页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK7754]
AK7754
Audio DSP with Stereo CODEC + MIC/HP-AMP
GENERAL DESCRIPTION
The AK7754 is a highly integrated audio digital signal processor (DSP) with two Audio I/F’s, Microphone and
Headphone Amplifier. The audio DSP has 1536step/fs (at 48KHz sampling) parallel processing power, and
AKM’s original Hands-free technology provides high performance noise and echo cancelling. The 96k-bit
delay memory allows surround processing, acoustic effect and parametric equalizers. As the AK7754 is a
RAM based DSP, it is programmable for user requirements. The internal SRC has various sampling rate
converting modes, corresponds many sampling rates without changing the DSP operating sampling
frequency. The AK7754 is available in a space saving small 48pin QFN package.
FEATURES
□ DSP Block
- Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point)
- Processing Speed: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz)
- Multiplication: 20 x 16 → 36-bit Double precision arithmetic available
- Divider 20 / 20 → 20bit
- ALU: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic
and logic operation
- Program RAM: 2048 x 36bit
- Coefficient RAM: 2048 x 16bit (F24 floating point)
- Data RAM: 512 x 24-bit (F24 floating point)
- Offset Register: 32 x 12bit
- Delay RAM1: 3072 x 24bit
- Delay RAM2: 2048 x 12bit
- Sampling rate: fs= 8.0k ~ 48kHz
- Master/Slave Operation
- Master Clock: 1536fs
(generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL)
□ Two Digital Interfaces (I/F 1, I/F 2)
- Digital Signal Input Port (4ch) MSB justified 24bit/LSB justified 24/20/16bit and I2S
- Digital Signal Input Port (6ch) MSB justified 24bit/ LSB justified 20/16bit and I2S
- Short / Long Frame
-24 bit linear, 8 bit A-law, 8 bit µ-law
□ Stereo 24bit ADC Block
- Sampling rate: 8 ~ 48kHz
- ADC Characteristics S/(N+D): 82dB ,DR, S/N: 89dB
- Three Analog Input Selectors (Differential, Single-ended Inputs)
- Channel Independent MIC, Analog Line Gain Amp (0dB, 9dB~27dB, 3dBstep)
- Channel Independent Digital Volume (24dB ~ -103dB, 0.5dB Step, Mute)
- Integrated DC offset canceling High Pass Filter
□ Digital Microphone I/F
MS1138-E-01-PB
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[AK7754]
□ Stereo 24bit DAC
- Sampling rate: 8 ~ 48kHz
- Digital Volume (12dB~-115dB, 0.5dB Step, Mute)
- Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
□ Line Outputs
- Single-ended or Differential Outputs
- S/(N+D): 91dB ,DR, S/N: 96dB
- Stereo Analog Volume (+0 ~ -28dB, 2.0dB Step, Mute)
□ Stereo Headphone Amplifier with a Volume Control
- Rated Output Power: 27mW/ch @16Ω
- S/(N+D): 70dB , S/N: 89dB
- Stereo Analog Volume (+0 ~ -50dB,1.0/2.0/4.0dB Step, Mute)
- Click Noise Free at Power ON/OFF
□ SRC Block
- 2ch x 1 system
- Input Sampling Frequency: 8kHz ~ 96kHz
- Output Sampling Frequency: 8kHz ~ 48kHz
□ Analog Bypass Mode
- Bypass Amplifier (0dB~-21dB, 3dB step)
□ Output Mixer
□ μP Interface: I2C Bus (400KHz Fast-Mode)
□ Power Supply
Analog
Digital1
Digital2
HP-Amp
AVDD: 3.0V ~ 3.6V (typ.3.3V)
DVDD: 3.0V ~ 3.6V (typ.3.3V)
DVDD18: 1.7V ~ 1.9V (typ.1.8V)
HVDD: 3.0V ~ 3.6V (typ.3.3V)
□ Operating temperature range: -20°C ~ 85°C
□ Package: 48pin QFN (0.5mm pitch)
MS1138-E-01-PB
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[AK7754]
■ Block Diagram
VCOM
MPRF
PMMP
pull down
VREF
MPWR
MIC POWER
HVDD
PMPSL
PMPSR
Open Drain
1
0
AVDD
DVDD
DVDD18
VSS
BPSL
BPSR
PMMICL
IN1L/IN1P
IN2L/IN1N
2
IN1L/IN1P
IN2L
0
1
PMLOL
MICL
IN1N
Line
PMADL/R
OUTL/OUTP
OUTR/OUTN
PMDAL/R
PMLINL
PMLINR
0
1
AINL
IN3L
IN3R
IN3L/DMCLK
IN3R/DMDAT
LINL
LINR
ADC
DAC
Line
1
0
PMLOR
PMHPL
AINR
DAL
DAR
PMMICR
IN1R/IN2P
IN2R
IN1R/IN2P
IN2R/IN2N
DIGMIC IF
MICR
HPL
IN2N
HP
DMCLK
DMDAT
HVCOM
LRCKOE
BICKOE
PMHPR
LRCKO
BICKO
CLKO
SDOUTAD
HPR
HP
CLKOE
MLRCLK0
MBITCLK0
MCLK0
XTO
XTI
MDSPCLK0
CLKGEN & CONT
LFLT
INITRSTN
TEST1
BICK1/JX1
LRCK1/JX0
SELDAI[1:0]
3
2
1
0
DIN3
JX2
DOUT3
GP0
SELJX2
JX2E
SELDOM[1:0]
1
0
3
2
SELMN
OUTME
0
1
RDY/SDOUTM
SO/RDY
JX1E
JX0E
1
0
JX1
1
0
SELSON
SELJX
RDY
SO
1
0
1
0
JX0
TEST2
CAD1
SCL
MICIF
CAD0
SDA
SRC
BICK2/JX1
LRCK2/JX0
SRCBICKO
SRCLRCKO
WDT
DSP
WDTEN
LOCKE
SRCLFLT
SDIN2/JX2
STO
UNLOCK
SRCO
SRCI
0
1
DIN2
SELDO2[1:0]
3
GP1
SELDI2
PMSRC
OUT2E
2
SDOUT2
1
0
DOUT2
SELDO1[1:0]
IRPT
3
OUT1E
2
SDOUT1
1
0
DIN1
SDIN1/JX2
DOUT1
PMDSP
Figure 1. Block Diagram
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[AK7754]
■ DSP Block Diagram
DLP0,DLP1
DLRAM
CP0,CP1
DP0,DP1
DRAM
512w x 24-Bit
512w x 24-Bit
OFREG
3072w x 24-Bit
2048w x 12-Bit
CRAM
32w x 12-Bit
2048w x 16-Bit
CBUS(16-Bit)
DBUS(24-Bit)
Micon I/F
MPX16
X
MPX20
Control
Serial I/F
PRAM
DEC
Y
2048w x 36-Bit
Multiply
16 x 20 → 36-Bit
PC
Stack: 5level(max)
TMP 12 x 24-Bit
24-Bit
36-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
SHIFT
40-Bit
40-Bit
A
B
2 x 24,16-Bit
DIN3 (ADC)
ALU
2 x 24,20,16-Bit DIN2 (SRC)
2 x 24,20,16-Bit DIN1
40-Bit
Overflow Margin: 4-Bit
40-Bit
∼
DR0
3
40-Bit
2 x 24,20,16-Bit DOUT3 (DAC)
2 x 24,20,16-Bit DOUT2
Over Flow Data
Generator
DOUT1
2 x 24,20,16-Bit
Division
20÷20→20
Peak Detector
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[AK7754]
■ Ordering Guide
AK7754EN
AKD7754
-20 ∼ +85°C
48pin QFN (0.5mm pitch)
Evaluation Board for AK7754
■ Pin Layout (TBD)
OUTL/OUTP
AVDD
37
38
RDY/SDOUTM
24
23
22
21
RDY
SDA
SCL
VSS4
39
40
VCOM
CAD0
CAD1
LRCK2/JX0
20
19
18
17
16
15
14
13
MPRF
MPWR
IN1R/IN2P
IN1L/IN1P
41
AK7754EN
42
43
44
45
46
47
48
Top View
BICK2/JX1
SDIN2/JX2
SDOUT2
IN2R/IN2N
IN2L/IN1N
IN3R/DMDAT
IN3L/DMCLK
SDOUT1
CLKO
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[AK7754]
PIN FUNCTION
No.
1
Name
I/O
O
Function
Classification
Analog Output
PLL RC component connect pin
Connect a capacitor and resistor between this pin and VSS4. This pin
outputs “L” during initial reset.
LFLT
Test1 Pin (Internal pull-down)
This pin must be connected to VSS1.
Crystal oscillator output pin
When a crystal oscillator is used, connect it between XTI and XTO. When
an external clock is used, leave this pin open. During initial reset, the output
of this pin is Hi-Z.
Crystal oscillator input pin/ Master Clock input
Connect a crystal oscillator between this pin and the XTO pin, or input an
external clock to the XTI pin. When CKM[2:0] bits= 0h, 1h, 2h, input “L”
to this pin.
2
3
TEST1
XTO
I
Test
O
System Clcok
4
XTI
I
5
6
7
DVDD
VSS1
DVDD18
JX2
SDIN1
JX1
BICK1
JX0
LRCK1
-
-
-
I
I
I
I
Power Supply for Digital Section 3.0V ~ 3.6V
Ground Pin 0V
Digital Power Supply Pin 1.7V~1.9V
Conditional Jump Pin2 (JX2E bit = “1”)
Serial Data Input Pin1
Conditional Jump Pin1 (JX2E bit = “1”)
Serial Bit Clock Input Pin1
Digital
Power Supply
Conditional Input
Data I/F
Conditional Input
Data I/F
Conditional Input
Data I/F
8
9
Conditional Jump Pin0 (JX2E bit = “1”)
LR Channel Select Clock Pin1
10
I
Serial Bit Clock Output Pin (BICKOE bit = “1”)
Outputs “L” during initial reset in master mode.
LR Channel Select Clock Pin (LRCKOE bit = “1”)
Outputs “L” during initial reset in master mode.
Clock Output Pin (CLKOE bit = “1”)
Outputs “L” during initial reset in master mode.
Serial Data Output Pin1
Outputs “L” during initial reset in master mode.
Serial Data Output Pin2
Outputs “L” during initial reset in master mode.
Conditional Jump Pin2 (JX2E bit = “1”)
Serial Data Input Pin2
Conditional Jump Pin1 (JX2E bit = “1”)
Serial Bit Clock Input Pin2 (for SRC)
System Clock
Output
System Clock
Output
11 BICKO
12 LRCKO
13 CLKO
O
O
O
O
O
System
Data I/F
Data I/F
14 SDOUT1
15 SDOUT2
JX2
16
I
I
I
I
Conditional Input
Data I/F
Conditional Input
Data I/F
SDIN2
JX1
BICK2
17
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[AK7754]
No.
18
Name
I/O
I
Function
Conditional Jump Pin0 (JX0E bit = “1”)
A conditional jump pin (JX0) is available by setting control register (JX0E)
to “1” when SCKSEK bit = “1”.
Classification
Conditional Input
Data I/F
JX0
LRCK2
I
I
I
I
LR Channel Select Clock Pin2 (for SRC)
19 CAD1
20 CAD0
21 SCL
I2C Bus Address Pin1
I2C Bus Address Pin0
I2C Bus Interface
I2C
I2C Bus Clock
22 SDA
23 RDY
I/O
O
Outputs “Hi-z” during initial reset.
Data Write Ready Output Pin for Microprocessor Interface
Data Write Ready Output Pin for Microprocessor Interface
(SELM bit= “0”)
Serial Data Monitering Selector Output Pin
Outputs “L” during initial reset.
Status Output Pin
Outputs “H” during initial reset.
Initial Reset Pin
Use to initialize the AK7754. This pin must be “L” when power up the
AK7754.
Microprocessor I/F
Microprocessor I/F
RDY
24
O
(SELM bit= “0”)
SDOUTM
O
O
25 STO
Status
Reset
Test
26 INITRSTN
I
Test2 Pin
27 TEST2
28 DVDD
29 VSS2
I
-
-
This pin must be connected to DVDD.
Digital
Power Supply
Digital
Power Supply for Digital Section 3.0V ~ 3.6V
Ground Pin 0V
Power Supply
SRC, PLL RC component connect pin
30 SRCLFLT
31 VSS3
O
-
Connect a 1μF capacitor between this pin and VSS2. This pin outputs “L” Analog Output
during initial reset.
Analog
Power Supply
Ground Pin 0V
Headphone Common Voltage Output Pin
32 HVCOM
O
-
Connect a of 1μF cap to VSS3. Do not use for an outside circuits. Outputs
“L” during initial reset.
Headphone
Analog
Power Supply
33 HVDD
34 HPR
35 HPL
Headphone Power Supply Pin 3.0V~3.6V
O Headphone Rch Output Pin
Outputs “L” during initial reset
O Headphone Lch Output Pin
Outputs “L” during initial reset
Analog Output
Analog Output
DAC Rch Output Pin
Outputs “L” during initial reset
Inverted Line Output Pin
Outputs “L” during initial reset
DAC Lch Output Pin
Outputs “L” during initial reset
DAC Non-inverted differential Analog Output Pin (LODIF bit= “1”)
Outputs “L” during initial reset
(LODIF bit= “0”)
(LODIF bit= “1”)
(LODIF bit= “0”)
OUTR
36
O
Analog Output
Analog Output
OUTN
O
OUTL
37
O
OUTP
O
-
Analog
Power Supply
38 AVDD
Analog Power Supply Pin 3.0V~3.6V
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[AK7754]
No.
Name
I/O
-
Function
Classification
Analog
Power Supply
Ground Pin 0V
39 VSS4
Analog common voltage
40 VCOM
O
Connect 0.1μF and 2.2μF capacitors in parallel to VSS4. Never to use for
an external circuit. Outputs “L” during initial reset
Ripple Filter Pin for Microphone Power Supply
Connect a 1uF capacitor between this pin and VSS4.
Power Supply Pin for Microphone
Analog Output
41 MPRF
42 MPWR
O
O
Analog Output
Analog Output
Analog Input
Analog Input
Analog Input
Analog Input
Outputs “Hi-Z” during initial reset
Rch Single-end Input Pin1
MIC Differential Non-Inverted Input Pin2
(MDIFR bit = “0”)
(MDIFR bit = “1”)
(MDIFL bit = “0”)
(MDIFL bit = “1”)
(MDIFR bit = “0”)
(MDIFR bit = “1”)
(MDIFL bit = “0”)
(MDIFL bit = “1”)
(DMIC bit = “0”)
(DMIC bit = “1”)
(DMIC bit = “0”)
(DMIC bit = “1”)
IN1R
43
I
I
IN2P
IN1L
IN1P
I Lch Single-end Input Pin1
I MIC Differential Non-inverted Input Pin1
I Rch Single-end Input Pin2
I MIC Differential Inverted Input Pin2
I
I
I
I
I
O
44
IN2R
IN2N
45
Lch Single-end Input Pin2
MIC Differential Inverted Input Pin1
Rch Single-end Input Pin3
Digital Microphone Data Input Pin
Lch Single-end Input Pin3
Digital Microphone Clock pin
IN2L
IN1N
46
IN3R
DMDAT
Analog Input
Digital Microphone
Analog Input
47
IN3L
DMCLK
48
Digital Microphone
Note: Do not leave digital input pins open.
■ Handling of Unused Pin
The following table illustrates recommended states for open pins:
Classification
Analog
Pin Name
Setting
Leave Open
IN1L/IN1P,IN1R/IN2P,IN2L/IN1N,IN2R/IN2N,IN3L,IN3R
CLKO, BICKO, LRCKO, SDOUT1-2, SDOUTM, STO,
SOUTM/RDY,XTO
Leave Open
Digital
SDIN1, SDIN2, BICK1, BICK2, LRCK1, LRCK2, XTI
Connect to VSS1
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[AK7754]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4= 0V: Note 1)
Parameter
Symbol
min
max
Unit
Power Supply Voltage (AVDD=DVDD)
Analog
AVDD
HVDD
DVDD
DVDD18
ΔGND
IIN
VINA
VIND1
Ta
-0.3
-0.3
-0.3
-0.3
-0.3
–
-0.3
-0.3
-20
-65
4.3
4.3
4.3
2.5
V
V
V
V
V
mA
V
V
ºC
ºC
Analog
Digital
Digital
Difference(VSS1~4)
Input Current (except for power supply pin)
Analog Input Voltage (Note 2)
Digital Input Voltage (Note 3)
Operating Ambient Temperature
Storage Temperature
0.3
±10
(AVDD+0.3) or 4.3
(DVDD+0.3) or 4.3
85
Tstg
150
Note 1. All indicated voltages are with respect to ground.
Note 2. VSS1-5 must be connected to the same ground plane.
Note 3. The maximum digital input voltage is smaller value between (DVDD+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4=0V: Note 1)
Parameter
Power Supply Voltage
Analog
Symbol
min
typ
max
Unit
AVDD
HVDD
DVDD
DVDD18
ΔVDD1
ΔVDD2
ΔVDD3
3.0
3.0
3.0
3.3
3.3
3.3
1.8
0
3.6
3.6
3.6
V
V
V
V
V
V
V
Analog
Digital
Digital
1.7
1.9
HVDD-AVDD
HVDD-DVDD
AVDD-DVDD
-0.3
-0.3
-0.3
+0.3
+0.3
+0.3
0
0
Note 4. The power supply sequence for AVDD, HVDD, DVDD and DVDD18 is not critical but all power supplies must
be On before start operating the AK7754.
Note 5. Do not turn off the power supply of the AK7754 with the power supply of the surrounding device turned on.
DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and
SCL pins.)
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
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[AK7754]
ANALOG CHARACTERISTICS (CODEC)
■ ADC Characteristics
(Ta=25ºC; AVDD=DVDD=HVDD=3.3V, DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; BICK1=64fs; Signal
Frequency 1kHz; Measurement frequency =20Hz~20kHz, fs=48kHz, PMSRC=PMHPL=PMHPR bits=“0”, CKM mode
6 (CKM[2:0]=6h) Unless otherwise specified.)
Parameter
min
typ
max
Unit
MIC/LINEIN Amplifier: IN1L,IN1R,IN2L,IN2R,IN3L,IN3R pins
Input Resistance
22.5
30
37.5
kΩ
Gain
Max (MGNL/R2-0, LINL/R2-0 bits = “0H”)
Min (MGNL/R2-0, LINL/R2-0 bits = “7H”)
-
-
0
+27
-
-
dB
dB
Bypass Amplifier: IN1L,IN1R,IN2L,IN2R,IN3L,IN3R pins (MGNL/R2-0 = 0h, LINL/R2-0 = 0h)
Gain
Max (BPGL/R2-0 bit = “0H”)
Min (BPGL/R2-0 bit = “7H”)
MIC Power Supply: MPWR pin
Output Voltage (Note 6)
-
-
0
-21
-
-
dB
dB
2.18
-
2.3
-
2.4
4
V
mA
Output Current
Stereo
ADC
Resolution
Dynamic Characteristics
24
Bits
IN1L/IN1R, IN2L/IN2R, IN3L/IN3R pins→ stereo ADC→ SDOUT1/2/M (VOLADL/R=30h(0dB)
(Note 12)
(Note 13)
(Note 12)
(Note 13)
(Note 12)
(Note 13)
70
74
74
81
74
81
77
82
82
89
82
89
dB
dB
dB
dB
dB
dB
S/(N+D) (-1dBFS)
Dynamic Range (A-weight)
S/N (A-weight)
Inter-Channel Isolation
(fin=1kHz) (Note 7)
DC accuracy
(Note 13)
90
105
dB
Channel Gain Mismatch
Analog Input
0.0
0.3
dB
Differential
(Note 8, Note 10)
Single-ended
(Note 9, Note 11)
(Note 12)
(Note 13)
(Note 12)
(Note 13)
±0.098
±1.1
0.196
2.2
Vpp
Vpp
Input Voltage
Input Voltage
±1.0
2.0
±1.2
2.4
Note 6. The output voltage is proportional to AVDD. Vout=0.76 x AVDD (typ.)
Note 7. Inter-channel isolation between IN1-3L and IN1-3R pins when –1dB FS signal is input.
Note 8. The input voltage is proportional to AVDD. Vin=±0.030 x AVDD (typ.)@MGNL2-0=MGNR2-0 bits =
“5h”(+21dB), Vin=±0.33 x AVDD (typ.) @MGNL2-0=MGNR2-0 bits = “0h”(+0dB)
Note 9. The input voltage is proportional to AVDD. Vin=0.059 x AVDD (typ.)@MGNL2-0=MGNR2-0 bits =
“5h”(+21dB), Vin=0.67 x AVDD (typ.) @MGNL2-0=MGNR2-0 bits = “0h”(+0dB)
Note 10. IN1P, IN1N, IN2P and IN2N pins
Note 11. IN1L, IN1R, IN2L, IN2R, IN3L and IN3R pins
Note 12. MGNL2-0=MGNR2-0 bits = “5h” (+21dB)
Note 13. MGNL2-0=MGNR2-0 bits = “0h” (+0dB)
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[AK7754]
■ DAC Characteristics
(Ta=25ºC; AVDD=DVDD=HVDD=3.3V, DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; BICK1=64fs; Signal
frequency 1kHz; Measurement frequency=20Hz~20kHz, fs=48kHz, PMSRC=PMHPL=PMHPR bits = “0”, CKM mode
6 (CKM[2:0]=6h, Unless otherwise specified.)
Parameter
min
typ
max
Unit
Stereo
DAC
Resolution
24
Bits
Dynamic Characteristics; Stereo DAC→OUTL/R pins VOLDAL/R=18h(0dB) LODIF=“0”
S/(N+D)
Dynamic Range (A-weight)
S/N
Inter-Channel Isolation (fin=1kHz) (Note 14)
DC accuracy
(0dBFS)
80
88
88
90
91
96
96
dB
dB
dB
dB
(A-weight)
110
Channel Gain Mismatch
0.0
0.5
dB
Analog Volume Characteristics
Min
0.0
28.0
2.0
dB
dB
dB
Gain Amount
Max
Step width
Analog Output
Output Voltage
(Note 15)
Single-End
Differential
2.06
±2.06
10
2.17
±2.17
2.28
±2.28
Vpp
Vpp
kΩ
Load Resistance
Load Capacitance
30
pF
Note 14. Inter-channel isolation between Lch and Rch of the DAC.
Note 15. Full scale output voltage. The output voltage is proportional to AVDD. Vout=0.67 x AVDD (typ.)
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[AK7754]
ANALOG CHARACTERISTICS (HP-Amp)
(Ta=25ºC; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; Signal frequency 1kHz;
Measurement frequency=20Hz~20kHz@48kHz; PMSRC bit=“0”), RL =16Ω; Circuit External Capacitance:
C1=C2=OPEN. CKM mode6, Unless otherwise specified.)
Parameter
min
typ
max
Unit
Analog Volume Characteristics
Gain
Max (HPGL,HPGR[4:0] bits= “1FH”)
-
-
+0
-50
1
-
-
-
-
-
dB
dB
dB
dB
dB
Min (HPGL,HPGR[4:0] bits= “01H”)
+0dB ∼ -16dB
-16dB ∼ -38dB
Step width
0.1
0.1
-
2
-38dB ∼ -50dB
4
Headphone-Amp Characteristics: DAC → HPL/HPR pins, RL=16Ω (Note 16)
Output Voltage
S/(N+D)
S/N
Inter channel Isolation
Inter channel Gain Mismatch
Load Resistance
Load Capacitance
Load Capacitance
1.68
60
83
60
-
16
-
-
1.87
70
89
75
0.0
-
2.06
-
-
-
1.0
-
Vpp
dB
dB
dB
dB
Ω
(-3dBFS)
(A-weighted)
(RL, Figure 2)
(C1, Figure 2)
(C2, Figure 2)
-
-
30
300
pF
pF
Note 16. Because of an asynchronous circuit operation, the characteristic may deteriorate when SRC is in operation.
Measurement
Point
HPL pin
HPR pin
HP-Amp
47μF
–
+
+
C1
C2
0.22μF
10Ω
RL
Figure 2. Headphone Amp Output Circuit
MS1138-E-01-PB
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[AK7754]
SRC CHARACTERISTICS
(Ta=25°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; Signal frequency 1kHz;
Measurement frequency= 20Hz~FSO/2)
Parameter
Resolution
Input Sample Rate
Output Sample Rate
THD+N
Symbol
min
typ
max
24
96
Unit
Bits
kHz
kHz
FSI
FSO
8
8
48
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=48kHz/8kHz
FSO/FSI=16kHz/48kHz
FSO/FSI=16kHz/44.1kHz
FSO/FSI=8kHz/48kHz
FSO/FSI=8kHz/44.1kHz
-111
-104
-111
-111
-111
-111
-104
-111
-78
dB
dB
dB
dB
dB
dB
dB
dB
dB
-103
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
112
112
112
112
112
112
112
112
112
dB
dB
dB
dB
dB
dB
dB
dB
dB
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=48kHz/8kHz
FSO/FSI=16kHz/48kHz
FSO/FSI=16kHz/44.1kHz
FSO/FSI=8kHz/48kHz
FSO/FSI=8kHz/44.1kHz
108
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz
Ratio between Input and Output Sample Rate
115
dB
-
FSO/FSI
0.167
6
MS1138-E-01-PB
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[AK7754]
DC CHARACTERISTICS
(Ta=-20ºC~85ºC; AVDD= HVDD= 3.0V~3.6V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V)
Parameter
Symbol
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOL
Iin
min
80%DVDD
typ
max
Unit
V
V
V
V
V
V
V
V
High level input voltage
Low level input voltage
(Note 17)
(Note 17)
20%DVDD
30%DVDD
35%DVDD
SCL, SDA High level input voltage
SCL, SDA Low level input voltage
DMDAT High level input voltage
DMDAT Low level input voltage
High level output voltage: Iout=-100μA (Note 18)
Low level output voltage: Iout=100μA (Note 18)
SDA Low level output voltage Iout=3mA
70%DVDD
65%DVDD
DVDD-0.4
0.4
0.4
±10
V
Input leak current
(Note 19)
(Note 20)
μA
μA
μA
Input leak current TEST1/2 pin
Input leak current XTI pin
Iid
Iix
22
26
Note 17. Except for the SCL, SDA pin.
Note 18. Except for the SDA pin. The DMCLK pin is included.
Note 19. Except for the TEST2 pin, TEST1 pin and XTI pin.
Note 20. The TEST1 pin has an internal pull-down device, nominally 150kΩ.
POWER CONSUMPTION
(Ta=-20ºC ~ 85ºC; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V, fin=1 KHz, 24 bit,
fs=48kHz, BICK1=64fs (CKM mode=4, BITFS mode=0), CODEC (Full-duplex mode, no output loads) and DSP
running with programmed that connects DSP DIN3 with DOUT1 and DIN1 with DOUT3.
Parameter
min
typ
max
Unit
Power Supplies: (Note 21)
Power-Up (IRSTN pin = “H”) CODEC + DSP + LineOut + HP
All Circuit Power-up
AVDD+DVDD
AVDD=DVDD=HVDD=3.3V,
HVDD
21
4.8
29
137
22
-
-
mA
mA
mA
mW
mA
mA
mA
DVDD18=1.8V
DVDD18
Power Consumption
AVDD+DVDD
AVDD=DVDD=HVDD=3.6V,
HVDD
38
7.5
70
5.0
31
DVDD18=1.9V
DVDD18
Reset (IRSTN pin = “L”), Reset condition (Note 22)
AVDD+DVDD+HVDD
-
1
3
10
200
μA
μA
DVDD18
Note 21. The actual power consumption of DVDD18 depends on the master clock frequency and the step size of the
DSP program. (BITFS bit = “2h” and DSPS bit = “0”)
Note 22. All digital input pins must be fixed to Logic High /Low.
MS1138-E-01-PB
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[AK7754]
DIGITAL FILTER CHARACTERISTICS
■ ADC Block
1. fs=8kHz
(Ta=-20ºC~85ºC, AVDD= HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=VSS3=VSS4=0V; fs=8 kHz;
Note 23)
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
Parameter
Passband (±0.1dB)
Symbol
min
0
typ
max
3.15
(Note 24)
PB
(-1.0dB)
(-3.0dB)
3.63
3.83
Stopband
Passband Ripple
SB
PR
SA
ΔGD
GD
4.66
68
(Note 24)
±0.1
0
Stopband Attenuation (Note 25, Note 26)
Group Delay Distortion
Group Deley
(Ts=1/fs)
16
Note 23. Frequencies of each amplitude characteristics are in proportion to fs (sampling rate). The characteristic of the
high pass filter is not included.
Note 24. The passband is from DC to 3.15kHz when fs=8kHz.
Note 25. The stopband is 4.66kHz to 507.34kHz when fs=8kHz.
Note 26. When fs = 8kHz, the analog modulator samples the input signal at 512kHz.
2. fs=48kHz
(Ta=-20ºC~85ºC, AVDD=HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=VSS3=VSS4=0V; fs=48
kHz; Note 27)
Parameter
Passband (±0.1dB) (Note 28)
Symbol
PB
min
0
typ
max
18.9
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
(-0.2dB)
(-3.0dB)
20.0
23.0
Stopband
Passband Ripple
Stopband Attenuation (Note 29,Note 30)
Group Delay Distortion
Group Delay
SB
PR
SA
ΔGD
GD
28.0
68
(Note 28)
±0.04
0
(Ts=1/fs)
16
Note 27. Frequencies of each amplitude characteristics are in proportion to fs (sampling rate).
Note 28. The passband is from DC to 18.9kHz when fs=48kHz.
Note 29. The stopband is 28kHz to 3.044MHz when fs=48kHz.
Note 30. When fs = 48kHz, the analog modulator samples the input signal at 3.07MHz.
MS1138-E-01-PB
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[AK7754]
■ DAC Block
1. fs=8kHz
(Ta=-20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V; VSS1=VSS2 = VSS3=VSS4=0V;
fs=48kHz; DEM1-0 bits= “0”, fs=8kHz; Note 27)
Unit
kHz
kHz
kHz
dB
Parameter
Passband (±0.05dB)
(-6.0dB)
Stopband
Passband Ripple
Symbol
min
0
typ
max
3.62
(Note 31)
(Note 31)
PB
4
SB
PR
SA
GD
4.37
64
±0.01
Stopband Attenuation (Ts=1/fs) (Note 32)
Group Delay
dB
Ts
24
Digital Filter + Analog Filter
Amplitude characteristic
20Hz~3.5kHz
±0.5
dB
2. fs=48kHz
(Ta=-20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V; VSS1=VSS2=VSS3=VSS4=0V;
fs=48kHz; DEM1-0 bits= “0”, fs=48kHz; Note 27)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband (±0.05dB)
(-6.0dB)
Stopband
Passband Ripple
Stopband Attenuation
Group Delay (Ts=1/fs) (Note 32)
Digital Filter + Analog Filter
(Note 31)
(Note 31)
PB
0
-
26.2
21.7
-
kHz
kHz
kHz
dB
dB
Ts
24.0
SB
PR
SA
GD
±0.01
64
-
24
Amplitude characteristic 0~20.0kHz
±0.5
dB
Note 31. Pass band and Stop band parameter is related to sampling frequency(fs). PB=0.4535fs (at-0.05dB),
SB=0.5465fs.
Note 32. The digital filter’s delay is calculated as the time from setting 24-bit data into the input register until an analog
signal is output.
MS1138-E-01-PB
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[AK7754]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V,
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
XTI
CKM[2:0]bits=4h-7h
a) with a Crystal Oscillator:
CKM[2:0]bits=6h
fXTI
fXTI
11.2896
12.288
16.9344
18.432
MHz
MHz
CKM[2:0]bits=7h
b) with an External Clock
Duty Cycle
40
50
60
%
CKM[2:0]bits=4h,6h
fXTI
fXTI
11.0
11.2896
12.288
16.9344
18.432
MHz
12.4
CKM[2:0]bits=5h,7h
16.5
8
MHz
kHz
18.6
48
LRCK1 Frequency @SCKSEL bit=0 (Note 33)
BICK1 Frequency @SCKSEL bit=0 (Note 34)
fs
High Level Width
Low Level Width
Frequency
tBCLKH
tBCLKL
fBCLK
fs
64
64
0.23
ns
ns
MHz
3.072
3.072
3.1
48
LRCK2 Frequency @SCKSEL bit=1 (Note 35)
BICK2 Frequency @SCKSEL bit=1 (Note 36)
8
KHz
High Level Width
Low Level Width
Frequency
tBCLKH
tBCLKL
fBCLK
64
64
0.23
ns
ns
MHz
3.1
Note 33. Input LRCK1 frequency is the same as sampling rate (fs).
Note 34. When BICLK1 is used as a master clock reference clock, it should be synchronized with LRCK1.
Note 35. Input LRCK2 frequency is the same as sampling rate (fs).
Note 36. When BICLK2 is used as a master clock reference clock, it should be synchronized with LRCK2.
■ SRC Input Clock
(Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V,
@SCKSEL bit =“0”)
Parameter
Symbol
min
typ
max
Unit
LRCLKI2 Frequency
fs
kHz
8
96
BITCLKI2 Frequency
Frequency
High Level Width
Low Level Width
MHz
ns
ns
fBCLK
tBCLKH
tBCLKL
0.23
32
32
3.072
6.2
MS1138-E-01-PB
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[AK7754]
■ Reset
(Ta= -20 ºC ~ 85 ºC, AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1=VSS2=VSS3=VSS4=0V)
Parameter
INITRSTN
Symbol
tRST
min
600
typ
max
Unit
ns
(Note 37)
Note 37. The INITRSTN pin should be “L” when power up the AK7754.
■ Audio Interface
1) SDIN1/2, SDOUT1/2/M
(Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V,
CL=20pF)
Parameter
DSP Section Input SDIN1/2
Symbol
min
typ
max
Unit
Delay Time from BICLK1 “↑” to LRCLK1
SCKSEL bit= “0” (Note 38)
Delay Time from LRCLK1 to BITCLK1 “↑”
SCKSEL bit= “0” (Note 39)
Delay Time from BICLK2 “↑” to LRCLK2
SCKSEL bit= “1” (Note 38)
Delay Time from LRCLK2 to BITCLK2 “↑”
SCKSEL bit= “1” (Note 39)
tBLRD
tLRBD
tBLRD
tLRBD
20
20
20
20
ns
ns
ns
ns
Serial Data Input Latch Setup Time
Serial Data Input Latch Hold Time
tBSIDS
tBSIDH
80
80
ns
ns
SRC Section Input SDIN2 (SCKSEL bit= “1”)
Delay Time from BICLK2 “↑” to LRCLK2 (Note 39)
Delay Time from LRCLK2 to BITCLK2 “↑” (Note 39)
Serial Data Input Latch Setup Time
tBLRD
tLRBD
tBSIDS
tBSIDH
20
20
40
40
ns
ns
ns
ns
Serial Data Input Latch Hold Time
Output SDOUT1, SDOUT2, SDOUTM
Delay Time from LRCLK1 to Serial Data Output (Note 40)
Delay Time from BICK1 “↓” to Serial Data Output (Note 41)
Delay Time from LRCKO to Serial Data Output (Note 40)
Delay Time from BICKO to Serial Data Output (Note 42)
tLRD
tBSOD
tLRD
80
80
80
80
ns
ns
ns
ns
tBSOD
SDIN1/2 →SDOUT1/2
(Note 43)
Delay Time from SDIN1/2 to SDOUT1/2 Output
tIOD
60
ns
Note 38. BITCLKI1 edge must not occur at the same time as LRCLKI1 edge.
Note 39. BITCLKI2 edge must not occur at the same time as LRCLKI2 edge.
Note 40. Except I2S.
Note 41. When BICK1 polarity is reversed, delay time is from BICK1 “↑”.
Note 42. When BICK2 polarity is reversed, delay time is from BICK2 “↑”.
Note 43. SDIN1 → SDOUT1: SELDO1[1:0] bits= “1h”, OUT1E bit= “1”
SDIN2 → SDOUT2: SELDO2[1:0] bits= “1h”, OUT2E bit= “1”
MS1138-E-01-PB
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[AK7754]
■ Digital Microphone (DMIC) Switching Characteristics
(Ta= -20˚C ~85˚C; AVDD=HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1= VSS2= VSS3= VSS4= 0V,
CL=100pF)
Parameter
Symbol
min
typ
max
Unit
DMDAT
DMDAT Setup Time
DMDAT Hold Time
DMCLK
tDMDS
tDMDH
50
0
ns
ns
Frequency
Duty Cycle
Rise Time
Fall Time
fDMCK
dDMCK
tDMCKR
tDMCKF
0.5
40
64fs
50
3.1
60
10
10
MHz
%
ns
ns
Note 44. Clock frequency is depend on the sampling rate (fs) which is set by CKM[1:0] or DFS[1:0] bits.
■ I2C BUS Interface
(Ta= -20ºC ~ 85ºC; AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V;
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
I2C Timing
SCL clock frequency
fSCL
tBUF
tHD:STA
400
KHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock
pulse)
1.3
0.6
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
μs
μs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
by Input Filter
μs
μs
μs
μs
μs
μs
ns
0.9
0.1
0.3
0.3
tF
tSU:STO
tSP
0.6
0
50
Capacitive load on bus
Note 45. I2C-bus is a trademark of NXP B.V.
Cb
400
pF
MS1138-E-01-PB
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[AK7754]
■ Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH1
VIL1
1/fs
1/fs
ts=1/fs
LRCK1
LRCK2
VIH1
VIL1
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH1
VIL1
BICK1
BICK2
tBCLKH
tBCLKL
Figure 3. System Clock
INITRSTN
tRST
VIL1
Figure 4. Reset
Note 46. The INITRSTN pin must be “L” when power-up/power-down the AK7754.
MS1138-E-01-PB
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[AK7754]
■ Audio Interface
VIH1
VIL1
LRCK1/2
tBLRD
tLRBD
VIH1
VIL1
BICK1/2
SDIN1/2
tBSIDS
tBSIDH
VIH1
VIL1
Figure 5. Audio Interface (DSP Section Slave Mode Input)
VIH1
VIL1
LRCK2
tBLRD
tLRBD
VIH1
VIL1
BICK2
SDIN2
tBSIDS
tBSIDH
VIH1
VIL1
Figure 6. Audio Interface (SRC Section Input)
VIH1
VIL1
LRCK1/2
tLRD
VIH1
VIL1
BICK1/2
tBSOD
tLRD
tBSOD
SDOUT1/2/M
50%DVDD
Figure 7. Audio Interface (Slave Mode Output)
MS1138-E-01-PB
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[AK7754]
50%DVDD
LRCKO
BICKO
tMBL
tMBL
50%DVDD
tBSIDS
tBSIDH
VIH1
VIL1
Figure 8. Audio Interface (Master Mode Input)
50%DVDD
50%DVDD
50%DVDD
LRCKO
BICKO
tLRD
tBSOD
tLRD
tBSOD
SDOUT1/2/M
Figure 9. Audio Interface (Master Mode Output)
MS1138-E-01-PB
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[AK7754]
■ Digital Microphone Interface
Input Interface
tDMCK
65%DVDD
DMCLK
50%DVDD
35%DVDD
tDMCKL
tDMCKR
tSFall
fDMCK = 1/tDMCK
dDMCK = 100 x tDMKL / tDMCK
Figure 10. DMCLK Clock Timing
DMCLK
DMDAT
50%DVDD
tDMDS
tDMDH
VIH3
VIL3
Figure 11. Audio Interface Timing, DCLKP bit = “1”)
DMCLK
DMDAT
50%DVDD
tDMDS
tDMDH
VIH3
VIL3
Figure 12. Audio Interface Timing, DCLKP bit = “0”)
I2C Bus Interface
VIH
VIL
SDA
SCL
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
Start
tSU:STO
Stop
Figure 13. I2C Bus Interface
MS1138-E-01-PB
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[AK7754]
PACKAGE
48pin QFN (Unit: mm)
7.00±0.10
6.75±0.10
0.40±0.10
B
+0.07
-0.05
A
0.23
0.50
C0.60MAX
5.1
M
0.10
AB
C
0.20
C
0.08
Note: The exposed pad on the bottom surface of the package must be open or connected to the ground.
■ Materials and Lead Specification
Package:
Lead frame:
Lead-finish:
Epoxy, Halogen (bromine and chlorine) free
Copper
Soldering (Pb free) plate
MS1138-E-01-PB
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[AK7754]
MARKING
AKM
AK7754EN
XXXXXXX
48
1
XXXXXXX: Date code identifier (7 digits)
REVISION HISTORY
Date (Y/M/D)
10/06/01
Revision Reason
Page
8
Contents
00
First
Edition
12/03/23
01
Error
PIN FUNCTION
Correction
IN2P (No. 43): MIC Differential Inverted Input Pin2
→MIC Differential Non-Inverted Input Pin2
IN2N (No. 45): MIC Differential Non-Inverted Input Pin2
→MIC Differential Inverted Input Pin2
MS1138-E-01-PB
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2012/03
[AK7754]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this document are
provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible
for the incorporation of these external circuits, application circuits, software and other related information in the design of
your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of
these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in
the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other
hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with
the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to r
esult, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system conta
ining it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to fun
ction or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the
product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims
arising from the use of said product in the absence of such notification.
Thank you for your access to AKM products information.
More detail product information is available, please contact our sales
office or authorized distributors.
MS1138-E-01-PB
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2012/03
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