AK7755EN_技术文档

[AK7755]

4. Block Diagram and Functions

■ Block Diagram

Figure 1. Block Diagram

014006643-E-00

2014/10

- 4 -

[AK7755]

■ DSP Block Diagram

OFREG

32w x 13-Bit

CP0, CP1

DP0, DP1

DLP0, DLP1

Pointer

Coefficient RAM

Data RAM

2048w x 24-Bit(20.4f)

Delay RAM

8192w x 24-Bit(20.4f)

2048w×24-Bit

CBUS(24-Bit)

DBUS(28-Bit)

Micon I/F

MPX24

X

MPX24

Control

Serial I/F

PRAM

DEC

Y

4096w×36-Bit

Multiply

24 ×24 → 48-Bit

PC

Stack : 5level(max)

TMP 12×24-Bit

28-Bit

48-Bit

PTMP(LIFO) 6×24-Bit

MUL

DBUS

SHIFT

DIN4

2×16/20/24-Bit

52-Bit

2×16/20/24-Bit DIN3

2×16/20/24-Bit DIN2

2×16/20/24-Bit DIN1

48-Bit

A

B

ALU

DOUT4

2×16/20/24-Bit

52-Bit

DOUT3

DOUT2

DOUT1

Overflow Margin: 4-Bit

52-Bit



DR0

3

Accelerator

Coefficient RAM

52-Bit

Data RAM

(ACCRAM)

2048w x 20-Bit

(ACDRAM)

2048w x 16-Bit

Over Flow Data

Generator

Division 2020→20

Peak Detector

Figure 2. DSP Block Diagram

014006643-E-00

2014/10

- 5 -

[AK7755]

5. Pin Configurations and Functions

■ Ordering Guide

AK7755EN/VN

AKD7755

-40  +85C

36-pin QFN (0.5mm pitch)

Evaluation Board for AK7755

■ Pin Layout

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

SCLK/SCL

SO/SDA

OUT1

AVDD

SDOUT1/EEST

AVSS

SDOUT2/JX3/MAT0

36pin QFN

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

LIN

SDOUT3/JX2/MAT1

(TOP VIEW)

DVSS

TVDD

XTI

XTO

AVDD

Input

Output

I/O

Power

Figure 3. Pin Layout

014006643-E-00

2014/10

- 6 -

[AK7755]

I2CSEL pin = “L”

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

SCLK

OUT1

AVDD

SO

SDOUT1/EEST

SDOUT2/JX3

SDOUT3/JX2

DVSS

AVSS

36pin QFN

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

LIN

(TOP VIEW)

TVDD

XTI

XTO

AVDD

Input

Output

I/O

Power

I2CSEL pin = “H”, EXTEEP pin = “L”

28

29

30

31

32

33

34

35

36

18

SCL

OUT1

AVDD

17

16

15

14

13

12

11

10

SDA

SDOUT1/EEST

SDOUT2/JX3

SDOUT3/JX2

DVSS

AVSS

36pin QFN

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

LIN

(TOP VIEW)

TVDD

XTI

XTO

AVDD

Input

Output

I/O

Power

014006643-E-00

2014/10

- 7 -

[AK7755]

I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

SCL

OUT1

AVDD

SDA

SDOUT1/EEST

SDOUT2/JX3

SDOUT3/JX2

DVSS

AVSS

36pin QFN

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

LIN

(TOP VIEW)

TVDD

XTI

XTO

AVDD

Input

Output

I/O

Power

I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

SCL

OUT1

AVDD

SDA

SDOUT1/EEST

MAT0

MAT1

DVSS

TVDD

XTI

AVSS

36pin QFN

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

LIN

(TOP VIEW)

XTO

AVDD

Input

Output

I/O

Power

014006643-E-00

2014/10

- 8 -

[AK7755]

■ Pin Functions

No.

1

Pin Name

VCOM

I/O

O

-

Function

Common Voltage Output Pin of Analog Block

▪ Connect a 2.2μF capacitor between AVSS.

▪ Do not connect to an external circuit.

Analog Ground Pin 0V

2

AVSS

I²C-BUS Select Pin

▪ I2CSEL pin = “L”: SPI Interface

▪ I2CSEL pin = “H”: I²C-bus Interface

The I2CSEL pin must be fixed to “L” (DVSS) or “H” (TVDD).

Serial Data Input2 Pin

External Conditional Jump1 Pin (JX1E bit = “1”)

Serial Data Input1 Pin

External Conditional Jump0 Pin (JX0E bit = “1”)

Status Output Pin

RDY Pin

3

I2CSEL

I

SDIN2

JX1

SDIN1

JX0

I

4

5

6

I

STO

O

I/O

RDY

LRCK

BICK

CLKO

7

8

9

LR Channel Select Pin (Internal pull-down)

I/O Serial Bit Clock Output Pin (Internal pull-down)

O

Clock Output Pin

Crystal oscillator output pin

10 XTO

O

▪ When a crystal oscillator is used, connect it between XTI and XTO.

▪ When a crystal oscillator is not used, leave this pin as open.

Crystal oscillator input pin

▪ When a crystal oscillator is used, connect it between XTI and XTO.

▪ When a crystal oscillator is not used, connect this pin to the external clock

or leave open.

11 XTI

I

12 TVDD

13 DVSS

-

I

Digital IO Power Supply Pin: 1.7~3.6V (typ. 3.3V)

Ground Pin 0V

SDOUT3

O Serial Data Output3 Pin

JX2

I

External Conditional Jump2 Pin (JX2E bit = “1”)

I2CSEL pin = EXTEEP pin = MATSEL pin = “H”

EEPROM Download Mat Select Address1

Serial Data Output2 Pin

External Conditional Jump3 Pin (JX3E bit = “1”)

I2CSEL pin = EXTEEP pin = MATSEL pin = “H”

EEPROM Download Mat Select Address0

Serial Data Output1 Pin

14

15

MAT1

I

SDOUT2

JX3

O

I

MAT0

I

SDOUT1

EEST

SO

O

16

17

EEPROM Interface Status

SO Pin (I2CSEL pin = “L”)

SDA

I/O I²CBUS Interface (I2CSEL pin = “H”)

Serial Data Clock Pin for SPI Interface (I2CSEL pin = “L”)

SCLK

SCL

I

▪ Set this pin to “H” when there is no clock input.

18

19

I²CBUS Interface Pin (I2CSEL pin = “H”)

I/O

EEPROM Download This becomes an output pin when EXTEEP pin = “H”.

Serial Data Input Pin for SPI Interface (I2CSEL pin = “L”)

▪ Set this pin to “L” when not used.

SI

I

EXTEEP

I

EEPROM Download Control Pin (I2CSEL pin = “H”)

014006643-E-00

2014/10

- 9 -

[AK7755]

ChipSelectN Pin for SPI Interface (I2CSEL pin = “L”)

CSN

I

▪ Set this pin to “H” when the AK7755 is in power-down mode or when the

microprocessor I/F is not used.

20

CAD

MATSEL

21 AVDD

I

-

I2CBUS Address Pin (I2CSEL pin = “H”)

EEPROM Mat Select Pin (I2CSEL pin = EXTEEP pin = “H”)

Analog Power Supply Pin: (typ. 3.3V)

Power-down N Pin

22 PDN

I

▪ The AK7755 can be powered-down by this pin.

▪ Set this pin to “L” upon power-up the AK7755.

LDO Select Pin

LDOE pin = “L”: 24 pin External 1.2V Power Supply

LDOE pin = “H”: 24 pin LDO Output (LDO Drive)

The LDOE pin must be fixed to “L(DVSS)” or “H(TVDD)”.

Power Supply Pin for Digital Core: (typ. 1.2V)

LDO Output (LDOE pin = “H”)

23 LDOE

DVDD

I

24

AVDRV

O

Connect a 1uF capacitor between this pin and DVSS. This pin must not be

connected to an external circuit.

25 DVSS

26 OUT2

27 OUT3

28 OUT1

29 AVDD

30 AVSS

-

O

-

Ground Pin 0V

Line Output 2 Pin

Line Output 3 Pin

Line Output 1 Pin

Analog Power Supply Pin: 3.3V (typ)

Analog Ground Pin 0V

-

IN4/INN2

DMCLK2

I

ADC Input Pin (AINE bit = “1”)

31

O Digital MIC Clock Output 2 Pin (DMIC2 bit = “1”)

IN3/INP2

DMDAT2

I

ADC Input Pin (AINE bit = “1”)

32

I Digital MIC Clock Input 2 Pin (DMIC2 bit = “1”)

IN2/INN1

DMCLK1

IN1/INP1

DMDAT1

I

ADC Input Pin (AINE bit = “1”)

O Digital MIC Clock Output 1 Pin (DMIC1 bit = “1”)

ADC Input Pin (AINE bit = “1”)

I Digital MIC Clock Input 1 Pin (DMIC1 bit = “1”)

33

I

34

35 LIN

36 AVDD

I

-

Mono ADC Input Pin

Analog Power Supply Pin: 3.3V (typ)

Note 1. All digital input pins must not be allowed to float. If analog input pins are not used, leave them open.

The I2CSEL pin, LDOE pin and CAD/MATSEL pin should be fixed to “L” (DVSS) or “H”

(TVDD).

■ Handling of Unused Pin

The unused I/O pins must be processed appropriately as below.

Classification Pin Name

Setting

LIN, IN1/INP1/DMDAT1, IN2/INN1/DMCLK1,

Analog

Digital

IN3/INP2/DMDAT2, IN4/INN2/DMCLK2, OUT1, OUT2, These pins must be open.

OUT3

STO/RDY, CLKO, XTI, XTO, SDOUT3/ JX2/MAT1,

SDOUT2/JX3/MAT0, SDOUT1/EEST, SO/SDA, LRCK, These pins must be open.

BICK

I2CSEL, SDIN2/JX1, SDIN1/JX0,

SCLK/SCL, SI/EXTEEP, CSN/CAD/MATSEL, LDOE

These pins must be

connected to DVSS.

014006643-E-00

2014/10

- 10 -

[AK7755]

Unit

6. Absolute Maximum Ratings

(AVSS=DVSS=0V; Note 2)

Parameter

Symbol

min

max

Power Supplies

Analog

AVDD

TVDD

DVDD

ΔGND

IIN

-0.3

－

-0.3

-40

-65

4.3

1.6

0.3

±10

V

mA

Digital1(I/F)

Digital2(Core)

DVSS-AVSS

(Note 2)

Input Current, Any Pin Except Supplies

Analog Input Voltage (Note 3)

Digital Input Voltage (Note 4)

Ambient Temperature

VINA

VIND

Ta

(AVDD+0.3)≤4.3

(TVDD+0.3)≤4.3

V

℃

85

Storage Temperature

Tstg

150

Note 2. All voltages with respect to ground. AVSS and DVSS must be the same voltage.

Note 3. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.

Note 4. The maximum digital input voltage is smaller value between (DVDD+0.3)V and 4.3V.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

7. Recommended Operating Conditions

(AVSS=DVSS=0V; Note 2)

Parameter

Symbol

min

typ

max

Unit

Power Supplies

Analog

AVDD

TVDD

DVDD

3.0

1.7

1.14

3.3

1.2

3.6

1.3

V

Digital1(I/F)

Digital2(Core)

Note 5. AVDD and TVDD must be powered up first before DVDD when DVDD is supplied externally

(LDOE pin = “L”). In this case, the power-up sequence between AVDD and TVDD is not critical.

When using the internal regulator (LDOE pin = “H”), the power-up sequence between AVDD and

TVDD is not critical. But all power supplies must be ON before starting operation of the AK7755

by PDN pin = “H”.

Note 6. Do not turn off the power supply of the AK7755 with the power supply of the surrounding device

turned on. Pull-up of SDA and SCL pins must not exceed TVDD.

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

014006643-E-00

2014/10

- 11 -

[AK7755]

8. Electrical Characteristics

■ Analog Characteristics

1. MIC Amplifier Gain

(Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V)

Parameter

Input Impedance

min

14

typ

20

0

max

Unit

kΩ

dB

MIC

AMP

MGNL[3:0]bits=0h, MGNR[3:0]bits=0h

2

MGNL[3:0]bits=1h, MGNR[3:0]bits=1h

MGNL[3:0]bits=2h, MGNR[3:0]bits=2h

MGNL[3:0]bits=3h, MGNR[3:0]bits=3h

MGNL[3:0]bits=4h, MGNR[3:0]bits=4h

MGNL[3:0]bits=5h, MGNR[3:0]bits=5h

MGNL[3:0]bits=6h, MGNR[3:0]bits=6h

MGNL[3:0]bits=7h, MGNR[3:0]bits=7h

MGNL[3:0]bits=8h, MGNR[3:0]bits=8h

MGNL[3:0]bits=9h, MGNR[3:0]bits=9h

MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah

MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh

MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch

MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh

MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh

MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh

4

6

8

10

12

14

16

18

21

24

27

30

33

36

Gain

2. Line-in Amplifier Gain

(Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V)

Parameter

Line-in Input Impedance

min

14

typ

20

0

-3

-6

max

Unit

kΩ

dB

AMP

LIGN[3:0]bits=0h

LIGN[3:0]bits=1h

LIGN[3:0]bits=2h

LIGN[3:0]bits=3h

LIGN[3:0]bits=4h

LIGN[3:0]bits=5h

LIGN[3:0]bits=6h

LIGN[3:0]bits=7h

LIGN[3:0]bits=8h

LIGN[3:0]bits=9h

LIGN[3:0]bits=Ah

LIGN[3:0]bits=Bh

LIGN[3:0]bits=Ch

LIGN[3:0]bits=Dh

LIGN[3:0]bits=Eh

LIGN[3:0]bits=Fh

-9

-12

-15

-18

-21

N/A

+3

+6

+9

+12

+15

+18

+21

Gain

(Note 7)

Note 7. If the output signal of line-in amplifier is input to the analog mixer, +18dB gain is added to the

signal at the mixer.

014006643-E-00

2014/10

- 12 -

[AK7755]

3. MIC Amp + ADC

Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;

Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz

Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz

CKM mode0(CKM[2:0]= “000”); BITFS[1:0]= “00” (64fs); Differential Input Mode

Parameter

MIC Amp Resolution

min

80

typ

max

24

Unit

Bit

+ ADC

Dynamic Characteristics (Differential Input mode)

Fs=48kHz (Note 12)

S/(N+D)

(-1dBFS)

91

88

89

85

102

93

95

89

102

93

95

Fs=48kHz (Note 13)

Fs=96kHz (Note 12)

Fs=96kHz (Note 13)

Fs=48kHz (A-weighted) (Note 12)

Fs=48kHz (A-weighted) (Note 13)

Fs=96kHz (Note 12)

dB

94

90

Dynamic

Range

(Note 8)

Fs=96kHz (Note 13)

Fs=48kHz (A-weighted) (Note 12)

Fs=48kHz (A-weighted) (Note 13)

Fs=96kHz (Note 12)

S/N

Fs=96kHz (Note 13)

89

105

Inter-Channel Isolation (Note 9)

DC accuracy (Differential Input)

Channel Gain Mismatch

Analog Input

Input Voltage

(Differential Input) (Note 10)

Input Voltage

(Single-ended Input) (Note 11)

dB

0.0

0.3

±2.4

2.4

(Note 12)

(Note 13)

(Note 12)

(Note 13)

±2.0

2.0

±2.2

±0.277

2.2

Vp-p

0.277

Note 8. S/(N+D) when -60dB FS signal is applied.

Note 9. Indicates inter-channel isolation between Lch and Rch when –1dBFS signal is input.

Note 10. INP1/INN1 and INP2/INN2 pins.

Note 11. IN1, IN2, IN3 and IN4 pins.

Note 12. MGNL/R[3:0] bits = 0h (0dB)

Note 13. MGNL/R[3:0] bits = 9h (18dB)

014006643-E-00

2014/10

- 13 -

[AK7755]

4. Line-in Amp + ADC

Ta=25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;

Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz

Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz

CKM mode0(CKM[2:0]= “000”); BITFS[1:0]= “00” (64fs);

Parameter

Line-in Amp Resolution

min

typ

max

24

Unit

Bit

+ ADC

Dynamic Characteristics

Fs=48kHz (Note 16)

77

90

86

Fs=48kHz (Note 17)

Fs=96kHz (Note 16)

Fs=96kHz (Note 17)

Fs=48kHz (A-weighted) (Note 16)

Fs=48kHz (A-weighted) (Note 17)

Fs=96kHz (Note 16)

S/(N+D)

(-1dBFS)

dB

88

85

100

90

95

86

100

90

92

Dynamic

Range

(Note 14)

Fs=96kHz (Note 17)

Fs=48kHz (A-weighted) (Note 16)

Fs=48kHz (A-weighted) (Note 17)

Fs=96kHz (Note 16)

S/N

dB

95

Fs=96kHz (Note 17)

86

Analog Input

Input Voltage (Note 15)

(Note 16)

(Note 17)

2.00

2.20

0.277

2.40

Vp-p

Note 14. S/(N+D) when -60dB FS signal is applied.

Note 15. The Lin pin.

Note 16. LIGN[3:0] bits = 0h (0dB)

Note 17. LIGN[3:0] bits = Eh (+18 dB)

014006643-E-00

2014/10

- 14 -

[AK7755]

5. Line-out AMP Gain

Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V

Parameter

min

typ

max Unit

dB

LOVOL1[3:0]bits=0h, LOVOL2[3:0]bits=0h,

LOVOL3[3:0]bits=0h

mute

LOVOL1[3:0]bits=1h, LOVOL2[3:0]bits=1h,

LOVOL3[3:0]bits=1h

LOVOL1[3:0]bits=2h, LOVOL2[3:0]bits=2h,

LOVOL3[3:0]bits=2h

LOVOL1[3:0]bits=3h, LOVOL2[3:0]bits=3h,

LOVOL3[3:0]bits=3h

LOVOL1[3:0]bits=4h, LOVOL2[3:0]bits=4h,

LOVOL3[3:0]bits=4h

LOVOL1[3:0]bits=5h, LOVOL2[3:0]bits=5h,

LOVOL3[3:0]bits=5h

LOVOL1[3:0]bits=6h, LOVOL2[3:0]bits=6h,

LOVOL3[3:0]bits=6h

LOVOL1[3:0]bits=7h, LOVOL2[3:0]bits=7h,

LOVOL3[3:0]bits=7h

LOVOL1[3:0]bits=8h, LOVOL2[3:0]bits=8h,

LOVOL3[3:0]bits=8h

LOVOL1[3:0]bits=9h, LOVOL2[3:0]bits=9h,

LOVOL3[3:0]bits=9h

LOVOL1[3:0]bits=Ah, LOVOL2[3:0]bits=Ah,

LOVOL3[3:0]bits=Ah

LOVOL1[3:0]bits=Bh, LOVOL2[3:0]bits=Bh,

LOVOL3[3:0]bits=Bh

LOVOL1[3:0]bits=Ch, LOVOL2[3:0]bits=Ch,

LOVOL3[3:0]bits=Ch

LOVOL1[3:0]bits=Dh, LOVOL2[3:0]bits=Dh,

LOVOL3[3:0]bits=Dh

LOVOL1[3:0]bits=Eh, LOVOL2[3:0]bits=Eh,

LOVOL3[3:0]bits=Eh

LOVOL1[3:0]bits=Fh, LOVOL2[3:0]bits=Fh,

LOVOL3[3:0]bits=Fh

-28

-26

-24

-22

-20

-18

-16

-14

-12

-10

-8

dB

Line

-out

Gain

AMP

-6

-4

-2

0

014006643-E-00

2014/10

- 15 -

[AK7755]

6. DAC+Line-out Amp

Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;

Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz

Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz

CKM mode0(CKM[2:0]=000); BITFS[1:0] bits = “00”; LOVOL1/2/3[3:0] bits = Fh(0dB);

Parameter

Resolution

min

typ

max

24

Unit

Bit

DAC

Dynamic Characteristics 1 (OUT1, OUT2, OUT3)

fs=48kHz

fs=96kHz

fs=48kHz (A-weighted)

fs=96kHz

fs=48kHz (A-weighted)

fs=96kHz

80

100

90

91

89

S/(N+D) (0 dBFS)

dB

106

101

106

101

110

Dynamic Range (Note 18)

S/N

dB

Inter-Channel Isolation (f=1kHz) (Note 19)

DC accuracy

Channel Gain Mismatch

Analog Output

Output Voltage

Load Resistance

Load Capacitance

0.0

0.5

2.74

30

dB

Vp-p

kΩ

pF

(Note 20)

2.28

10

2.51

Note 18. S/(N+D) when -60dB FS signal is applied.

Note 19. Indicates inter-channel isolation between Lch and Rch of DAC when –1dBFS signal is input.

Note 20. Full-scale output voltage. The output voltage is proportional to AVDD (AVDD x 0.76).

014006643-E-00

2014/10

- 16 -

[AK7755]

■ DC Characteristics

(Ta= -40 to 85C, AVDD=3.3V, DVDD=1.2V, TVDD=1.7 to 3.6V, AVSS=DVSS=0V)

Parameter

Symbol

min

typ

max

Unit

High Level Input Voltage

Low Level Input Voltage

VIH

VIL

VIH

VIL

80%TVDD

V

20%TVDD

30%TVDD

SCL, SDA High Level Input Voltage

SCL, SDA Low Level Input Voltage

DMDAT1, DMDAT2 High Level Input Voltage

(DMIC1, DMIC2 bit = “1”)

DMDAT1, DMDAT2 Low Level Input Voltage

(DMIC1, DMIC2 bit = “1”)

High Level Output Voltage Iout= -100A (Note 21)

Low Level Output Voltage Iout=100A (Note 22)

SDA Low Level Output Voltage

Iout=3mA

DMCLK1, DMCLK2 High Level Output Voltage

Iout = -80A

70%TVDD

VIH2 65%AVDD

VIL2

V

35%AVDD

0.3

TVDD-0.3

V

VOH

VOL

TVDD≥2.0V

TVDD<2.0V

0.4

20%TVDD

V

VOH2 AVDD-0.4

VOL2

(DMIC1, DMIC2 bit = “1”)

DMCLK1, DMCLK2 Low Level Output Voltage

Iout = 80A

0.4

(DMIC1, DMIC2 bit = “1”)

Input Leak Current (Note 23)

Input Leak Current at Pulled-down Pins (Note 24)

Input Leak Current at XTI pin

Iin

Iid

lix

±10

A

77

17

Note 21. Except XTO pin

Note 22. Except SDA and XTO pins.

Note 23. Internal Pulled-down pins, except the XTI pin

Note 24. The LRCK, BICK, SDOUT2/JX3/MAT0 and SDOUT3/JX2/MAT1 pins are internal

pulled-down pins (typ. 43 kΩ@3.3V).

■ Power Consumptions

(Ta=25C, AVDD=3.0 to 3.6V (typ=3.3V, max=3.6V), TVDD=1.7 to 3.6V (typ=3.3V, max=3.6V),

DVDD=1.14 to 1.3V (typ=1.2V, max=1.3V), AVSS=DVSS=0V)

Parameter

AVDD

TVDD

DVDD

AVDD

TVDD

AVDD

TVDD

DVDD

AVDD

TVDD

min

typ

16

3

25

48

3

10

200

1

max

24

4.5

40

72

4.5

Unit

mA

uA

Power consumptions in operation 1 (Note 25)

(LDOE pin = “L”)

Power consumptions in operation 2 (Note 25)

(LDOE pin = “H”)

Power consumptions in power-down

(PDN pin= “L”, LDOE pin = “L”)

Power consumptions in power-down

(PDN pin= “L”, LDOE pin = “H”)

1

Note 25. DVDD power consumption will be changed depending on DSP programs.

(e.g. It will be 6mA when using AKM’s Hands Free program.)

014006643-E-00

2014/10

- 17 -

[AK7755]

■ Digital Filter Characteritics

1. ADC

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

fs=48kHz (Note 26))

Parameter

Passband

(Note 27)

Symbol

PB

min

0

typ

max

20.7

Unit

kHz

dB

+0.14dB ~ 0.12dB

-0.87dB

21.6

22.8

-3.0dB

Stoppband

Passband Ripple

SB

PR

28.4

65

(Note 27)

±0.14

Stopband Ripple (Note 28, Note 29)

Group Delay Distorsion

Group Daley

SA

△GD

GD

dB

μs

Ts

0

12.5

(Ts=1/fs)

Note 26. The passband and stopband frequencies scale with “fs” (system sampling rate). The characteristic

of the high pass filter is not included.

Note 27. The passband is from DC to 18.9kHz when fs=48kHz.

Note 28. The stopband is 28kHz to 3.044MHz when fs=48kHz.

Note 29. When fs = 48kHz, the analog modulator samples the input signal at 3.072MHz. There is no

attenuation of an input signal in band (n x 3.072MHz ±21.99kHz; n=0, 1, 2, 3…) of integer times

of the sampling frequency by the digital filter.

2. DAC

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

fs=48kHz)

Parameter

Passband (Note 30) (±0.05dB)

(-6.0dB)

Stopband (Note 30)

Passband Ripple

Stopband Attenuation

Group Delay (Ts=1/fs) (Note 31)

Digital Filter + Analog Filter

Symbol

PB

min

0

Typ

24

max

21.7

Unit

kHz

dB

SB

PR

SA

GD

26.2

64

±0.05

dB

Ts

24

Amplitude Characteristics

20Hz to 20.0kHz

±0.5

dB

Note 30. The passband and stopband frequencies are proportional to “fs” (system sampling rate), and

represents PB=0.4535 × fs(@0.05dB) and SB=0.5465 × fs, respectively.

Note 31. The digital filter delay is calculated as the time from setting data into the input register until an

analog signal is output.

014006643-E-00

2014/10

- 18 -

[AK7755]

■ Switching Characteristics

1. System Clock

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

CL=20pF)

Parameter

Symbol

min

typ

max

Unit

a) with a Crystal Oscillator:

11.2896

12.288

16.9344

18.432

MHz

CKM[2:0]bits=0h

fXTI

CKM[2:0]bits=1h

MHz

b) with an External Clock

Duty Cycle

40

50

60

%

11.2896

12.288

16.9344

18.432

CKM[2:0]bits=0h,2h

fXTI

11.0

12.4

MHz

CKM[2:0]bits=1h

LRCK Frequency

fXTI

fs

16.5

8

18.6

96

MHz

kHz

(Note 32)

48

BICK Frequency

TDM256 bit = “0”

(Normal Interface)

(Note 33)

High Level Width

Low Level Width

Frequency

High Level Width

Low Level Width

Frequency

tBCLKH

tBCLKL

fBCLK

tBCLKH

tBCLKL

fBCLK

64

0.23

32

1.8

ns

MHz

ns

MHz

6.2

3.072

TDM256 bit = “1”

(TDM Interface)

12.3

12.288

Note 32. RCK frequency and sampling rate (fs) should be the same.

Note 33. When BICK is the source of the master clock, it should be synchronized to LRCK and have stable

frequency.

1/fXTI

tXTI=1/fXTI

XTI

VIH

VIL

1/fs

ts=1/fs

1/fs

VIH

LRCK

VIL

1/fBCLK

tBCLK=1/fBCLK

VIH

VIL

BICK

tBCLKH

tBCLKL

Figure 4. System Clock Timing

014006643-E-00

2014/10

- 19 -

[AK7755]

2. Power Down

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V)

Parameter

Symbol

min

typ

max

Unit

PDN Pulse Width (Note 34)

tRST

600

ns

Note 34. The PDN pin must be set “L” when power up the AK7755.

PDN

tRST

VIL

Figure 5. Reset Timing

3. Serial Data Interface

SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

CL=20pF)

Parameter

Symbol min

typ

max Unit

Slave Mode

Delay Time from BICK “↑” to LRCK (Note 35)

Delay Time from LRCK to BICK “↑” (Note 35)

Serial Data Input Latch Setup Time

Serial Data Input Latch Hold Time

Delay Time from LRCK to Serial Data Output (Note 36)

Delay Time from BICK “↓” to LRCK Output (Note 37)

Master Mode

tBLRD 20

tLRBD 20

tBSIDS 20

tBSIDH 20

tLRD

ns

20

tBSOD

32, 48

64, 256

50

BICK Frequency

fBCLK

fs

BICK Duty Cycle

Delay Time from BICK “↓” to LRCK (Note 37)

Serial Data Input Latch Setup Time

%

ns

12

tMBL

-12

tBSIDS 20

tBSIDH 20

tLRD

Serial Data Input Latch Hold Time

Delay Time from LRCK to Serial Data Output (Note 36)

Delay Time from BICK “↓” or “↑”to LRCK Output (Note 37)

SDINn → SDOUTn (n=1, 2)

20

tBSOD

Delay Time from SDINn to SDOUTn Output

tIOD

60

ns

Note 35. BICK edge must not occur at the same time as LRCK edge.

If BICK polarity was inverted, the counting edge of BICK will be “↓”.

Note 36. Except I²S.

Note 37. When the polarity of BICK1 is inverted, delay time is from BICK1 “↑”.

SDOUT

n=1,2,3

50%TVDD

tIOD

VIH

VIL

SDINn

n=1,2

Figure 6. Serial Interface Delay Time from SDINn to SDOUTn Output

014006643-E-00

2014/10

- 20 -

[AK7755]

3-1. Slave Mode

LRCK

VIH

VIL

tBLRD

tLRBD

VIH

VIL

BICK

tBSIDS

tBSIDH

VIH

VIL

SDINn

n=1,2

Figure 7. Serial Interface Input Timing in Slave Mode

VIH

VIL

LRCK

BICK

tLRD

VIH

VIL

tBSOD

tLRD

tBSOD

SDOUTn

n=1,2,3

50%TVDD

Figure 8. Serial Interface Output Timing in Slave Mode

3-2. Master Mode

LRCK

50%TVDD

tMBL

BICK

tBSIDS

tBSIDH

VIH

VIL

SDINn

n=1,2

Figure 9. Serial Interface Input Timing in Master Mode

50%TVDD

LRCK

BICK

tLRD

50%TVDD

tBSOD

tLRD

SDOUTn

n=1,2,3

Figure 10. Serial Interface Output Timing in Master Mode

- 21 -

014006643-E-00

2014/10

[AK7755]

4. SPI Interface

4-1. Clock Reset (CKRESTN bit = “0”)

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

CL=20pF)

Parameter

Microcontroller Interface Signal

SCLK Frequency

Symbol

min

typ

max

3.5

Unit

fSCLK

tSCLKL

tSCLKH

MHz

ns

SCLK Low Level Width

SCLK High Level Width

Microcontroller → AK7755

CSN High Level Width

Time from CSN “↑” to PDN “↑”

Time from PDN“↑” to CSN “↓”

Time from RQN“↓” to SCLK“↓”

Time from SCLK“↑” to CSN“↑”

SI Latch Setup Time

120

tWRQH

tRST

tIRRQ

tWSC

tSCW

tSIS

300

360

1

360

480

120

ns

ms

ns

SI Latch Hold Time

tSIH

AK7755 → Microcontroller

SO Output Delay Time from SCLK “↓”

SO Output Hold Time from SCLK “↑”

(Note 38)

tSOS

tSOH

120

ns

120

Note 38. Except when input the eighth bit of the command code.

4-2. PLL Clock (CKRESTN bit = “1”)

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

CL=20pF)

Parameter

Microcontroller Interface Signal

SCLK Frequency

Symbol

min

typ

max

7

Unit

fSCLK

tSCLKL

tSCLKH

MHz

ns

SCLK Low Level Width

SCLK High Level Width

Microcontroller → AK7755

CSN High Level Width

Time from CSN “↑” to PDN “↑”

Time from PDN“↑” to CSN “↓”

Time from RQN“↓” to SCLK“↓”

Time from SCLK“↑” to CSN“↑”

SI Latch Setup Time

60

tWRQH

tRST

tIRRQ

tWSC

tSCW

tSIS

150

180

1

150

240

60

ns

ms

ns

SI Latch Hold Time

tSIH

60

AK7755 → Microcontroller

SO Output Delay Time from SCLK “↓”

SO Output Hold Time from SCLK “↑”

(Note 38)

tSOS

tSOH

60

ns

60

Note 39. It takes 10ms at maximum until PLL is locked, after setting CKRESTN bit to “1” from “0”.

014006643-E-00

2014/10

- 22 -

[AK7755]

VIH

VIL

SCLK

tSCLKL

1/fSCLK

tSCLKH

1/fSCLK

VIH

VIL

PDN

CSN

VIH

VIL

tRST

tIRRQ

Figure 11. SPI Interface Timing 1

VIH

VIL

tWRQH

CSN

SI

VIH

VIL

tSIS

tSIH

VIH

VIL

SCLK

tWSC

tSCW

tWSC

tSCW

Figure 12. SPI Interface Timing 2 (Microcontroller → AK7755)

VIH

VIL

SCLK

VIH

VIL

SO

tSOH

tSOS

Figure 13. SPI Interface Timing 3 (AK7755 → Microcontroller)

014006643-E-00

2014/10

- 23 -

[AK7755]

5. I²C-BUS Interface

(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,

CL=20pF)

Parameter

I2C Timing

SCL clock frequency

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first Clock pulse)

Clock Low Time

Symbol

min

typ

max

400

Unit

fSCL

tBUF

kHz

s

ns

1.3

0.6

1.3

0.6

0

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise Suppressed By Input Filter

Capacitive load on bus

0.9

0.1

0.3

tF

tSU:STO

tSP

0.6

0

50

400

Cb

pF

VIH

SDA

VIL

tLOW tR

tHIGH

tBUF

tF

tSP

VIH

VIL

SCL

tHD:STA

Stop Start

tHD:DAT

tSU:DAT tSU:STA

Start

tSU:STO

Stop

Figure 14. I²C BUS Interface Timing

6. Digital Microphone Interface

(AVDD=3.0~3.6V, TVDD=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V, Ta= -40C~85C;

CL=100pF)

Parameter

Symbol

min

typ

max

Unit

DMDAT1, DMDAT2

Serial Data Input Latch Setup Time

Serial Data Input Latch Hold Time

DMCLK1, DMCLK2

Clock Frequency (Note 40)

Duty Cycle

tDMDS

tDMDH

50

0

ns

fDMCK

dDMCK

tDMCKR

tDMCKF

0.5

40

64fs

50

6.2

60

10

MHz

%

ns

Rise Time

Fall Time

ns

Note 40. Clock frequency is determined by the sampling rate (fs) selected by DFS[2:0] bits.

014006643-E-00

2014/10

- 24 -

[AK7755]

tDMCK

65%AVDD

50%AVDD

35%AVDD

DMCLK1/2

tDMCKL

tDMCKF

tDMCKR

fDMCK = 1 / tDMCK

dDMCK = 100 x tDMKL / tDMCK

50%AVDD

DMCLK1/2

DMDAT1/2

tDMDS

tDMDH

VIH2

VIL2

DCLKP1, DCLKP2 bit = “1”

50%AVDD

DMCLK1/2

DMDAT1/2

tDMDS

tDMDH

VIH2

VIL2

DCLKP1, DCLKP2 bit = “0”

Figure 15. Digital Microphone Interface Timing Wave Form

014006643-E-00

2014/10

- 25 -

[AK7755]

9. Functional Description

■ System Clock

Master/Slave mode switching, clock source pin select for internal master clock (MCLK) generating clock

(ICLK), and ICLK frequency change are controlled by CKM [2:0] clock mode select bits. CKM[2:0] bits

can only be set during clock reset.

Use of

CKM CKM Master

ICLK

Source

Sampling Frequency

fs (Note 41)

Input pin(s) required for

system clock

crystal

oscillator

Available

Not

Available

Not

Available

Not

mode [2:0]

Slave

0

1

000

001

Master

XTI

DFS[2:0]bits

XTI(12.288MHz)

XTI(18.432MHz)

XTI(12.288MHz), BICK,

LRCK

2

3

5

010

011

101

Slave

XTI

DFS[2:0]bits

Fs=16kHz Fixed

BICK

BICK, LRCK

BICK, LRCK(fs=8kHz)

Available

Note 41. The sampling frequency is set by DFS[2:0] bits (CONT00). The BICK frequency is set by

BITFS[1:0] bits.

Note 42. In CKM mode 2, XTI, BICK and LRCK must be synchronized but the phase is not critical.

Note 43. CKM mode5 is the mode that operates DSP, ADC and DAC by 16kHz sampling frequency when

LRCK sampling frequency is 8kHz. The BICK sampling frequency for LRCK is set by

BITFS[1:0] bits.

1. Relationship between MCLK Generating Clock (ICLK) and MCLK

ICLK

REFCLK

MCLK

XTI Pin

Divider

PLL

CKM mode 0/1/2

CKM mode 3/5

(MCLK Source)

ICLK

REFCLK

BICK Pin

(MCLK Source)

Figure 16. Relation Ship between ICLK and MCLK

2. Sampling Frequency Select

FS mode DFS[2:0] fs: Sampling Frequency

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

8kHz

12kHz (11.025kHz)

16kHz

24kHz (22.05kHz)

32kHz

48kHz (44.1kHz)

96kHz (88.2kHz)

N/A

014006643-E-00

2014/10

- 26 -

[AK7755]

2-1. Master Mode (CKM mode 0, 1: Using XTI Input Clock)

fs: Sampling Frequency

XTI

CKM

mode

CKM

[2:0]

Input Frequency Range

(MHz)

Use of Chrystal

Oscillator

fs:48kHz series fs:44.1kHz series

0

1

000

001

12.288MHz

18.432MHz

11.2896MHz

16.9344MHz

11.0 to 12.4

16.7 to 18.6

Available

Input system clock to the XTI pin by setting BITFS[1:0] bits. The internal counter which is synchronized to

XTI generates LRCK(1fs) and BICK(64fs, 48fs, 32fs, 256fs). BICK frequency can be selected by

BITFS[1:0] bits. The BICK output will be in two different frequencies if setting BITFS[1:0] bits = 1h

(48kHz) when the sampling frequency is 12kHz, 24kHz, 48kHz or 96kHz (DFS[2:0]). LRCK and BICK are

not output during system reset.

XTI

External Clock

AK7755

XTO

Figure 17. Using Crystal Oscillator (CKM mode 0/1)

Using External Clock (CKM mode 0/1)

2-2. Slave Mode1 (CKM mode 2: XTI Input Clock）

fs: sampling frequency

XTI

fs:48kHz

12.288MHz

Input Frequency Range

(MHz)

11.2896MHz 11.0 to 12.4

CKM

mode

CKM

[2:0]

Use of Chrystal

Oscillator

fs:44.1kHz

2

010

Not Available

Required System Clocks are XTI, LRCK and BICK. XTI and LRCK must be synchronized, but the phase

between these clocks is not important. The system sampling rate is controlled by DFS[2:0] bits. The

sampling frequency of BICK is set by BITFS[1:0] bits.

2-3. Slave Mode 2 (CKM mode 3: BICK Input Clock)

In CKM mode 3, required system clocks are BICK and LRCK. In this mode, BICK is used for clock source

instead of XTI. This clock is multiplied directly by a PLL to generate the master clock (MCLK). Therefore

BICK with two different frequencies cannot be used. BICK and LRCK must be synchronized. Set BICK

frequency for LRCK by BITFS[1:0] bits. The sampling rate is determined by DFS[2:0] bits setting. In

applications which do not need the XTI pin of the AK7755, leave this pin open.

014006643-E-00

2014/10

- 27 -

[AK7755]

2-4. Slave Mode 3 (CKM mode 5: BICK Input Clock)

CKM mode5 is the mode that operates DSP, ADC and DAC by 16kHz sampling frequency when LRCK

sampling frequency is 8kHz. Set BICK frequency against LRCK by BITFS[1:0] bits. Each sampling

frequency is fixed (LRCK = 8kHz, DSP/ADC/DAC = 16kHz).

AK7755

SDIN2

SDOUT2

SDOUT3

(fs=16kHz)

DSP/ADC/DAC

(fs=16kHz)

LRCK

BICK

SDIN1

16k/8k

Converter

SDOUT1

(fs=8kHz)

Figure 18. Slave Mode3 (CKM mode5) Sampling Frequency Setting

fs: Sampling Frequency

DFS

[2:0]

0h

1h

2h

3h

4h

5h

6h

7h

BITFS

[1:0]

0h

1h

2h

3h

0h

1h

2h

3h

0h

1h

2h

3h

0h

1h

2h

3h

0h

1h

2h

3h

0h

1h

2h

3h

0h

1h

2h

3h

－

BICK Frequency

44.1kHz series 48kHz series

fs

8kHz

BICK

64fs

48fs

32fs

256fs

64fs

48fs

32fs

256fs

64fs

48fs

32fs

256fs

64fs

48fs

32fs

256fs

64fs

48fs

32fs

256fs

64fs

48fs

32fs

256fs

64fs

48fs

32fs

256fs

－

470.4kHz

352.8kHz

512kHz

384kHz

235.2kHz

256kHz

8kHz

1881.6kHz

705.6kHz

2048kHz

768kHz

12kHz

16kHz

24kHz

32kHz

48kHz

96kHz

N/A

352.8kHz

384kHz

2822.4kHz

940.8kHz

705.6kHz

3072kHz

1024kHz

768kHz

470.4kHz

512kHz

3763.2kHz

1.4112MHz

1058.4MHz

705.6kHz

4096kHz

1.536MHz

1.152MHz

768kHz

5.6448MHz

1.8816MHz

1.4112MHz

0.9408MHz

7.5264MHz

2.8224MHz

2.1168MHz

1.4112MHz

11.2896MHz

5.6448MHz

4.2336MHz

2.8224MHz

22.5792MHz

－

6.144MHz

2.048MHz

1.536MHz

1.024MHz

8.192MHz

3.072MHz

2.304MHz

1.536MHz

12.288MHz

6.144MHz

4.608MHz

3.072MHz

24.576MHz

－

(N/A: Not available)

Table 1. Clock Select

014006643-E-00

2014/10

- 28 -

[AK7755]

BITFS[1:0] bits = 0h @(LRIF[1:0] bits = 0h)

Right ch

LRCK

Left ch

BICK

32×BICK

Figure 19. BITFS[1:0] bits = 0h(64fs) (LRIF[1:0]bits = 0h)

BITFS[1:0] bits = 1h @(LRIF[1:0] bits = 0h)

Right ch

LRCK

BICK

Left ch

24×BICK

Figure 20. BITFS[1:0] bit s= 1h(48fs) (LRIF[1:0]bits = 0h)

BITFS[1:0] bits = 2h @(LRIF[1:0] bits = 0h)

Right ch

LRCK

Left ch

BICK

16×BICK

Figure 21. BITFS[1:0] bits = 2h(32fs) (LRIF[1:0]bits = 0h)

Refer to Figure 40 and Figure 42 when BITFS[1:0] bits = 3h (256fs).

014006643-E-00

2014/10

- 29 -

[AK7755]

■ Control Register Settings

Control registers are reset by a power down release (PDN pin = “L” → “H”). Since control registers

CONT00-CONT01 are related to clock generation, they must be changed during clock reset (CKRSTN bit

(CONT01: D0) = “0”). CONT12-CONT19 can be written during operation. The other control registers must

be changed during clock reset or system reset (CRESETN bit (CONT0F: D3) and DSPRESETN bit

(CONT0F: D2) = “0”) to avoid errors and noises.

CONT0D: D6, CONT1A: D4, CONT26: D0 and CONT2A: D7 bits must be set to “1” during system reset.

Once these bits are set to “1”, the value will be kept until power down the AK7755 (PDN pin = “L”). Do

not write to the CONT1F-CONT25, CONT27-CONT29 and CONT2B-CONT3F registers.

CONT00-CONT1E, CONT26, CONT2A

Name

D7

D6

D5

D4

D3

AINE

D2

DFS[2]

CLKS[1]

D1

D0

DFS[0]

CKRESETN

JX0E

BANK[0]

WAVP[0]

Default

00h

CONT00

CONT01

CONT02

CONT03

CONT04

0

CKM[2]

LRDOWN

BCKP

DIF2[0]

DRMS[0]

CKM[1]

BITFS[1]

LRIF[1]

DOF2[1]

DRAM[1]

CKM[0]

BITFS[0]

LRIF[0]

DOF2[0]

DRAM[0]

DFS[1]

CLKS[0]

JX1E

BANK[1]

WAVP[1]

JX2E

CLKS[2]

TDMMODE[1] TDMMODE[0]

BANK[3]

POMODE

TDM256

DIF2[1]

DRMS[1]

ACCRAM

CLRN

BANK[2]

0

00h

CONT05

JX3E

FIRMODE1

FIRMODE2

SUBMODE1 SUBMODE2 MEMDIV[1] MEMDIV[0]

00h

CONT06

CONT07

CONT08

CONT09

CONT0A

CONT0B

CONT0C

CONT0D

CONT0E

CONT0F

CONT10

CONT11

CONT12

CONT13

DEM[1]

DOF4[1]

SELDAI[1]

DIFR

CLKOE

0

DEM[0]

DOF4[0]

SELDAI[0]

INR

BICKE

0

DIFDA[1]

DOF3[1]

SELDO3[1]

DIFL

DIFDA[0]

DOF3[0]

SELDO3[0]

INL

0

DIF1[2]

DOF1[2]

SELDO2[0]

LO3SW2

OUT3E

DIF1[1]

DOF1[1]

SELMIX[1]

LO3SW1

OUT2E

DIF1[0]

DOF1[0]

SELMIX[0]

SELMIX[2]

OUT1E

00h

80h

00h

30h

18h

00h

30h

00h

SELDO2[1]

LO3SW3

0

LRCKE

0

DSM

STO

0

1

ATSPAD

0

PMAD2L

PML1

PLLLOCKE

CKADJ[5]

MGNR[1]

LIGN[1]

LOVOL2[1]

VOLADL[5]

ATSPDA

0

SELDO1[2]

0

PMLO1

DSPRESETN

0

CKADJ[2]

MGNL[2]

LOVOL3[2]

LOVOL1[2]

VOLADL[2]

SELDO1[1]

0

PMDAR

PMAD2R

0

CKADJ[1]

MGNL[1]

LOVOL3[1]

LOVOL1[1]

VOLADL[1]

SELDO1[0]

DLS

PMDAL

PMADR

0

WDTEN

CKADJ[7]

MGNR[3]

LIGN[3]

PMADL

0

CRCE

CKADJ[6]

MGNR[2]

LIGN[2]

LOVOL2[2]

VOLADL[6]

PMLO3

LRDETN

SOCFG

CKADJ[4]

MGNR[0]

LIGN[0]

LOVOL2[0]

VOLADL[4]

PMLO2

CRESETN

SELSTO

CKADJ[3]

MGNL[3]

LOVOL3[3]

LOVOL1[3]

VOLADL[3]

DLRDY

CKADJEN

CKADJ[0]

MGNL[0]

LOVOL3[0]

LOVOL1[0]

VOLADL[0]

CONT14 LOVOL2[3]

CONT15 VOLADL[7]

CONT16 VOLADR[7] VOLADR[6] VOLADR[5] VOLADR[4] VOLADR[3] VOLADR[2] VOLADR[1] VOLADR[0]

CONT17 VOLAD2L[7] VOLAD2L[6] VOLAD2L[5] VOLAD2L[4] VOLAD2L[3] VOLAD2L[2] VOLAD2L[1] VOLAD2L[0]

CONT18 VOLDAL[7]

VOLDAL[6]

VOLDAL[5]

VOLDAL[4]

VOLDAL[3]

VOLDAL[2]

VOLDAL[1]

VOLDAL[0]

CONT19 VOLDAR[7] VOLDAR[6] VOLDAR[5] VOLDAR[4] VOLDAR[3] VOLDAR[2] VOLDAR[1] VOLDAR[0]

CONT1A

CONT1B AMGNR[3]

CONT1C

ADMUTE

AD2MUTE

AMGNR[2]

0

DAMUTE

AMGNR[1]

0

1

ADRCRE

AMGNL[3]

0

ADRCLE

AMGNL[2]

0

MICRZCE

AMGNL[1]

0

MICLZCE

AMGNL[0]

0

AMGNR[0]

0

CONT1D VOLAD2R[7] VOLAD2R[6] VOLAD2R[5] VOLAD2R[4] VOLAD2R[3] VOLAD2R[2] VOLAD2R[1] VOLAD2R[0]

CONT1E

CONT26

CONT2A

DMIC1

DMCLKP1

DMCLKE1

DMIC2

DMCLKP2

DMCLKE2

0

1

0

1

0

014006643-E-00

2014/10

- 30 -

[AK7755]

Default

CONT00: Clock Setting 1, Analog Input Setting

Write during clock reset.

W

R

Name

D7 D6

D5

D4

D3

D2

D1

D0

C0h 40h CONT00

0

CKM[2] CKM[1] CKM[0] AINE DFS[2] DFS[1] DFS[0] 00h

D6, D5, D4: CKM[2:0] Clock Mode Setting

CKM

mode

CKM Master

[2:0] Slave

Main Clock

fs

System Clock

0

1

2

3

000

001

010

011

Master XTI=12.288MHz fixed fs=8~96kHz

Master XTI=18.432MHz fixed fs=8~96kHz

XTI

(default)

Slave

XTI=12.288MHz fixed fs=8~96kHz

XTI, BICK, LRCK

BICK, LRCK

BICK,

BICK

fs=8~96kHz

5

101

Slave

BICK

fs=16kHz

LRCK(fs=8kHz)

TDM256 bit (CONT02: D7) = “1” cannot be used in CKM mode5.

D3: AINE Analog Input Setting (IN1/INP1, IN2/INN1, IN3/INP2, IN4/INN2 pin)

0: Not Using Analog Input (default)

1: Using Analog Input

Set AINE bit to “1” first before other control register settings when using the IN1/INP1, IN2/INN1,

IN3/INP2 and IN4/INN2 pins as analog inputs. The AK7755 starts charging to a capacitor connected

to each pin by this setting.

Set AINE bit to “0” when using digital microphones (DMIC1 or DMIC2 bit (CONT1E: D7, D4)=

“1”).

D2, D1, D0: DFS[2:0] Sampling Frequency

fs

8kHz

DFS mode

DFS[2:0]

000

0

1

2

3

4

5

6

7

(default)

001

010

011

100

101

110

111

12kHz

16kHz

24kHz

32kHz

48kHz

96kHz

N/A

Multiply 44.1/48 to calculate the values for multiple sampling frequencies of 44.1kHz.

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 31 -

[AK7755]

CONT01: Clock Setting 2 and JX2 Setting

Write during clock reset.

W

R

Name

D7

D6

LR

DOWN

D5

BITFS BITFS CLKS

[1] [0] [2]

D4

D3

D2

CLKS

[1]

D1

CLKS

[0]

D0

CK

RESETN

Default

00h

C1h 41h CONT01 JX2E

D7: JX2E External Conditional Jump 2 Enable

0: JX2 is Disabled (default), No. 14-pin output (SDOUT3) when OUT3E bit (CONT0A:D2) = “1”

1: JX2 is Enabled, No. 14-pin Input

D6: LRDOWN LRCK Sampling Frequency Select

0: LRCK Sampling frequency set by DFS[2:0] bits (CONT00: D2-D0). (default)

1: LRCK Half frequency of the setting value by DFS[2:0] bits

The AK7755 can output the LRCK which is half frequency of the setting value by DFS[2:0] bits

in master mode (CKM mode 0, 1(CONT00: D6-D4)). This mode is used when

LRCK/BICK/SDIN1/SDOUT1 is driven by fs= 8kHz while the AK7755 is driven by fs= 16kHz

in master mode. LRDOWN bit = “1” cannot be set when TDM256 bit (CONT02: D7) = “1”.

D5, D4: BITFS[1:0] BICK fs Select

BITFS

mode

BITFS

[1:0]

00

01

10

BICK Note

0

1

2

3

64fs

48fs

512kHz(@fs=8kHz),3.072MHz(@fs=48kHz)

(default)

384kHz(@fs=8kHz),2.304MHz(@fs=48kHz)

256kHz(@fs=8kHz),1.536MHz(@fs=48kHz)

2.048MHz(@fs=8kHz),12.288MHz(@fs=48kHz)

32fs

256fs

11

This setting is valid in both slave and master modes.

Set the BICK input sampling frequency against LRCK, in Slave mode (CKM2, 3 and 5).

Set the BICK output sampling frequency against LRCK in Master mode (CKM0 and 1).

The BICK output will be in two different frequencies if setting BITFS[1:0] bits = 1h (48kHz) when

the sampling frequency is 12kHz, 24kHz, 48kHz or 96kHz (DFS[2:0]).

D3, D2, D1: CLKS[2:0] CLKO Output Clock Select

CLKS mode CLKS[2:0]

fs=48kHz

12.288MHz

6.144MHz

3.072MHz

8.192MHz

4.096MHz

2.048MHz

256fs

fs=44.1kHz

11.2896MHz

5.6448MHz

2.8224MHz

7.5264MHz

3.7632MHz

1.8816MHz

256fs

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

(default)

XTI or BICK

D0: CKRESETN Clock Reset

0: Clock Reset (default)

1: Clock Reset Release

014006643-E-00

2014/10

- 32 -

[AK7755]

CONT02: Serial Data Format, JX1, 0 Setting

Name D7 D6 D5

W

R

D4

D3

D2

D1

D0

Default

C2h 42h CONT02 TDM256 BCKP LRIF[1] LRIF[0] TDM

TDM

JX1E JX0E 00h

MODE[1] MODE[0]

D7: TDM256, TDM Select

0: Normal Interface (default)

1: TDM Interface

BICK is fixed to 256fs. Set BITFS[1:0] bits = 3h (CONT01: D5, D4). Format is selected by

LRIF[1:0] bits setting (CONT02: D5, D4). In this mode, CKM mode 5(CONT00: D6-D4) is not

available. TDM256 bit cannot be set to “1” when LRDOWN bit (CONT00: D6) = “1”. In TDM

mode, a 96kHz sampling frequency is not available. DFS[2:0] bits (CONT00: D2-D0) setting

must be lower than 5h (48kHz).

D6: BCKP BICK Edge Select

BCKP bit BICK edge referenced to LRCK edge

0

1

falling (FE)

rising (RE)

(default)

D5, D4: LRIF[1:0] LRCK I/F Format

Mode LRIF[1:0]bit

Digital I/F Format

0

1

2

3

00

01

10

11

Standard (MSB justified/ LSB justified) (default)

I²S Compatible

PCM Short Frame

PCM Long Frame

In standard format mode, MSB justified and 24/20/16 bit LSB justified formats are selectable by DIF1

bits (CONT06: D2-D0), DIF2 bits (CONT03: D7, D6), DIFDA bits (CONT06: D5, D4), DOF1 bits

(CONT07: D2-D0), DOF2 bits (CONT03: D5, D4), DOF3 bits (CONT07: D5, D4), and DOF4 bits

(CONT07: D7, D6). In other modes, MSB justified format should be selected by DIF1-2 bits, DAF bit

and DOF1-4 bits.

D3, D2: TDMMODE[1:0] DSPDIN3, DSPDIN4 Input Source Select (Valid when TDM256bit = “1”)

TDMMODE

Mode

DSPDIN4 Lch

DSPDIN4 Rch

DSPDIN3 Lch

DSPDIN3 Rch

[1:0]

00

01

10

11

0

1

2

3

SDIN1 SLOT7

SDOUTAD Lch

N/A

SDIN1 SLOT8

SDOUTAD Rch

N/A

SDIN1 SLOT5

SDOUTAD2 Lch

N/A

SDIN1 SLOT6

SDOUTAD2 Rch

N/A

(default)

D1: JX1E External Conditional Jump1 Enable

0: JX1 is invalid (default)

1: JX1 is valid

D0: JX0E External Conditional jump0 Enable

0: JX0 is invalid (default)

1: JX0 is valid

014006643-E-00

2014/10

- 33 -

[AK7755]

Default

CONT03: Delay RAM, DSP Input / Output Setting

Name D7 D6 D5 D4 D3

W

R

D2

D1

D0

C3h 43h CONT03

0

BANK[3] BANK[2] BANK[1] BANK[0] 00h

D7, D6: DIF2[1:0] DSP DIN2 Input Format Select

DIF2 Mode DIF2[1:0] Input Data Format

0

1

2

3

00

01

10

11

MSB (24-bit)

LSB 24-bit

LSB 20-bit

LSB 16-bit

(default)

Set “00” for I²S compatible, PCM Short and PCM Long formats.

Set “11” when BITFS[1:0] bits (CONT01: D5, D4) = 2h (32fs).

D5, D4: DOF2[1:0] DSP DOUT2 Output Format Select

DOF2 Mode DOF2[1:0] Output Data Format

0

1

2

3

00

01

10

11

MSB (24-bit)

LSB 24-bit

LSB 20-bit

LSB 16-bit

(default)

Set “00” for I²S compatible, PCM Short and PCM Long formats.

Set “11” when BITFS[1:0] bits = 2h (32fs).

D3, D2, D1, D0: BANK[3:0] DLRAM mode Setting

DLRAM

Partition

mode

Delay RAM

Bank1

BANK

[3:0]

Bank0

Linear 20.4f

Ring 20.4f

8192 words

7168 words

6144 words

5120 words

4096 words

3072 words

0

1

2

3

4

5

0000

0001

0010

0011

0100

0101

0

(default)

1024 words

2048 words

3072 words

4096 words

5120 words

6

7

8

0110

0111

1000

1001

1111

6144 words

7168 words

8192 words

2048 words

1024 words

0

9-15

N/A

014006643-E-00

2014/10

- 34 -

[AK7755]

Default

CONT04: Data RAM, CRAM Setting

W R Name D7 D6

D5

D4

D3

D2 D1

D0

C4h 44h CONT04 DRMS[1] DRMS[0] DRAM[1] DRAM[0] POMODE 0

WAVP[1] WAVP[0] 00h

D7, D6: DRMS[1:0] Data RAM Size Setting

DSP Data RAM

DRAM DRMS

Bank1

Memory

size[words]

512

Bank0

Memory

size[words]

1536

mode

[1:0]

0

1

2

3

00

01

10

11

(default)

1024

1536

N/A

1024

512

D5, D4: DRAM[1:0] Data RAM Addressing mode Setting

DSP Data RAM

Addressing DRAM

mode

[1:0]

Bank1 DP1

Bnak0 DP0

0

1

2

3

00

01

10

11

Ring

Linear

Ring

Linear

Ring

Linear

(default)

D3: POMODE DLRAM Pointer 0 Select

0: DBUS Immediate (default)

1: OFREG

D1, D0: WAVP[1:0] CRAM Memory Assignment

WAVP mode WAVP[1:0]

FFT Point Number

0

1

2

3

00

01

10

11

33word

65word

129word

257word

128

256

512

(default)

1024

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 35 -

[AK7755]

CONT05: Accelerator Setting, JX3 Setting

W

R

Name

D7

D6

D5

D4

D3

D2

D1

D0

Default

ACCRAM

CLRN

FIR

SUB

MODE1 MODE2

SUB

MEM MEM

DIV[1] DIV[0]

C5h 45h CONT05

JX3E

00h

MODE1 MODE2

D7: ACCRAMCLRN Accelerator CRAM Clear Setting

0: Accelerator CRAM is cleared by 0 data after releasing reset. (default)

1: Accelerator CRAM is not cleared after releasing reset.

D6: JX3E External Conditional Jump3 Enable

0: JX3 Disable (default), No. 15 pin output (SDOUT2) when OUT2E bit (CONT0A:D1) = “1”

1: JX3 Enable, No. 15 pin Input

D5: FIRMODE1 Accelerator Ch1 Operation Select

0: Adaptive Filter (default)

1: FIR Filter

D4: FIRMODE2 Accelerator Ch2 Operation Select

0: Adaptive Filter (default)

1: FIR Filter

D3: SUBMODE1 Accelerator Ch1 Mode Select

0: Fullband (default)

1: Subband

D2: SUBMODE2 Accelerator Ch2 Mode Select

0: Fullband (default)

1: Subband

D1, D0: MEMDIV[1:0] Accelerator Memory Select

MODE

MEMDIV[1:0]

ch1

ch2

0

1

2

3

00

01

10

11

2048

1792

1536

1024

-

(default)

256

512

1024

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 36 -

[AK7755]

Default

CONT06: DAC De-emphasis, DAC and DSP Input Format Settings

Name D7 D6 D5 D4 D3 D2

W

R

D1

D0

C6h 46h CONT06 DEM[1] DEM[0] DIFDA[1] DIFDA[0] 0

DIF1[2] DIF1[1] DIF1[0] 00h

D7, D6: DEM[1:0] DAC De-emphasis Setting (50/15μs)

DEM mode

DEM[1:0]

Sampling Frequency fs

0

1

2

3

00

01

10

11

OFF

48kHz

44.1kHz

32kHz

(default)

D5, D4: DIFDA[1:0] DAC Input Format Select

DIFDA mode DIFDA[1:0] Input Data Format

MSB justified (24-bit)

0

1

2

3

00

01

10

11

(default)

LSB justified 24-bit

LSB justified 20-bit

LSB justified 16-bit

Set “00” for I²S Compatible, PCM Short and PCM Long formats.

Set “11” when BITFS[1:0] bits (CONT01: D5, D4) =2h (32fs).

Set “00” when connecting MIXOUT or DSP-DOUT4 to DAC input.

D2, D1, D0: DIF1[2:0] DSP DIN1 Input Format Select

DIF1 Mode DIF1[2:0] Input Data Format

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

MSB (24-bit)

LSB 24-bit

LSB 20-bit

LSB 16-bit

MSB 8-bit μ-Law

MSB 8-bit A-Law

N/A

(default)

N/A

Set “000” for I²S Compatible, PCM Short and PCM Long formats.

Set “011” when BITFS[1:0]=2h (32fs).

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 37 -

[AK7755]

Default

CONT07: DSP Output Format Setting

Name D7 D6

W

R

D5

D4

D3 D2

D1

D0

C7h 47h CONT07 DOF4[1] DOF4[0] DOF3[1] DOF3[0] 0 DOF1[2] DOF1[1] DOF1[0] 00h

D7, D6: DOF4[1:0] DSP DOUT4 Output Format Select

DOF4 mode

DOF4[1:0]

Output Data Format

MSB justified (24-bit)

LSB justified 24-bit

LSB justified 20-bit

LSB justified 16-bit

0

1

2

3

00

01

10

11

(default)

Set “00” for I²S Compatible, PCM Short and PCM Long formats.

Set “11” when BITFS[1:0] bits (CONT01: D5, D4) =2h (32fs).

Set “00” when connecting to the DAC.

D5, D4: DOF3[1:0] DSP DOUT3 Output Format Select

DOF3 mode

DOF3[1:0]

Output Data Format

MSB justified (24-bit)

LSB justified 24-bit

LSB justified 20-bit

LSB justified 16-bit

0

1

2

3

00

01

10

11

(default)

Set “00” for I²S Compatible, PCM Short and PCM Long formats.

Set “11” when BITFS[1:0] bits=2h (32fs).

D2, D1, D0: DOF1[2:0] DSP DOUT1 Output Format Select

DOF1 mode

DOF1[2:0] Output Data Format

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

MSB (24-bit)

LSB 24-bit

LSB 20-bit

LSB 16-bit

MSB 8-bit μ-Law

MSB 8-bit A-Law

N/A

(default)

N/A

Set “000” for I²S Compatible, PCM Short and PCM Long formats.

Set “011” when BITFS[1:0] bits=2h (32fs).

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 38 -

[AK7755]

CONT08: DAC Input, SDOUT2/3 Output, Digital Mixer Input Setting

W

R

Name

D7

D6

[0]

D5

[1]

D4

D3

[1]

D2

[0]

D1

[1]

D0

[0]

Default

00h

SELDAI SELDAI SELDO3 SELDO3 SELDO2 SELDO2 SELMIX SELMIX

[1]

C8h 48h CONT08

[0]

D7, D6: SELDAI[1:0] DAC Input Select

SELDAI mode

SELDAI[1:0]

Input Data

0

1

2

3

00

01

10

11

DSP DOUT4 (default)

MIXOUT

SDIN2

SDIN1

Set DIFDA[1:0] bits (CONT06: D5, D4) = 0h when selecting DSP DOUT4 or MIXOUT.

D5, D4: SELDO3[1:0] SDOUT3 pin Output Select

SELDO3 mode SELDO3[1:0]

Output Data

DSP DOUT3

MIXOUT

DSP DOUT4

SDOUTAD2

0

1

2

3

00

01

10

11

(default)

The output format is fixed to MSB 24-bit when selecting SDOUTAD2 or MIXOUT.

D3, D2: SELDO2[1:0] SDOUT2 pin Output Select

SELDO2 mode SELDO2[1:0]

Output Data

DSP DOUT2 (default)

GP1

SDIN2

SDOUTAD2

0

1

2

3

00

01

10

11

The output format is fixed to MSB 24-bit when selecting SDOUTAD2.

(CONT09 D0), D1, D0: SELMIX[2:0] Digital Mixer Input Select

SELMIX mode SELMIX[2:0] MIXOUT Lch

MIXOUT Rch

1

000

SDOUTAD Lch

SDOUTAD Rch

(default)

SDOUTAD Lch/2

+ SDOUTAD2 Lch/2

1

001

SDOUTAD Rch

SDOUTAD Rch /2

+ SDOUTAD2 Rch/2

SDOUTAD2 Rch

DSP-DOUT4 Rch

SDOUTAD Rch

2

010

SDOUTAD Lch

SDOUTAD2 Lch

DSP-DOUT4 Lch

SDOUTAD2 Lch

DSP-DOUT4 Lch

SDOUTAD Lch

3

4

5

6

7

011

100

101

110

111

DSP-DOUT4 Rch

014006643-E-00

2014/10

- 39 -

[AK7755]

Default

CONT09: Analog Input / Output Setting

Name D7 D6 D5 D4 D3

W

R

D2

D1

D0

C9h 49h CONT09 DIFR INR DIFL INL LO3SW3 LO3SW2 LO3SW1 SELMIX[2] 00h

D7, D6: DIFR, INR ADC Rch Analog Input

AK7755

INL bit

IN1/INP1 pin

IN2/INN1 pin

DIFR bit INR bit

ADC Rch

IN3

IN4

INP2/INN2

ADC

Lch

0

1

0

1

X

(default)

MIC-Amp

DIFL bit

INR bit

IN3/INP2 pin

IN4/INN2 pin

D5, D4: DIFL, INL ADC Lch Analog Input

ADC

Rch

DIFL bit INL bit

ADC Lch

IN1

IN2

INP1/INN1

0

1

0

1

X

(default)

DIFR bit

Figure 22. Analog Input Select

D3: LO3SW3 OUT3 Mixing Select 3

0: LIN off (default)

1: LIN on

D2: LO3SW2 OUT3 Mixing Select 2

0: DAC Rch off (default)

1: DAC Rch on

D1: LO3SW1 OUT3 Mixing Select 1

0: DAC Lch off (default)

1: DAC Lch on

AK7755

Mono

ADC

Stereo

DAC Lch

OUT1 pin

OUT2 pin

LIN pin

LOVOL1[3:0]

LIGN[3:0]

Stereo

DAC Rch

LO3SW1

LO3SW2

LO3SW3

LOVOL2[3:0]

LOVOL3[3:0]

M

I

X

OUT3 pin

Figure 23. OUT3 Output Select

D0: SELMIX[2] Digital Mixer Input Select

Refer to CONT08: D1, D0, SELMIX[2:0] bits

014006643-E-00

2014/10

- 40 -

[AK7755]

Default

CONT0A: CLK and SDOUT Output Setting

W

R

Name

D7

D6

D5

D4 D3 D2

D1

D0

CAh 4Ah

CONT0A CLKOE BICKOE LRCKOE

0

OUT3E OUT2E OUT1E 00h

D7: CLKOE CLKO pin Setting

0: CLKO= “L” (default)

1: CLKO Output Enable

D6: BICKOE BICK pin Output Setting

0: BICKO= “L” (default)

1: BICKO Output Enable

This setting is invalid in Slave mode (CKM mode 2, 3, and 5 (CONT00: D6-D4)).

D5: LRCKOE LRCK pin Output Setting (Master Mode)

0: LRCKO= “L” (default)

1: LRCKO Output Enable

This setting is invalid in Slave mode (CKM mode2, 3 and 5).

D2: OUT3E

0: SDOUT3= “L” (default)

1: SDOUT3 Output Enable Valid when JX2E bit (CONT01: D7) = “0”

D1: OUT2E

0: SDOUT2= “L” (default)

1: SDOUT2 Output Enable Valid when JX3E bit (CONT05: D6) = “0”

D0: OUT1E

0: SDOUT1= “L” (default)

1: SDOUT1 Output Enable

Write “0” into the “0” registers.

CONT0B: TEST Setting

W

R

Name

D7 D6 D5 D4

D3 D2

D1

0

D0

0

Default

00h

CBh 4Bh CONT0B 0

0

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 41 -

[AK7755]

Default

CONT0C: ADC, DAC Volume Transition Time and SDOUT1 Output Settings

Name D7 D6 D5 D4 D3 D2 D1 D0

W

R

CCh 4Ch CONT0C DSM 0

ATSPAD ATSPDA 0

SELDO1[2] SELDO1[1] SELDO1[0] 00h

D7: DSM Delta Sigma Module Sampling CLK Setting

0: DSMCLK 256fs (default)

1: DSMCLK 12.288MHz

D5: ATSPAD ADC Volume Transition Time Setting

0: 1/fs (default)

1: 4/fs

D4: ATSPDA DAC Volume Transition Time Setting

0: 1/fs (default)

1: 4/fs

D2, D1, D0: SELDO1[2:0] SDOUT1 Pin Output Select

SELDO1 mode SELDO1[2:0] Output Data

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

DSP DOUT1

GP0

SDIN1

SDOUTAD

EEST

SDOUTAD2

N/A

(default)

N/A

The output format is fixed to MSB 24-bit when selecting SDOUTAD or SDOUTAD2.

Write “0” into the “0” registers.

CONT0D: STO Status Read and EEPROM Download Setting

W

R

Name

D7

STO

D6

1

D5

0

D4

0

D3

0

D2

0

D1

0

D0

DLS

Default

80h

CDh 4Dh CONT0D

D7: STO Status Output

0: Internal Error Status

1: Normal Operation (default)

This is a read only register.

D6: 1

Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F:D3) = “0” and

DSPRESETN bit (CONT0F: D2) = “0”).

D0: DLS Start EEPROM Downloading

0: Normal Operation (default)

1: Start EEPROM Downloading

This setting is valid when the I2CSEL pin= “H”. Register settings and DSP programs can be

downloaded from an external EEPROM by setting the EXTEEP pin = “H” or DLS bit = “1”.

However, when selecting memory mat (I2CSEL pin = MATSEL pin = “H”), downloading cannnot be

executed by DLS bit.

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 42 -

[AK7755]

CONT0E: ADC, DAC, Lineout Power Management

Name D7 D6 D5 D4

W

R

D3

D2

D1

D0

Default

00h

CEh 4Eh CONT0E PMADR PMADL PMAD2L PMLO3 PMLO2 PMLO1 PMDAR PMDAL

D7: PMADR Power Management (MIC-Amp Rch + ADC Rch)

0: Power-down (default)

1: Start Normal Operation after releasing CODEC Reset (CRESETN bit (CONT0F: D3) = “1”).

D6: PMADL Power Management (MIC-Amp Lch + ADC Lch)

0: Power- down (default)

1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).

D5: PMAD2L Power Management (ADC2 Lch)

0: Power- down (default)

1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).

D4: PMLO3 Lineout 3 Power Management

0: Power- down (default)

1: Normal Operation

D3: PMLO2 Lineout 2 Power Management

0: Power- down (default)

1: Normal Operation

D2: PMLO1 Lineout 1 Power Management

0: Power- down (default)

1: Normal Operation

D1: PMDAR Power Management (DAC Rch)

0: Power- down (default)

1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).

D0: PMDAL Power Management (DAC Lch)

0: Power- down (default)

1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).

014006643-E-00

2014/10

- 43 -

[AK7755]

Default

CONT0F: Reset Settings, Lineout and Digital MIC2 Rch Power Managements

W

R

Name

D7 D6 D5

D4

D3

D2

D1

D0

CFh 4Fh CONT0F 0

0

PML1 LRDETN CRESETN DSPRESETN

DLRDY 00h

PMAD2R

D5: PMLI Line-in Power Management

0: Power-down (default)

1: Normal Operation

D4: LRDETN Slave Mode Automatic System Reset Setting

0: LRCK Detect ON (default)

1: LRCK Detect OFF

When this bit is “0”, if the LRCK is stopped or the LRCK phase is shifted more than 1/4fs, the

AK7755 enters system reset state automatically.

D3: CRESETN CODEC Reset N

0: CODEC Reset (default)

1: CODEC Reset Release

CODEC means the ADC and the DAC.

D2: DSPRESETN DSP Reset N

0: DSP Reset (default)

1: DSP Reset Release

The AK7755 is in system reset state when CRESETN bit = “0” and DSPRESETN bit = “0”.

D1: PMAD2R Power Managements of ADC2 Rch (only when using digital microphone)

0: Power-down (default)

1: The AK7755 enters normal operation after releasing CODEC Reset (CRESETN bit = “1”).

D0: DLRDY DSP Download Ready

0: Normal Operation (default)

1: Program Downloading

DSP programs and coefficient data can be downloaded by setting this bit to “1” during clock reset

(CKRESETN bit = “0”) or when the main clock is stopped. This bit must be set to “0” after finishing

the downloading.

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 44 -

[AK7755]

Default

CONT10: Function Settings

Name D7

W

R

D6

D5

D4

D3

D2 D1 D0

D0h 50h CONT10 WDTEN CRCE PLLLOCKE SOCFG SELSTO 0

0

CKADJEN 00h

D7: WDTEN WDT (watchdog timer) Setting

0: WDTE Enable (default)

1: WDTE Disable

D6: CRCE CRC (cyclic redundancy check) Setting

0: CRC Disable (default)

1: CRC Enable

D5: PLLLOCKE PLL LOCK Detection

0: PLL LOCK Disable (default)

1: PLL LOCK Enable

D4: SOCFG SO pin Hi-Z Select

0: Hi-Z (default)

1: CMOSL

D3: SELSTO STO/RDY Pin Selecting Status Out

0: STO (default)

1: RDY

D0: CKADJEN Clock Adjustment Enable

0: CKADJ DISABLE (default)

1: CKADJ ENABLE

Write this bit to “1” when setting CONT11 CKADJ[7:0] bits.

Write “0” into the “0” registers.

CONT11: DSPMCLK Availability Ratio Setting

W

R

Name D7

CK

D6

CK

D5

CK

D4

CK

D3

CK

D2

CK

D1

CK

D0

CK

Default

00h

D1h 51h CONT11

ADJ[7]) ADJ[6]) ADJ[5]) ADJ[4]) ADJ[3]) ADJ[2]) ADJ[1]) ADJ[0])

D7-D0: CKADJ [7:0] DSPMCLK Availability Ratio Setting

Availability = (256-CKADJ) / 256

0000_0000: 100% driving (Normal) (default)

0000_0001: 99.6% driving

•

• •

1000_0000: 50% driving

•

• •

1111_1110: 0.8% driving

1111_1111: 0.4% driving

Set CONT10 CKADJEN bit to “1” when using this register.

DSPMCLK must always be more than 10 times of SCLK.

For example, when SCLK is 2MHz, the setting should be lower than 0hD6 (214) since CKADJ[7:0] <

256 – (2 x 10 x 256) / 122.88 = 214.33.

014006643-E-00

2014/10

- 45 -

[AK7755]

Default

CONT12: Microphone Gain Setting

W

R

Name

D7

D6

[2]

D5

[1]

D4

[0]

D3

[3]

D2

D1

[1]

D0

[0]

MGNR MGNR MGNR MGNR MGNL MGNL MGNL MGNL

D2h 52h CONT12

00h

[3]

[2]

D7, D6, D5, D4: MGNR[3:0] Microphone Input Rch Gain Setting

MGNR mode

MGNR[3:0]

Microphone Input Rch

Gain

(default)

0

1

2

3

4

5

6

7

8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0dB

2dB

4dB

6dB

8dB

10dB

12dB

14dB

16dB

18dB

21dB

24dB

27dB

30dB

33dB

36dB

9

A

B

C

D

E

F

D3, D2, D1, D0: MGNL[3:0] Microphone Input Lch Gain

MGNL mode

MGNL[3:0]

Microphone Input Lch

Gain

0dB

(default)

0

1

2

3

4

5

6

7

8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2dB

4dB

6dB

8dB

10dB

12dB

14dB

16dB

18dB

21dB

24dB

27dB

30dB

33dB

36dB

9

A

B

C

D

E

F

014006643-E-00

2014/10

- 46 -

[AK7755]

CONT13: Line-in/Lineout 3 Volume Setting

W

R

Name

D7

D6

D5

D4

D3

D2

D1

D0

Default

00h

LOVOL3 LOVOL3 LOVOL3 LOVOL3

[3]

D3h 53h CONT13 LIGN[3] LIGN[2] LIGN[1] LIGN[0]

[2]

[1]

[0]

・D7, D6, D5, D4: LIGN[3:0] Line-in Volume Setting

LIGN mode

LIGN[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Line-in Volume Setting

0dB

(default)

0

1

2

3

4

5

6

7

8

-3dB

-6dB

-9dB

-12dB

-15dB

-18dB

-21dB

N/A

+3dB

+6dB

+9dB

+12dB

+15dB

+18dB

+21dB

9

A

B

C

D

E

F

・D3, D2, D1, D0: LOVOL3[3:0] Line-out 3 Volume Setting

LOVOL3 mode LOVOL3[3:0] Line-out 3 Volume Setting

(default)

0

1

2

3

4

5

6

7

8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Mute

-28dB

-26dB

-24dB

-22dB

-20dB

-18dB

-16dB

-14dB

-12dB

-10dB

-8dB

9

A

B

C

D

E

F

-6dB

-4dB

-2dB

0dB

014006643-E-00

2014/10

- 47 -

[AK7755]

CONT14: Line-out 1, Line-out 2 Volume Setting

Name D7 D6 D5 D4

LOVOL2 LOVOL2 LOVOL2 LOVOL2 LOVOL1 LOVOL1 LOVOL1 LOVOL1

W

R

D3

[3]

D2

[2]

D1

[1]

D0

[0]

Default

00h

D4h 54h CONT14

[3]

[2]

[1]

[0]

D7, D6, D5, D4: LOVOL2[3:0] Line-out 2 Volume Setting

LOVOL2 mode

LOVOL2[3:0]

Lineout 2 Volume Setting

(default)

0

1

2

3

4

5

6

7

8

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

Mute

-28dB

-26dB

-24dB

-22dB

-20dB

-18dB

-16dB

-14dB

-12dB

-10dB

-8dB

9

A

B

C

D

E

F

-6dB

-4dB

-2dB

0dB

D3, D2, D1, D0: LOVOL1[3:0] Line-out 1 Volume Setting

LOVOL1 mode

LOVOL1[3:0]

Lineout 1 Volume Setting

(default)

0

1

2

3

4

5

6

7

8

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

Mute

-28dB

-26dB

-24dB

-22dB

-20dB

-18dB

-16dB

-14dB

-12dB

-10dB

-8dB

9

A

B

C

D

E

F

-6dB

-4dB

-2dB

0dB

CONT15-16-17: ADC, ADC2 Lch Digital Volume Setting

W

R

Name

D7

VOL

D6

VOL

D5

VOL

D4

VOL

D3

VOL

D2

VOL

D1

VOL

D0

VOL

Default

30h

D5h 55h CONT15

D6h 56h CONT16

D7h 57h CONT17

ADL[7] ADL[6] ADL[5] ADL[4] ADL[3] ADL[2] ADL[1] ADL[0]

VOL VOL VOL VOL VOL VOL VOL VOL

ADR[7] ADR[6] ADR[5] ADR[4] ADR[3] ADR[2] ADR[1] ADR[0]

VOL VOL VOL VOL VOL VOL VOL VOL

AD2L[7] AD2L[6] AD2L[5] AD2L[4] AD2L[3] AD2L[2] AD2L[1] AD2L[0]

30h

Refer to “2-3. ADC, ADC2 digital volume”.

014006643-E-00

2014/10

- 48 -

[AK7755]

CONT18-19: DAC Digital Volume Setting

W

R

Name

D7

VOL

D6

VOL

D5

VOL

D4

VOL

D3

VOL

D2

VOL

D1

VOL

D0

VOL

Default

18h

D8h 58h CONT18

D9h 59h CONT19

DAL[7] DAL[6] DAL[5] DAL[4] DAL[3] DAL[2] DAL[1] DAL[0]

VOL VOL VOL VOL VOL VOL VOL VOL

DAR[7] DAR[6] DAR[5] DAR[4] DAR[3] DAR[2] DAR[1] DAR[0]

18h

Refer to “2. DAC digital volume”.

CONT1A: ADC/DAC MUTE, ADRC and Zero-cross Settings

W

R

Name

D7

D6

D5

D4

D3

D2

D1

D0

Default

AD

AD2

DA

DAh 5Ah CONT1A

1

ADRCRE ADRCLE MICRZCE MICLZCE 00h

MUTE MUTE MUTE

D7: ADMUTE ADC MUTE Setting

0: Stereo ADC MUTE Release (default)

1: Stereo ADC MUTE

D6: ADMMUTE ADC2 MUTE Setting

0: ADC2 MUTE Release (default)

1: ADC2 MUTE

D5: DAMUTE DAC MUTE Setting

0: DAC MUTE Release (default)

1: DAC MUTE

D4: 1

Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F: D3) = “0” and

DSPRESETN bit (CONT0F: D2) = “0”).

D3: ADRCRE Analog Dynamic Range Controller Rch Enable Setting

0: ADRC Rch DISABLE (default)

1: ADRC Rch ENABLE

D2: ADRCLE Analog Dynamic Range Controller Lch Enable Setting

0: ADRC Lch DISABLE (default)

1: ADRC Lch ENABLE

D1: MICRZCE MICGAIN Rch Zero-corss Enable

0: Rch Zero-cross Detection ON (default)

1: Rch Zero-cross Detection OFF

D0: MICLZCE MICGAIN Lch Zero-cross Enable

0: Lch Zero-cross Detection ON (default)

1: Lch Zero-cross Detection OFF

Write “0” into the “0” registers.

014006643-E-00

2014/10

- 49 -

[AK7755]

CONT1B: Microphone Gain Read Register when using ADRC

W

-

R

Name

D7

D6

D5

D4

D3

D2

D1

D0

Default

00h

AMGNR AMGNR AMGNR AMGNR AMGNL AMGNL AMGNL AMGNL

[3] [2] [1] [0] [3] [2] [1] [0]

5Bh CONT1B

This register is a read only register.

AMGNR[3:0] bits will be valid when ADRCRE bit (CONT1A: D3) = “1”, and AMGNL[3:0] will be valid

when ADRCLE bit (CONT1A: D2) = “1”. The microphone gain value set by DSP can be readout.

CONT1C: TEST Setting

W

R

Name

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Default

00h

DCh 5Ch CONT1C

Write “0” into the “0” registers.

CONT1D: ADC2 Rch Digital Volume Setting

W

R

Name

D7

VOL

D6

VOL

D5

VOL

D4

VOL

D3

VOL

D2

VOL

D1

VOL

D0

VOL

Default

30h

DDh 5Dh CONT1D

AD2R[7] AD2R[6] AD2R[5] AD2R[4] AD2R[3] AD2R[2] AD2R[1] AD2R[0]

Refer to “2-3. ADC2 Digital Volume”.

CONT1E: Digital Microphone Interface Setting

W

R

Name

D7

D6

D5

D4

D3

D2

D1 D0 Default

DDh 5Dh CONT1D DMIC1 DMCLKP1 DMCLKE1 DMIC2 DMCLKP2 DMCLKE2 0

0

00h

D7: DMIC1 Digital Microphone 1 Select

0: Not Using DMIC1 (default)

1: Using DMIC1

When DMIC1 bit = “1” or DMIC2 bit = “1”, pin number 31~ 34 become digital microphone interfaces,

and analog inputs are not available.

D6: DMCLKP1 Digital Microphone 1 Channel Setting

DMCLKP1

DMCLK1 pin = “H”

DMCLK1 pin = “L”

0

1

Rch

Lch

Rch

(default)

D5: DMCLKE1 Digital Microphone 1 Clock Setting

0: DMCLK1 pin = “L” (default)

1: DMCLK1 64fs (Output Enable)

・D4: DMIC2 Digital Microphone 2 Select

0: Not Using DMIC2 (default)

1: Using DMIC2

When DMIC1 bit = “1” or DMIC2 bit = “1”, pin number 31 ~ 34 become digital microphone

interfaces, and analog inputs are not available.

・D3: DMCLKP2 Digital Microphone 2 Channel Setting

DMCLKP2

DMCLK2 pin = “H”

DMCLK2 pin = “L”

0

1

Rch

Lch

Rch

(default)

・D2: DMCLKE2 Digital Microphone 2 Clock Setting

0: DMCLK2 pin = “L” (default)

1: DMCLK1 64fs (Output Enable)

014006643-E-00

2014/10

- 50 -

[AK7755]

Do not write data into CONT21 - CONT25.

CONT26

W

R

Name

D7 D6 D5 D4 D3 D2 D1 D0 Default

00h

E6 66h CONT26 0

0

1

D0: 1

Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F: D3) = “0” and

DSPRESETN bit (CONT0F: D2) = “0”).

Write “0” into the “0” registers.

Do not write data into CONT27 - CONT29.

CONT2A

W

R

Name

D7 D6 D5 D4 D3 D2 D1 D0 Default

00h

EA 6Ah CONT2A 1

0

D7: 1

Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F: D3) = “0” and

DSPRESETN bit (CONT0F: D2) = “0”).

Write “0” into the “0” registers.

Do not write data into CONT2B – CONT2F.

014006643-E-00

2014/10

- 51 -

[AK7755]

■ Power-up Sequence

1. When not downloading settings and programs from EEPROM

The AK7755 should be powered up when the PDN pin = “L”. AVDD and TVDD must be powered up first

before DVDD when DVDD is supplied externally (LDOE pin = “L”). In this case, the power-up sequence

between AVDD and TVDD is not critical. Control register settings are initialized by the PDN pin = “L”.

Set the PDN pin to “H” to start the power supply circuits for REF (analog reference voltage source)

generator and digital circuits (only when LDOE pin = “H”) after all power supplies are fed. Control register

access must be made after 1ms from the PDN pin = “H”. Set AINE bit (CONT00: D3) to “1” fist when

using the IN1/INP1, IN2/INN1, IN3/INP2 and IN4/INN2 pins as analog inputs.

The PLL starts operation by a clock reset release (CKRESETN bit (CONT01: D0) = “0” → “1”) and

generates the internal master clock after setting control registers. Therefore, necessary system clock must be

input and control register settings for CONT00 ~ CONT01 are must be finished before releasing the clock

reset.

Interfacing with the AK7755 except control register settings should be made when PLL oscillation is

stabilized after clock reset release (take a 10ms interval or confirm “H” level output of PLLLOCK signal

from the STO/RDY pin) (Figure 24). However, DSP program and coefficient data can be written even

when the system clock is stopped. DSP programs and coefficient data can be written in 1ms by setting

DLRDY bit =“0” → “1” (CONT0F, D0). DLRDY bit (CONT0F: D0) must be set to “0” after the download

(Figure 25).

When using a crystal oscillator in master mode, set the CKM[2:0] bits (CONT00: D6-D4) = 0h or 1h, and

release the clock reset after crystal oscillation is stabilized. The stabilizing time of crystal oscillation is

dependent on the crystal and external circuits.

The system clock must not be stopped except during the clock reset and power-down mode.

TVDD,AVDD

DVDD

PDN (pin)

CONT Reg. Setting

SI(SPI),SDA(I2C)

DSP Program

CKRESETN bit (Reg.)

DSPRESETN bit(Reg.)

CRESETN bit(Reg.)

XTI,BICK (pin)

Clock Stabilizataion

Internal PLLCLK

(Internal Master Clock)

600ns(min) 1ms(min)

Before PLL stable oscillation

access is not permitted

(10ms)

Command code and DSP

Program download

Power OFF

（No time limitation）

Figure 24. Power-up Sequence 1 (When not downloading from EEPROM)

(With External Power Supply (LDOE pin = “L”), No downloading from EEPROM)

014006643-E-00

2014/10

- 52 -

[AK7755]

TVDD, AVDD

DVDD

PDN(Pin)

SI(spi), SDA(i2c)

DLRDY=1

DLRDY=0

DSP Program

CONT Reg.Setting

CKRESETN bit (Reg.)

DSPRESETN bit(Reg)

CRESETN bit(Reg)

XTI,BICK(Pin)

Clock Stabilization

Internal PLLCLK

(Internal Master Clock)

Before PLL stable oscillation

access is not permitted

(10ms)

Power OFF

600ns(min) 1ms(min)

1ms(min)

Figure 25. Power-up Sequence 2

(With External Power Supply (LDOE pin = “L”), DLRDY Setting, No downloading from EEPROM)

2. When downloading settings and programs from EEPROM

When downloading programs from an EEPROM, I²C interface (I2CSEL pin = “H”) and a 12.288MHz

clock input to the XTI pin are necessary, or a 12.288MHz crystal oscillator must be connected to the XTI

and XTO pins. In this case, only CKM mode 0 and 2 (CONT00: D6-D4) are available. The AK7755 should

be powered up when the PDN pin = “L”. AVDD and TVDD must be powered up first before DVDD when

DVDD is supplied externally (LDOE pin = “L”). In this case, the power-up sequence between AVDD and

TVDD is not critical. Set the PDN pin to “H” to start the power supply circuits for REF (analog reference

voltage source) generator and internal digital circuit (only when the LDOE pin = “H”) after all power

supplies are fed. There are three ways to start downloading control register settings, DSP programs and

Coefficient RAM: by PDN pin (1) (Figure 26), by EXTEEP pin (2) (Figure 26) and by DLS bit (3) (Figure

27).

014006643-E-00

2014/10

- 53 -

[AK7755]

TVDD, AVDD

DVDD

PDN(pin)

(1)

XTI(pin)

Clock Stabilization(12.288MHz)

I2CSEL(pin)

EXTEEP(pin)

(2)

SDA(pin) ^{(EEPROM→AK7755)}

EEST(pin)

CONT Reg. Setting, DSP Program

Success

Error

STO(pin)

CKRESETN bit (Reg.)

DSPRESETN bit(Reg.)

CRESETN bit(Reg.)

Power OFF

600ns(min) 1ms(min)

Figure 26. Power-up Sequence 3

(With External Power Supply (LDOE pin = “L”), Downloading from EEPROM (1)(2))

(1) Start Downloading by PDN pin

Power ON (AVDD, TVDD), I2CSEL pin=“H”, EXTEEP pin=“H”→ (DVDD→), PDN pin=“L”→“H”

(2) Start Downloading EXTEEP pin (Dotted Line)

Power ON (AVDD, TVDD), I2CSEL pin = “H” → (DVDD→), PDN pin = “L” → “H”

→ EXTEEP pin = “L” → “H”

TVDD, AVDD

DVDD

PDN(pin)

(1)

XTI(pin)

Clock Stabilization(12.288MHz)

(3)

I2CSEL(pin)

DLS bit

(uP→AK7755)

(EEPROM→AK7755)

SDA(pin)

DLS=1

CONT Reg. Setting, DSP Program

EEST(pin)

Success

Error

STO(pin)

CKRESETN bit (Reg.)

DSPRESETN bit(Reg.)

CRESETN bit(Reg.)

Power OFF

600ns(min) 1ms(min)

Figure 27. Power-up Sequence 4

(With External Power Supply (LDOE pin = “L”), Downloading from EEPROM (3))

(3) Start Downloading DLS bit

Power ON (AVDD, TVDD), I2CSEL pin=“H”→(DVDD→), PDN pin=“L”→“H” →DLS bit = “0”→“1”

014006643-E-00

2014/10

- 54 -

[AK7755]

■ LDO (Internal Circuit Drive Regulator)

The AK7755 has a regulator for driving internal digital circuits (LDO). When using the LDO, the LDOE

pin must be fixed to “H” and connect a 1μF (±30%) capacitor between the AVDRV pin and the VSS pin.

The LDO starts operation by releasing power-down mode, and control register write/read can be made 1ms

after the power-down release.

The AK7755 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by a

short of the AVDRV pin to VSS and etc., and an overvoltage protection circuit to protect from exceeded

voltage when the voltage to the AVDRV pin gets too high. When these protection circuits perform, internal

circuits are powered down and the STO pin outputs “L”. The internal circuit will not return to a normal

operation until being reset by the PDN pin after removing the problems.

TVDD,AVDD

LDOE (pin)

AVDRV (pin)

PDN (pin)

STO (pin)

CONT Reg. Setting

SI(SPI),SDA(I2C)

DSP Program

CKRESETN bit (Reg.)

DSPRESETN bit(Reg.)

CRESETN bit(Reg.)

XTI,BICK (pin)

Clock Stabilization

Internal PLLCLK

(Internal Master Clock)

Power OFF

600ns(min) 1ms(min)

Before PLL stable oscillation

access is not permitted

(10ms)

Command code and DSP

Program download

（No time limitation）

Figure 28. Power-up Sequence 5

(With LDO (LDOE pin = “H”), No downloading from EEPROM)

■ Power-down Sequence

The AK7755 should be powered down when the PDN pin = “L”. Stop external clocks during this

power-down state and then OFF the power supplies. Do not input external clocks when the power supplies

are off (a current will flow through protection diodes). AVDD and TVDD must be powered down after

DVDD when DVDD is supplied externally (LDOE pin = “L”). In this case, the power-down sequence

between AVDD and TVDD is not critical.

TVDD,AVDD

DVDD

PDN(pin)

Power OFF

Figure 29. Power-down Sequence

014006643-E-00

2014/10

- 55 -

[AK7755]

■ Power-down and Reset

1. Power-down, Reset and Power Management of the AK7755

The AK7755 has four types of power-down and reset functions that are power-down (PDN pin), Clock

reset (CLKRESETN bit (CONT01:D0)), CODEC reset (CRESETN bit(CONT0F:D3)) and DSP reset

(DSPRESETN bit(CONT0F:D2)). Each block can be powered-down by power management registers.

2. Power-down

The AK7755 is powered down by setting the PDN pin = “L”. The PDN pin must be set to “L” when

power up the AK7755. The statuses of output pins in power-down mode are shown below.

LDOE pin = “L” (External 1.2V supply mode)

Power-down Mode Status

No

1

6

7

8

9

10

11

14

15

16

Pin Name

I/O Power-down Mode Status No

Pin Name

SO/SDA

SCLK/SCL

OUT3

I/O

O

I/O

I

I/O

I

VCOM

STO/RDY

LRCK

BICK

CLKO

O

L

H

L

H

L

17

18

26

27

28

31

32

33

34

Hi-Z

I/O

O

I

OUT2

OUT1

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

XTO

XTI

JX2/SDOUT3/JX2/MAT1

I/O

O

SDOUT2/JX3/MAT1

SDOUT1

Note 44. [I/O] indicates Input / Output attribute of each pin.

LDOE pin = “H” (LDO mode)

Power-down Mode Status

I/O

No

1

6

7

8

Pin Name

VCOM

STO/RDY

LRCK

BICK

CLKO

XTO

I/O

O

I/O

O

I

I/O

O

No

17

18

24

26

27

28

31

32

33

34

Pin Name

SO/SDA

SCLK/SCL

AVDRV

L

H

L

I/O

O

Hi-Z

L

OUT3

OUT2

OUT1

O

I/O

I

Hi-Z

9

10

11

14

15

16

IN4/INN2/DMCLK2

IN3/INP2/DMDAT2

IN2/INN1/DMCLK1

IN1/INP1/DMDAT1

XTI

JX2/SDOUT3/JX2/MAT1

SDOUT2/JX3/MAT1

I/O

I

SDOUT1

3. Power-down Release

3-1. LDOE = “L” (External 1.2V supply mode)

DVDD, TVDD and AVDD should be supplied when the PDN pin = “L”. By bringing the PDN pin “H”

600ns (min) after all power supplies are fed (DVDD, TVDD and AVDD), REF voltage circuit (Analog

reference voltage) starts operation. Control register write / read should be made 1ms after bringing the

PDN pin = “H” (Figure 24). AVDD and TVDD must be powered up first before DVDD. In this case,

the power-up sequence between AVDD and TVDD is not critical.

3-2. LDOE = “H” (LDO mode)

TVDD and AVDD should be supplied when the PDN pin = “L”. By bringing the PDN pin “H” 600ns

(min) after TVDD and AVDD are fed, the power supply circuits for REF generator and internal digital

circuit start operation. Control register write / read should be made 1ms after bringing the PDN pin =

“H” (Figure 28).

014006643-E-00

2014/10

- 56 -

[AK7755]

4. Clock Reset

Clock reset is defined as when CKRESERN bit (CONT01: D0) = “0” after power-down release (PDN

pin = “H”). The AK7755 is in the clock reset state after releasing power-down. At this time, all internal

blocks of the AK7755, except the REF circuit and the power supply circuit for digital block, are in

power-down mode. Even the PLL for internal master clock generation is not in operation.

Control register write/read should be made 1ms (min.) after power-down release. Clock generating

control registers (CONT00 ~ CONT01) must be set during clock reset. AINE bit (CONT00: D3) should

be set to “1” first when using the IN1/INP1, IN2/INN1, IN3/INP2 and IN4/INN2 pins as analog inputs.

DSP program and coefficient RAM data writing to the DSP become available in 1ms by setting

DLRDY bit (CONT0F: D0) = “0” → “1” during clock reset (CKRESETN bit = “0”). DLRDY bit must

be set to “0” when finishing downloading. Necessary system clock (XTI@CKM mode0-2 or

BICK@CKM mode 3, 5(CONT00: D6-D4)) must be input before releasing the clock reset (Figure 16).

The PLL for internal master clock starts operation and generating master clock when the clock reset

state is released (CKRESETN bit = “1”). Do not send DSP programs, coefficient data or a command

code for system reset release from a microcontroller to the AK7755 until the PLL oscillation is

stabilized (for 10ms or during Low output period of the PLLLOCK signal from the STO pin).

System clocks must be changed during a clock reset or in power-down mode (PDN pin = “L”). The

AK7755 enters clock reset state by setting CKRESETN bit to “0” after system reset. The PLL and the

internal clock are stopped by this clock reset and the clock change can be done safely. Change register

settings and system clock frequencies during the clock reset. After a system clock is stabilized, the PLL

starts operation by setting CKRESETN bit to “1”.

CKM mode0

CKM mode3

XTI

BICK

CSN

SCLK (Simplified)

SI

0xCF 0x00

0xC1 0x00

0xC0 0x3x

0xC1 0x01

0xCF 0x0C

CRESETN / DSPRESETN

CKRESETN

PLL Stable

Oscillation

Input Clock Changeable Period

Command Code &

DSP Program Transmitting Period

Figure 30. Clock Reset Sequence (e.g. CKM mode0 → CKM mode 3)

014006643-E-00

2014/10

- 57 -

[AK7755]

5. System Reset

System reset is defined as when CRESETN bit (CONT0F: D3) = “0” and DSPRESETN bit (CONT0F:

D2) = “0” after clock reset is released (CKRESETN bit (CONT01: D0) = “1”). PRAM and CRAM

downloading should be executed in this state. PRAM and CRAM accessing of the AK7755 should be

made when PLL oscillation is stabilized after clock reset release (take a 10ms interval or confirm “H”

level output of PLLLOCK signal from the STO pin).

System reset is released when either CODEC reset (CRESETN bit) or DSP reset (DSPRESETN bit) is

released (“0” → “1”) after DSP programs and coefficient data are transmitted. Then the AK7755 starts

generating necessary clocks for ADC, DAC and DSP operations. A system reset image is shown below.

CRESETN bit

SRESETN

DSPRESETN bit

Figure 31. System Reset Structure

In slave mode, the AK7755 starts operation in synchronization of an LRCK rising edge (falling edge in

I²S mode) when system reset is released. If the LRCK is stopped or the LRCK phase is shifted more

than 1/4fs, the AK7755 becomes the system reset state automatically. In this case, the system reset state

is released if the LRCK is input again.

■ RAM Clear

The AK7755 has a RAM clear function. After system reset release (during RUN), data RAM and delay

RAM are cleared by “0” (RAM clear). The internal PLL must have a stable oscillation before system

reset release. The required time to clear RAM is 400µs.

In the RAM clear sequence, it is possible to send commands to the DSP. (DSP is stopped during RAM

clear sequence. The sent command is accepted automatically after this sequence is completed.)

PDN (pin)

DSPRESETN bit

RAM Clear

DSP Start

RAM Clear Period

DSP Program

Operation Start

Figure 32. RAM Clear Sequence

014006643-E-00

2014/10

- 58 -

[AK7755]

■ Serial Data Interface

Serial audio data pins; the SDIN1, SDIN2, SDOUT1, SDOUT2 and SDOUT3 pins are interfaced with

an external system by LRCK and BICK. Control register settings are needed to use these interfaces

(Refer to ■ Block Diagram (Figure 1) and Control register setting).

The data format is 2's compliment MSB first. I/O format supports MSB justified, LSB justified, I²S

compatible and PCM format. (In I²S compatible/PCM mode, all audio data input and output pins are in

I²S compatible/PCM format, respectively.)

The input (SDIN1 and SDIN2) format is 24-bit MSB justified at default. 24-bit/20-bit/16-bit LSB

justified, I²S and PCM formats are also selectable by control register DIF[1:0] bits. The output

(SDOUT1, ADOUT2 and SDOUT3) format is 24-bit MSB justified at default. 24-bit/20-bit/16-bit LSB

justified, I²S and PCM formats are selectable by setting DOF[1:0] bits. The SDOUT1 also supports 8-bit

MSB justified μ-Law and 8-bit MSB justifid A-Law formats. The output data of the ADC (SDOUTAD

and SDOUTAD2) is fixed to 24-bit MSB justified.

DIFDIF2, DIFDA[1:0]

DIF1[2:0]

mode LRIF[1:0]

or

DOF2, 3, 4[1:0]

000h

or

BITFS[1:0] Format

DOF1[2:0]

MSB 24-bit 64fs

0

1

2

3

4

5

6

7

8

0h

1h

2h

3h

4h

5h

0h

0h/1h

0h/1h/2h

0h

000h

0h

LSB 24-bit 64fs/48fs

LSB 20-bit 64fs/48fs

LSB 16-bit 64fs/48fs/32fs

MSB 8-bit μ-Law

011h

102h

113h

N/A

000h

MSB 8-bit A-Law

0h

I²S Compatible

011h

102h

113h

PCM Short Frame 64fs/256fs

PCM Long Frame 64fs/256fs

0h/3h

Serial Data Format Examples

1. MSB justified (mode 0)

LRCK

Left ch

Right ch

BICK

31 30 29 28 27

10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27

10 9 8 7 6 5 4 3 2 1 0

M: MSB, L: LSB

SDIN1, 2

DIF Mode 0

M 22 2120 19

2

1 L

M 22 21 20 19

2

1 L

SDOUT1, 2, 3

DOF Mode 0

M: MSB, L: LSB

M 22 2120 19

2

1 L

Figure 33. MSB Justified BICK 64fs

014006643-E-00

2014/10

- 59 -

[AK7755]

2. LSB justified (mode1, 2, 3)

LRCK

Left ch

Right ch

BICK

31 30

23 22 21 20 19 18 17 16 15 14

1 0 31 30

23 22 21 20 19 18 17 16 15 14

1 0

1 L

SDIN1, 2

DIF Mode 1

Don’t care M 22 21 20 19 18 17 16 15 14

1 L Don’t care M 22 21 20 19 18 17 16 15 14

SDIN1, 2

DIF Mode 2

Don’t care

M 18 17 16 15 14

M 14

1 L Don’t care

M 18 17 16 15 14

1 L

SDIN1, 2

DIF Mode 3

M 14

M: MSB, L: LSB

SDOUT1, 2, 3

DOF Mode 1

MSB

22 21 20 19 18 17 16 15 14

1 L

MSB

22 21 20 19 18 17 16 15 14

1 L

SDOUT1, 2, 3

DOF Mode 2

18 17 16 15 14

14

18 17 16 15 14

14

SDOUT1, 2, 3

DOF Mode 3

Figure 34. LSB Justified BICK 64fs

LRCK

BICK

Left ch

Right ch

23 22 21 20 19 18 17 16 15 14 13 12 11 10

M 22 21 20 19 18 17 16 15 14 13 12 11 10

L

1 0

23 22 21 20 19 18 17 16 15 14 13 12 11 10

M 22 21 20 19 18 17 16 15 14 13 12 11 10

1 0

SDIN1,2

DIF mode1

1

L

1

SDIN1,2

DIF mode2

Don’t care M 18 17 16 15 14 13 12 11 10

1

L Don’t care M 18 17 16 15 14 13 12 11 10

1

L

SDIN1,2

DIF mode3

Don’t care

M 14 13 12 11 10

L Don’t care

M 14 13 12 11 10

M:MSB,L:LSB

SDOUT1,2,3

DOF mode1

M 22 21 20 19 18 17 16 15 14 13 12 11 10

L

1

L

M 22 21 20 19 18 17 16 15 14 13 12 11 10

1

SDOUT1,2,3

DOF mode2

MSB

18 17 16 15 14 13 12 11 10

14 13 12 11 10

L MSB

18 17 16 15 14 13 12 11 10

14 13 12 11 10

SDOUT1,2,3

DOF mode3

Figure 35. LSB Justified BICK 48fs

014006643-E-00

2014/10

- 60 -

[AK7755]

LRCK

BICK

Left ch

Right ch

1

0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

15 14 13 12 11 10 9 8 7 6 5 4 3

2

0

L

SDIN1,2

DIF mode3

M 14 13 12 11 10 9 8 7

6

5 4 3 2 1 L

M 14 13 12 11 10 9 8 7

6

5 4 3 2

1

SDOUT1,2,3

DOF mode3

L

M 14 13 12 11 10 9 8 7 6 5 4 3 2

1

L

M 14 13 12 11 10 9 8 7 6 5 4 3 2

Figure 36. LSB Justified BICK 32fs

3. MSB 8-bit μ-Law、MSB 8-bit A-Law (mode 4,5)

LRCK

BICK

Left ch

Right ch

31 30 29 28 27 26 25 24

M 6 5 4 3 2 1 L

7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24

7 6 5 4 3 2 1 0

SDIN1

DIF mode4/5

M:MSB,L:LSB

M 6 5 4 3 2 1 L

M 22 21 20 19 18 17 16

SDOUT1

DOF mode4/5

M:MSB,L:LSB

M 6 5 4 3 2 1 L

M 22 2120 19 18 17 16

SDIN2

DIF mode0

M:MSB,L:LSB

1 L

SDOUT2,3

M:MSB,L:LSB

1 L

DOF mode0

Figure 37. MSB Justified 8-bit μ-Law, 8-bit A-Law BICK 64fs

4. I²S (mode6)

LRCK

BICK

Left ch

Right ch

31 30 29 28 27

M 22 21 20

10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27

10 9 8 7 6 5 4 3 2 1 0

M: MSB, L: LSB

SDIN1, 2

3 2 1 L

M 22 21 20

3 2 1 L

M: MSB, L: LSB

SDOUT1, 2, 3

M 22 21 20

3 2 1 L

Figure 38. I²S BICK 64fs

014006643-E-00

2014/10

- 61 -

[AK7755]

5. PCM Short Frame (mode7)

tBCLK

LRCK

SF

BICK

63 62 61 60 59

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

10 9 8 7 6 5 4 3 2 1

0

SDIN1, 2

M 22 21 20 19

2

1 L

M 22 21 20 19

2

1 L

SDOUT1, 2, 3

M: MSB, L: LSB

M 22 21 20 19

Right ch

Left ch

Figure 39. 64fs PCM Short Frame

tBCLK

LRCK

SF

BICK

255 254 253 252 251

234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219

202 201 200 199 198

3 2 1 0

SDIN1,2

M 22 21 20 19

2 1 L

M 22 21 20 19

2 1 L

SDOUT1,2,3

M:MSB,L:LSB

M 22 21 20 19

2 1 L

Left ch

Right ch

tBCLK × 32

tBCLK × 256

Figure 40. PCM Short Frame 256fs

6. PCM Long Frame (mode8)

tBCLK ≤ t ≤ ts-tBCLK

LRCK

BICK

LF

63 62 61 60 59

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

10 9 8 7 6 5 4 3 2 1

0

SDIN1, 2

tBCLK

M 22 21 20 19

2

1 L

M 22 21 20 19

2

1 L

SDOUT1, 2, 3

M: MSB, L: LSB

M 22 21 20 19

2

1 L

Left ch

tBCLK × 32

Right ch

tBCLK × 32

Figure 41. 64fs PCM Long Frame

014006643-E-00

2014/10

- 62 -

[AK7755]

LRCK

BICK

LF

255 254 253 252 251

234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219

202 201 200 199 198

4 3 2 1 0

SDIN1, 2

tBCLK

M:MSB,L:LSB

M 22 21 20 19

2 1 L

M 22 21 20 19

2 1 L

SDOUT1, 2, 3

M 22 21 20 19

2 1 L

Left ch

Right ch

tBCLK × 32

tBCLK × 256

Figure 42. PCM Long Frame 256fs

7. TDM Mode

TDM interface formats shown below are available by setting TDM256 bit = “1”. BITFS[1:0] bits should

be set to 3h since BICK is fixed to 256fs.

Mode LRIF[1:0] TDMMODE[1:0]

Format

Note

0

1

2

3

4

5

6

7

8

0h

1h

2h

3h

0h

1h

2h

0h

1h

2h

0h

1h

2h

0h

1h

2h

MSB 24-bit

SLOT7 and 8 Inputs Not Available

SLOT5, 6, 7 and 8 Inputs Not Available

I²S Compatible

PCM Short Frame

SLOT7 and 8 Inputs Not Available

SLOT5, 6, 7 and 8 Inputs Not Available

PCM Short Frame SLOT7 and 8 Inputs Not Available

PCM Short Frame SLOT5, 6, 7 and 8 Inputs Not Available

PCM Long Frame

PCM Long Frame SLOT7 and 8 Inputs Not Available

PCM Long Frame SLOT5, 6, 7 and 8 Inputs Not Available

9

10

11

014006643-E-00

2014/10

- 63 -

[AK7755]

256BICK

LRCK(master)

LRCK(slave)

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT8

BICK(256fs)

32 BICK

23

22

0

23 22

0

23

22

0

23 22

0

23

22

0

23 22

0

23

22

0

23 22

0

SDOUT1

DOUT1L

DOUT1R

DOUT2L

DOUT2R

DOUT3L

DOUT3R

DOUT4L

DOUT4R

SDIN1(TDM mode0) 23

23 22

22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23

22

0

23 22

0

DIN1R

DIN2R

DIN3L

DIN3R

DIN4L

DIN4R

DIN1L

DIN2L

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

SDIN1(TDM mode1)

SDIN1(TDM mode2)

SDOUTAD

Rch

SDOUTAD

Lch

DIN3R

DIN1L

DIN1R

DIN2L

DIN2R

DIN3L

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

22

0

23

SDOUTAD2

Lch

SDOUTAD

Rch

SDOUTAD2

Rch

SDOUTAD

Lch

DIN1R

DIN2R

DIN1L

DIN2L

(don’t care)

SDIN2

Figure 43. TDM mode MSB Justified 24-bit (Internal signals are indicated by dotted lines)

256BICK

LRCK(master)

LRCK(slave)

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT8

BICK(256fs)

32 BICK

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDOUT1

DOUT1L

DOUT1R

DOUT2L

DOUT2R

DOUT3L

DOUT3R

DOUT4L

DOUT4R

SDIN1(TDM mode3)

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

DIN1R

DIN2R

DIN3L

DIN3R

DIN4L

DIN4R

DIN1L

DIN2L

SDIN1(TDM mode4)

SDIN1(TDM mode5)

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDOUTAD

Rch

SDOUTAD

Lch

DIN1R

DIN2R

DIN3L

DIN3R

DIN1L

DIN2L

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDOUTAD2 SDOUTAD2

Lch Rch

SDOUTAD

Rch

SDOUTAD

Lch

DIN1R

DIN2R

DIN1L

DIN2L

(don’t care)

SDIN2

Figure 44. TDM mode I²S Compatible (Internal signals are indicated by dotted lines)

014006643-E-00

2014/10

- 64 -

[AK7755]

256BICK

LRCK

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT8

BICK(256fs)

32 BICK

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDOUT1

DOUT1L

DOUT1R

DOUT2L

DOUT2R

DOUT3L

DOUT3R

DOUT4L

DOUT4R

SDIN1(TDM mode6)

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

DIN1R

DIN2R

DIN3L

DIN3R

DIN4L

DIN4R

DIN1L

DIN2L

SDIN1(TDM mode7)

SDIN1(TDM mode8)

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDOUTAD

Rch

SDOUTAD

Lch

DIN1R

DIN2R

DIN3L

DIN3R

DIN1L

DIN2L

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDOUTAD2 SDOUTAD2

Lch Rch

SDOUTAD

Rch

SDOUTAD

Lch

DIN1R

DIN2R

DIN1L

DIN2L

(don’t care)

SDIN2

Figure 45. TDM mode PCM Short Frame (Internal signals are indicated by dotted lines)

256BICK

LRCK

SLOT5

SLOT6

SLOT7

SLOT8

SLOT1

SLOT2

SLOT3

SLOT4

BICK(256fs)

32 BICK

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

SDOUT1

DOUT1L

DOUT1R

DOUT2L

DOUT2R

DOUT3L

DOUT3R

DOUT4L

DOUT4R

SDIN1(TDM mode9) 23

22

0

23 22

0

23

23 22

22

0

23 22

0

23

22

0

23 22

0

23

22

0

23 22

0

DIN1R

DIN2R

DIN3L

DIN3R

DIN4L

DIN4R

DIN1L

DIN2L

23 22

0

23 22

0

22

0

23 22

0

23

22

0

23 22

0

22

0

SDIN1(TDM mode10)

23 22

0

SDOUTAD

Rch

SDOUTAD

Lch

DIN3R

DIN1R

DIN2R

DIN3L

DIN1L

DIN2L

SDIN1(TDM mode11)

23 22

0

23

23 22

0

23

22

23

0

23 22

0

22

0

23 22

0

23

22

0

22

0

SDOUTAD2

Lch

SDOUTAD

Rch

SDOUTAD2

Rch

SDOUTAD

Lch

DIN1R

DIN2R

DIN1L

(don’t care)

DIN2L

SDIN2

Figure 46. TDM mode PCM Long Frame (Internal signals are indicated by dotted lines)

014006643-E-00

2014/10

- 65 -

[AK7755]

■ μP Interface Setting and Pin Status

SPI or I²C bus interface mode can be selected by the I2CSEL pin. Pin statuses that are changed by I2CSEL

pin setting are shown below.

I2CSEL

L

PDN

L

SO/SDA

SCLK/SCL

Input

Hi-Z (CSN pin = “H”)

function(CSN pin = “L”)

“Hi-Z”→ pull-up

function

SPI Interface

I²C BUS

L

H

Input

H

L

H

“Hi-Z”→ pull-up

function

Note 45. The CSN pin must be set to “H” when not interfacing to a micro controller or the AK7755 is in

power-down mode in SPI interface mode.

■ SPI Interface (I2CSEL pin = “L”)

1. Configuration

The access format is: Command code (8bits) + Address + Data (MSB First).

Bit Length

Command Code

8

MSB bit is R/W flag. The following 7-bits indicate access area such

as PRAM/ CRAM/Registers.

Address

16 or 0

Valid only for those cases where accessed areas have addresses such

as PRAM /CRAM/OFREG. When no address is assigned, there is no

data.

Data

Later Section Write or Read data

SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.

Write operation

CSN

SCLK

SI

don’tcare

(L/H)

X (L/H)

Data (write)

Command Code (8bit)

Address (16bit or 0bit)

Hi-Z

Low

Hi-Z

Low

SO

Echo Back

Figure 47. SPI Interface Write

Read operation

CSN

SCLK

SI

don’tcare

(L/H)

X (L/H)

Command Code (8bit)

Address (16bit or 0bit)

Echo Back

Hi-Z

Low

Hi-Z

Low

SO

Data (read)

Figure 48. SPI Interface Read

014006643-E-00

2014/10

- 66 -

[AK7755]

2. Command Code

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

R/W flag

Area to be accessed

Accompanying data to the access area

R/W Flag: Write at “1”, Read at “0”.

Access data and accompanying data

BIT6 BIT5 BIT4 BIT3~0

0

1

0

1

0

Number of Write

0100

Write preparation to CRAM during RUN

Write preparation to OFREG during RUN

Write operation to CRAM during RUN

Write operation to OFREG during RUN

0010

0

1

1000

0100

0010

Write/Read operation to PRAM during system reset

Write/Read operation to CRAM during system reset

Write/Read operation to OFREG during system reset

Write/Read operation to ACRAM (Accelerator

Coefficient RAM) during system reset

Internal control registers 00h~0Fh

Internal control registers 10h~1Fh

Device Identification (Read only)

Internal control registers 26h

1011

1

0

1

0

1

0

Register Address

0000

0110

1010

Internal control registers 2Ah

1

0000

Error Status Read

0010

CRC Write/Read

0100

Write operation of JX code

0110

Read operation from MIR1

1000

Read operation from MIR2

1010

Read operation from MIR3

1100

Read operation from MIR4

3. Address

The address description is always LSB justified. Accessing command code BIT[6:4]= “000” to “011”

requires a 16-bit address. Accessing command code BIT[6:4]= “100” to “111” requires no address.

014006643-E-00

2014/10

- 67 -

[AK7755]

4. Data

The length of write data depends on the write area size. When accessing RAM, data may be written to

sequential address locations by writing data continuously.

Write

Address

Command

Data Length Description

Write preparation to CRAM during RUN.

Command code BIT3~BIT0 bits determines the amount of write

operation. (0x80 # of write: 1, 0x81 # of write: 2, ----, 0x8F # of

write: 16) If the actual amount of write operations exceeds the

defined amount, that data will be ignored.

0x80~0x8F 16bit

0x90~0x9F 16bit

24bit×n

Write preparation to OFREG during RUN

Command code BIT3~BIT0 bits determines the amount of write

operation. (0x90 # of write: 1, 0x91 # of write: 2, ----, 0x9F # of

write: 16) If the actual amount of write operations exceeds the

defined amount, that data will be ignored.

Write operation to OFREG during RUN. 0 address should be

written.

24bit×n

None

0xA2

16bit

0xA4

0xB2

0xB4

0xB8

0xBB

16bit

None

24bit×n

40bit×n

24bit×n

8bit

Write operation to CRAM during RUN. 0 address should be written.

Write operation to OFREG during system reset

Write operation to CRAM during system reset

Write operation to PRAM during system reset

Write operation to ACRAM during system reset

Write operation to Control Registers 00~1Fh

0xC0~0xDF None

0xE6

0xEA

0xF2

0xF4

None

8bit

16bit

8bit

Write operation to Control Register 26h

Write operation to Control Register 2Ah

CRC Write

Write operation of External Conditional Jump Code

Data length is defined by the command code which specifies the area to be accessed. When accessing

RAM, data may be read from sequential address locations by reading data continuously. Writing other

than this command code is prohibited.

014006643-E-00

2014/10

- 68 -

[AK7755]

Read

Command Address Data Length Description

0x24

0x32

0x34

0x38

0x3B

16bit

24bit×n

40bit×n

24bit×n

8bit

CRAM/OFREG Preparation Data Read during RUN

Read operation form OFREG during system reset

Read operation from CRAM during system reset

Read operation from PRAM during system reset

Read operation from ACRAM during system reset

Write operation to Control Registers 00~1Fh

Device Identification

Write operation to Control Register 26h

Write operation to Control Register 2Ah

DSP Error Status Read

CRC result Read

Read operation from MIR1

28-bit is upper-bit justified. Lower 4-bits are for validity flags.

Read operation from MIR2

28-bit is upper-bit justified. Lower 4-bits are for validity flags.

Read operation from MIR3

28-bit is upper-bit justified. Lower 4-bits are for validity flags.

Read operation from MIR4

28-bit is upper-bit justified. Lower 4-bits are for validity flags.

0x40~0x5F None

0x60

0x66

0x6A

0x70

0x72

None

16bit

0x76

0x78

0x7A

0x7C

32bit

None

Reading other than this command code is prohibited.

5. Echo-Back Mode

The AK7755 has an echo-back mode that the device outputs write data sequentially from the SO pin.

5-1. Write Sequence

CSN

don’tcare

(L/H)

COMMAND

ADDRESS1

COMMAND

ADDRESS2

ADDRESS1

DATA1

DATA2

DATA1

COMMAND

ADDRESS1

COMMAND

SI

SO

ADDRESS2

Hi-Z or Low

Figure 49. Echo-Back Writing 1 (SPI)

The input data of the SI pin is echoed back on the SO pin by shifting 8-bit to the right.

CSN

n=3~5

0xB4

0x00

DATA1

DATAn

DATA1

Dummy 8bit

DATAn

SI

SO

X (Hi-Z or low)

X (Hi-Z or Low)

COMMAND

ADDRESS1

ADDRESS2

Figure 50. Echo-Back Writing 2 (SPI)

It is possible to verify the written data by inputting an extra 8-bit clock. If the dummy data is more than

the data length, this dummy data is written on the next address. (40 bits for PRAM, 24 bits for CRAM

and 24 bits for OFREG writings)

014006643-E-00

2014/10

- 69 -

[AK7755]

5-2. Read Sequence1 (with PRAM, CRAM, OFREG addresses)

CSN

don’tcare

(L/H)

COMMAND

ADDRESS1

COMMAND

ADDRESS2

ADDRESS1

COMMAND

ADDRESS1

SI

SO

Hi-Z or Low

READ DATA

COMMAND

Figure 51. Read Sequence1 in Echo-Back Mode (SPI)

Data of the address2 field is not echoed back in read operation. The read data on the SO pin is output

after writing to the address2 field.

5-3. Read Sequence2 (No Register address）

CSN

don’tcare

(L/H)

COMMAND

SI

SO

Hi-Z or Low

READ DATA

Figure 52. Read Sequence2 in Echo Back Mode (SPI)

Data output has priority in read sequence.

6. Format

6-1. Write Operation during System Reset

1. Program RAM (PRAM) Write (during system reset)

Field

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0xB8

0 0 0 0 0 0 0 0

0 0 0 0 D35 D34 D33 D32

D31~D24

(5) DATA2

(6) DATA3

D23~D16

(7) DATA4

D15~D8

(8) DATA5

D7~D0

Five bytes of data may be written continuously for each address.

2. Coefficient RAM (CRAM) Write (during system reset)

Field

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0xB4

0 0 0 0 0 A10 A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

D23~D16

(5) DATA2

D15~D8

(6) DATA3

D7~D0

Three bytes of data may be written continuously for each address.

014006643-E-00

2014/10

- 70 -

[AK7755]

3. Offset REG (OFREG) Write (during system reset)

Field

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

(5) DATA2

(6) DATA3

0xB2

0 0 0 0 0 0 0 0

0 0 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0

0 0 0 D12 D11 D10 D9 D8

D7~D0

Three bytes of data may be written continuously for each address.

4. Accelerator Coefficient RAM (ACRAM) Write (during system reset)

Field

Write data

0xBB

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0

0 0 0 0 A10 A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

D19~D12

(5) DATA2

D11~D4

(6) DATA3

D3~D0 0 0 0 0

Three bytes of data may be written continuously for each address.

6-2. Write Operation during System Reset / RUN

1. Control Register Write (during system reset / RUN)

Field

Write data

(1) COMMAND Code

(2) DATA

0xC0~0xDF, 0xE6, 0xEA

D7~D0

2. External Conditional Jump Code Write (during system reset / RUN)

Field

Write data

(1) COMMAND Code

(2) DATA

0xF4

D7~D0

3. CRC Code Write (during system reset / RUN)

Field

Write data

(1) COMMAND Code

(2) DATA

(3) DATA

0xF2

D15~D8

D7~D0

6-3. Write Operation during RUN

1. Coefficient RAM (CRAM) Write Preparation (during RUN)

Preparation

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0x80~0x8F (one data at 80h, sixteen data at 8Fh)

0 0 0 0 0 A10 A9 A8

A7 ~ A0

D23~D16

(5) DATA2

D15~D8

(6) DATA3

D7~D0

014006643-E-00

2014/10

- 71 -

[AK7755]

2. Coefficient RAM (CRAM) Write Operation (RUN)

Execute

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

0xA4

0 0 0 0 0 0 0 0

Note 46. The COMMAND determines the length of the data. If the written data exceeds the allotted

amount, the excess data is ignored.

3. Offset REG (OFREG) Write Preparation (during RUN)

Preparation

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0x90~0x9F (one data at 0x90, sixteen data at 0x9F)

0 0 0 0 0 0 0 0

0 0 0 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0

(5) DATA2

(6) DATA3

0 0 0 D12 D11 D10 D9 D8

D7~D0

4. Offset REG (OFREG) Write Operation (during RUN)

Execute

Write data

(1) COMMAND Code

(2) ADDRESS1

(3) ADDRESS2

0xA2

0 0 0 0 0 0 0 0

Note 47. The COMMAND determines the length of the data. If the written data exceeds the allotted

amount, the excess data is ignored.

6-4. Read Operation during System Reset

1. Program RAM (PRAM) Read (during system reset)

Field

Write data

Readout data

(1) COMMAND Code 0x38

0 0 0 0 0 0 0 0

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0 0 0 0 D35 D34 D33 D32

D31~D24

(5) DATA2

(6) DATA3

D23~D16

(7) DATA4

D15~D8

(8) DATA5

D7~D0

Five bytes of data may be written continuously for each address.

2. Coefficient RAM (CRAM) Read (during system reset)

Field Write data

(1) COMMAND Code 0x34

Readout data

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

(5) DATA2

(6) DATA3

0 0 0 0 0 A10 A9 A8

A7 ~ A0

D23~D16

D15~D8

D7~D0

Three bytes of data may be written continuously for each address.

014006643-E-00

2014/10

- 72 -

[AK7755]

3. Offset REG (OFREG) Read (during system reset)

Field Write data

(1) COMMAND Code 0x32

Readout data

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0 0 0 0 0 0 0 0

0 0 0 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0

D15~D8

(5) DATA2

(6) DATA3

D7~D0

Three bytes of data may be written continuously for each address.

4. Accelerator Coefficient RAM (CRAM) Read (during system reset)

Field

Write data

Readout data

(1) COMMAND Code 0x3B

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

0 0 0 0 0 A10 A9 A8

A7 ~ A0

D19~D12

(5) DATA2

D11~D4

(6) DATA3

D3~D0 0 0 0 0

Three bytes of data may be written continuously for each address.

6-5. Read Operation during System Rest / RUN

1. Control Register Read (during system reset / RUN)

Field

Write data

Readout data

D7~D0

(1) COMMAND Code 0x40~0x5F, 0x66, 0x6A

(2) DATA

2. Device Identification (during system rest / RUN)

Field

Write data

Readout data

(1) COMMAND Code 0x60

(2) DATA

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

5

1

0

1

0

5

1

3. CRC Result Reading (during system reset / RUN)

Field

Write data

Readout data

(1) COMMAND Code 0x72

(2) DATA1

(3) DATA2

D15~D8

D7~D0

4. DSP Error Status Read (during system reset / RUN)

Field Write data Output

(1) COMMAND Code 0x70

(2) DATA

Active low output

D7: CRCERRN: 0: CRC error

D6: WDTERRN : 0: Watch Dog Timer error

D5: GP0

D4: GP1

D3: PLLLOCK

D2: N/A

0:clear 1: set

0:unlock 1:lock

D1: N/A

D0: N/A

014006643-E-00

2014/10

- 73 -

[AK7755]

6-6. Read Operation during RUN

1. CRAM Write Preparation Read (during RUN)

Field

Write data

Readout data

(1) COMMAND Code 0x24

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

(5) DATA2

(6) DATA3

A15~A8

A8~A0

D23~D16

D15~D8

D7~D0

2. OFREG Write Preparation Read (during RUN)

Field

Write data

Readout data

(1) COMMAND Code 0x24

(2) ADDRESS1

(3) ADDRESS2

(4) DATA1

(5) DATA2

(6) DATA3

A15~A8

A8~A0

0 0 0 0 0 0 0 0

D15~D8

D7~D0

3. MIR1/2/3/4 Read (during RUN)

Field

Write data

Readout data

(1) COMMAND Code 0x76(MIR1)

0x78(MIR2)

0x7A(MIR3)

0x7C(MIR4)

(2) DATA1

D27~D20

(3) DATA2

D19~D12

(4) DATA3

D11~D4

(5) DATA4

D3 D2 D1 D0 (flag3) (flag2) (flag1) (flag0)

Note 48. Data is valid only when all flags are zero.

7. Timing

7-1. RAM Writing Timing during System Reset

Write to Program RAM (PRAM), Coefficient RAM (CRAM), Offset REG (OFREG) and Accelerator

Coefficient RAM (CRAM) during system reset in the order of command code, address and data. The

PRAM start address is fixed to 0h. When writing the data to consecutive address locations, continue to

input data only. PRAM address is incremented by 1 automatically.

DSPRESETN bit

CSN

SCLK

don’t care

(L/H)

don’t care

(L/H)

Command

Address

DATA

SI

RDY = “H”

Figure 53. Writing to RAM at Consecutive Address Locations (SPI)

014006643-E-00

2014/10

- 74 -

[AK7755]

DSPRESETN bit

CSN

SCLK

don’tcare

(L/H)

don’tcare

(L/H)

don’tcare

(L/H)

Command Address DATA

SI

RDY = “H”

Figure 54. Writing to RAM at Random Address Locations (SPI)

7-2. RAM Writing Timing during RUN

These operations are to rewrite the Coefficient RAM (CRAM) and Offset REG (OFREG) during

RUN. Data writing is executed in two steps; write preparation and write execution. The written data

can be confirmed by reading the write preparation data.

1. Write Preparation

After inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the

starting address of write (16 bits all “0”) and the number of data assigned by command code in this

order. In slave mode, a write preparation command is prohibited for “2 LRCK” cycles (2/fs) after

releasing DSP reset (DSPRESETN bit).

2. Write Preparation Data Confirmation

After write preparation, prepared data for writing can be confirmed. Address and Data are read in this

order by write preparation data confirmation command “24h”. The data will be “0x000001” when

reading more than write preparation data. Execute write preparation again when the address and data

are disturbed by external noise.

3. Write Execution

Upon completion of this operation, execute a RAM write during RUN by inputting the corresponding

command code and address (16 bits, all “0”) in this order.

Note 49. Execute write preparation, write preparation read and write execution in this order. When

writing to RAM without a write preparation sequence, a malfunction occurs. Access operation

by a microcontroller is prohibited until RDY changes to “H”.

Write modification of the RAM content is executed whenever the RAM address for modification is

assigned. For example, when 5 data are written, from RAM address “10”, it is executed as shown

below.

RAM execution address

Write execution position

7

8

9

10 11 13 16 11 12 13 14 15

↓

○

↑

○

Note 50. Address “13” is not executed until rewriting address “12”.

014006643-E-00

2014/10

- 75 -

[AK7755]

DSPRESETN bit= “1”

CSN

(Ex.) When # of DATA is 4

CRAM Command Code 0x83

OFREG Command Code 0x93

SCLK

don’tcare

(L/H)

don’tcare

(L/H)

Command

Code

Address DATA0

DATA1

DATAn-1 DATAn

SI

RDY = “H”

CRAM 0x80(# of DATA: 1)~0x8F(# of DATA: 16)

OFREG 0x90(# of DATA: 1)~0x9F(# of DATA: 16)

Figure 55. CRAM/OFREG Write Preparation (SPI)

DSPRESTN bit= “1”

CSN

SCLK

don’t care

(L/H)

don’t care

(L/H)

0x24

SI

Hi-Z or Low

SO

Address

DATA

RDY= “H”

Figure 56. CRAM/OFREG Write Preparation Confirm (SPI)

DSPRESETN bit= “1”

CSN

SCLK

don’tcare

(L/H)

Command

0 0 0 0 0 0 0 0

SI

CRAM0xA4, OFREG0xA2

max 400ns

RDY

RDYLG (Note 52)

Figure 57. CRAM/OFREG Write (SPI)

Note 51. If the DSP program is designed to refer all coefficients which may be changed by an external

microcontroller, RDY signal rises to high within 2LRCK after a writing command. No further

access to DSP is permitted until this write operation is completed. However, while the CSN pin is

“L” level, RDY signal keeps “L” level.

014006643-E-00

2014/10

- 76 -

[AK7755]

7-3. External Conditional Jump

External Conditional Jump Code Writing (during System Reset and RUN)

(1) COMMAND

(2) DATA

0xF4

D7~D0

External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the

designated register on the rising edge of LRCKO. The RDY pin changes to “L” when the command code

is transferred, and it changes to “H” when write operations are completed. When any single bit of “1”

data in 8-bit External Jump code matches an “1” bit data in the IFCON field, a Jump instruction is

executed. Then, the RDY pin changes to “H” when the rise of LRCKO is captured. Access operation by

microcontroller is prohibited until the RDY pin changes to “H”. IFCON field is the area where the

external conditions are written. This Jump code is reset to 00h by setting the IRSTN pin to “L”, but it is

not reset by System Reset.

7

■

6

■

5

■

4

■

↑

3

■

2

■

1

■

0

■

External Conditional Jump Code

Check if “1” of IFCON field corresponds with External Conditional Jump including Jump pins

by at least one at the same location.

7

↓

0

IFCON Field

External Conditional Jump Code



■



■



■



■



■



■



■



■

DSPRESETN bit

SCLK

don’tcare

(L/H)

don’tcare

(L/H)

F4h

D7…D0

SI

CSN

LRCK

RDY

Next command write is available

Figure 58. External Conditional Timing in System Reset (SPI)

DSPRESETN bit

SCLK

SI

don’tcare

(L/H)

don’tcare

(L/H)

F4h

D7 … D0

CSN

LRCK

RDY

Figure 59. External Conditional Jump Timing during RUN (SPI)

014006643-E-00

2014/10

- 77 -

[AK7755]

7-4. RAM Reading Timing during System Reset

Read Program RAM (PRAM), Coefficient RAM (CRAM), Offset REG (OFREG) and Accelerator

Coefficient RAM (ACRAM) during System Reset in the order of the input Command code and the

Address. After writing the Command, the data comes out from the SO pin synchronous with falling

edge of SCLK. (The SI pin input data is “Don’t care”) When reading Data at consecutive address

locations, continue to input SCLK as is.

DSPRESETN bit

CSN

SCLK

don’t care

(L/H)

don’t care

(L/H)

Command

Address

SI

Hi-Z or Low

Echo Back Output

SO

RDY = “H”

DATA

Figure 60. RAM Reading at Consecutive Address (SPI)

7-5. RAM Reading Timing during System Reset and RUN

Write a command code, to read control registers, device identification code, CRC result and error

status during RUN time or system reset state. After completing a Command code write, the data comes

out from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”)

DSPRSTN bit

CSN

SCLK

SI

don’tcare

(L/H)

don’tcare

(L/H)

Command

Address

Hi-Z or Low

SO

Echo Back Output

DATA

RDY = “H”

Figure 61. AM Reading during System Reset/RUN (SPI)

014006643-E-00

2014/10

- 78 -

[AK7755]

■ I²C Bus Interface (I2CSEL pin= “H”)

Access to the AK7755 registers and RAM is controlled by an I²C bus. The AK7755 supports fast-mode

I²C-bus (max: 400kHz) only.

1. Data Transfer

In order to access any IC devices on the I²C bus, input a start condition first, followed by a single Slave

address which includes the Devices Address. IC devices on the BUS compare this Slave address with

their own addresses and the IC device which has an identical address with the Slave address generates an

acknowledgement. An IC device with the identical address then executes either a read or a write

operation. After the command execution, input a Stop condition.

1-1. Data Change

Change the data on the SDA line while the SCL line is “L”. The SDA line condition must be stable

and fixed while the clock is “H”. Change the Data line condition between “H” and “L” only when the

clock signal on the SCL line is “L”. Change the SDA line condition while the SCL line is “H” only

when the start condition or stop condition is input.

SCL

SDA

DATA LINE

STABLE :

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 62. Data Change (I²C)

1-2. Start Condition and Stop Condition

A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is

“H”. All instructions are initiated by a Start condition. A stop condition is generated by the transition

of “L” to “H” on the SDA line while the SCL line is “H”. All instructions end by a Stop condition.

SCL

SDA

START CONDITION

STOP CONDITION

Figure 63. Start Condition and Stop Condition (I²C)

014006643-E-00

2014/10

- 79 -

[AK7755]

1-3. Repeated Start Condition

When a Start condition is received again instead of a Stop condition, the bus changes to a Repeated

Start condition. A Repeated Start condition is functionally the same as a Start condition.

SCL

SDA

START CONDITION

Repeated Start CONDITION

Figure 64. Repeated Start Conditions (I²C)

1-4. Acknowledge

An external device that is sending data to the AK7755 releases the SDA line (“H”) after receiving one

byte of data. An external device that receives data from the AK7755 then sets the SDA line to “L” at

the next clock. This operation is called “acknowledgement”, and it enables verification that the data

transfer has been properly executed. The AK7755 generates an acknowledgement upon receipt of a

Start condition and a Slave address. For a write instruction, an acknowledgement is generated

whenever receipt of each byte is completed. For a read instruction, succeeded by generation of an

acknowledgement, the AK7755 releases the SDA line after outputting data at the designated address,

and it monitors the SDA line condition. When the Master side generates an acknowledgement without

sending a Stop condition, the AK7755 outputs data at the next address location. When no

acknowledgement is generated, the AK7755 ends data output (not acknowledged).

Clock pulse

for acknowledge

SCL FROM

MASTER

1

8

9

DATA

OUTPUT BY

TRANSMITTER

not acknowledge

acknowledge

DATA

OUTPUT BY

RECEIVER

START

CONDITION

Figure 65. Generation of Acknowledgement (I²C)

014006643-E-00

2014/10

- 80 -

[AK7755]

1-5. The First Byte

The First Byte, which includes the Slave-address, is input after the Start condition is set, and a target IC

device that will be accessed on the bus is selected by the Slave-address. The Slave-address is configured

with the upper 7-bits. When the I2CSEL pin = “H” and the EXTEEP pin = “L”, data of the upper 6-bits is

“001100”. The next 1 bit is the address bits that select the desired IC which are set by the CAD pin. The

slave address will be “0011000” when the I2CSEL pin =“H” and the EXTEEP pin = “L”. However, the

CAD pin should be set to “L” if the MATSEL pin = “L” to set the slave address to “0011000” when

downloading from EEPROM by DLS bit even if the I2CSEL pin =“H” and the EXTEEP pin = “L”.

When the Slave-address is inputted, an external device that has the identical device address generates an

acknowledgement and instructions are then executed. The 8^thbit of the First Byte (lowest bit) is allocated

as the R/W Bit. When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the write

instruction is executed.

Note 52. In this document, there is a case that describes a “Write Slave-address assignment” when both

address bits match and a Slave-address at R/W Bit = “0” is received. There is a case that

describes “Read Slave-address assignment” when both address bits matches and a Slave-address

at R/W Bit = “1” is received.

0

1

0

CAD

R/W

When I2CSEL pin = “H” and EXTEEP pin = “L”

0

1

0

R/W

When I2CSEL pin = “H” and EXTEEP pin = “H”, or using DLS bit

Figure 66. First Byte Configuration (I²C)

1-6. The Second and Succeeding Bytes

The data format of the second and succeeding bytes of the AK7755 Transfer / Receive Serial data

(command code, address and data in microcontroller interface format) on the I²C BUS are all

configured with a multiple of 8-bits. When transferring or receiving those data on the I²C BUS, they

are divided into an 8-bit data stream segment and they are transferred / received with the MSB side

data first with an acknowledgement in-between.

Example)

When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:

2

(1)マイコンインターフェースのフォーマット

(1)I C のフォーマット

(1) Microcontroller Interface Format

(2) I C Format

A1

B2

C3

A1

B2

C3

A

24BIT

8BIT

…Acknowledge

A

Figure 67. Division of Data (I²C)

Note 53. In this document, there is a case that describes a write instruction command code which is

received at the second byte as “Write Command”. There is a case that describes a read

instruction command code which is received at the second byte as “Read Command”.

014006643-E-00

2014/10

- 81 -

[AK7755]

2. Write Sequence

In the AK7755, when a “Write-Slave-address assignment” is received at the first byte, the write

command at the second byte and data at the third and succeeding bytes are received. At the data block,

address and write data are received in a single-byte unit each in accordance with a command code. The

number of write data bytes is fixed by the received command code.

S

T

O

P

T

A

R

T

R/W="0"

Slave

Address

Command

Code

S

Data(n)

Data(n+1)

Data(n+x)

P

SDA

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Figure 68. Write Sequence (I²C)

3. Read Sequence

In the AK7755, when a “write- slave-address assignment” is received at the first byte, the read command

at the second byte and the data at the third and succeeding bytes are received. At the data block, the

address is received in a single byte unit in accordance with a read command code. When the last address

byte (or command code if no address assignment is specified) is received and an acknowledgement is

transferred, the read command waits for the next restart condition. When a “read slave-address

assignment” is received at the first byte, data is transferred at the second and succeeding bytes. The

number of readable data bytes is fixed by the received read command.

After reading the last byte, assure that a “not acknowledged” signal is received. If this “not

acknowledged” signal is not received, the AK7755 continues to send data regardless whether data is

present or not, and since it does not release the BUS, the stop condition cannot be properly received.

R

E

S

T

A

R

T

S

T

A

R

T

S

T

R/W="0"

R/W="1"

O

P

Slave

Address

Command

code

Slave

Address

S

Data(n)

Data(n+1)

Data(n+x)

P

Data(n)

SDA

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

N

A

C

K

A

C

K

Figure 69. Read Sequence (I²C)

014006643-E-00

2014/10

- 82 -

[AK7755]

4. Acknowledgement Polling

The AK7755 cannot receive instructions while the RDY pin (Data Write Ready pin) is at low level.

The maximum transition time of the RDY pin from low level to high level is 2/fs (fs: sampling

frequency), but it is possible to confirm in a faster cycle that the RDY pin has become high by

checking the AK7755 internal condition, which is made by verifying the acknowledgement.

4-1. Generation of “Not Acknowledged”

The AK7755 does not accept command codes until the RDY pin is set to a high level, when a

command is received to set the RDY pin to a low level. In order to confirm the RDY pin condition, a

“Write Slave-Address assignment” should be sent after a Start condition. If the RDY pin is then at a

low level, “Acknowledgement” is not generated at the succeeding clock (generation of “Not

Acknowledged”). After sending “Not Acknowledged”, the BUS is released and all receiving data are

ignored until the next start condition (behaves as if it received Slave address of other device).

4-2. When Read Slave-address assignment is received without receiving read command code

Data read in the AK7755 can be made only in the previously documented Read sequence. Data cannot

be read out without receiving a read command code. The AK7755 generates a “Not Acknowledged”

when a “Read Slave-address Assignment” is received without proper receipt of read command.

5. Limitation in use of I²C Interface

The I2C interface does not support the following features.

No operation in Hs Mode (max:3.4MHz). The AK7755 Supports FAST mode (max:400KHz).

Note 54. Do not turn off the power of the AK7755 whenever the power supplies of other devices of the

same system are turned on. The source of the pull-up of SDA and SCL of I²C BUS must not

exceed the TVDD. (The diode exists for TVDD in the SDA and SCL pins.)

014006643-E-00

2014/10

- 83 -

[AK7755]

■ Analog Input Block

1. Microphone Input Selector

Either analog input or digital microphone interface can be chosen for the AK7755. Set AINE bit

(CONT00: D3) to “1” when using #31-34 pins as analog input pins, and set DMIC1(CONT1E: D7) or

DMIC2 bit (CONT1E: D4) to “1” when using these pins as digital microphone interface. ADC input

signals can be switched by DIFL bit (CONT09: D5), DIFR bit (CONT09: D7), INL bit (CONT09: D4)

and INTR bit (CONT09: D6) for analog inputs. When DIFL bit = “0” and DIFR bit = “0”, input signals

of IN1, IN2, IN3 and IN4 pins for microphone amplifiers can be selected by INL and INR bits. When

DIFL bit = “1” and DIFR bit = “1”, a differential input is acceptable as input pins becomes INP1/INN1

pins and INP2/INN2 pins.

AK7755

INL bit

IN1/INP1/DMDAT1 pin

IN2/INN1/DMCLK1 pin

ADC

Lch

MIC-Amp

DIFL bit

INR bit

IN3/INP2/DMDAT2 pin

IN4/INN2/DMCLK2 pin

ADC

Rch

MIC-Amp

DIFR bit

Figure 70. Microphone Input Selector

ADC Lch Microphone Input Selector ADC Rch Microphone Input Selector

DIFL bit INL bit

ADC Lch

IN1

DIFR bit INR bit

ADC Rch

IN3

0

1

(default)

0

1

(default)

0

IN2

0

IN4

1

X

INP1/INN1

1

X

INP2/INN2

(x: Do not care)

014006643-E-00

2014/10

- 84 -

[AK7755]

2. Microphone Input Gain

The AK7755 has a microphone gain amplifier. L and R channel gains can be set independently by

MGNL[3:0] bits (CONT12: D3-D0) and MGNR[3:0] bits (CONT12: D7-D4). Input impedance is typ.

20k. This gain amplifier executes zero cross detection when changing the gain by setting MICLZCE bit

(CONT1A: D0) = “1” / MICRZCE bit (CONT1A: D1) = “1”. Zero cross detection is executed on L and

R channels independently. Timeout period of the zero cross detection is 16ms. When MICLZCE bit =

“0” / MICRZCE bit = “0”, zero cross detection is not performed and the volume is changed immediately

when register is written.

When writing to MGNL3-0/MGNR3-0 bits continually, take an interval of zero crossing timeout periods

or more. If the MGNL3-0/MGNR3-0 bits are changed before zero crossing, the volume of Lch and Rch

may differ. When the volume that is same as the present is set, the zero crossing counter is not reset and

timeout according to the previous writing timing.

Zero Crossing Timeout

When MICLZCE bit = “1” / MICRZCE bit = “1”, the Lch/Rch volume level are changed independently

by zero crossing detection or zero crossing timeout.

fs

48kHz

Zero cross Timeout Period

16ms

MGNL[3] MGNL[2] MGNL[1] MGNL[0]

MGNR[3] MGNR[2] MGNR[1] MGNR[0]

Mode

Input Gain

0

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0dB

2dB

4dB

6dB

8dB

10dB

12dB

14dB

16dB

18dB

21dB

24dB

27dB

30dB

33dB

36dB

(default)

9

A

B

C

D

E

F

Table 2. Microphone Input Gain

3. Analog DRC (ADRC)

The microphone input gain can be set by DSP programs with the AK7755. This function is enabled by

setting ADRCRE bit = “1”/ADRCLE bit = “1” (CONT1A: D3/D2). In this setting, control registers

MGNL[3:0] and MDNR[3:0] bits (CONT12) are not valid. By reading AMGNL[3:0] (CONT1B:

D3-D0) / AMGNR[3:0] (CONT1B: D7-D4) bits, gain settings can be downloaded externally.

When MICLZCE bit = “1”/MICRZCE bit = “1”, the Lch/Rch volume level are changed independently

by zero crossing detection or zero crossing timeout. Please refer to the AK7755 programing manual for

DSP programs.

014006643-E-00

2014/10

- 85 -

[AK7755]

4. LINE Input Gain Amplifier

The AK7755 has a gain amplifier for line inputs. It is enabled by setting PMLI bit (CONT0F: D5) =

“1”, and it outputs a signal to the L channel of the ADC2. LIGN[3:0] bits (CONT13: D7-D4) controls

the gain. The typical input impedance is 20k (typ). A pop noise occurs if the input gain is changed

during operation.

The AK7755 becomes digital microphone interface mode when DMIC2 bit (CONT1E: D4) = “1”.

Digital microphone input data to the DMDAT2 pin is input to the Lch/Rch of the ADC2.

ADC2 Input Setting

DMIC2 bit

ADC2 Lch Input

LIN

Digital Microphone

ADC2 Rch Input

No

Digital Microphone

0

1

(default)

Mode LIGN[3] LIGN[2] LIGN[1]

LIGN[0]

Input Gain

0dB (default)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-3dB

-6dB

-9dB

2

3

4

5

6

7

8

9

A

B

C

D

E

F

-12dB

-15dB

-18dB

-21dB

N/A

+3dB

+6dB

+9dB

+12dB

+15dB

+18dB

+21dB

Table 3. Line Input Gain

014006643-E-00

2014/10

- 86 -

[AK7755]

■ ADC Block

1. ADC High Pass Filter

A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off

frequency of the HPF is approximately 1Hz (at fs=48kHz).

fs

48kHz

3.73Hz

44.1kHz

3.43Hz

8kHz

0.62Hz

Cut-off frequency

2. ADC Soft Mute

2-1. Description

The ADC block has a digital soft mute circuit. The soft mute operation is performed in the digital

domain. The output signal is attenuated to -∞ in “ADC Digital Volume Level x ATT transition time”

from the current ADC Digital Volume Setting Level by setting ADMUTE and AD2MUTE bits to “1”.

When the ADMUTE (CONT1A: D7) and AD2MUTE (CONT1A: D6) bits are returned to “0”, the

mute is cancelled and the output attenuation gradually changes to ADC Digital Volume Setting Level

in “ADC Digital Volume Level x ATT transition time”. If the soft mute is cancelled before attenuating

to -∞ after starting the operation, the attenuation is discontinued and returned to ADC Digital Volume

Setting Level by the same cycle. The soft mute is effective for changing the signal source without

stopping the signal transmission. The transition time from 0dB to -∞ and vice versa is 828 LRCK

cycles.

The soft mute function works when the ADC is in operation. The attenuation value is initialized by the

PDN pin = “L”.

SMUTE Register Value

Group Delay (GD)

0dB

Attenuation

828/fs

-∞dB

828/fs

Output Image

Figure 71. ADC Soft Mute

2-2. Input Selector Switching Sequence

The input selector should be changed after soft muting to avoid the switching noise of the input

selector.

· Input Selector Switching Sequence

1. Enable soft mute before changing the channel.

2. Change the Channel.

3. Disable softer mute.

ADMUTE

(2)

(1)

DATT Level

Attenuation

(3)

-∞

Channel

IN1/IN3

IN2/IN4

Figure 72. ADC Input Channel Switching Sequence Example

- 87 -

014006643-E-00

2014/10

[AK7755]

The period of (1) varies by the setting value of DATT bit. The transition time of attenuation amount

from 0dB to -∞ and vice versa is shown below.

ATSPAD

(1)Period (max)

fs=48kHz

17.25ms

LRCK Cycle

828/fs

828/fs x 4

fs=44.1kHz

18.82ms

75.27ms

fs=8kHz

103.5ms

414ms

0

1

69ms

When changing channels, the input channel should be changed during (2). The period of (2) should be

around 200ms because there is some DC difference between the channels (3).

2-3. ADC Digital Volume

The ADC of the AK7755 has channel-independent digital volume control (256 levels, 0.5dB step).

VOLADL [7:0] bits (CONT15:D7-D0), VOLADR [7:0] bits (CONT16:D7-D0), VOLAD2L [7:0] bits

(CONT17:D7-D0) and VOLAD2R [7:0] bits (CONT1D:D7-D0) control these volume values

independently.

ADC Stereo Lch ADC Stereo Rch

ADC2 Lch

ADC2 Rch

Attenuation Level

VOLADL [7:0]

VOLADR [7:0]

VOLAD2L [7:0] VOLAD2R [7:0]

00h

01h

02h

:

00h

01h

02h

:

00h

01h

02h

:

00h

01h

02h

:

+24.0dB

+23.5dB

+23.0dB

:

2Fh

30h

31h

:

2Fh

30h

31h

:

2Fh

30h

31h

:

2Fh

30h

31h

:

+0.5dB

0.0dB

-0.5dB

:

(default)

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

-102.5dB

-103.0dB

Mute (-∞)

Table 4. ADC Digital Volume Level Setting

Transition time between set values can be selected by ATSPAD bit (CONT0C: D5).

MODE

ATSPAD

ATT speed

1/fs

0

1

0

1

4/fs

Table 5. ADC Volume Transition Time Setting

The transition between set values is soft transition of 1021 levels in Mode 0. It takes 1021/fs

(21.3ms@fs=48kHz) from 00h to FFh(MUTE). If the PDN pin is set to “L”, the VOLADL/R[7:0] bits

are initialized to 30h.

014006643-E-00

2014/10

- 88 -

[AK7755]

code

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

dB

code

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

dB

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

code

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

dB

-8.0

-8.5

-9.0

code

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

dB

code

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

dB

code

A0h

A1h

A2h

A3h

A4h

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

dB

code

C0h

C1h

C2h

C3h

C4h

C5h

C6h

C7h

C8h

C9h

CAh

CBh

CCh

CDh

CEh

CFh

D0h

D1h

D2h

D3h

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

dB

code

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

F0h

F1h

F2h

F3h

F4h

F5h

F6h

F7h

dB

24.0

23.5

23.0

22.5

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

9.5

-24.0

-24.5

-25.0

-25.5

-26.0

-26.5

-27.0

-27.5

-28.0

-28.5

-29.0

-29.5

-30.0

-30.5

-31.0

-31.5

-32.0

-32.5

-33.0

-33.5

-34.0

-34.5

-35.0

-35.5

-36.0

-36.5

-37.0

-37.5

-38.0

-38.5

-39.0

-39.5

-40.0

-40.5

-41.0

-41.5

-42.0

-42.5

-43.0

-43.5

-44.0

-44.5

-45.0

-45.5

-46.0

-46.5

-47.0

-47.5

-48.0

-48.5

-49.0

-49.5

-50.0

-50.5

-51.0

-51.5

-52.0

-52.5

-53.0

-53.5

-54.0

-54.5

-55.0

-55.5

-56.0

-56.5

-57.0

-57.5

-58.0

-58.5

-59.0

-59.5

-60.0

-60.5

-61.0

-61.5

-62.0

-62.5

-63.0

-63.5

-64.0

-64.5

-65.0

-65.5

-66.0

-66.5

-67.0

-67.5

-68.0

-68.5

-69.0

-69.5

-70.0

-70.5

-71.0

-71.5

-72.0

-72.5

-73.0

-73.5

-74.0

-74.5

-75.0

-75.5

-76.0

-76.5

-77.0

-77.5

-78.0

-78.5

-79.0

-79.5

-80.0

-80.5

-81.0

-81.5

-82.0

-82.5

-83.0

-83.5

-84.0

-84.5

-85.0

-85.5

-86.0

-86.5

-87.0

-87.5

-88.0

-88.5

-89.0

-89.5

-90.0

-90.5

-91.0

-91.5

-92.0

-92.5

-93.0

-93.5

-94.0

-94.5

-95.0

-95.5

-96.0

-96.5

-97.0

-97.5

-98.0

-98.5

-99.0

-99.5

-9.5

-10.0

-10.5

-11.0

-11.5

-12.0

-12.5

-13.0

-13.5

-14.0

-14.5

-15.0

-15.5

-16.0

-16.5

-17.0

-17.5

-18.0

-18.5

-19.0

-19.5

-20.0

-20.5

-21.0

-21.5

-22.0

-22.5

-23.0

-23.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

-5.5

-.6.0

-6.5

-7.0

-7.5

F8h -100.0

F9h -100.5

FAh -101.0

FBh -101.5

FCh -102.0

FDh -102.5

FEh -103.0

9.0

8.5

FFh

Mute

Table 6. ADC Digital Volume Setting List

014006643-E-00

2014/10

- 89 -

[AK7755]

■ DAC Blocks

1. De-emphasis Filter

The AK7755 has a digital de-emphasis filter (tc=50/15µs) by IIR filter, corresponding to 48kHz

sampling frequency. DEM[1:0] bits control the de-emphasis filter.

DEM mode

DEM[1:0]

Sampling Frequency (fs)

0

1

2

3

00

01

10

11

OFF

48kHz

44.1kHz

32kHz

(default)

Table 7. De-emphasis Control

2. DAC Digital Volume Control

The DACs of the AK7755 have channel independent volume control (256 levels, 0.5 step). The

VOLDAL/R[7:0] bits (CONT18: D7-D0 / CONT19: D7-D0), set the attenuation level of each DAC

channel.

DAC Lch VOLDAL

DAC Rch VOLDAR [7:0]

Attenuation Level

[7:0]

00h

01h

02h

:

00h

01h

02h

:

+12.0dB

+11.5dB

+11.0dB

:

17h

18h

19h

:

17h

18h

19h

:

+0.5dB

0.0dB

-0.5dB

:

(default)

FDh

FEh

FFh

FDh

FEh

FFh

-114.5dB

-115.0dB

Mute (-∞)

Table 8. DAC Digital Volume Setting

Transition time between set values can be selected by ATSPDA bit (CONT0C: D5).

MODE

ATSPDA

ATT speed

1/fs

0

1

0

1

4/fs

Table 9. DAC Volume Transition Time Setting

The transition between set values is soft transition of 1021 levels in Mode 0. It takes 1021/fs

(21.3ms@fs=48kHz) from 00h to FFh (MUTE) in Mode 0. If the PDN pin is set to “L”, the

VOLDAL/R[7:0] bits are initialized to 18h.

014006643-E-00

2014/10

- 90 -

[AK7755]

code dB

code DB

code dB

00h 12.0 20h -4.0

01h 11.5 21h -4.5

02h 11.0 22h -5.0

03h 10.5 23h -5.5

40h -20.0 60h -36.0 80h -52.0 A0h -68.0 C0h -84.0 E0h -100.0

41h -20.5 61h -36.5 81h -52.5 A1h -68.5 C1h -84.5 E1h -100.5

42h -21.0 62h -37.0 82h -53.0 A2h -69.0 C2h -85.0 E2h -101.0

43h -21.5 63h -37.5 83h -53.5 A3h -69.5 C3h -85.5 E3h -101.5

04h 10.0 24h -.6.0 44h -22.0 64h -38.0 84h -54.0 A4h -70.0 C4h -86.0 E4h -102.0

05h 9.5

06h 9.0

07h 8.5

08h 8.0

09h 7.5

0Ah 7.0

0Bh 6.5

0Ch 6.0

0Dh 5.5

0Eh 5.0

0Fh 4.5

10h 4.0

11h 3.5

12h 3.0

13h 2.5

14h 2.0

15h 1.5

16h 1.0

17h 0.5

18h 0.0

25h -6.5

26h -7.0

27h -7.5

28h -8.0

29h -8.5

2Ah -9.0

2Bh -9.5

45h -22.5 65h -38.5 85h -54.5 A5h -70.5 C5h -86.5 E5h -102.5

46h -23.0 66h -39.0 86h -55.0 A6h -71.0 C6h -87.0 E6h -103.0

47h -23.5 67h -39.5 87h -55.5 A7h -71.5 C7h -87.5 E7h -103.5

48h -24.0 68h -40.0 88h -56.0 A8h -72.0 C8h -88.0 E8h -104.0

49h -24.5 69h -40.5 89h -56.5 A9h -72.5 C9h -88.5 E9h -104.5

4Ah -25.0 6Ah -41.0 8Ah -57.0 AAh -73.0 CAh -89.0 EAh -105.0

4Bh -25.5 6Bh -41.5 8Bh -57.5 ABh -73.5 CBh -89.5 EBh -105.5

2Ch -10.0 4Ch -26.0 6Ch -42.0 8Ch -58.0 ACh -74.0 CCh -90.0 ECh -106.0

2Dh -10.5 4Dh -26.5 6Dh -42.5 8Dh -58.5 ADh -74.5 CDh -90.5 EDh -106.5

2Eh -11.0 4Eh -27.0 6Eh -43.0 8Eh -59.0 AEh -75.0 CEh -91.0 EEh -107.0

2Fh -11.5 4Fh -27.5 6Fh -43.5 8Fh -59.5 AFh -75.5 CFh -91.5 EFh -107.5

30h -12.0 50h -28.0 70h -44.0 90h -60.0 B0h -76.0 D0h -92.0 F0h -108.0

31h -12.5 51h -28.5 71h -44.5 91h -60.5 B1h -76.5 D1h -92.5 F1h -108.5

32h -13.0 52h -29.0 72h -45.0 92h -61.0 B2h -77.0 D2h -93.0 F2h -109.0

33h -13.5 53h -29.5 73h -45.5 93h -61.5 B3h -77.5 D3h -93.5 F3h -109.5

34h -14.0 54h -30.0 74h -46.0 94h -62.0 B4h -78.0 D4h -94.0 F4h -110.0

35h -14.5 55h -30.5 75h -46.5 95h -62.5 B5h -78.5 D5h -94.5 F5h -110.5

36h -15.0 56h -31.0 76h -47.0 96h -63.0 B6h -79.0 D6h -95.0 F6h -111.0

37h -15.5 57h -31.5 77h -47.5 97h -63.5 B7h -79.5 D7h -95.5 F7h -111.5

38h -16.0 58h -32.0 78h -48.0 98h -64.0 B8h -80.0 D8h -96.0 F8h -112.0

19h -0.5 39h -16.5 59h -32.5 79h -48.5 99h -64.5 B9h -80.5 D9h -96.5 F9h -112.5

1Ah -1.0 3Ah -17.0 5Ah -33.0 7Ah -49.0 9Ah -65.0 BAh -81.0 DAh -97.0 FAh -113.0

1Bh -1.5 3Bh -17.5 5Bh -33.5 7Bh -49.5 9Bh -65.5 BBh -81.5 DBh -97.5 FBh -113.5

1Ch -2.0 3Ch -18.0 5Ch -34.0 7Ch -50.0 9Ch -66.0 BCh -82.0 DCh -98.0 FCh -114.0

1Dh -2.5 3Dh -18.5 5Dh -34.5 7Dh -50.5 9Dh -66.5 BDh -82.5 DDh -98.5 FDh -114.5

1Eh -3.0 3Eh -19.0 5Eh -35.0 7Eh -51.0 9Eh -67.0 BEh -83.0 DEh -99.0 FEh -115.0

1Fh -3.5 3Fh -19.5 5Fh -35.5 7Fh -51.5 9Fh -67.5 BFh -83.5 DFh -99.5 FFh Mute

Table 10. DAC Digital Volume Setting List

3. DAC Soft Mute

The DAC block has a digital soft mute circuit. The soft mute operation is performed in the digital

domain. The input signal is attenuated to -∞ in “DAC Digital Volume Level x ATT transition time”

from the current DAC Digital Volume Setting Level by setting DAMUTE bit (CONT1A: D5) to “1”.

When the DAMUTE bit is returned to “0”, the mute is cancelled and the input attenuation gradually

changes to DAC Digital Volume Setting Level in “DAC Digital Volume Level x ATT transition

time”. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation

is discontinued and returned to DAC Digital Volume Setting Level by the same cycle. The soft mute is

effective for changing the signal source without stopping the signal transmission. The soft mute

function works when the DAC is in operation. Since the DAC block is in reset state, there is a

possibility that a click noise occurs by a reset and a reset release when CRESETN bit (CONT0F: D3)

= “0” and PMDAL/R bit (CONT0E: D0/D1) = “0”. This click noise should be muted externally. The

attenuation value is initialized by the PDN pin = “L”.

(Setting+2)/fs(max)

DAMUTE Register

(Setting+2)/fs(max)

0dB

Attenuation

-∞dB

GD

Output Image

Soft Mute Operation

Figure 73. DAC Soft Mute Operation

- 91 -

014006643-E-00

2014/10

[AK7755]

■ Analog Output Block

The AK7755 can output an analog mixing signal of DAC and line-in amplifier outputs from the OUT3

pin. AD conversion is available by setting PMAD2L bit (CONT0E: D5) to “1” even when the analog

mixing output is ON.

AK7755

Mono

ADC

Stereo

DAC Lch

OUT1 pin

OUT2 pin

LIN pin

LOVOL1[3:0]

LOVOL2[3:0]

LIGN[3:0]

Stereo

DAC Rch

LO3SW1(SW1)

M

I

X

LO3SW2(SW2)

LO3SW3(SW3)

OUT3 pin

LOVOL3[3:0]

Figure 74. Analog Output Circuit

1. Line Output Amplifier

The AK7755 has a line output amplifier. The maximum amplitude is 0.76 × AVDD (2.51[Vpp]

@AVDD=3.3V) and load resistance is 10k (min). LOVOL1/2/3[3:0] bits (CONT14: D3-D0/

CONT14: D7-D4/ CONT13: D3-D0) control the stereo line output volume. A pop noise occurs if the

output gain is changed during operation.

LOVOL1,L2,L3[3:0]

Attenuation

Mute(default)

-28dB

LOVOL1, L2, L3[3:0]

Attenuation

-14dB

-12dB

-10dB

-8dB

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

-26dB

-24dB

-22dB

-20dB

-18dB

-16dB

Ah

Bh

Ch

Dh

Eh

Fh

-6dB

-4dB

-2dB

0dB

Table 11. Line Output Volume

2. Output1 and Output2

The OUT1 and OUT2 pins are connected to the L and R channels of the internal stereo DAC,

respectively. The relationship of each control bit and the OUT1 and OUT2 pins are shown below.

The OUT1 and OUT2 pins output settings are controlled by PMLO1/2 bit (CONT0E: D2/D3),

PMDAL/R bit (CONT0E: D0 /D1) and LOVOL1/2[3:0] bits (CONT014: D3-D0/D7-D4).

PMLO1 bit PMDAL bit

LOVOL1[3:0] bits

OUT1 pin Output

Hi-Z

1/2 x AVDD

DAC Lch Output

0

1

X

0

1

X

0h(mute)

1h-Fh

1

PMLO2 bit PMDAR bit

LOVOL2[3:0] bits

OUT2 pin Output

Hi-Z

1/2 x AVDD

DAC Rch Output

0

1

X

0

1

X

0h(mute)

1h-Fh

1

014006643-E-00

2014/10

- 92 -

[AK7755]

3. OUT3 (Analog Mixer）

The AK7755 can output an analog mixing signal of DAC and line-in amplifier outputs from the OUT3

pin by setting LO3SW1 bit (CONT09: D1), LO3SW2 bit (CONT09: D2) and LO3SW3 bit (CONT09:

D3).

The line-out amplifier is powered up by setting PMLO3 bit = “1”. Each switch is disconnected and the

OUT3 pin outputs 1/2 × AVDD when LOVOL3[3:0] bits (CONT13: D3-D0) = 0h. L and R channel

signals of the DAC are input to the mixer by setting LO3SW1 bit and LO3SW2 bit to “1” while the

setting of LOVOL3[3:0] bits is not 0h. L and R channel signals of the DAC are not gained by the mixer

block.

The output signal of line-in amplifier is input to the mixer by setting LO3SW3 bit to “1” while the

setting of LOVOL3[3:0] bits is not 0h. Adjust the input voltage and line-in amplifier gain (LIGN[3:0]

bits (CONT13: D7-D4)) to prevent the mixing output exceeds 0.67 × AVDD[Vpp] since the line-in

amplifier output is gained +18dB by the mixer block.

The maximum amplitude of the line-out output is 0.76 × AVDD[Vpp]. VOLDAL[7:0] bits (CONT18:

D7-D0), VOLDAR[7:0] bits (CONT19: D7-D0), LIGN[3:0] bits and LOVOL3[3:0] bits should be

adjusted to not exceed this maximum level.

PMLO3

LOVOL3[3:0]

X

LO3SW1

LO3SW2

LO3SW3

SW1

OFF

ON

SW2

OFF

ON

SW3

OFF

ON

OFF

ON

OFF

ON

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

0h(mute)

1h-Fh

ON

OFF

ON

OFF

ON

Table 12. OUT3 pin Output Switching Setting

014006643-E-00

2014/10

- 93 -

[AK7755]

■ Simple Write Error Check

RAM and register data can be checked by cyclic redundancy check (CRC). It realizes a simple error

check of a written data.

1. Checked Data

1-1. SPI Interface

The serial input data of the AK7755 can be checked from a falling edge of the CSN signal to rising

edge of the CSN signal.

· Serial Data D (x): Input data from a falling edge to a rising edge of the CSN.

· Generating Polynomial: G(x)=x¹⁶+x¹²+x⁵+1 (default=0)

· R(x) is defined as the remainder when D(x) is divided by G(x).

CSN

SCLK

don’tcare

X (L/H)

SI

Data (write)

Command Code (8bit)

Address (16bit or 0bit)

1-2. I²C Interface

The data after second byte: command code, address and data are checked. (Acknowledge is not

included in the checked data. Therefore, if the command code, address and data are the same as when

SPI interface is used, the CRC error result will also be the same.) The first byte which includes slave

address is excluded. The first byte can be checked with Acknowledge.

· Serial Data D(x): Command Code, Address and Data (Expect slave address)

· Generating Polynomial: G(x)=x¹⁶+x¹²+x⁵+1 (default=0)

· R (x) is defined as the remainder when D(x) is divided by G(x).

2. Simple Write Error Check Sequence

There are two ways to execute a simple write error check.

2-1. CRC Result Reading

(1) Write serial data D(x) that need to be checked.

(2) Read CRC result (the remainder R(x)) by the command code 72h.

(3) Check the result by a microcomputer.

(4) Repeat (1) ~ (3) when checking another serial data.

Note 55. The internal CRC result is not reflected by the command code

2-2. Checking by the STO pin

(1) Set control register CRCE bit to “1”.

(2) Write serial data D(x) that need to be checked.

(3) Write the remainder R(x) of D(x) ti registers by the command code F2H.

(4) The SDO pin outputs “H” when the calculated remainder of D(x) divided by G(x) equals to the

R(x) value. If not, the STO pin outputs “L”.

(5) Repeat (2) ~ (4) when checking another serial data.

Note 56. The STO pin keeps “L” output until an appropriate remainder R(x) is written to the registers.

014006643-E-00

2014/10

- 94 -

[AK7755]

■ EEPROM Interface

1. Data Download

The AK7755 has EEPROM boot mode to read out necessary data from an external EEPROM to the

internal memory via I²C bus. A hands-free function is easily realized in the system using EEPROM

without extra overloads on the microprocessor. The external EEPROM should be connected to the I²C

interface of the AK7755 (I2CSEL pin= “H”). A SPI interface type EEPROM cannot be connected. Write

data as shown in “2. Program Map” to the EEPROM.

Control registers can shift the WRITE command code and data in 2 BYTE unit. However, the data

location from the PRAM WRITE command code (0034h) to OFREG address 31LSB (689Ch) is fixed.

Set “1010000” to I²C slave address of the EEPROM when 256K bit, and set “101000+A16” when 1M

bit.

The AK7755 starts downloading the data from the EEPROM when setting the EXTEEP pin to “H” or

DLS bit (CONT0D: D0) to “1” while the EXTEEP pin = “L” after inputting a 12.288MHz clock to the

XTI pin or connecting a 12.288MHz crystal oscillator to the XTI pin and the XTO pin. The EEST

(SDOUT1) pin goes to “H” while downloading data and the AK7755 becomes an I²C master. Do not

write/read to the other devices that are connected to the same I²C bus during downloading. The EEST

pin returns to “L” after downloading data and the AK7755 will be in I²C slave mode. Interfacing to a

microcontroller becomes available when the EEST pin = “L”.

When accessing the AK7755 after downloading data by CRC function, set CRCE bit (CONT10: D6) to

“0” before access the AK7755. The EEPROM download period is 0.8s (max). Set the EXTEEP pin “H”

→ “L” → “H” or DLS bit (CONT0D, D0) “1” → “0” → “1” to start a data downloading again.

However, data downloading cannnot be executed by DLS bit when selecting memory mat (I2CSEL pin

= MATSEL pin = “H”).

μP

STO

GPI1

GPI2

Control

EEST (SDOUT1)

SCL

SDA

EEPROM

μP/

EEPROM

Interface

μP/

EEPROM

Interface

EEPROM

SCL

SDA

SCL

SDA

SCL

SDA

EXTEEP

I2CSEL = “H”

I2CSEL= “H”

PDN

Figure 75. EEPROM Connection (Left: EEPROM only, Right: CPU and EEPROM)

014006643-E-00

2014/10

- 95 -

[AK7755]

2. Program Map

EEPROM Address DATA

Note

C0h

DATA

C1h

DATA

C2h

DATA

C3h

DATA

C4h

DATA

C5h

DATA

C6h

DATA

C7h

DATA

C8h

DATA

C9h

DATA

CAh

DATA

CCh

DATA

D0h

DATA

D1h

DATA

D2h

DATA

D3h

DATA

D4h

DATA

D5h

DATA

D6h

DATA

D7h

DATA

D8h

DATA

D9h

DATA

DAh

DATA

00h

CONT00 Write Command Code

CONT00 Data

CONT01 Write Command Code

CONT01 Data

CONT02 Write Command Code

CONT02 Data

CONT03 Write Command Code

CONT03 Data

CONT04 Write Command Code

CONT04 Data

CONT05 Write Command Code

CONT05 Data

CONT06 Write Command Code

CONT06 Data

CONT07 Write Command Code

CONT07 Data

CONT08 Write Command Code

CONT08 Data

CONT09 Write Command Code

CONT09 Data

CONT0A Write Command Code

CONT0A Data

CONT0CWrite Command Code

CONT0C Data

CONT10 Write Command Code

CONT10 Data

CONT11 Write Command Code

CONT11 Data

CONT12 Write Command Code

CONT12 Data

CONT13 Write Command Code

CONT13 Data

CONT14 Write Command Code

CONT14 Data

CONT15 Write Command Code

CONT15 Data

CONT16 Write Command Code

CONT16 Data

CONT17 Write Command Code

CONT17 Data

CONT18 Write Command Code

CONT18 Data

CONT19 Write Command Code

CONT19 Data

CONT1A Write Command Code

CONT1A Data

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

Dummy Data0 0 (Note 58)

00h

Dummy Data0

Dummy Data1

1

0

1

Dummy Data2 0 (Note 57)

00h

Dummy Data2

1

014006643-E-00

2014/10

- 96 -

[AK7755]

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h

B8h

00h

PRAM WRITE Command Code

PRAM Address MSB side

PRAM Address LSB side

PRAM Address0 MSB 8-bit Data

PRAM Address0 MSB-1 8-bit Data

PRAM Address0 MSB-2 8-bit Data

PRAM Address0 MSB-3 8-bit Data

PRAM0 DATA39-32

PRAM0 DATA31-24

PRAM0 DATA23-16

PRAM0:DATA15-8

PRAM0 DATA7-0

PRAM1 DATA39-32

PRAM1 DATA31-24

PRAM1 DATA23-16

PRAM1:DATA15-8

PRAM1 DATA7-0

PRAM2 DATA39-32

• • •

PRAM Address0 LSB

8-bit Data

PRAM Address1 MSB 8-bit Data

PRAM Address1 MSB-1 8-bit Data

PRAM Address1 MSB-2 8-bit Data

PRAM Address1 MSB-3 8-bit Data

PRAM Address1 LSB 8-bit Data

PRAM Address2 MSB-1 8-bit Data

• • •

5031h

5032h

5033h

5034h

5035h

5036h

5037h

5038h

5039h

503Ah

503Bh

503Ch

503Dh

PRAM4094 DATA7-0

PRAM4095 DATA39-32

PRAM4095 DATA31-24

PRAM4095 DATA23-16

PRAM4095 DATA15-8

PRAM4095 DATA7-0

B4h

PRAM Address4094 LSB

8-bit Data

PRAM Address4095 MSB 8-bit Data

PRAM Address4095 MSB-1 8-bit Data

PRAM Address4095 MSB-2 8-bit Data

PRAM Address4095 MSB-3 8-bit Data

PRAM Address4095 LSB 8-bit Data

CRAM WRITE Command Code

CRAM Address MSB side

00h

CRAM Address LSB side

CRAM0 DATA23-16

CRAM0 DATA15-8

CRAM0 DATA7-0

CRAM1 DATA23-16

• • •

CRAM Address0 MSB

CRAM Address0 MSB-1

CRAM Address0 LSB

CRAM Address1 MSB

8-bit Data

• • •

6836h

6837h

6838h

6839h

683Ah

683Bh

683Ch

683Dh

683Eh

683Fh

6840h

CRAM2046 DATA7-0

CRAM2047 DATA23-16

CRAM2047 DATA15-8

CRAM2047 DATA7-0

B2h

CRAM Address2046 LSB

CRAM Address2047 MSB

CRAM Address2047 MSB-1 8-bit Data

CRAM Address2047 LSB 8-bit Data

OFREG WRITE Command Code

OFREG Address MSB side

OFREG Address LSB side

OFREG Address0 MSB

OFREG Address0 MSB-1

OFREG Address0 LSB

OFREG Address1 MSB

8-bit Data

00h

OFREG0 DATA23-16

OFREG0 DATA15-8

OFREG0 DATA7-0

OFREG1 DATA23-16

• • •

8-bit Data

• • •

6899h

689Ah

689Bh

689Ch

OFREG30 DATA7-0

OFREG31 DATA23-16

OFREG31 DATA15-8

OFREG Address30 LSB

OFREG Address31 MSB

OFREG Address31 MSB-1

OFREG Address31 LSB

8-bit Data

OFREG31 DATA7-0

689Dh

689Eh

689Fh

68A0h

68A1h

68A2h

68A3h

CDh

CONT0D Write Command Code

40h

CONT0D Data

E6h

01h

EAh

80h

CONT26 Write Command Code

CONT26 Data

CONT2A Write Command Code

CONT2A Data

CEh

CONT0E WRITE Command Code

68A4h

68A5h

68A6h

68A7h

68A8h

68A9h

68AAh

DATA

CFh

DATA

00h

CONT0E Data

CONT0F WRITE Command Code

CONT0F Data

Dummy Data0_0

Dummy Data0_1

Dummy Data1_0

Dummy Data1_1

00h

014006643-E-00

2014/10

- 97 -

[AK7755]

68ABh

68ACh

68ADh

68AEh

68AFh

68B0h

68B1h

68B2h

68B3h

68B4h

68B5h

00h

F2h

Dummy Data2_0

Dummy Data2_1

Dummy Data3_0

Dummy Data3_1

Dummy Data4_0

Dummy Data4_1

Dummy Data5_0

Dummy Data5_1

Dummy Data6_0

Dummy Data6_1

CRC WRITE Command Code

68B6h

68B7h

68B8h

• • •

CRC DATA15-8

CRC DATA7-0

00h

• • •

00h

CRC MSB 8-bit Data

CRC LSB 8-bit Data

Reserve

7FFFh

Reserve

Note 57. DSPRESETN bit (CONT0F: D2) must be “0” when downloading a DSP program. Especially this

setting is necessary when changing the DSP program during operation by selecting EEPROM

mat.

Note 58. A WRITE command for arbitrary control register can be written to Dummy data *_0, and write

register setting for the control register to Dummy data*_1 in the table above.

Data transffer from EEPROM can be confirmed by writing R(x) (16-bit) data to CRCDATA (addr:

787Ch, 787Dh) which is the remainder of serial data D(x) from addres 0000h to 68B7h devided by a

generating polynominal; G(x)=x¹⁶+x¹²+x⁵+1 (Initial Value= 0).

3. EEPROM Automatic Re-downloading

When a programmed WDT or CRC error is detected, automatic re-downloading of the EEPROM data is

available up to 4 times by setting the EXPEEP pin = “H”. When an error occurs after re-downloading

more than 4 times, “L” level is output on the STO pin and the device stops. The device status can be

checked by reading STO bit (CONT0D: D7). The CRC function is enabled by setting CRCE bit

(CONT10: D6) to “1”. The default setting of CRCE bit is “0” (disabled).

This setting is initialized (error count: 0) by the PDN pin = “L”. It is not initialized by a clock reset.

4. EEPROM Mat Select

The pin number 20 becomes the MATSEL pin that enables EEPROM program mat selecting when the

EXTEEP pin = “H”.

Connect a 256K-bit EEPROM and bring the MATSEL pin = “L” when not selecting the EEPROM mat.

Connect a 1M-bit EEPROM and bring the MATSEL pin = “H” when selecting the EEPROM mat. In

this case, the pin number 14 (MAT1) and 15 (MAT0) are address pins of the mat select.

Single program is stored in every 256K bits as a program map. The EEPROM can store four programs

in total. The MAT1 and MAT0 pins select a program to download to the AK7755. OUT3E bit

(CONT0A, D2) and OUT2E bit (CONT0A, D1) must not set to “1” when selecting an EEPROM mat

(MATSEL pin = “H”).

MAT1

(14pin)

MAT0

(15pin)

EEPROM Storing

Beginning Address

17’h00000

17’h08000

17’h10000

I²C 1st Byte

Program No.

1

2

3

4

0

1

0

1

0

1

“1 0 1 0 0 0 0 R/Wn

“1 0 1 0 0 0 1 R/Wn”

17’h18000

014006643-E-00

2014/10

- 98 -

[AK7755]

■ Digital Microphone Interface

1. Digital MIC Connection

Four digital microphones can be connected to the AK7755 at the maximum. When DMIC1 (CONT1E:

D7) or DMIC2 (CONT1E: D4) bit is set to “1”, the #34 pin becomes DMDAT1 (digital microphone data

input), the #33 pin becomes DMCLK1 (digital microphone clock supply) pins, the #32 pin becomes

DMDAT2 pin and the #31 pin becomes DMCLK2 pin.

The DMCLK1/2 clock is an input to a digital microphone from the AK7755. The digital microphone

outputs 1bit data, which is generated by Modulator using DMCLK1/2 clock, to the DMDAT1/2 pin.

DMIC1/2 bit controls power up/down of the digital block (Decimation Filter and Digital Filter).

DCLKE1/2 bit (CONT1E: D5/D2) controls ON/OFF of the output clock from the DMCLK1/2 pin. When

the AK7755 is powered down (PDN pin= “L”), the DMCLK1/2 and DMDAT1/2 pins become floating

state. Pull-down resistors must be connected to DMCLK and DMDAT pins externally to avoid this

floating state. Figure 76 shows a stereo 4ch connection example.

AVDD

AK7755

VDD

DMCLK1(64fs)

DMIC1 or DMIC2 bit = “1”



100k



AMP

Modulator

SDOUTAD

Decimation Digital

DMDAT1

Filter

Lch

100k

DMIC1 bit = “1”

VDD





Modulator

AMP

Rch

VDD

DMCLK2(64fs)

DMIC1 or DMIC2 bit = “1”



100k



AMP

Modulator

Decimation Digital

SDOUTAD2

DMDAT2

Filter

Lch

100k

DMIC2 bit = “1”

VDD





AMP

Modulator

Rch

Figure 76. Connection Example for 4ch Stereo Digital Microphone

014006643-E-00

2014/10

- 99 -

[AK7755]

2. Interface

The input data channel of the DMDAT1/2 pin is set by DCLKP1/2 bit (CONT1E: D6/D3). When

DCLKP1/2 bit = “1”, L channel data is input to the decimation filter if the DMCLK1/2 pin= “H”, and R

channel data is input if the DMCLK1/2 = “L”. When DCLKP1/2 bit = “0”, R channel data is input to the

decimation filter while DMCLK1/2 pin= “H”, and L channel data is input while DMCLK1/2 pin= “L”.

The DMCLK1/2 pin only supports 64fs. It outputs “L” when DCLKE1/2 bit = “0”, and outputs 64fs clock

when DCLKE1/2 bit = “1”. The output data through “the Decimation and Digital Filters” is 24bit full

scale when the 1bit data density is 0%~100%.

DCLKP1 bit

DMCLK1 pin = “H” DMCLK1 pin = “L”

0

1

Rch

Lch

Rch

(default)

DCLKP2 bit DMCLK2 pin = “H” DMCLK2 pin = “L”

0

1

Rch

Lch

Rch

(default)

Table 13. Data Input/Output Timing with Digital MIC

DMCLK1/2(64fs)

DMDAT1/2(Lch)

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

DMDAT1/2(Rch)

Figure 77. Data Input/Output Timing with Digital MIC (DCLKP1/2 bit = “1”)

DMCLK1/2(64fs)

Valid

Data

Valid

Data

Valid

Data

Valid

Data

DMDAT1/2(Lch)

DMDAT1/2(Rch)

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Figure 78. Data Input/Output Timing with Digital MIC (DCLKP1/2 bit = “0”)

■ Digital Mixer

ADC output (SDATAD), ADC2 output (SDATAD2) and DSP-DOUT4 data can be mixed into a signle

serial data by a mixer circuit. SELMIX[2:0] bits (CONT09: D0, CONT08: D1, D0) control mixing

setting. Delay time of the mixer circuit is 4Ts (4/fs).

SELMIX SELMIX

MIXOUT Lch

MIXOUT Rch

mode

[2:0]

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

SDOUTAD Lch

SDOUTAD Lch/2 + SDOUTAD2 Lch/2

SDOUTAD Rch

(default)

SDOUTAD Lch/2 + SDOUTAD2 Lch/2

SDOUTAD2 Rch

DSP-DOUT4 Rch

SDOUTAD Rch

SDOUTAD Lch

SDOUTAD2 Lch

DSP-DOUT4 Lch

SDOUTAD2 Lch

DSP-DOUT4 Lch

SDOUTAD Lch

DSP-DOUT4 Rch

Table 14. Digital Mixer Output Setting

014006643-E-00

2014/10

- 100 -

[AK7755]

10. Recommended External Circuits

■ Connection Diagram

1. I2CSEL pin = “L”, LDOE pin = “L”

3

“L”

I2CSEL

LDOE

CSN

23

20

19

18

17

6

CLOCK

&

9

CLKO

8

BICK

7

LRCK

16

15

14

5

SI

SDOUT1

SDOUT2

SDOUT3

SDIN1

SDIN2

uP

Audio I/F

SCLK

SO

4

STO/RDY

22

PDN

RESET

CONTROL

1

31

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

28

26

27

1

32

33

34

35

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

Digital Core 1.2V

24

DVDD

10

0.1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 79. Serial Interface Connection with External Power Supply

2. I2CSEL pin = “L”, LDOE pin = “H”

3

“L”

I2CSEL

LDOE

CSN

23

20

19

18

17

6

“H”

CLOCK

&

9

CLKO

8

BICK

7

LRCK

16

15

14

5

SI

SDOUT1

SDOUT2

SDOUT3

SDIN1

SDIN2

uP

Audio I/F

SCLK

SO

4

STO/RDY

22

PDN

RESET

CONTROL

1

31

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

28

26

27

1

32

33

34

35

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

24

AVDRV

1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

0.1

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 80. Serial Interface Connection with Internal LDO

014006643-E-00

2014/10

- 101 -

[AK7755]

3. I2CSEL pin = “H”, EXTEEP pin = “L”, LDOE pin = “L”

3

“H”

“L”

I2CSEL

LDOE

23

19

CLOCK

&

9

CLKO

8

“L”

BICK

EXTEEP

7

LRCK

16

15

14

SDOUT1

SDOUT2

SDOUT3

SDIN1

SDIN2

20

18

17

6

CAD

SCL

Audio I/F

uP

5

4

SDA

STO/RDY

22

RESET

1

31

PDN

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

CONTROL

32

33

34

35

1

28

26

27

1

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

Digital Core 1.2V

24

DVDD

10

0.1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 81. I²C Interface Connection with External Power Supply

4. I2CSEL pin = “H”, EXTEEP pin = “L”, LDOE pin = “H”

3

“H”

“L”

I2CSEL

LDOE

23

19

CLOCK

&

9

CLKO

8

BICK

EXTEEP

7

LRCK

16

15

14

5

SDOUT1

SDOUT2

SDOUT3

SDIN1

SDIN2

20

18

17

6

CAD

SCL

Audio I/F

uP

4

SDA

STO/RDY

22

RESET

1

31

PDN

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

CONTROL

32

33

34

35

1

28

26

27

1

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

24

AVDRV

1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

0.1

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 82. I²C Interface Connection with Internal LDO

014006643-E-00

2014/10

- 102 -

[AK7755]

5. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”, LDOE pin = “L”

3

“H”

“L”

I2CSEL

LDOE

23

19

20

CLOCK

&

9

CLKO

8

“H”

“L”

BICK

EXTEEP

MATSEL

7

LRCK

16

15

14

5

SDOUT1

SDOUT2

SDOUT3

SDIN1

SDIN2

Audio I/F

uP

18

17

6

4

SCL

SDA

EEPROM

256Kbit

STO/RDY

1

31

22

RESET

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

PDN

CONTROL

32

33

34

35

1

28

26

27

1

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

Digital Core 1.2V

24

DVDD

10

0.1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 83. I²C Interface Connection with External Power Supply and EEPROM

6. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”, LDOE pin = “H”

3

“H”

I2CSEL

LDOE

23

19

20

CLOCK

&

9

CLKO

8

“H”

“L”

BICK

EXTEEP

MATSEL

7

LRCK

16

15

14

5

SDOUT1

SDOUT2

SDOUT3

SDIN1

SDIN2

Audio I/F

uP

18

17

6

4

SCL

SDA

EEPROM

256Kbit

STO/RDY

1

31

22

RESET

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

PDN

CONTROL

32

33

34

35

1

28

26

27

1

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

24

AVDRV

1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

0.1

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 84. I²C Interface Connection with Internal LDO and EEPROM

014006643-E-00

2014/10

- 103 -

[AK7755]

7. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”, LDOE pin = “L”

3

“H”

“L”

I2CSEL

LDOE

23

19

20

CLOCK

&

9

CLKO

BICK

8

“H”

EXTEEP

MATSEL

7

16

LRCK

SDOUT1

Audio I/F

5

4

uP

SDIN1

SDIN2

18

17

6

SCL

SDA

EEPROM

1Mbit

STO/RDY

MAT0

15

14

MAT1

1

31

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

RESET

CONTROL

22

32

33

34

35

PDN

1

28

26

27

1

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

Digital Core 1.2V

24

DVDD

10

0.1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 85. I²C Interface Connection with External Power Supply and EEPROM (Mat Select ON)

8. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”, LDOE pin = “H”

3

“H”

I2CSEL

LDOE

23

19

20

CLOCK

&

9

CLKO

BICK

8

“H”

EXTEEP

MATSEL

7

16

LRCK

SDOUT1

Audio I/F

5

4

uP

SDIN1

SDIN2

18

17

6

SCL

SDA

EEPROM

1Mbit

STO/RDY

MAT0

15

14

MAT1

1

31

IN4/INN2

IN3/INP2

IN2/INN1

IN1/INP1

LIN

22

RESET

CONTROL

32

33

34

35

PDN

1

28

26

27

1

OUT1

OUT2

OUT3

1

1

AK7755

VCOM

2.2

24

AVDRV

1

Analog +3.3V

21,29,36

Digital IO 1.8～3.3V

10

AVDD

AVSS

12

10

0.1

TVDD

DVSS

0.1

2,30

13,25

Rd

10

11

XTO

XTI

CL=22pF/15pF

Figure 86. I²C Interface Connection with Internal LDO and EEPROM (Mat Select ON)

014006643-E-00

2014/10

- 104 -

[AK7755]

■ Peripheral Circuit

1. Ground

AVSS and DVSS must be connected to the same analog ground plane. Decoupling capacitors,

particularly small capacity capacitors, should be connected as close as possible to the AK7755.

2. Reference Voltage

The AVDD voltage controls analog signal range. VCOM is a common voltage of this chip and the

VCOM pin outputs AVDD/2. A 2.2µF ceramic capacitor connected between the VCOM and AVSS pins

eliminates the effects of high frequency noise. The ceramic capacitor should be connected as close as

possible to the VCOM pin. The VCOM pin must not be connected to external circuits. Digital signal

lines, especially clock signal line should be kept away as far as possible from the VCOM pin in order to

avoid unwanted coupling into the AK7755.

3. Analog Input

Analog input signals are applied to the modulator through the input pin of each channel. Input voltage is

±FS = ±(AVDD-AVSS) x 2.2/3.3 for differential pin and FS = (AVDD-AVSS) x 2.2/3.3 for single-end

pin. When AVDD = 3.3V and AVSS=0.0V, the differential input range is ±2.20Vpp (typ) and it is

2.20Vpp (typ) for single-ended input. The digital output code format is 2's complements. DC offset can

be cancelled by an internal HPF.

The AK7755 samples the analog inputs in 3.072MHz at fs = 48kHz. The digital filter removes noise in

the range from 30kHz to 3.042MHz. The AK7755 includes an anti-aliasing filter (RC filter) to attenuate

a noise around the range from 3.042MHz to 3.072MHz witch is not removed by the HPF. An external

Low Pass Filter is not necessary since most of audio signals do not have large noise in the band around

3.072MHz. However, it is recommended to connect a Low Pass Filter before the ADC when a signal

with large out-of-band noises is input.

The analog source voltage to the AK7755 is +3.3V (typ). Voltage of AVDD + 0.3V or more, voltage of

AVSS – 0.3V or less, and current of 10mA or more must not be applied to analog input pins. Excessive

current will damage the internal protection circuit and will cause latch-up, damaging the IC. If the

external analog circuit voltage is ±15V, the analog input pins must be protected from signals which are in

absolute maximum rating level or more.

10k

68p

22μ

2.20Vpp

10k

+

10k

-

+

Signal

+

-

INP*

+

1μ

+

INN*

1μ

2.20Vpp

Figure 87. Input Buffer Circuit Example (Differential Input)

014006643-E-00

2014/10

- 105 -

[AK7755]

4. Analog Output

The analog line-outputs are single-ended. The output signal range is 0.76 × AVDD Vpp (typ.) centered

around VCOM voltage. The input code format is in 2’s complement. The output voltage is a positive full

scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal voltage at 000000H

is VCOM. The VCOM voltage is AVDD/2 (typ). The internal switched-capacitor filter (SCF) and

continuous-time filter (CTF) attenuate the noise generated by the delta-sigma modulator beyond the audio

passband.

5. Connection to Digital Circuit

To minimize the noise from digital circuits, the digital output of the AK7755 must be connected to CMOS

or low voltage logic ICs such as 74HC and 74AC for CMOS and 74LV, 74LV-A, 74ALVC and 74AVC for

low voltage logic ICs.

6. Cristal Oscillator

The resistor and capacitor values for the oscillator RC circuit are shown blow.

TVDD = 3.0 - 3.6V

XTAL

Oscillator

12.288MHz

18.432MHz

XTI, XTO pin

Connection Capacity

22pF

CKM mode

R1_max

C0_max

0

1

120Ω

80Ω

2.5pF

15pF

TVDD = 1.7 - 3.0V

CKM mode

XTAL

XTI, XTO pin

Connection Capacity

10pF

R1_max

C0_max

Oscillator

12.288MHz

18.432MHz

1.2pF

0

1

50Ω

25Ω

10pF

Table 15. Crystal Oscillator

014006643-E-00

2014/10

- 106 -

[AK7755]

11. Package

■ Outline Dimensions

■ Package & Lead frame material

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

014006643-E-00

2014/10

- 107 -

[AK7755]

■ Marking

AKM

7755EN

XXXX

36

1

1) Pin #1 indication

2) Date Code: XXXX(4 digits)

3) Marking Code: 7755EN

AKM

7755VN

XXXX

36

1

1) Pin #1 indication

2) Date Code: XXXX(4 digits)

3) Marking Code: 7755VN

014006643-E-00

2014/10

- 108 -

[AK7755]

12. Revision History

Date (Y/M/D) Revision Reason

14/10/20 00 First Edition

Page Contents

IMPORTANT NOTICE

0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the

information contained in this document without notice. When you consider any use or application

of AKM product stipulated in this document (“Product”), please make inquiries the sales office of

AKM or authorized distributors as to current status of the Products.

1. All information included in this document are provided only to illustrate the operation and

application examples of AKM Products. AKM neither makes warranties or representations with

respect to the accuracy or completeness of the information contained in this document nor grants

any license to any intellectual property rights or any other rights of AKM or any third party with

respect to the information in this document. You are fully responsible for use of such information

contained in this document in your product design or applications. AKM ASSUMES NO

LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM

THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.

2. The Product is neither intended nor warranted for use in equipment or systems that require

extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which

may cause loss of human life, bodily injury, serious property damage or serious public impact,

including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace

industry, medical equipment, equipment used for automobiles, trains, ships and other

transportation, traffic signaling equipment, equipment used to control combustions or explosions,

safety devices, elevators and escalators, devices related to electric power, and equipment used in

finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in

writing.

3. Though AKM works continually to improve the Product’s quality and reliability, you are

responsible for complying with safety standards and for providing adequate designs and safeguards

for your hardware, software and systems which minimize risk and avoid situations in which a

malfunction or failure of the Product could cause loss of human life, bodily injury or damage to

property, including data loss or corruption.

4. Do not use or otherwise make available the Product or related technology or any information

contained in this document for any military purposes, including without limitation, for the design,

development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or

missile technology products (mass destruction weapons). When exporting the Products or related

technology or any information contained in this document, you should comply with the applicable

export control laws and regulations and follow the procedures required by such laws and

regulations. The Products and related technology may not be used for or incorporated into any

products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or

foreign laws or regulations.

5. Please contact AKM sales representative for details as to environmental matters such as the RoHS

compatibility of the Product. Please use the Product in compliance with all applicable laws and

regulations that regulate the inclusion or use of controlled substances, including without limitation,

the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of

noncompliance with applicable laws and regulations.

6. Resale of the Product with provisions different from the statement and/or technical features set

forth in this document shall immediately void any warranty granted by AKM for the Product and

shall not create or extend in any manner whatsoever, any liability of AKM.

7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior

written consent of AKM.

014006643-E-00

2014/10

- 109 -


型号：	AK7755EN
厂家：	ASAHI KASEI MICROSYSTEMS
描述：	Consumer Circuit, PQCC36, QFN-36 商用集成电路
文件：	总109页 (文件大小：2295K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AK7755EN [AKM]

相关型号：

AK7755EN_16

AK7756

AK7756EN

AK7756VF

AK7757VQ

AK7758

AK7758VN

AK7770EQ

AK7780

AK7780VQ

AK7782

AK7782VQ