AKD4554-E [AKM]
Evaluation board Rev.0 for AK4554; 评估板Rev.0的AK4554
| 型号： | AKD4554-E |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Evaluation board Rev.0 for AK4554 |
| 文件： | 总27页 (文件大小：823K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AKD4554]
AKD4554-E
Evaluation board Rev.0 for AK4554
GENERAL DESCRIPTION
AKD4554-E is an evaluation board for the portable digital audio 16bit A/D and D/A converter, AK4554.
The AKD4554-E can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly.
The AKD4554 has the interface with AKM’s ADC evaluation boards. Therefore, it’s easy to evaluate the
D/A section. The AKD4554-E also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
Ordering guide
AKD4554 -E --- Evaluation board for AK4554
FUNCTION
• Compatible with 2 types of interface
- Direct interface with AKM’s A/D & D/A converter evaluation boards
- DIT/DIR with optical input/output
REG
VDD
AGND DGND
Opt In
Regulator
AK4114
DIT/DIR
Opt Out
AINL/
AINR
AK4554
AOUTL/
AOUTR
10pin Header
DSP
Figure 1. AKD4554-E Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM077900>
2005/03
- 1 -
ASAHI KASEI
[AKD4554]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
[VDD] (Orange)
[REG] (Red)
[AGND] (Black)
[DGND] (Black)
= 1.6 ∼ 3.6V : for VDD of AK4554
= 5.0V
= 0V
: for regulator
: for analog ground (including VSS of AK4554)
: for logic ground
= 0V
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4554 should be reset once bringing SW2 (PDN) “OFF” upon power-up.
<KM077900>
2005/03
- 2 -
ASAHI KASEI
[AKD4554]
Evaluation mode
Applicable Evaluation Mode
1) Evaluation of loopback mode (default)
2) Evaluation of D/A using A/D converted data
3) Evaluation of D/A using DIR (Optical Link)
4) Evaluation of A/D using D/A converted data
5) Evaluation of A/D using DIT (Optical Link)
6) All interface signals including master clock are fed externally.
5)
AKD43XX
4)
D/A Board
PORT2
DIT
PORT3
AKD4554-E
10pin-Header
1)
CD Player
PORT1
DIR
3)
AKD53XX
A/D Board
2)
1) Evaluation of loopback mode. (default)
Nothing should be connected to PORT1/PORT3.
JP4
JP5
JP6
JP7
MCLK
SCLK
LRCK
SDTI
DIR
ADC
<KM077900>
2005/03
- 3 -
ASAHI KASEI
[AKD4554]
2) Evaluation of D/A using A/D converted data.
D/A part can be evaluated by connecting with AKM’s A/D evaluation boards via PORT3.
Nothing should be connected to PORT1
JP4
JP5
JP6
JP7
MCLK
SCLK
LRCK
SDTI
DIR
ADC
3) Evaluation of D/A using DIR. (Optical link)
PORT1 (TORX141) is used. DIR generates MCLK, SCLK, LRCK and SDATA from the received data
through optical connector (TORX141). Used for the evaluation using CD test disk. Nothing should be
connected to PORT2/PORT3.
JP4
JP5
JP6
JP7
MCLK
SCLK
LRCK
SDTI
DIR
ADC
4) Evaluation of A/D using D/A converted data.
A/D part can be evaluated by connecting with AKM’s D/A evaluation boards via PORT3.
Nothing should be connected to PORT1.
JP4
JP5
JP6
JP7
MCLK
SCLK
LRCK
SDTI
DIR
ADC
<KM077900>
2005/03
- 4 -
ASAHI KASEI
[AKD4554]
5) Evaluation of A/D using DIT. (Optical link)
PORT2 (TOTX141) is used. DIT generates audio bi-phase signal from received data and which is output
through optical connector (TOTX141). It is possible to connect AKM’s D/A converter evaluation boards
on the digital-amplifier, which equips DIR input.
JP4
JP5
JP6
JP7
MCLK
SCLK
LRCK
SDTI
DIR
ADC
6) All interfacing signals (MCLK, SCLK, LRCK) are fed from the external circuit through PORT3.
Under the following set-up, all external signals needed for the AK4554 to operate could be fed through
PORT3.
JP4
JP5
JP6
JP7
MCLK
SCLK
LRCK
SDTI
DIR
ADC
<KM077900>
2005/03
- 5 -
ASAHI KASEI
[AKD4554]
DIP switch set up
Upper-side is “ON” (“H”) and lower side is “OFF” (“L”).
[SW1]: Set up the AK4554 and AK4114.
.
SW No.
SW Name
Mode
AK4554 and AK4114 Audio Format Setting
Always OFF.
1
DIF2, 0
2
3
DEM1
DEM0
Set up the de-emphasis of AK4554
(See table 2)
4
NC
No use
Table 1. DIPswitch set-up of AK4114
DEM1
(SW1-#2)
DEM0
(SW1-#3)
OFF
Mode
OFF
OFF
44.1kHz
OFF
ON
ON
ON
OFF
ON
48kHz
32kHz
Table 2. DIPswitch set up of de-emphasis
<KM077900>
2005/03
- 6 -
ASAHI KASEI
[AKD4554]
Other jumper pins set up
[JP1] (GND): Connection between AGND and DGND
open:Both grounds are separated on board.<default>
short: Both grounds are connected on board.
[JP2] (REG): Select to regulator
open:On-board regulator is not used. <default>
short: On-board regulator is used.(The connector “VDD” can be open.)
[JP3] (PWR): Pull up power supply select for SDTO.
VDD: Connected to VDD of AK4554. <default>
D3V: Supplied from regulator (3V).
The function of the toggle SW.
Upper-side is “ON” and lower side is “OFF”.
[SW2] (PDN):
Resets the AK4554 and AK4114. Keep “ON” during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
<KM077900>
2005/03
- 7 -
ASAHI KASEI
[AKD4554]
Input Circuit
C28
4.7u
J1
6
AINR
4
3
R20
560
AINL/AINR
C29
4.7u
AINL
R21
560
Figure 2. Input circuit on board
Output Circuit
R24
220
J2
6
AOUTR
4
3
C30
22u
R23
10k
AOUTL/AOUTR
R25
220
AOUTL
C31
22u
R22
10k
Figure 3. Output circuit on board
* AKM assumes no responsibility for the trouble when using the circuit examples.
<KM077900>
2005/03
- 8 -
ASAHI KASEI
[AKD4554]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit : Audio Precision, System two
• MCLK
• SCLK
: 256fs
: 64fs
• fs
: 44.1kHz
• Bit
: 16bit
• Power Supply
• Interface
• Temperature
: VDD = VP = 2.5V, VD = 5V
: DIT/DIR
: Room
1. ADC
VDD
2.5V
Parameter
Measured Filter
20kHz LPF
20kLPF + A-weighted
20kLPF + A-weighted
AINL
AINR
81.0 dB
89.2 dB
89.2 dB
S/(N+D) (-0.5dBFS)
D-Range (-60dBFS)
S/N (0 data)
80.9 dB
89.4 dB
89.3 dB
2. DAC
VDD
2.5V
Parameter
S/(N+D) (0dBFS)
D-Range (-60dBFS)
S/N (0 data)
Measured Filter
20kHz LPF
22kLPF + A-weighted
AOUTL
84.5 dB
91.6 dB
91.9 dB
AOUTR
84.5 dB
91.7 dB
92.1 dB
22kLPF + A-weighted
<KM077900>
2005/03
- 9 -
ASAHI KASEI
[AKD4554]
3.PLOT DATA
3-1 ADC
AKM
AK4554 ADC THD+N vs.Input Level
VDD=2.5V, fs=44.1kHz, fin=1kHz
-60
-62
-64
-66
-68
-70
-72
d
B
-74
F
-76
S
-78
-80
-82
-84
-86
-88
-90
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Fig. 1 THD+N vs. Input Level
AKM
AK4554 ADC THD+N vs. Input Frequency
VDD=2.5V, fs=44.1kHz, Input Level=-0.5dB
-60
-62
-64
-66
-68
-70
-72
d
B
-74
F
-76
S
-78
-80
-82
-84
-86
-88
-90
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.2 THD+N vs. Input Frequency
<KM077900>
2005/03
- 10 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 ADC Linearity
VDD=2.5V, fs=44.1kHz, fin=1kHz
+0
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Fig.3 Linearity
AKM
AK4554 ADC Frequency Response
VDD=2.5V, fs=44.1kHz, Input level=-0.5dB
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
d
B
F
S
-2.2
-2.4
-2.6
-2.8
-3
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.4 Frequency Response
<KM077900>
2005/03
- 11 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 ADC FFT Plot
VDD=2.5V, fs=44.1kHz, fin=1kHz, Input Level=-0.5dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
-80
F
S
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.5 FFT Plot (Input Level = -0.5dB)
AKM
AK4554 ADC FFT Plot
VDD=2.5V, fs=44.1kHz, fin=1kHz, Input Level=-60dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
-80
F
S
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.6 FFT Plot (Input Level = -60dB)
<KM077900>
2005/03
- 12 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 ADC FFT
VDD=2.5V, fs=44.1kHz, Input Level=-0.5dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
-80
F
S
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.7 FFT Plot (no signal)
Fig.8 Crosstalk (red : L--->R, blue : R--->L)
<KM077900>
2005/03
- 13 -
ASAHI KASEI
[AKD4554]
3-2. DAC
AKM
AK4554 DAC THD+N vs. Input Level
VDD=2.5V, fs=44.1kHz, fin=1kHz
-60
-62
-64
-66
-68
-70
-72
-74
-76
d
B
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
r
A
-100
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Fig.9 THD+N vs. Input Level
AKM
AK4554 DAC THD+N vs. Input Frequency
VDD=2.5V, fs=44.1kHz, Input Level=0dB
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
r
A
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.10 THD+N vs. Input Frequency
<KM077900>
2005/03
- 14 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 DAC Linearity
VDD=2.5V, fs=44.1kHz, fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
-60
-70
r
A
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Fig.11 Linearity
AKM
AK4554 DAC Frequency Response
VDD=2.5V, fs=44.1kHz, Input Level=0dB
+1
+0.9
+0.8
+0.7
+0.6
+0.5
+0.4
+0.3
+0.2
+0.1
+0
d
B
r
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
A
-1
2k
4k
6k
8k
10k
Hz
12k
14k
16k
18k
20k
Fig.12 Frequency Response
<KM077900>
2005/03
- 15 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 DAC FFT Plot
VDD=2.5V, fs=44.1kHz,fin=1kHz, Input Level=0dB
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.13 FFT Plot (Input Level = 0dB)
AKM
AK4554 DAC FFT Plot
VDD=2.5V, fs=44.1kHz,fin=1kHz, Input Level=-60dB
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.14 FFT Plot (Input Level = -60dB)
<KM077900>
2005/03
- 16 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 DAC FFT
VDD=2.5V, fs=44.1kHz, Input Level=0dB
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig.15 FFT Plot (no data)
Fig.16 Crosstalk (red : L--->R, blue : R--->L)
<KM077900>
2005/03
- 17 -
ASAHI KASEI
[AKD4554]
AKM
AK4554 DAC out-band-noise
VDD=2.5V, fs=44.1kHz, Input=no data
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Fig.17 Out band noise
<KM077900>
2005/03
- 18 -
ASAHI KASEI
[AKD4554]
Revision History
Date
(YY/MM/DD)
05/03/31
Manual
Revision
KM077900
Board
Revision
0
Reason
Contents
First Edtion
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM077900>
2005/03
- 19 -
A
B
C
D
E
REG
VDD
AGND
DGND
R2
220
C1
4.7u
J2
T45_R
T45_O
T45_BK T45_BK
6
J1
6
C2
R1
4
3
4
3
22u
10k
R3
560
AOUTL/AOUTR
R4
220
AINL/AINR
REG
(5V)
VA
E
D
C
B
A
E
D
C
B
A
(1.6-3.6V)
C4
4.7u
C3
22u
R5
10k
REG
JP1
GND
R6
560
DGND
AGND
T1
TA4803F
IN
OUT
VD
C5
0.1u
C7
+
47u
C8
C6
0.1u
0.1u
U1
1
16
15
14
13
12
11
10
9
VCOM
AINR
AINL
AOUTR
AOUTL
PWDAN
PWADN
SCLK
VA
JP2
REG
2
3
4
5
6
7
8
L1
(short)
1
2
PWDAN
C10
47u
+
R7
5.1
VSS
C11
10u
C9
+
LVC
VDD
0.1u
R8 51
R9 51
R10 51
R12 51
VDD
BCLK
MCLK
LRCK
SDTI
DEM0
DEM1
SDTO
MCLK
LRCK
R11 51
SDTI
AK4554
DEM0
DEM1
4554_SDTO
Title
Size
AKD4554-E
Document Number
Rev
0
A3
AK4554
Date:
Sheet
E
of
Monday, February 28, 2005
1
4
A
B
C
D
A
B
C
D
E
VD
L2
47u
VD
E
D
C
B
A
E
D
C
B
A
PORT1
VCC
DIP SW
3
C14
10u
2
1
GND
OUT
C13
+
DIF2, 0
DEM1
DEM0
C12
0.1u
R13
470
10u
TORX141
C15
0.1u
AK4555
ON
OFF
OFF
ON
OFF
ON
44.1k
OFF
48k
AK4550/4
OFF
OFF
ON
ON
32k
C16
R14
18k
0.47u
VD
SW1
RP1
VD
4
3
2
1
DIF2,0
DEM 1
DEM 0
1
2
3
6
5
4
VD
U2
U3A
1
MODE2
R15
1k
LED1
ERF
47k
14
2
7
DEM0
DEM1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
2
1
IPS0
INT0
OCKS0
OCKS1
CM1
74HC14
NC
3
DIF0
TEST2
DIF1
NC
4
5
CM0
4114_PDN
6
TP1 EXTCLK
PDN
1
C17
5p
AK4114
7
DIF2
IPS1
P/SN
XTL0
XTL1
VIN
XTI
X1
11.2896MHz
C18
5p
8
XTO
9
DAUX
MCKO2
BICK
SDTO
10
11
12
VD
DIR_BICK
SDTO
DIR_SDTO
C19
0.1u
C20
DIR_LRCK
DIR_MCKO
0.1u
VD
VD
C21
10u
C22
10u
R16
5.1
PORT2
3
2
IN
VD
VCC
1
GND
TOTX141
C23
0.1u
Title
Size
AKD4554-E
Document Number
Rev
0
A3
DIR/DIT
Date:
Sheet
E
of
Monday, February 07, 2005
2
4
A
B
C
D
A
B
C
D
E
E
D
C
B
A
E
D
C
B
A
JP3 PWR
VDD
D3V
VDD
VD
R17
1k
U4
7
2
14
U5A
1
4554_SDTO
LVC
SDTO
74LVC07ANS
11
12
13
14
15
16
17
18
10
20
9
8
7
6
5
4
3
2
19
1
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
A8
A7
A6
A5
A4
A3
A2
A1
G2
G1
PWDAN
JP4MCLK
JP5SCLK
JP6LRCK
DIR_MCKO
DIR_BICK
DIR_LRCK
MCLK
BCLK
LRCK
SDTI
GND
C24
0.1u
PORT3
MCLK
BICK
LRCK
SDTI
VD
1
2
3
4
5
10 GND
9
8
7
6
GND
VCC
NC
NC
VD
SDTO
LVC
74LVC541
DSP
R19
10k
R18
10k
VD
D1
1S1588
VD
U3B
14
U3C
5
14
6
7
3
4
7
4114_PDN
74HC14
74HC14
L
H
ADC
SDTO
SW2
PDN
C25
0.1u
for
74HC14
for
JP7
SDTI
74LVC07ANS
VD
LVC
DIR_SDTO
DIR
C26
0.1u
C27
0.1u
Title
Size
AKD4554-E
Document Number
Rev
0
A3
LOGIC
Date:
Sheet
of
4
Monday, February 07, 2005
3
A
B
C
D
E
A
B
C
D
E
E
D
C
B
A
E
D
C
B
A
VD
LVC
U5B
U5C
U5D
U5E
U5F
7
4
14
3
5
74LVC07ANS
74LVC07ANS
74LVC07ANS
74LVC07ANS
74LVC07ANS
7
6
14
U3D
9
14
8
7
7
8
14
9
74HC14
7
10
14
U3E
11
14
10
7
11
13
74HC14
7
12
14
U3F
13
14
12
7
74HC14
Title
Size
AKD4554-E
Document Number
Rev
0
A3
PIN
Date:
Sheet
of
Monday, February 07, 2005
4
4
A
B
C
D
E
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