AKD4626 [AKM]
High Performance Multi-channel Audio CODEC; 高性能多通道音频编解码器
| 型号： | AKD4626 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | High Performance Multi-channel Audio CODEC |
| 文件： | 总40页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK4626A]
AK4626A
High Performance Multi-channel Audio CODEC
GENERAL DESCRIPTION
The AK4626A is a single chip CODEC that includes two channels of ADC and six channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the newly developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input
interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control
may be set directly by pins or programmed through a separate serial interface.
The AK4626A has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital
surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver
such as the AK4112B. The AK4626A is available in a small 44pin LQFP package which will reduce
system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
- Overflow flag
6ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
High Jitter Tolerance
TTL Level Digital I/F
3-wire Serial and I2C Bus µP I/F for mode setting
Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
128fs for fs=120kHz to 192kHz
Power Supply: 4.5 to 5.5V
Power Supply for output buffer: 2.7 to 5.5V
Small 44pin LQFP
AK4626 Pin Compatible
MS0397-E-00
2005/06
- 1 -
ASAHI KASEI
[AK4626A]
Block Diagram
Audio
I/F
LIN
ADC
ADC
HPF
HPF
RIN
RX1
XTI
RX2
RX3 RX4
XTO
DIR
MCLK
LRCK
BICK
LOUT1
ROUT1
LPF
LPF
DAC
DAC
DATT
DATT
MCLK
MCKO
LRCK
BICK
AK4112B
LRCK
BICK
DAUX
SDTO
LOUT2
ROUT2
LPF
LPF
LPF
LPF
DAC
DAC
DAC
DAC
DATT
DATT
DATT
DATT
Format
Converter
LRCK
BICK
SDOUT
AC3
SDOS
SDTO
LOUT3
ROUT3
SDIN
SDTI1
SDTI2
SDTI3
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
SDIN3
AK4626A
Block Diagram (DIR and AC-3 DSP are external parts)
MS0397-E-00
2005/06
- 2 -
ASAHI KASEI
[AK4626A]
Ordering Guide
AK4626AVQ
AKD4626
-40 ∼ +85°C
44pin LQFP(0.8mm pitch)
Evaluation Board for AK4626A
Pin Layout
SDOS
I2C
1
33
32
31
30
29
28
27
26
25
24
23
DZF2/OVF
RIN
2
SMUTE
BICK
3
LIN
4
NC
AK4626AVQ
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS0
5
TST5
6
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
7
Top View
8
9
10
11
MS0397-E-00
2005/06
- 3 -
ASAHI KASEI
[AK4626A]
Compatibility with AK4527B
1. Functions
Functions
AK4527B
Up to 96kHz
Not available
256 levels
Soft mute function is independent of
Digital attenuator.
Differential input
AK4626A
Up to 192kHz
Available
128 levels
Soft mute function is not independent of
Digital attenuator.
DAC Sampling frequency
TDM128 (96kHz)
Digital Attenuator
Soft Mute
Analog Input (ADC)
Single-ended Input
2. Pin Configuration
pin#
11
12
18
19
20
21
22
29
30
31
32
44
AK4527B
DFS
NC
TEST
NC
ADIF
CAD1
CAD0
LIN-
LIN+
RIN-
RIN+
LOOP1
AK4626A
DFS0
TST1
TST2
CAD1
CAD0
TST3
TST4
TST5
NC
LIN
RIN
TDM0
3. Register
Addr
AK4527B
AK4626A
TDM0
TDM1
00H
00H
01H
Not available
Not available
DFS
DFS0
01H
09H
0AH
Not available
Not available
Not available
DFS1
ATS1, ATS0
DZFM3
MS0397-E-00
2005/06
- 4 -
ASAHI KASEI
No. Pin Name
[AK4626A]
PIN/FUNCTION
I/O
I
Function
(Note 1)
1
SDOS
SDTO Source Select Pin
“L”: Internal ADC output, “H”: DAUX input
SDOS pin should be set to “L” when TDM= “1”.
Control Mode Select Pin
2
3
I2C
I
I
“L”: 3-wire Serial, “H”: I2C Bus
SMUTE
Soft Mute Pin
(Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
Audio Serial Data Clock Pin
4
5
6
7
8
9
BICK
I
I
I
I
I
O
I
I
LRCK
SDTI1
SDTI2
SDTI3
SDTO
Input Channel Clock Pin
DAC1 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
Audio Serial Data Output Pin
10 DAUX
11 DFS0
AUX Audio Serial Data Input Pin
Double Speed Sampling Mode Pin (Note 1)
“L”: Normal Speed, “H”: Double Speed
Test Pin
This pin should be connected to DVSS.
Zero Input Detect Enable Pin
12 TST1
13 DZFE
I
I
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
14 TVDD
15 DVDD
16 DVSS
17 PDN
-
-
-
I
Output Buffer Power Supply Pin, 2.7V∼5.5V
Digital Power Supply Pin, 4.5V∼5.5V
Digital Ground Pin, 0V
Power-Down & Reset Pin
When “L”, the AK4626A is powered-down and the control registers are reset to default
state. If the state of P/S or CAD1-0 changes, then the AK4626A must be reset by PDN.
18 TST2
I
Test Pin
This pin should be connected to DVSS.
19 CAD1
20 CAD0
21 TST3
I
I
O
Chip Address 1 Pin
Chip Address 0 Pin
Test Pin
This pin should be left floating.
22 TST4
O
Test Pin
This pin should be left floating.
MS0397-E-00
2005/06
- 5 -
ASAHI KASEI
[AK4626A]
No. Pin Name
23 LOUT3
24 ROUT3
25 LOUT2
26 ROUT2
27 LOUT1
28 ROUT1
29 TST5
I/O
O
O
O
O
O
O
I
Function
DAC3 Lch Analog Output Pin
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
Test pin (Internal pull-down pin)
This pin should be left floating or connected to AVSS.
30 NC
-
No Connect
No internal bonding.
31 LIN
32 RIN
33 DZF2
I
I
O
Lch Analog Input Pin
Rch Analog Input Pin
Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to
“H”. It always is in “L” when P/S is “H”.
OVF
O
O
Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the analog input of Lch or Rch overflows.
Common Voltage Output Pin, AVDD/2
34 VCOM
Large external capacitor around 2.2µF is used to reduce power-supply noise.
Positive Voltage Reference Input Pin, AVDD
Analog Power Supply Pin, 4.5V∼5.5V
35 VREFH
36 AVDD
37 AVSS
38 DZF1
I
-
-
Analog Ground Pin, 0V
O
Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to
“H”. Output is selected by setting DZFE pin when P/S is “H”.
Master Clock Input Pin
39 MCLK
40 P/S
I
I
Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
Audio Data Interface Format 0 Pin in parallel control mode
Chip Select Pin in 3-wire serial control mode
41 DIF0
CSN
I
I
This pin should be connected to DVDD at I2C bus control mode
Audio Data Interface Format 1 Pin in parallel control mode
Control Data Clock Pin in serial control mode
42 DIF1
SCL/CCLK
I
I
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus)
Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 3 DACs.
43 LOOP0
SDA/CDTI
44 TDM0
I
I/O Control Data Input Pin in serial control mode
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus)
I
TDM I/F Format Mode Pin (Note 1)
“L”: Normal mode, “H”: TDM mode
Notes: 1. SDOS, SMUTE, DFS0, and TDM0 pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All digital input pins except for pull-down should not be left floating.
MS0397-E-00
2005/06
- 6 -
ASAHI KASEI
[AK4626A]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 5)
Parameter
Power Supplies
Symbol
AVDD
DVDD
TVDD
∆GND
IIN
min
-0.3
-0.3
-0.3
-
max
6.0
6.0
6.0
0.3
Units
V
V
V
V
mA
V
Analog
Digital
Output buffer
|AVSS-DVSS|
(Note 6)
Input Current (any pins except for supplies)
Analog Input Voltage
-
±10
AVDD+0.3
VINA
-0.3
Digital Input Voltage
(Expect LRCK, BICK pins)
(LRCK, BICK pins)
Ambient Temperature (power applied)
VIND1
VIND2
Ta
-0.3
-0.3
-40
-65
DVDD+0.3
TVDD+0.3
85
V
V
°C
°C
Storage Temperature
Tstg
150
Notes: 5. All voltages with respect to ground.
6. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 5)
Parameter
Power Supplies
(Note 7)
Symbol
AVDD
DVDD
TVDD
min
4.5
4.5
2.7
typ
5.0
5.0
5.0
max
5.5
5.5
Units
V
V
Analog
Digital
Output buffer
5.5
V
Notes: 5. All voltages with respect to ground.
7. The power up sequence between AVDD, DVDD and TVDD is not critical.
Do not turn off only the AK4626A under the condition that a surrounding device is powered on and the I2C bus
is in use.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0397-E-00
2005/06
- 7 -
ASAHI KASEI
[AK4626A]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz,
20Hz~40kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics
Resolution
24
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
S/(N+D)
(-0.5dBFS)
fs=48kHz
84
-
92
86
102
96
102
102
96
fs=96kHz
DR
(-60dBFS)
fs=48kHz, A-weighted
fs=96kHz
94
88
93
94
88
93
90
fs=96kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
S/N
(Note 8)
fs=96kHz, A-weighted
102
110
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
0.2
20
3.10
25
50
0.3
-
3.30
dB
ppm/°C
Vpp
Input Voltage
AIN=0.62xVREFH
2.90
15
Input Resistance
Power Supply Rejection
(Note 9)
(Note 10)
kΩ
dB
DAC Analog Output Characteristics
Resolution
24
Bits
90
88
88
S/(N+D)
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
80
78
-
95
88
94
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
106
100
106
100
106
DR
(-60dBFS)
-
106
100
106
100
106
S/N
(Note 11)
fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
95
88
94
-
-
90
fs=192kHz, A-weighted
Interchannel Isolation
110
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
0.2
20
3.0
0.5
-
3.25
dB
ppm/°C
Vpp
Output Voltage
AOUT=0.6xVREFH
2.75
5
Load Resistance
kΩ
Power Supply Rejection
(Note 10)
50
dB
Notes: 8. S/N measured by CCIR-ARM is 98dB(@fs=48kHz).
9. Input resistance is 16kΩ typically at fs=96kHz.
10. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage.
11. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
MS0397-E-00
2005/06
- 8 -
ASAHI KASEI
[AK4626A]
Parameter
min
typ
max
Units
Power Supplies
Power Supply Current (AVDD+DVDD+TVDD)
Normal Operation (PDN = “H”)
AVDD
fs=48kHz,96kHz
fs=192kHz
45
34
18
24
27
80
67
51
27
36
40
mA
mA
mA
mA
mA
µA
DVDD+TVDD fs=48kHz
fs=96kHz
(Note 12)
(Note 13)
fs=192kHz
Power-down mode (PDN = “L”) TST=”L”
200
Notes: 12. TVDD=0.1mA(typ).
13. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS.
MS0397-E-00
2005/06
- 9 -
ASAHI KASEI
[AK4626A]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 14)
PB
0
-
-
18.9
-
-
kHz
kHz
kHz
±0.1dB
-0.2dB
-3.0dB
20.0
23.0
Stopband
SB
PR
SA
GD
∆GD
28
68
kHz
dB
dB
1/fs
µs
Passband Ripple
Stopband Attenuation
Group Delay
±0.04
(Note 15)
16
0
Group Delay Distortion
ADC Digital Filter (HPF):
Frequency Response
(Note 14) -3dB
FR
1.0
6.5
Hz
Hz
-0.1dB
DAC Digital Filter:
Passband
(Note 14) -0.1dB
-6.0dB
PB
0
-
26.2
21.8
-
kHz
kHz
kHz
dB
dB
1/fs
24.0
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
±0.02
54
(Note 15)
19.2
DAC Digital Filter + Analog Filter:
±0.2
±0.3
±1.0
FR
FR
FR
dB
dB
dB
Frequency Response: 0 ∼ 20.0kHz
40.0kHz (Note 16)
80.0kHz (Note 16)
Notes:
14. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs.
15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to
setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog
signal.
16. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz.
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
VIH
VIL
min
2.2
-
typ
-
-
max
-
0.8
Units
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
(SDTO, LRCK, BICK pin:
(DZF1, DZF2/OVF pins:
Low-Level Output Voltage
(SDTO, DZF1, DZF2/OVF pins: Iout= 100µA)
Iout=-100µA)
Iout=-100µA)
VOH
VOH
TVDD-0.5
AVDD-0.5
-
-
-
-
V
V
VOL
VOL
Iin
-
-
-
-
-
-
0.5
0.4
±10
V
V
µA
(SDA, LRCK, BICK pin:
Iout= 3mA)
Input Leakage Current
(Note 17)
Note 17: TST2 pin has an internal pull-down device, nominally 100kohm.
MS0397-E-00
2005/06
- 10 -
ASAHI KASEI
[AK4626A]
SWITCHING CHARACTERISTICS
(Ta=-40°C∼85°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
256fsn, 128fsd:
fCLK
8.192
27
27
12.288
20
20
16.384
15
15
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd:
Pulse Width Low
Pulse Width High
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
18.432
24.576
tCLKL
tCLKH
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
“H” time
fsn
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
“L” time
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
“H” time
fsd
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
“L” time
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
LRCK to SDTO(MSB)
BICK “↓” to SDTO
(Note 18)
(Note 18)
40
40
SDTI1-3,DAUX Hold Time
SDTI1-3,DAUX Setup Time
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO
SDTI1 Hold Time
(Note 18)
(Note 18)
20
10
10
SDTI1 Setup Time
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO
(Note 18)
(Note 18)
20
SDTI1-2 Hold Time
10
10
SDTI1-2 Setup Time
Notes: 18. BICK rising edge must not occur at the same time as LRCK edge.
MS0397-E-00
2005/06
- 11 -
ASAHI KASEI
[AK4626A]
Parameter
Symbol
min
typ
max
Units
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
100
-
-
-
-
-
-
-
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 19)
1.0
0.3
-
tF
tSU:STO
tSP
4.0
0
Pulse Width of Spike Noise Suppressed by Input Filter
50
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
(Note 20)
(Note 21)
tPD
tPDV
150
ns
1/fs
522
Notes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. The AK4626A can be reset by bringing PDN “L” to “H” upon power-up.
21. These cycles are the number of LRCK rising from PDN rising.
22. I2C is a registered trademark of Philips Semiconductors.
MS0397-E-00
2005/06
- 12 -
ASAHI KASEI
[AK4626A]
Timing Diagram
1/fCLK
VIH
VIL
MCLK
LRCK
BICK
tCLKH
tCLKL
1/fsn, 1/fsd
VIH
VIL
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing (TDM= “0”)
1/fCLK
VIH
VIL
MCLK
LRCK
BICK
tCLKH
tCLKL
1/fs
VIH
VIL
tLRH
tLRL
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing (TDM= “1”)
MS0397-E-00
2005/06
- 13 -
ASAHI KASEI
[AK4626A]
VIH
VIL
LRCK
BICK
tBLR
tLRS
tLRB
VIH
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (TDM= “0”)
VIH
VIL
LRCK
BICK
tBLR
tLRB
VIH
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (TDM= “1”)
MS0397-E-00
2005/06
- 14 -
ASAHI KASEI
[AK4626A]
VIH
VIL
CSN
tCSS
tCCKL tCCKH
VIH
VIL
CCLK
CDTI
tCDS tCDH
C0
VIH
VIL
C1
R/W
A4
WRITE Command Input Timing (3-wire Serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
VIL
CCLK
CDTI
VIH
VIL
D3
D2
D1
D0
WRITE Data Input Timing (3-wire Serial mode)
VIH
SDA
SCL
VIL
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
tHD:STA
Stop Start
tHD:DAT
tPD
tSU:DAT tSU:STA
tSU:STO
Stop
Start
I2C Bus mode Timing
VIH
VIL
PDN
tPDV
SDTO
50%TVDD
Power-down & Reset Timing
MS0397-E-00
2005/06
- 15 -
ASAHI KASEI
[AK4626A]
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4626A, are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS = “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each
sampling speed is set automatically. (Table 2, 3, 4). In Auto Setting Mode (ACKS = “1”), as MCLK frequency is detected
automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to
set DFS.
External clocks (MCLK, BICK) should always be present whenever the AK4626A is in normal operation mode (PDN =
“H”). If these clocks are not provided, the AK4626A may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the AK4626A should be in the power-down mode (PDN
= “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4626A is in the power-down mode
until MCLK and LRCK are input.
DFS1
DFS0
Sampling Speed (fs)
Default
0
0
1
0
1
0
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK (MHz)
384fs
BICK (MHz)
64fs
256fs
8.1920
11.2896
12.2880
512fs
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
2.0480
2.8224
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
MCLK (MHz)
192fs
BICK (MHz)
64fs
128fs
256fs
88.2kHz
96.0kHz
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
5.6448
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)
LRCK
fs
MCLK (MHz)
BICK (MHz)
64fs
128fs
192fs
256fs
176.4kHz
192.0kHz
22.5792
24.5760
-
-
-
-
11.2896
12.2880
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
(Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.)
MS0397-E-00
2005/06
- 16 -
ASAHI KASEI
[AK4626A]
MCLK
512fs
256fs
128fs
Sampling Speed
Normal
Double
Quad
Table 5. Sampling Speed (Auto Setting Mode)
LRCK
fs
MCLK (MHz)
Sampling
Speed
128fs
256fs
512fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
16.3840
22.5792
24.5760
Normal
22.5792
24.5760
-
-
-
-
Double
Quad
-
22.5792
24.5760
-
-
Table 6. System Clock Example (Auto Setting Mode)
De-emphasis Filter
The AK4626A includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in
Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz,
48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2:
DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”).
Mode
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
DEM1
DEM0
DEM
44.1kHz
OFF
48kHz
32kHz
0
1
2
3
0
0
1
1
0
1
0
1
Default
Table 7. De-emphasis control
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and
scales with sampling rate (fs).
MS0397-E-00
2005/06
- 17 -
ASAHI KASEI
[AK4626A]
Audio Serial Interface Format
When TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is
MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are
latched on the rising edge of BICK.
Figures 1∼4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”,
the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input
formats can be used for 16-20bit data by zeroing the unused LSBs.
Mode
TDM0
DIF1
DIF0
SDTO
SDTI1-3,
DAUX
LRCK
I/O
BICK
TDM 1
I/O
I
24bit, Left
justified
24bit, Left
justified
20bit, Right
justified
24bit, Right
justified
0
1
0
0
0
0
0
0
0
1
H/L
H/L
I
I
≥ 48fs
I
≥ 48fs
24bit, Left
justified
24bit, Left
justified
Default
2
3
0
0
0
0
1
1
0
1
H/L
L/H
I
I
I
I
≥ 48fs
≥ 48fs
24bit, I2S
24bit, I2S
Table 8. Audio data formats (Normal mode)
The audio serial interface format becomes the TDM mode if TDM0 pin is set to “H”. In the TDM256 mode, the serial data
of all DAC (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins are ignored. BICK should be fixed to
256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown in
Table 9. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of
BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM mode.
TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four channels;
L1, R1, L2, R2) is input to the SDTI1 pin. Other two data (L3, R3) are input to the SDTI2. TDM0 pin and TDM0 register
should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register should be set to “H” if
Double Speed Mode is selected in TDM128 Mode.
Mode
TDM 1
TDM0
DIF1
DIF0
SDTO
SDTI1
LRCK
I/O
BICK
I/O
I
24bit, Left
justified
24bit, Left
justified
20bit, Right
justified
24bit, Right
justified
4
5
0
0
1
1
0
0
0
1
I
I
256fs
↑
↑
256fs
I
24bit, Left
justified
24bit, Left
justified
6
7
0
0
1
1
1
1
0
1
I
I
256fs
256fs
I
I
↑
↓
24bit, I2S
24bit, I2S
Table 9. Audio data formats (TDM256 mode)
Mode
TDM 1
TDM0
DIF1
DIF0
SDTO
SDTI1,
SDTI2
LRCK
BICK
I/O
I/O
I
24bit, Left
justified
24bit, Left
justified
20bit, Right
justified
24bit, Right
justified
8
9
1
1
1
1
0
0
0
1
I
128fs
128fs
↑
↑
I
I
24bit, Left
justified
24bit, Left
justified
10
11
1
1
1
1
1
1
0
1
I
I
128fs
128fs
I
I
↑
↓
24bit, I2S
24bit, I2S
Table 10. Audio data formats (TDM128 mode)
MS0397-E-00
2005/06
- 18 -
ASAHI KASEI
[AK4626A]
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
24
28
25
25
29
31
0
1
BICK(64fs)
23 22
12 11 10
19 18
0
23 22
12 11 10
19 18
Don’t Care
0
23
SDTO(o)
SDTI(i)
8
7
1
0
8
7
1
0
Don’t Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
31
0
1
BICK(64fs)
SDTO(o)
23 22
16 15 14
23 22
0
23 22
16 15 14
23 22
Don’t Care
0
23
8
7
1
0
8
7
1
0
Don’t Care
SDTI(i)
LRCK
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
23 22
2
2
1
1
0
0
23 22
23 22
2
2
1
1
0
0
23
23
Don’t Care
Don’t Care
SDTI(i)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
23 22
2
2
1
1
0
0
23 22
23 22
2
2
1
1
0
0
Don’t Care
Don’t Care
SDTI(i)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
MS0397-E-00
2005/06
- 19 -
ASAHI KASEI
[AK4626A]
256 BICK
LRCK
BICK(256fs)
SDTO(o)
23 22
0
23 22
0
23 22
Lch
Rch
32 BICK
32 BICK
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19
SDTI1(i)
R1
R2
R3
L1
L2
L3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 5. Mode 4 Timing
256 BICK
LRCK
BICK(256fs)
SDTO(o)
23 22
0
23 22
0
23 22
Lch
Rch
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
SDTI1(i)
R1
R2
R3
L1
L2
L3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 6. Mode 5 Timing
256 BICK
LRCK
BICK(256fs)
SDTO(o)
23 22
0
23 22
0
23 22
Lch
32 BICK
Rch
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
SDTI1(i)
R1
32 BICK
R2
32 BICK
R3
32 BICK
L1
32 BICK
L2
32 BICK
L3
32 BICK
32 BICK
32 BICK
Figure 7. Mode 6 Timing
256 BICK
LRCK
BICK(256fs)
SDTO(o)
23
0
23
0
23
23
Lch
32 BICK
Rch
32 BICK
23
0
23
0
23
0
23
0
23
0
23
0
SDTI1(i)
R1
32 BICK
R2
32 BICK
R3
32 BICK
L1
32 BICK
L2
32 BICK
L3
32 BICK
32 BICK
32 BICK
Figure 8. Mode 7 Timing
MS0397-E-00
2005/06
- 20 -
ASAHI KASEI
[AK4626A]
128 BICK
LRCK
BICK(128fs)
SDTO(o)
23 22
0
23
22
19
0
23 22
Lch
Rch
32 BICK
32 BICK
18
18
18
18
19
0
0
0
0
19 18
0
19 18
0
19
SDTI1(i)
SDTI2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
19
19
19
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
Figure 9. Mode 8 Timing
128 BICK
LRCK
BICK(128fs)
23 22
0
23
22
23
0
23 22
Lch
Rch
32 BICK
32 BICK
22
22
0
0
22
22
0
0
23
0
0
19
23
22
23 22
SDTI1(i)
SDTI2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
19
23
23
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
Figure 10. Mode 9 Timing
128 BICK
LRCK
BICK(128fs)
SDTO(o)
23 22
0
0
23
22
0
0
23 22
Lch
Rch
32 BICK
32 BICK
22
22
23 22
23
2
23
23
23 22
0
22
0
23 22
SDTI1(i)
SDTI2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
0
23 22
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
Figure 11. Mode 10 Timing
MS0397-E-00
2005/06
- 21 -
ASAHI KASEI
[AK4626A]
128 BICK
LRCK
BICK(128fs)
SDTO(o)
23
23
0
23
23
22
22
0
0
23 22
Lch
Rch
32 BICK
32 BICK
22
22
0
0
23
0
23
23
22
23 22
0
SDTI1(i)
SDTI2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
22
0
23
23
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
Figure 12. Mode 11 Timing
MS0397-E-00
2005/06
- 22 -
ASAHI KASEI
[AK4626A]
Overflow Detection
The AK4626A has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”
at serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output
for overflowed analog input has the same group delay as ADC (GD = 16/fs = 333µs @fs=48kHz). OVF is “L” for 522/fs
(=11.8ms @fs=48kHz) after PDN = “↑”, and then overflow detection is enabled.
Zero Detection
The AK4626A has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L”
and DZFE = “L” (Table 11). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2
channels. However DZF2 pin becomes OVF pin if OVFE bit is set to “1”. Zero detection mode is set to mode 0 if DZFE=
“H” regardless of P/S pin. DZF1 is AND of all six channels and DZF2 is disabled (“L”) at mode 0. Table 12 shows the
relation of P/S, DZFE, OVFE and DZF.
When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2)
pin goes to “H”. DZF1(DZF2) pin immediately goes to “L” if input data of any channels in the group 1(group 2) is not
zero after going DZF1(DZF2) “H”.
DZFM
AOUT
L2
Mode
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L1
R1
R2
L3
R3
0
1
2
3
4
5
6
7
8
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
disable (DZF1=DZF2 = “L”)
Default
Not Available
9
10
11
12
13
14
15
disable (DZF1=DZF2 = “L”)
Table 11. Zero detect control
P/S pin
“H” (parallel mode)
DZFE pin
“L”
OVFE bit
disable
disable
“0”
DZF mode
Mode 7
Mode 0
Selectable
Selectable
Mode 0
DZF1 pin
“L”
AND of 6ch
Selectable
Selectable
DZF2/OVF pin
“L”
“H”
“L”
“L”
“L” (serial mode)
Selectable
OVF output
“L”
“1”
“0”
“1”
“H”
AND of 6ch
AND of 6ch
Mode 0
OVF output
Table 12. DZF1-2 pins outputs
MS0397-E-00
2005/06
- 23 -
ASAHI KASEI
[AK4626A]
Digital Attenuator
The AK4626A has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can
be set by each ATT7-0 bits (Table 13).
ATT7-0
00H
01H
02H
:
Attenuation Level
0dB
Default
-0.5dB
-1.0dB
:
7DH
7EH
7FH
-62.5dB
-63dB
MUTE (-∞)
:
FEH
FFH
MUTE (-∞)
MUTE (-∞)
Table 13. Attenuation level of digital attenuator
Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 14). Transition between set
values is the soft transition. Therefore, the switching noise does not occur in the transition.
Mode
ATS1
ATS0
ATT speed
1792/fs
896/fs
256/fs
256/fs
Default
0
1
2
3
0
0
1
1
0
1
0
1
Table 14. Transition time between set values of ATT7-0 bits
The transition between set values is soft transition of 1792 levels in mode 0. It takes 1792/fs (37.3ms@fs=48kHz) from
00H(0dB) to 7FH(MUTE) in mode 0. If PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs are 00H when
RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value.
MS0397-E-00
2005/06
- 24 -
ASAHI KASEI
[AK4626A]
Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 14) from the current ATT level. When the SMUTE pin is returned to
“L”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
(1)
(1)
ATT Level
Attenuation
(3)
-
∞
GD
(2)
GD
AOUT
(4)
8192/fs
DZF1,2
Notes:
(1) ATT_DATA×ATT transition time (Table 14). For example, in Normal Speed Mode, this time is 1792LRCK cycles
(1792/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to 7FH
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at all the channels of the group are continuously zeros for 8192 LRCK cycles, DZF pin of each
channel goes to “H”. DZF pin immediately goes to “L” if the input data of either channel of the group are not zero
after going DZF “H”.
Figure 13. Soft mute and zero detection
System Reset
The AK4626A should be reset once by bringing PDN = “L” upon power-up. The AK4626A is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4626A is in the
power-down mode until MCLK and LRCK are input.
MS0397-E-00
2005/06
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ASAHI KASEI
[AK4626A]
Power-Down
The ADC and DACs of AK4626A are placed in the power-down mode by bringing PDN “L” and both digital filters are
reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up. In case
of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 14 shows the sequences of
the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal
register values are not initialized. When PWADN = “0”, SDTO goes to “L”. When PWDAN = “0”, the analog outputs go
to VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted
externally if the click noise influences system application.
PDN
(1)
522/fs
ADC Internal
State
Normal Operation
Power-down
Power-down
Init Cycle
516/fs
Normal Operation
(2)
DAC Internal
State
Normal Operation
GD
Init Cycle
Normal Operation
GD
(3)
ADC In
(Analog)
(4)
ADC Out
(Digital)
(5)
“0”data
DAC In
(Digital)
“0”data
(3)
GD
GD
(6)
(6)
DAC Out
(Analog)
(7)
Don’t care
Clock In
MCLK,LRCK,SCLK
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(9)
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click
noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4626A should be in the power down
mode.
(8) DZF pins are “L” in the power-down mode (PDN = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF= “L” for 10∼11/fs after PDN= “↑”.
Figure 14. Power-down/up sequence example
MS0397-E-00
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ASAHI KASEI
[AK4626A]
Reset Function
When RSTN = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go
to VCOM voltage, DZF1-2 pins go to “H” and SDTO pin goes to “L”. Because some click noise occurs, the analog output
should muted externally if the click noise influences system application. Figure 15 shows the power-up sequence.
RSTN bit
4~5/fs (9)
1~2/fs (9)
Internal
RSTN bit
(1)
516/fs
ADC Internal
State
Digital Block Power-down
Digital Block Power-down
Normal Operation
Normal Operation
Init Cycle
DAC Internal
State
Normal Operation
GD
Normal Operation
(2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
(5)
(6)
DAC Out
(Analog)
(7)
Don’t care
Clock In
MCLK,LRCK,SCLK
4∼5/fs (8)
DZF1/DZF2
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) The analog outputs go to VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, “1”
should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 15. Reset sequence example
MS0397-E-00
2005/06
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ASAHI KASEI
[AK4626A]
Serial Control Interface
The AK4626A can control its functions via registers. Internal registers may be written by 2 types of control mode. The
chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4626A should be reset by PDN pin.
* Writing to control register is invalid when PDN = “L”.
* AK4626A does not support the read command.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max).
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 16. 3-wire Serial Control I/F Timing
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2005/06
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ASAHI KASEI
[AK4626A]
(2) I2C-bus Control Mode (I2C= “H”)
AK4626A supports the standard-mode I2C-bus (max:100kHz). Then AK4626A does not support a fast-mode
I2C-bus system (max:400kHz). The CSN pin should be connected to DVDD at the I2C-bus mode.
Figure 17 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition.
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data
direction bit (R/W) (Figure 18). The most significant five bits of the slave address are fixed as “00100”. The next
two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The
hard-wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4626A and R/W
bit is “0”, the AK4626A generates the acknowledge and the write operation is executed. If R/W bit is “1”, the
AK4626A generates the not acknowledge since the AK4626A can be only a slave-receiver. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 22).
The second byte consists of the address for control registers of the AK4626A. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 20). Those data after the second byte contain control data. The
format is MSB first, 8bits (Figure 20). The AK4626A generates an acknowledge after each byte has been received.
A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on
the SDA line while SCL is HIGH defines a STOP condition (Figure 20).
The AK4626A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4626A generates an acknowledge, and awaits the next data again. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal
5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address
exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data
will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 23) except for the START and the STOP
condition.
S
S
T
O
P
T
A
R
T
R/W
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 17. Data transfer sequence at the I2C-bus mode
0
*
0
1
0
0
CAD1 CAD0
R/W
A0
(Those CAD1/0 should match with CAD1/0 pins)
Figure 18. The first byte
*
*
A4
A3
A2
A1
D1
(*: Don’t care)
Figure 19. The second byte
D7
D6
D5
D4
D3
D2
D0
Figure 20. Byte structure after the second byte
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2005/06
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ASAHI KASEI
[AK4626A]
SDA
SCL
S
P
start condition
stop condition
Figure 21. START and STOP conditions
DATA
OUTPUT BY
MASTER
not acknowledge
DATA
OUTPUT BY
SLAVE(AK4529)
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 22. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 23. Bit transfer on the I2C-bus
MS0397-E-00
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ASAHI KASEI
[AK4626A]
Mapping of Program Registers
Addr Register Name
00H Control 1
01H Control 2
02H LOUT1 Volume Control
03H ROUT1 Volume Control
04H LOUT2 Volume Control
05H ROUT2 Volume Control
06H LOUT3 Volume Control
07H ROUT3 Volume Control
08H De-emphasis
D7
0
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
D6
0
D5
TDM1
LOOP1 LOOP0
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
D4
TDM0
D3
DIF1
D2
DIF0
D1
0
D0
SMUTE
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
DEMC0
DFS1
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
0
SDOS
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
DFS0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ACKS
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
DEMC1
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
DEMA1 DEMA0 DEMB1 DEMB0
09H ATT speed & Reset
Control
0
0
ATS1 ATS0
0
0
0
RSTN
0AH Zero detect
OVFE
DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
Note: For addresses from 0BH to 1FH, data is not written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized
to their default values.
SMUTE, DFS0, SDOS and TDM0 are ORed with pins.
MS0397-E-00
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ASAHI KASEI
[AK4626A]
Register Definitions
Addr Register Name
00H Control 1
Default
D7
0
0
D6
0
0
D5
D4
D3
DIF1
1
D2
DIF0
0
D1
0
0
D0
SMUTE
0
TDM1 TDM0
0
0
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is ORed with the SMUTE pin if P/S = “L”.
DIF1-0: Audio Data Interface Modes (see Table 8, 9, 10)
Initial: “10”, mode 2
TDM1-0: TDM Format Select (see Table 8, 9, 10)
Mode TDM1 TDM0
SDTI
1-3
1
Sampling Speed
Normal, Double, Four Times Speed
Normal Speed
0
1
2
0
0
1
0
1
1
1-2
Normal, Double Speed
Register bit of TDM0 is ORed with the TDM0 pin if P/S = “L”.
TDM0 pin should be “L” if the register control is used.
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ASAHI KASEI
[AK4626A]
Addr Register Name
01H Control 2
Default
D7
0
0
D6
D5
D4
D3
D2
DFS0
0
D1
ACKS
0
D0
0
0
DFS1 LOOP1 LOOP0 SDOS
0
0
0
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are
ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode.
DFS1-0: Sampling speed mode (see Table 1.)
Register bit of DFS0 is ORed with DFS0 pin if P/S = “L”.
The setting of DFS is ignored at ACKS bit “1”.
SDOS: SDTO source select
0: ADC
1: DAUX
Register bit of SDOS is ORed with SDOS pin if P/S = “L”.
SDOS should be set to “0” at TDM bit “1”.
In the case of PWADN=”0” and PWDAN=”0”, the setting of SDOS becomes invalid. And ADC is selected.
The output of SDTO becomes “L” at PWADN=”0”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3
RIN → ROUT1, ROUT2, ROUT3
The digital ADC output (DAUX input if SDOS = “1”) is connected to the digital DAC input. In this
mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode
becomes mode 2 at mode 0, and mode 3 at mode 1, respectively.
10: SDTI1(L) → SDTI2(L), SDTI3(L)
SDTI1(R) → SDTI2(R), SDTI3(R)
In this mode the input DAC data to SDTI2-3 is ignored.
11: N/A
LOOP1-0 should be set to “00” at TDM bit “1”.
In the case of PWADN=”0” and PWDAN=”0”, the setting of LOOP1-0 becomes invalid. And ADC is selected.
And it becomes the normal operation (No loop back).
MS0397-E-00
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ASAHI KASEI
[AK4626A]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H LOUT1 Volume Control
03H ROUT1 Volume Control
04H LOUT2 Volume Control
05H ROUT2 Volume Control
06H LOUT3 Volume Control
07H ROUT3 Volume Control
Default
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
0
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
0
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
0
0
0
ATT7-0: Attenuation Level (see Table 13.)
Addr Register Name
08H De-emphasis
Default
D7
0
D6
0
D5
D4
D3
D2
D1
D0
DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0
0
0
0
1
0
1
0
1
DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (see Table 7.)
Initial: “01”, OFF
DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (see Table 7.)
Initial: “01”, OFF
DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (see Table 7.)
Initial: “01”, OFF
MS0397-E-00
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ASAHI KASEI
[AK4626A]
Addr Register Name
09H ATT speed & Reset
D7
0
D6
0
D5
ATS1
0
D4
ATS0
0
D3
0
D2
0
D1
0
D0
RSTN
1
Control
Default
0
0
0
0
0
RSTN: Internal timing reset
0: Reset. DZF1-2 pins go to “H”, but registers are not initialized.
1: Normal operation
ATS1-0: Digital attenuator transition time setting (see Table 14.)
Initial: “00”, mode 0
Addr Register Name
0AH Zero detect
Default
D7
OVFE
0
D6
D5
D4
D3
D2
D1
D0
DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
0
1
1
1
1
1
1
PWDAN: Power-down control of DAC1-3
0: Power-down
1: Normal operation
PWADN: Power-down control of ADC
0: Power-down
1: Normal operation
PWVRN: Power-down control of reference voltage
0: Power-down
1: Normal operation
DZFM3-0: Zero detect mode select (see Table 11.)
Initial: “0111”, disable
OVFE: Overflow detection enable
0: Disable, pin#33 becomes DZF2 pin.
1: Enable, pin#33 becomes OVF pin.
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ASAHI KASEI
[AK4626A]
SYSTEM DESIGN
Figure 24 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Condition: TVDD=5V, 3-wire serial control mode, CAD1-0 = “00”
Analog 5V
+
10u
uP
2.2u
+
0.1u
0.1u
Digital
Audio
Source
(DIR)
SDOS
I2C
DZF2
RIN
1
2
33
32
31
30
29
28
27
26
25
24
23
LIN
SMUTE
BICK
3
NC
4
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS0
TST5
ROUT1
LOUT1
ROUT2
LOUT2
5
Audio
DSP
6
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
AK4626A
7
(MPEG/
AC3)
8
9
ROUT3
LOUT3
10
11
0.1u
10u
+
5
Power-down
control
Digital Ground
Analog Ground
Figure 24. Typical Connection Diagram
MS0397-E-00
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ASAHI KASEI
[AK4626A]
Digital Ground
Analog Ground
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
SDOS
I2C
DZF2/OVF
RIN
System
Controller
SMUTE
BICK
LIN
NC
TST5
LRCK
SDTI1
SDTI2
SDTI3
SDTO
AK4626A
ROUT1
LOUT1
ROUT2 26
LOUT2 25
ROUT3 24
10 DAUX
11 DFS0
23
LOUT3
Figure 25. Ground Layout
Note: AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4626A requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up
sequence is not critical. AVSS and DVSS of the AK4626A must be connected to analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as near to the AK4626A as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference Inputs
The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1µF
ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic
capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from
VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid
unwanted coupling into the AK4626A.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and
nominally 0.62 x VREFH Vpp (typ)@fs=48kHz. The ADC output data format 2’s compliment. The DC offset is removed
by the internal HPF.
The AK4626A samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples
of 64fs. The AK4626A includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
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ASAHI KASEI
[AK4626A]
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the
supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a
positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma
modulator of DAC beyond the audio passband.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
Peripheral I/F Example
The AK4626A can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for
output buffer (TVDD) of the AK4626A should be 3.3V when the peripheral devices operate at a nominal 3.3V supply.
Figure 26 shows an example with the mixed system of 3.3V and 5V.
5V for input
3.3V Analog
3.3V Digital
Audio signal
PLL
I/F
DSP
AK4112B
3.3V for output
5V Analog
5V Digital
uP &
Others
Analog Digital
Control signal
AK4626A
Figure 26. Power supply connection example
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ASAHI KASEI
[AK4626A]
PACKAGE
44pin LQFP (Unit: mm)
1.70max
12.80 0.30
±
0 0.2
∼
10.00
23
33
34
44
22
12
1
11
0.37 0.10
±
0.17 0.05
±
0 10
°∼
°
0.60 0.20
±
0.15
Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy
Cu
Lead frame surface treatment:
Solder (Pb free) plate
MS0397-E-00
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ASAHI KASEI
[AK4626A]
MARKING
AK4626AVQ
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4626AVQ
4) Asahi Kasei Logo
Revision History
Date (YY/MM/DD)
05/06/03
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0397-E-00
2005/06
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