AKD4627 [AKM]
High Performance Multi-channel Audio CODEC; 高性能多通道音频编解码器
| 型号： | AKD4627 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | High Performance Multi-channel Audio CODEC |
| 文件： | 总46页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK4627]
AK4627
High Performance Multi-channel Audio CODEC
GENERAL DESCRIPTION
The AK4627 is a single chip audio CODEC that includes four ADC channels and six DAC channels. The
converters are designed with Enhanced Dual Bit architecture for the ADC’s, and Advanced Multi-Bit
architecture for the DAC, enabling very low noise performance. The AK4627 ADC supports both
single-ended and differential inputs and outputs. A wide range of applications can be realized, including
home theater, pro audio and car audio. The AK4627 is available in a 48-pin LQFP package.
FEATURES
4ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-ended / Differential Input
- S/(N+D): 92dB (Single-ended, Differential)
- Dynamic Range, S/N: 102dB (Single-ended), 103dB (Differential)
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
6ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
High Jitter Tolerance
TTL Level Digital I/F
3-wire Serial and I2C Bus µP I/F for mode setting
Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
128fs for fs=120kHz to 192kHz
Power Supply: 4.5 to 5.5V
Power Supply for output buffer: 2.7 to 5.5V
Small 48pin LQFP
MS1278-E-02
2012/03
- 1 -
[AK4627]
■ Block Diagram
Audio
I/F
LIN1+/LIN1
LIN1-
ADC
ADC
ADC
ADC
HPF
HPF
HPF
HPF
RIN1+/RIN1
RIN1-
SDTO1
SDTO2
SDTO1
SDTO2
LIN2+/LIN2
LIN2-
RIN2+/RIN2
RIN2-
MCLK
LRCK
BICK
MCLK
LRCK
BICK
LOUT1
ROUT1
LOUT2
ROUT2
DAC
DAC
LPF
LPF
DATT
DATT
DATT
DATT
LPF
LPF
DAC
DAC
DAC
DAC
SDTI1
SDTI2
SDTI3
SDIN1
SDIN2
SDIN3
LOUT3
ROUT3
LPF
DATT
DATT
LPF
AK4627
Block Diagram
MS1278-E-02
2012/03
- 2 -
[AK4627]
■ Ordering Guide
AK4627VQ
-40 ∼ +105°C
Evaluation Board for AK4627
48pin LQFP(0.5mm pitch)
AKD4627
■ Pin Layout
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
TST5
RIN2-
RIN2+/RIN2
LIN2-
TST4
TST2
LIN2+/LIN2
RIN1-
I2C/TST6
DFS0
AK4627
RIN1+/RIN1
LIN1-
TST3
SDTI3
SDTI2
Top View
LIN1+/LIN1
TST1
SDTI1
LRCK
SGL
DZFE
BICK
SMUTE
MCLK
MS1278-E-02
2012/03
- 3 -
[AK4627]
PIN/FUNCTION
No. Pin Name
I/O Function
1
2
CAD0
CAD1
PS
I
I
I
Chip Address 0 Pin
Chip Address 1 Pin
Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
ADC1 Audio Serial Data Output Pin
ADC2 Audio Serial Data Output Pin
Output Buffer Power Supply Pin, 2.7V∼5.5V
Digital Power Supply Pin, 4.5V∼5.5V
Digital Ground Pin, 0V
3
4
5
6
7
8
SDTO1
SDTO2
TVDD
DVDD
VSS1
O
O
-
-
-
TDM0
I
TDM I/F Format Mode Pin in parallel control mode
“L”: Normal mode, “H”: TDM mode
9
SDA/CDTI
I/O Control Data Input Pin in serial control mode
I2C pin= “L”: CDTI (3-wire Serial), I2C pin= “H”: SDA (I2C Bus)
DIF1
SCL/CCLK
I
I
Audio Data Interface Format 1 Pin in parallel control mode
Control Data Clock Pin in serial control mode
10
11
I2C pin= “L”: CCLK (3-wire Serial), I2C pin= “H”: SCL (I2C Bus)
Audio Data Interface Format 0 Pin in parallel control mode
Chip Select Pin in 3-wire serial control mode
DIF0
CSN
I
I
This pin should be connected to DVDD at I2C bus control mode
Power-Down & Reset Pin
PDN
I
When “L”, the AK4627 is powered-down and the control registers are reset to default
state. If the state of PS pin or CAD1-0 pins change, then the AK4627 must be reset by
the PDN pin.
12
13 MCLK
14 BICK
15 LRCK
16 SDTI1
17 SDTI2
18 SDTI3
I
I
I
I
I
I
I
Master Clock Input Pin
Audio Serial Data Clock Pin
Input Channel Clock Pin
DAC1 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
Test Pin
This pin should be connected to VSS1
Double Speed Sampling Mode Pin (Note 1)
“L”: Normal Speed, “H”: Double Speed
Control Mode Select Pin (PS pin = “L”)
“L”: 3-wire Serial, “H”: I2C Bus
Test Pin (PS pin = “H”)
TST3
19
DFS0
20
I
I
I
I2C
21
TST6
This pin should be connected to VSS1
TST2
22
Test Pin
This pin should be connected to VSS1.
Test Pin
This pin should be open.
TST4
23
TST5
24
Test Pin
This pin should be open.
25 LOUT3
26 ROUT3
27 LOUT2
28 ROUT2
29 LOUT1
30 ROUT1
O
O
O
O
O
O
DAC3 Lch Analog Output Pin
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
MS1278-E-02
2012/03
- 4 -
[AK4627]
No. Pin Name
I/O Function
VCOM
O
Common Voltage Output Pin, AVDD/2
31
Large external capacitor around 2.2µF is used to reduce power-supply noise.
Positive Voltage Reference Input Pin, AVDD
Analog Power Supply Pin, 4.5V∼5.5V
32 VREFH
I
-
AVDD
33
34 VSS2
35 DZF1
-
O
Analog Ground Pin, 0V
Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
36 DZF2
O
Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
ADC2 Rch Analog Negative Input Pin (SGL pin = “L”)
ADC2 Rch Analog Positive Input Pin (SGL pin = “L”)
ADC2 Rch Analog Input Pin (SGL pin = “H”)
ADC2 Lch Analog Negative Input Pin (SGL pin = “L”)
ADC2 Lch Analog Positive Input Pin (SGL pin = “L”)
ADC2 Lch Analog Input Pin (SGL pin = “H”)
ADC1 Rch Analog Negative Input Pin (SGL pin = “L”)
ADC1 Rch Analog Positive Input Pin (SGL pin = “L”)
ADC1 Rch Analog Input Pin (SGL pin = “H”)
ADC1 Lch Analog Negative Input Pin (SGL pin = “L”)
ADC1 Lch Analog Positive Input Pin (SGL pin = “L”)
ADC1 Lch Analog Input Pin (SGL pin = “H”)
Test Pin
37 RIN2-
38 RIN2+
RIN2
39 LIN2-
40 LIN2+
LIN2
I
I
I
I
I
I
I
I
I
I
I
I
41 RIN1-
RIN1+
RIN1
42
43 LIN1-
44 LIN1+
LIN1
45 TST1
This pin should be connected to VSS1.
46 SGL
I
I
Single-ended Input Mode Select Pin.
“L”: ADC Differential Input Mode
“H”: ADC Single-ended Input Mode
Zero Input Detect Enable Pin
47 DZFE
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
Soft Mute Pin (Note 1)
48 SMUTE
I
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
Note 1. SMUTE and DFS0 pins are ORed with register data when the PS pin= “L”.
Note 2. The output pin (DZF1 and DZF2) of zero detection results of each lineout channels can be selected by DZFM3-0
bits when the PS pin and DZFE pin= “L”. (Table 11)
Note 3. All digital input pins except for pull-down should not be left floating.
MS1278-E-02
2012/03
- 5 -
[AK4627]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 4)
Parameter
Power Supplies
Symbol
AVDD
DVDD
TVDD
IIN
VINA
VIND
Ta
min
-0.3
-0.3
-0.3
-
-0.3
-0.3
-40
max
6.0
6.0
Unit
V
V
V
mA
V
V
°C
°C
Analog
Digital
Output buffer
6.0
Input Current (any pins except for supplies)
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (power applied) (Note 6)
Storage Temperature
±10
AVDD+0.3
DVDD+0.3
105
Tstg
-65
150
Note 4. All voltages with respect to ground.
Note 5. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 6. In case that PCB wiring density is 100% or more.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 4)
Parameter
Power Supplies
(Note 7)
Symbol
AVDD
DVDD
TVDD
min
4.5
4.5
2.7
typ
5.0
5.0
5.0
max
5.5
5.5
Unit
V
V
Analog
Digital
Output buffer
5.5
V
Note 4. All voltages with respect to ground.
Note 7. The power up sequence between AVDD, DVDD and TVDD is not critical. Do not turn off only the AK4627 under
the condition that a surrounding device is powered on and the I2C bus is in use.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1278-E-02
2012/03
- 6 -
[AK4627]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=TVDD=5V; VSS1=VSS2=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz,
20Hz~40kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
ADC Analog Input Characteristics (Single-ended Inputs)
Resolution
S/(N+D)
24
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
(-0.5dBFS)
(-60dBFS)
fs=48kHz
fs=96kHz
84
-
96
92
102
99
105
102
99
DR
fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
94
88
93
94
88
93
90
S/N
(Note 11)
fs=96kHz, A-weighted
105
110
Interchannel Isolation
DC Accuracy (Single-ended Inputs)
Interchannel Gain Mismatch
Gain Drift
0.2
20
3.4
14
11
50
0.3
-
3.6
dB
ppm/°C
Vpp
kΩ
kΩ
dB
Input Voltage
AIN=0.68xVREFH
3.2
10
fs=48kHz
fs=96kHz
Input Resistance
Power Supply Rejection
(Note 9)
ADC Analog Input Characteristics (Differential inputs)
S/(N+D)
(-0.5dBFS)
fs=48kHz
fs=96kHz
fs=48kHz, A-weighted
fs=96kHz
84
-
96
94
dB
dB
dB
dB
dB
dB
dB
dB
dB
DR
(-60dBFS)
95
89
94
95
89
94
90
103
100
106
103
100
106
110
fs=96kHz, A-weighted
S/N
(Note 11)
fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
Interchannel Isolation
DC Accuracy (Differential inputs)
Interchannel Gain Mismatch
Gain Drift
0.2
20
±3.4
32
0.3
-
±3.6
dB
ppm/°C
Vpp
kΩ
Input Voltage
AIN=0.68xVREFH (Note 8)
±3.2
22
fs=48kHz
fs=96kHz
Input Resistance
19
kΩ
Power Supply Rejection
(Note 9)
50
-
dB
Common Mode Rejection Ratio (CMRR)
(Note 10)
60
dB
MS1278-E-02
2012/03
- 7 -
[AK4627]
DAC Analog Output Characteristics
Resolution
S/(N+D)
24
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
(0dBFS)
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
80
78
-
95
88
94
-
98
98
98
DR
(-60dBFS)
106
100
106
100
106
106
100
106
100
106
110
-
S/N
(Note 12)
95
88
94
-
-
90
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
0.2
20
3.0
0.5
-
3.25
dB
ppm/°C
Vpp
Output Voltage
AOUT=0.6xVREFH
2.75
5
Load Resistance
Load Capacitance
Power Supply Rejection
kΩ
pF
dB
25
(Note 10)
50
Note 8. (LIN+) – (LIN-) or (RIN+) – (RIN-); this value is proportional to VREFH voltage.
Note 9. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held +5V.
Note 10. VREFH is held +5V, the input bias voltage is set to AVDD1, AVDD2 x 0.5. The 1kHz, 1.52Vpp signal is applied
to LIN- and LIN+ with same phase (e.g. shorted) or RIN- and RIN+. The CMRR is measured as the attenuation
level from 1.52Vpp = -7dBFS.
Note 11. S/N measured by CCIR-ARM is 98dB(@fs=48kHz).
Note 12. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
Parameter
min
typ
max
Unit
Power Supplies
Power Supply Current (AVDD+DVDD+TVDD)
Normal Operation (PDN = “H”)
AVDD
fs=48kHz, 96kHz
fs=192kHz
57
34
19
27
27
80
86
51
29
40
40
mA
mA
mA
mA
mA
μA
DVDD+TVDD fs=48kHz
fs=96kHz
(Note 13)
(Note 14)
fs=192kHz
Power-down mode (PDN = “L”)
200
Note 13. TVDD=0.1mA(typ).
Note 14. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held VSS1.
MS1278-E-02
2012/03
- 8 -
[AK4627]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband
(Note 15)
PB
0
-
-
18.9
-
-
kHz
kHz
kHz
±0.1dB
-0.2dB
-3.0dB
20.0
23.0
Stopband
SB
PR
SA
GD
ΔGD
28
68
kHz
dB
dB
1/fs
μs
Passband Ripple
Stopband Attenuation
Group Delay
±0.04
(Note 16)
16
0
Group Delay Distortion
ADC Digital Filter (HPF):
Frequency Response
(Note 15) -3dB
FR
1.0
6.5
Hz
Hz
-0.1dB
DAC Digital Filter:
Passband
(Note 15) -0.1dB
-6.0dB
PB
0
-
26.2
21.8
-
kHz
kHz
kHz
dB
dB
1/fs
24.0
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
±0.02
54
(Note 16)
19.2
DAC Digital Filter + Analog Filter:
FR
FR
FR
dB
dB
dB
Frequency Response: 0 ∼ 20.0kHz
±0.2
±0.3
±1.0
40.0kHz (Note 17)
80.0kHz (Note 17)
Note 15. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs.
Note 16. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal
to setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog
signal.
Note 17. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz.
DC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
VIH
VIL
min
2.2
-
typ
-
-
max
-
0.8
Unit
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
(SDTO1-2 pins:
(DZF1, DZF2 pins:
Low-Level Output Voltage
Iout=-100μA)
Iout=-100μA)
VOH
VOH
TVDD-0.5
AVDD-0.5
-
-
-
-
V
V
(SDTO1-2, DZF1, DZF2 pins: Iout= 100μA)
VOL
VOL
Iin
-
-
-
-
-
-
0.5
0.4
±10
V
V
μA
(SDA pin:
Iout= 3mA)
Input Leakage Current
MS1278-E-02
2012/03
- 9 -
[AK4627]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
256fsn, 128fsd:
fCLK
8.192
27
27
12.288
20
20
16.384
15
15
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd, 128fsq:
Pulse Width Low
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
18.432
24.576
tCLKL
tCLKH
Pulse Width High
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
fsn
fsd
fsq
Duty
32
64
128
45
48
96
192
55
kHz
kHz
kHz
%
Duty Cycle
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
“H” time
fsn
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
“L” time
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
“H” time
fsn
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
“L” time
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
LRCK to SDTO(MSB)
BICK “↓” to SDTO1-2
SDTI1-3 Hold Time
(Note 18)
(Note 18)
40
40
20
20
SDTI1-3 Setup Time
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO1
SDTI1 Hold Time
(Note 18)
(Note 18)
20
10
10
SDTI1 Setup Time
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO1
SDTI1-2 Hold Time
(Note 18)
(Note 18)
20
10
10
SDTI1-2 Setup Time
Note 18. BICK rising edge must not occur at the same time as LRCK edge.
MS1278-E-02
2012/03
- 10 -
[AK4627]
Parameter
Symbol
min
typ
max
Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
-
400
-
-
-
-
-
-
-
1.0
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 19)
tF
tSU:STO
tSP
Cb
0.6
0
-
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
pF
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO1-2 valid
(Note 20)
(Note 21)
tPD
tPDV
150
ns
1/fs
522
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 20. The AK4627 can be reset by bringing the PDN pin “L” to “H” upon power-up.
Note 21. These cycles are the number of LRCK rising from the PDN pin rising edge.
Note 22. I2C-bus is a trademark of NXP B.V.
MS1278-E-02
2012/03
- 11 -
[AK4627]
■ Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fsn, 1/fsd
VIH
VIL
LRCK
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing (TDM0 bit= “0”)
1/fCLK
VIH
VIL
MCLK
LRCK
BICK
tCLKH
tCLKL
1/fs
VIH
VIL
tLRH
tLRL
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing (TDM0 bit= “1”)
MS1278-E-02
2012/03
- 12 -
[AK4627]
VIH
VIL
LRCK
BICK
tBLR
tLRS
tLRB
VIH
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (TDM0 bit= “0”)
VIH
VIL
LRCK
BICK
tBLR
tLRB
VIH
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (TDM0 bit= “1”)
MS1278-E-02
2012/03
- 13 -
[AK4627]
VIH
VIL
CSN
tCSS
tCCKL tCCKH
VIH
VIL
CCLK
CDTI
tCDS tCDH
C0
VIH
VIL
C1
R/W
A4
WRITE Command Input Timing (3-wire Serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
VIL
CCLK
CDTI
VIH
VIL
D3
D2
D1
D0
WRITE Data Input Timing (3-wire Serial mode)
VIH
SDA
SCL
VIL
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
tHD:STA
Stop Start
tHD:DAT
tPD
tSU:DAT tSU:STA
tSU:STO
Stop
Start
I2C Bus mode Timing
VIH
VIL
PDN
tPDV
SDTO
50%TVDD
Power-down & Reset Timing
MS1278-E-02
2012/03
- 14 -
[AK4627]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4627, are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0 and DFS1 bits (Table 1). The frequency of MCLK at
each sampling speed is set automatically. (Table 2, Table 3, Table 4). In Auto Setting Mode (ACKS bit= “1”), as MCLK
frequency is detected automatically (Table 5) and the internal master clock becomes the appropriate frequency (Table 6),
it is not necessary to set DFS bits.
The AK4627 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation
mode, and the analog output goes to VCOM (typ). When MCLK and LRCK are input again, the AK4627 is powered up.
After exiting reset following power-up, the AK4627 is not fully operational until MCLK and LRCK are input.
DFS1
DFS0
Sampling Speed (fs)
0
0
1
0
1
0
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
(default)
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK (MHz)
384fs
BICK (MHz)
64fs
256fs
8.1920
11.2896
12.2880
512fs
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
2.0480
2.8224
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
MCLK (MHz)
192fs
BICK (MHz)
64fs
128fs
256fs
88.2kHz
96.0kHz
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
5.6448
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode(DFS1 bit= “0”, DFS0 bit= “1”), 128fs and 192fs are not available for ADC.)
LRCK
fs
MCLK (MHz)
BICK (MHz)
64fs
128fs
192fs
256fs
176.4kHz
192.0kHz
22.5792
24.5760
-
-
-
-
11.2896
12.2880
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
(Note: At Quad speed mode(DFS1bit= “1”, DFS0 bit= “0”) are not available for ADC.)
MS1278-E-02
2012/03
- 15 -
[AK4627]
MCLK
512fs
256fs
128fs
Sampling Speed
Normal
Double
Quad
Table 5. Sampling Speed (Auto Setting Mode)
LRCK
fs
MCLK (MHz)
Sampling
Speed
128fs
256fs
512fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
16.3840
22.5792
24.5760
Normal
22.5792
24.5760
-
-
-
-
Double
Quad
-
22.5792
24.5760
-
-
Table 6. System Clock Example (Auto Setting Mode)
■ Differential/Single-ended Input selection
The AK4627 supports differential inputs (Figure 1) by setting the SGL pin = “L”, and single-ended inputs (Figure 2) by
setting the SGL pin= “H”. When single-ended input mode, L/RIN1-2 pins should be open, because L/RIN1-2 pins output
an invert signal of the input signal. The AK4627 includes an anti-aliasing filter (RC filter) for both differential input and
the single-ended input.
AK4627
AK4627
L/RIN+
L/RIN
LPF
LPF
SCF
SCF
LPF
L/RIN-
L/RIN-
(Open)
Figure 1. Differential Input (SGL pin = “L”)
Figure 2. Single-ended Input (SGL pin = “H”)
MS1278-E-02
2012/03
- 16 -
[AK4627]
■ De-emphasis Filter
The AK4627 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in
Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz,
48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2:
DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”).
Mode
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
DEM1
DEM0
DEM
44.1kHz
OFF
48kHz
32kHz
0
1
2
3
0
0
1
1
0
1
0
1
(default)
Table 7. De-emphasis control
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz
and scales with sampling rate (fs).
MS1278-E-02
2012/03
- 17 -
[AK4627]
■ Audio Serial Interface Format
When TDM1 bit = “0” and TDM0 pin = “L” or when TDM1-0 bits = “00”, four modes can be selected by the DIF1-0 bits
as shown in Table 8. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1-2 are clocked out on
the falling edge of BICK and the SDTI1-3 are latched on the rising edge of BICK.
Mode 2, 3, 6, 7, 10, 11 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs.
Mode TDM 1 TDM0
DIF1 DIF0
SDTO1-2
SDTI1-3
LRCK
BICK
24bit, Left 20bit, Right
justified justified
24bit, Left 24bit, Right
0
1
0
0
0
0
0
0
0
1
H/L
I
I
I
I
≥ 48fs
H/L
≥ 48fs
justified
24bit, Left
justified
justified
24bit, Left
justified
(default)
2
3
0
0
0
0
1
1
0
1
H/L
L/H
I
I
I
I
≥ 48fs
≥ 48fs
24bit, I2S
24bit, I2S
Table 8. Audio data formats (Normal mode)
The audio serial interface format becomes the TDM mode when the TDM0 pin is set to “H”. The serial data of all ADC
(four channels) are output from the SDTO1 pin and the SDTO2 pin outputs “L”. In the TDM256 mode, the serial data of
all DAC (six channels) are input to the SDTI1 pin. The input data to SDTI2-3 pins are ignored. BICK should be fixed to
256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by DIF1-0 bits as shown in
Table 9. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1 is clocked out on the falling edge
of BICK and the SDTI1 is latched on the rising edge of BICK. LOOP1-0 bits should be set to “0” at the TDM mode.
TDM128 Mode can be set by TDM1 bit as show in Table 10. In Double Speed Mode, the serial data of DAC (four
channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other two data (L3 and R3) are input to the SDTI2 pin. The TDM0
pin (or TDM0 register) should be set to “H” (or “1”) if TDM256 Mode is selected. The TDM0 register and TDM1 register
should be set to “1” if Double Speed Mode is selected in TDM128 Mode.
Mode TDM 1 TDM0 DIF1 DIF0
SDTO1
SDTI1
LRCK
I/O
BICK
I/O
24bit, Left 20bit, Right
justified justified
24bit, Left 24bit, Right
4
5
0
0
1
1
0
0
0
1
I
I
256fs
I
↑
↑
256fs
I
justified
24bit, Left
justified
justified
24bit, Left
justified
6
7
0
0
1
1
1
1
0
1
I
I
256fs
256fs
I
I
↑
↓
24bit, I2S
24bit, I2S
Table 9. Audio data formats (TDM256 mode)
Mode TDM 1 TDM0 DIF1 DIF0
SDTO1
SDTI1,
SDTI2
LRCK
BICK
I/O
I/O
24bit, Left 20bit, Right
justified justified
24bit, Left 24bit, Right
8
9
1
1
1
1
0
0
0
1
I
128fs
128fs
I
↑
↑
I
I
justified
24bit, Left
justified
justified
24bit, Left
justified
10
11
1
1
1
1
1
1
0
1
I
I
128fs
128fs
I
I
↑
↓
24bit, I2S
24bit, I2S
Table 10. Audio data formats (TDM128 mode)
MS1278-E-02
2012/03
- 18 -
[AK4627]
LRCK
0
0
0
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
24
28
25
25
29
31
31
31
31
0
0
0
0
1
BICK(64fs)
SDTO(o)
23 22
12 11 10
19 18
0
23 22
12 11 10
19 18
Don’t Care
0
23
8
7
1
0
8
7
1
0
Don’t Care
SDTI(i)
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 0 Timing
LRCK
1
2
8
9
10
24
25
31
0
1
2
8
9
10
1
1
1
BICK(64fs)
SDTO(o)
23 22
16 15 14
23 22
0
23 22
16 15 14
23 22
Don’t Care
0
23
8
7
1
0
8
7
1
0
Don’t Care
SDTI(i)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 1 Timing
LRCK
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
30
BICK(64fs)
SDTO(o)
23 22
23 22
2
2
1
1
0
0
23 22
23 22
2
2
1
1
0
0
23
23
Don’t Care
Don’t Care
SDTI(i)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 2 Timing
LRCK
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
BICK(64fs)
SDTO(o)
23 22
23 22
2
2
1
1
0
0
23 22
23 22
2
2
1
1
0
0
Don’t Care
Don’t Care
SDTI(i)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 3 Timing
MS1278-E-02
2012/03
- 19 -
[AK4627]
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19
SDTI1(i)
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 7. Mode 4 Timing
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
SDTI1(i)
R1
R2
R3
L1
L2
L3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 8. Mode 5 Timing
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
SDTI1(i)
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK
Figure 9. Mode 6 Timing
256 BICK
LRCK
BICK(256fs)
SDTO1(o)
23
0
23
0
23
0
23
0
23
23
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
23
0
23
0
23
0
23
0
23
0
23
0
SDTI1(i)
R1
32 BICK
R2
32 BICK
R3
32 BICK
L1
32 BICK
L2
32 BICK
L3
32 BICK
Figure 10. Mode 7 Timing
MS1278-E-02
2012/03
- 20 -
[AK4627]
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
22
0
22
0
23 22
23
0
23 22
23
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
19 18
0
0
19 18
0
0
19 18
0
19 18
0
19
SDTI1(i)
SDTI2(i)
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
18
18
19
19
19
L3
R3
32 BICK
32 BICK
Figure 11. Mode 8 Timing
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
23 22
0
0
23 22
0
0
23 22
23 22
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
22
22
23
0
0
23
0
0
23 22
0
23 22
0
19
SDTI1(i)
SDTI2(i)
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23 22
19
L3
R3
32 BICK
32 BICK
Figure 12. Mode 9 Timing
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
22
0
0
23 22
0
0
23 22
0
23 22
23
0
0
23 22
L2
R2
L1
R1
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23 22
23 22
23 22
0
23 22
SDTI1(i)
SDTI2(i)
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
22
23 22
0
23 22
23
0
L3
R3
32 BICK
32 BICK
Figure 13. Mode 10 Timing
MS1278-E-02
2012/03
- 21 -
[AK4627]
128 BICK
LRCK
BICK(128fs)
SDTO1(o)
23 22
0
0
23 22
0
0
23 22
0
0
23 22
0
0
23
23
L1
R1
L2
R2
32 BICK
32 BICK
23 22
23 22
23 22
23 22
SDTI1(i)
SDTI2(i)
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
22
0
22
0
23
23
23
L3
R3
32 BICK
32 BICK
Figure 14. Mode 11 Timing
MS1278-E-02
2012/03
- 22 -
[AK4627]
■ Zero Detection
The AK4627 has two pins for zero detect flag outputs. The output pin (DZF1 and DZF2 pins) for zero detection results of
each lineout channels can be selected by DZFM3-0 bits when the PS pin and DZFE pin = “L” (Table 11). Zero detection
mode is set to mode 0 when the DZFE pin= “H” regardless of the PS pin. The DZF1 pin outputs AND result of all six
channels and the DZF2 pin is disabled (“L”) at mode 0.
When the input data of all lineout channels of DZF1 (DZF2) pin are continuously zeros for 8192 LRCK cycles, the DZF1
(DZF2) pin becomes “H”. The DZF1 (DZF2) pin immediately returns to “L” if input data of any channel of DZF1 (DZF2)
pin is not zero.
DZFM
AOUT
Mode
3
2
1
0
L1
R1
L2
R2
L3
R3
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
disable (DZF1=DZF2 = “L”)
DZF1
DZF1
(default)
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
9
10
11
12
13
14
15
disable (DZF1=DZF2 = “L”)
Table 11. Zero detect control
MS1278-E-02
2012/03
- 23 -
[AK4627]
■ Digital Attenuator
The AK4627 has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can
be set by each ATT7-0 bits (Table 12).
ATT7-0
00H
01H
02H
:
Attenuation Level
0dB
(default)
-0.5dB
-1.0dB
:
7DH
7EH
7FH
-62.5dB
-63dB
MUTE (-∞)
:
FEH
FFH
MUTE (-∞)
MUTE (-∞)
Table 12. Attenuation level of digital attenuator
Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 13). Transition between set
values is soft transition. Therefore, the switching noise does not occur in the transition.
Mode
ATS1
ATS0
ATT speed
1792/fs
896/fs
256/fs
256/fs
(default)
0
1
2
3
0
0
1
1
0
1
0
1
Table 13. Transition time between set values of ATT7-0 bits
The transition between set values is soft transition of 1792 levels in mode 0. It takes 1792/fs (37.3ms@fs=48kHz) from
00H(0dB) to 7FH(MUTE). When the PDN pin becomes “L”, the ATTs are initialized to 00H. The ATTs are 00H when
RSTN bit= “0”. When RSTN bit return to “1”, the ATTs fade to their current value.
Note: The attenuation level is calculated in 11bit accuracy.
MS1278-E-02
2012/03
- 24 -
[AK4627]
■ Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin changes to “H”, the output signal is attenuated
by -∞ during ATT_DATA×ATT transition time (Table 13) from the current ATT level. When the SMUTE pin returns to
“L”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT
level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit
(1)
(1)
ATT Level
Attenuation
(3)
-
∞
GD
(2)
GD
AOUT
(4)
8192/fs
DZF1,2
Notes:
(1) ATT_DATA×ATT transition time (Table 13). For example, in Normal Speed Mode, this time is 1792LRCK cycles
(1792/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to 7FH
(2) The analog output corresponding to the digital input has group delay. (GD)
(3) If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT level by
the same cycle.
(4) When the input data at all the channels of the group are continuously zeros for 8192 LRCK cycles, the DZF pin of
each channel becomes “H”. The DZF pin immediately returns to “L” if the input data of either channel of the group
are not zero.
Figure 15. Soft mute and zero detection
■ System Reset
The AK4627 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4627 is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4627 is in the
power-down mode until MCLK and LRCK are input.
MS1278-E-02
2012/03
- 25 -
[AK4627]
■ Power-Down
The ADC and DACs of AK4627 are placed in the power-down mode by bringing the PDN “L” and both digital filters are
reset at the same time. Bringing the PDN pin=“L” also resets the control registers to their default values. In the
power-down mode, the analog outputs become to VCOM voltage and DZF1-2 pins output “L”. This reset should always
be made after power-up. In case of ADC, an analog initialization cycle starts after exiting the power-down mode.
Therefore, the output data, SDTO1-2 become available after 516 cycles of LRCK clock. In case of the DAC, an analog
initialization cycle starts after exiting the power-down mode. The analog outputs are VCOM voltage during the
initialization. Figure 16 shows the power-down/up sequences.
All ADCs and all DACs can be powered-down by PWADN and PWDAN bits respectively. DAC1-3 can be power-down
individually by PDDA1-3 bits. In this case, the internal register values are not initialized. When PWADN bit= “0” and
PDAD1-2 bits = “0”, SDTO1-2 become “L”. When PWDAN bit = “0” and PDDA1-3 bits= “0”, the analog outputs go to
VCOM voltage and DZF1-2 pins go to “H”. As some click noise occurs, the analog output should be muted externally if
the click noise influences system applications.
PDN
(1)
516/fs
ADC Internal
State
Normal Operation
Power-down
Power-down
Init Cycle
512/fs
Normal Operation
(2)
DAC Internal
State
Normal Operation
GD
Init Cycle
Normal Operation
GD
(3)
ADC In
(Analog)
(4)
ADC Out
(Digital)
(5)
“0”data
DAC In
(Digital)
“0”data
(3)
GD
GD
(6)
(6)
DAC Out
(Analog)
(7)
Clock In
MCLK,LRCK,SCLK
Don’t care
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(9)
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(4) ADC outputs “0” data in power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4627 should be in the power-down mode.
(8) DZF pins are “L” in power-down mode (PDN pin= “L”).
(9) Mute the analog output externally if the click noise (6) influences system application.
(10) DZF1-2 pins are “L” for 10∼11/fs after PDN = “↑”.
Figure 16. Power-down/up sequence example
MS1278-E-02
2012/03
- 26 -
[AK4627]
■ Reset Function
(1) Reset by RSTN bit
When RSTN bit = “0”, ADC and DACs are powered-down but the internal registers are not initialized. The analog outputs
go to VCOM voltage, DZF1-2 pins output “H” and the SDTO1-2 pins outputs “L”. As some click noise occurs, the analog
output should be muted externally if the click noise influences system application. Figure 17 shows the power-up
sequence.
RSTN bit
4~5/fs (9)
1~2/fs (9)
Internal
RSTN bit
(1)
516/fs
ADC Internal
State
Digital Block Power-down
Digital Block Power-down
Normal Operation
Normal Operation
Init Cycle
DAC Internal
State
Normal Operation
GD
Normal Operation
(2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
(5)
(6)
DAC Out
(Analog)
(7)
Don’t care
Clock In
MCLK,LRCK,SCLK
4∼5/fs (8)
DZF1/DZF2
Notes:
(1) The analog part of the ADC is initialized after exiting reset state.
(2) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(3) ADC outputs “0” data in power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system application.
(5) The analog outputs become VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in reset mode. When exiting reset mode, “1” should
be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) The DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 17. Reset sequence example
MS1278-E-02
2012/03
- 27 -
[AK4627]
(2) Reset by MCLK, LRCK or BICK stop
The AK4627 is automatically placed in reset state when MCLK, LRCK or BICK is stopped during normal operation
(RSTN pin = “H”). In this reset state, the analog output becomes VCOM voltage, and SDTO1-2, DZF1-2 pins output “L”,
but register values are not initialized. When MCLK, LRCK or BICK are input again, the AK4627 is powered up. After
exiting reset following power-up, the ADC enters initializing cycle. Therefore, SDTO1-2 output data is not stable in 516x
LRCK cycle. After exiting reset following power-up, the DAC enters initializing cycle. The analog output becomes
VCOM voltage during this initializing cycle. Figure 19 shows the reset sequence by clock stop.
RSTN bit
Clock In
MCLK, BICK, LRCK
CLK Stop
(1)
516/fs
ADC Internal
State
Normal Operation
Power-down
Power-down
Init Cycle
512/fs
Normal Operation
(2)
DAC Internal
State
Normal Operation
GD
Init Cycle
Normal Operation
GD
(3)
ADC In
(Analog)
(4)
ADC Out
(Digital)
(5)
“0”data
DAC In
(Digital)
“0”data
(3)
GD
GD
(6)
(7)
(6)
DAC Out
(Analog)
10∼11/fs (10)
DZF1/DZF2
External
Mute
(8)
Mute ON
Notes:
(1) The analog section of the ADC is initialized after exiting reset state.
(2) The analog section of the DAC is initialized after exiting reset state.
(3) The Digital output corresponding to a specific analog input, and the analog ouput corresponding to a specific digital
input have group delay (GD).
(4) ADC output is “0” data during reset.
(5) Click noise occurs at the end of initilizing cycle of the ADC. Mute the digital output if click noise influences
systemapplications.
(6) Click noise occurs within 20usec from MCLK, LRCK or BICK stop/start.
(7) DZF1-2 pins output “L” during reset.
(8) Mute the analog output externally if click noise (6) influences system applications.
Figure 18. Reset 2 Sequence Example
MS1278-E-02
2012/03
- 28 -
[AK4627]
■ ADC partial Power-Down Function
All of the ADCs can be powered-down individually by PDAD2-1 bits. The analog part and the digital part of the ADC are
in power-down mode when the PDAD2-1 bits = “1”. The analog section of ADCs are initialized after exiting the
power-down state. Digital outputs corresponding to analog inputs have group delay (GD). ADC outputs “0” data in
power-down state. Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the
click noise influences system applications. Figure 19 shows the power-down and power-up sequences by PDAD2-1 bits.
PDAD2-1 bit
Power Down Channel
ADCDigital
Normal Operation
Power-down
Power-down
Power-down
Normal Operation
516/fs (1)
Init Cycle
Normal Operation
Internal State
516/fs (1)
Init Cycle
ADC Analog
Internal State
Normal Operation
GD
Normal Operation Power-down
Normal Operation
(2)
GD
(2)
ADC In
(Analog)
(3)
“0”data
ADC Out
(Digital)
(4)
(4)
Normal Operation Channel
(2)
(2)
GD
GD
ADC In
(Analog)
(3)
“0”data
ADC Out
(Digital)
Clock In
MCLK,LRCK,SCLK
Note:
(1) The analog part of the ADC is initialized after exiting reset state.
(2) Analog outputs corresponding to the digital inputs have group delay (GD).
(3) ADC outputs “0” data in power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system applications.
Figure 19. ADC partial power-down example
MS1278-E-02
2012/03
- 29 -
[AK4627]
■ DAC partial Power-Down Function
All DACs of AK4627 can be powered-down individually by PDDA1-3 bits. The analog part of DAC is in power-down
mode by PDDA1-3 bits = “1”, however, the digital part is not powered-down. Even if all DACs were set in power-down
mode by the partial power-down bits, the digital part continues an operation. The analog output channels which are
powered-down by PDDA1-3 bits are fixed to the VCOM voltage. Although DZF detection is in operation, DZF detection
results of these analog output channels are not reflected to DZF1-2 pins. Some click noise occurs in both set-up and
release of power-down. Mute the analog output externally or set PDDA1-3 bits when PWDAN bit = “0” or RSTN bit =
“0”, if click noise aversely affects system performance. Figure 20 shows the power-down/up sequences by PDDA1-3 bits.
PDDA1-3 bit
Power Down Channel
DAC Digital
Normal Operation
Internal State
DAC Analog
Internal State
Normal Operation
Power-down
Normal Operation
“0”data
Power-down
NormalOperation
GD
DAC In
(Digital)
(1)
GD
(3)
(2)
(3)
(3)
(3)
(2)
(4)
DAC Out
(Analog)
8192/fs
DZF Detect
Internal State
(4)
Normal Operation Channel
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
8192/fs
DZF Detect
Internal State
Clock In
MCLK,LRCK,SCLK
(5)
(6)
DZF1/DZF2
Notes:
(1) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(2) Analog outputs of the DAC when powered down by PDDA1-3 bits = “1” are fixed to the VCOM voltage.
(3) Immediately after PDDA1-3 bits are changed, a click noise occurs at the output of the channel which is changed by
the own PDDA bits.
(4) Although DZF detection is in operation, DZF detection results of powered-down DAC analog output channels are
not reflected to DZF1-2 pins.
(5) DZF detection of the DAC which is in power-down mode is ignored, and DZF1-2 pins become “H”.
(6) When signal is input to a DAC, even if other DACs are powered-down by partial power-down by PDDA bits,
DXF1-2 pins do not become “H”. Mute the analog output externally if the click noise influences system
applications.
Figure 20. DAC partial power-down example
MS1278-E-02
2012/03
- 30 -
[AK4627]
■ Serial Control Interface
The AK4627’s functions are controlled through registers. The registers may be written by two types of control modes.
The chip address is determined by the state of the CAD0 and CAD1 inputs. The PDN pin = “L” initializes the registers to
their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit but the register data will not be
initialized. When the PS pin state is changed, the AK4627 should be reset by the PDN pin.
* Writing to control register is invalid when the PDN pin = “L”.
(1) 3-wire Serial Control Mode (I2C pin= “L”)
Internal registers may be written through the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this
interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”, Write only), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK
and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of
CSN. The clock speed of CCLK is 5MHz(max).
* The AK4627 does not support read commands in 3wire serial control mode.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 21. 3-wire Serial Control I/F Timing
MS1278-E-02
2012/03
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[AK4627]
(2) I2C-bus Control Mode (I2C pin= “H”)
The AK4627 supports the fast-mode I2C-bus (max: 400kHz).
1. WRITE Operations
Figure 22 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 28). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data
direction bit (R/W) (Figure 23). The most significant five bits of the slave address are fixed as “00100”. The next
two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The
hard-wired input pins (CAD1 pin and CAD0 pin) set these device address bits. If the slave address matches that of
the AK4627, the AK4627 generates an acknowledge and the operation is executed. R/W bit = “1” indicates that the
read operation is to be executed. “0” indicates that the write operation is to be executed.
The second byte consists of the address for control registers of the AK4627. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 24). Those data after the second byte contain control data. The format is
MSB first, 8bits (Figure 25). The AK4627 generates an acknowledge after each byte has been received. A data
transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA
line while SCL is HIGH defines a STOP condition (Figure 28).
The AK4627 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4627 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal
5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address
exceed 0DH prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data
will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only be changed when the clock signal on the SCL line is LOW (Figure 30) except for the START and the
STOP condition.
S
S
T
O
P
T
A
R
T
R/W
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 22. Data transfer sequence at the I2C-bus mode
0
0
0
1
0
0
CAD1 CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 23. The first byte
0
0
A4
A3
A2
D2
A1
D1
A0
D0
Figure 24. The second byte
D7
D6
D5
D4
D3
Figure 25. Byte structure after the second byte
MS1278-E-02
2012/03
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[AK4627]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4627. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 16H prior to generating stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
The AK4627 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK4627 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4627 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4627
ceases transmission.
S
S
T
O
P
T
A
R
T
R/W="1"
Slave
Address
S
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 26. CURRENT ADDRESS READ
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing a slave address
with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit =“1”. The AK4627 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4627 ceases transmission.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W="0"
R/W="1"
Slave
Address
Sub
Address(n)
Slave
Address
S
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 27. RANDOM ADDRESS READ
MS1278-E-02
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[AK4627]
SDA
SCL
S
P
start condition
stop condition
Figure 28. START and STOP conditions
DATA
OUTPUT BY
MASTER
not acknowledge
DATA
OUTPUT BY
SLAVE(AK4529)
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 29. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 30. Bit transfer on the I2C-bus
MS1278-E-02
2012/03
- 34 -
[AK4627]
■ Mapping of Program Registers
Addr Register Name
00H Control 1
01H Control 2
02H LOUT1 Volume Control
03H ROUT1 Volume Control
04H LOUT2 Volume Control
05H ROUT2 Volume Control
06H LOUT3 Volume Control
07H ROUT3 Volume Control
08H De-emphasis
D7
0
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
D6
0
D5
TDM1
LOOP1 LOOP0
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
D4
TDM0
D3
DIF1
0
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
D2
DIF0
D1
0
D0
SMUTE
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
DEMC0
DFS1
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1
DFS0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ACKS
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
DEMC1
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
DEMA1 DEMA0 DEMB1 DEMB0
09H ATT speed
0
0
ATS1 ATS0 PDDA3 PDDA2
PDDA1
RSTN
& Power Down Control
0AH Zero detect
0DH Power Down Control
0
0
DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
PDAD2 PDAD1
0
0
0
0
0
Note: For addresses 0BH, 0CH, 0EH and 0FH, data must not be written.
When the PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized
to their default values.
SMUTE and DFS0 bits are ORed with pins.
MS1278-E-02
2012/03
- 35 -
[AK4627]
■ Register Definitions
Addr Register Name
00H Control 1
Default
D7
0
0
D6
0
0
D5
D4
D3
DIF1
1
D2
DIF0
0
D1
0
0
D0
SMUTE
0
TDM1 TDM0
0
0
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is ORed with the SMUTE pin when the PS pin= “L”.
DIF1-0: Audio Data Interface Modes (Table 8, Table 9, Table 10)
Initial: “10”, mode 2
TDM1-0: TDM Format Select (Table 8, Table 9, Table 10)
Mode
TDM1
TDM0
Data Output
Pins
Data Input
Pins
Sampling Speed
0
1
2
3
0
0
1
1
0
1
0
1
SDTO1-2
SDTO1
-
SDTI1-3
SDTI1
-
Normal, Double, Quad Speed
Normal Speed
N/A
SDTO1
SDTI1-2
Normal, Double Speed
(N/A: Not Available)
MS1278-E-02
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[AK4627]
Addr Register Name
01H Control 2
Default
D7
0
0
D6
D5
D4
D3
0
0
D2
DFS0
0
D1
ACKS
0
D0
0
0
DFS1 LOOP1 LOOP0
0
0
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS bits
are ignored. When this bit is “0”, DFS0 and DFS1 bits set the sampling speed mode.
DFS1-0: Sampling speed mode (Table 1)
Register bit of DFS0 is ORed with DFS0 pin when the PS pin= “L”.
The settings of DFS bits are ignored at ACKS bit “1”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN1 → LOUT1, LOUT2, LOUT3
RIN1 → ROUT1, ROUT2, ROUT3
The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to
SDTI1-3 is ignored. In loopback mode, the actual audio format is forced to mode2 when the SDTO
audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting
is for mode3. (Table 8)
10: SDTI1(L) → SDTI2(L), SDTI3(L)
SDTI1(R) → SDTI2(R), SDTI3(R)
In this mode the input DAC data to SDTI2-3 is ignored.
11: LIN2 → LOUT1, LOUT2, LOUT3
RIN2 → ROUT1, ROUT2, ROUT3
The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to
SDTI1-3 is ignored. In loopback mode, the actual audio format is forced to mode2 when the SDTO
audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting
is for mode3. (Table 8)
MS1278-E-02
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[AK4627]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H LOUT1 Volume Control
03H ROUT1 Volume Control
04H LOUT2 Volume Control
05H ROUT2 Volume Control
06H LOUT3 Volume Control
07H ROUT3 Volume Control
Default
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT7 ATT6
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
0
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
0
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
0
0
0
ATT7-0: Attenuation Level (Table 12)
Addr Register Name
08H De-emphasis
Default
D7
0
0
D6
1
1
D5
D4
D3
D2
D1
D0
DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0
0
1
0
1
0
1
DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (Table 7)
Initial: “01”, OFF
DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (Table 7)
Initial: “01”, OFF
DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (Table 7)
Initial: “01”, OFF
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[AK4627]
Addr Register Name
09H ATT speed
D7
0
D6
0
D5
ATS1
0
D4
ATS0
0
D3
PDDA3
0
D2
PDDA2
0
D1
PDDA1
0
D0
RSTN
1
& Power Down Control
Default
0
0
RSTN: Internal timing reset
0: Reset. DZF1-2 pins go to “H”, but registers are not initialized.
1: Normal operation
ATS1-0: Digital attenuator transition time setting (Table 13)
Initial: “00”, mode 0
PDDA3-1: Power-down control (0: Power-up, 1: Power-down)
PDDA1: Power down control of DAC1
PDDA2: Power down control of DAC2
PDDA3: Power down control of DAC3
Addr Register Name
0AH Zero detect
Default
D7
0
0
D6
DZFM3
0
D5
DZFM2
1
D4
DZFM1
1
D3
D2
D1
D0
PWDAN
1
DZFM0 PWVRN PWADN
1
1
1
PWDAN: Power-down control of DAC1-3
0: Power-down
1: Normal operation
PWADN: Power-down control of ADC
0: Power-down
1: Normal operation
PWVRN: Power-down control of reference voltage
0: Power-down
1: Normal operation
DZFM3-0: Zero detect mode select (Table 11)
Initial: “0111”, disable
Addr Register Name
0DH Power Down Control
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
D0
PDAD2 PDAD1
0
0
PDAD2-1: Power-down control (0: Power-up, 1: Power-down)
PDAD1: Power down control of ADC1
PDAD2: Power down control of ADC2
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[AK4627]
SYSTEM DESIGN
Figure 31 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Condition: TVDD=5V, 3-wire serial control mode, CAD1-0 = “00”
Analog 5V
+
10u
MUTE
2.2u
+
MUTE
MUTE
MUTE
MUTE
MUTE
0.1u
0.1u
26 25
36 35 34 33 32 31 30 29 28 27
2.2u
TST5
RIN2-
24
23
22
21
20
19
18
17
16
15
14
13
37
38
TST4
TST2
RIN2+/RIN2
39 LIN2-
I2C/TST6
DFS0
40
41
42
43
44
LIN2+/LIN2
RIN1-
TST3
RIN1+/RIN1
LIN1-
AK4627
SDTI3
SDTI2
SDTI1
Audio
DSP
LIN1+/LIN1
45
46
47
48
TST1
SGL
LRCK
BICK
DZFE
SMUTE
MCLK
1
2
3
4
5
6
7
9 10
11 12
8
Digital
Audio
Source
0.1u
10u
(DIR)
+
Power-down
control
5
uP
Analog Ground
Digital Ground
Figure 31. Typical Connection Diagram
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[AK4627]
Digital Ground
Analog Ground
DZF2 36
1
CAD0
CAD1
35
34
33
32
31
30
29
28
DZF1
VSS2
2
3
System
Controller
P/S
AVDD
VREFH
VCOM
4
SDTO1
5
SDTO2
AK4627
6
TVDD
ROUT1
LOUT1
ROUT2
7
DVDD
8
VSS1
9
TDM0/SDA/CDTI
DIF1/SCL/CCLK
LOUT2 27
ROUT3 26
LOUT3 25
10
11 DIF0/CSN
PDN
12
Figure 32. Ground Layout
Note: VSS1 and VSS2 must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4627 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up
sequence is not critical. VSS1 and VSS2 of the AK4627 must be connected to analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as near to the AK4627 as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference Inputs
The voltage of VREFH sets the analog input/output range. The VREFH pin is normally connected to the AVDD pin with
a 0.1µF ceramic capacitor in between the VSS2 pin. VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor
in parallel with a 0.1µF ceramic capacitor attached to between the VCOM and VSS2 pins eliminates the effects of high
frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away
from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4627.
3. Analog Inputs
The ADC inputs correspond to single-ended and differential which able to select by the SGL pin. When the inputs are
single-ended, the signal is internally biased to the common voltage (AVDD1x1/2) with 14kΩ(typ) resistance. The input
signal range scales with the supply voltage and nominally 0.68xVREFH Vpp (typ) @fs=48kHz. When the inputs are
differential, the signal is internally biased to the common voltage (AVDD2x1/2) with 32kΩ(typ) resistance. The input
signal range between LIN(RIN)+ and LIN(RIN)− scales with the supply voltage and nominally ±0.68xVREFH Vpp (typ)
@fs=48kHz .The ADC output data format is 2’s complement. The internal HPF removes the DC offset.
The AK4627 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
the sampling frequency of analog inputs. The AK4627 includes an anti-aliasing filter (RC filter) to attenuate a noise
around the sampling frequency of analog inputs.
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[AK4627]
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the
supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a
positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma
modulator of DAC beyond the audio passband.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
5. External Analog Inputs Circuit
Figure 33 shows the input buffer circuit example 3. The input level of this circuit is ±3.4Vpp.
Analog In
3.4Vpp
AIN+
+
2.2uF
50%
-
AK4627
Analog In
3.4Vpp
AIN-
+50%
-
2.2uF
Figure 33. Input buffer circuit example 1 (AC coupled differential input)
Figure 34 shows the input buffer circuit example 3. The input level of this circuit is 3.4Vpp.
Analog In
3.4Vpp
AIN+
+ 50%
2.2uF
-
AK4627
AIN-
Open
Figure 34. Input buffer circuit example 2 (AC coupled single-ended input)
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[AK4627]
6. Peripheral I/F Example
The AK4627 supports signals from external devices which are operated on 3.3V power supplies for TTL inputs. The
power supply for output buffer (TVDD) should be 3.3V when those external devices are connected. Figure 35 shows an
I/F example when 3.3V and 5V power supply devices are used.
5V for input
3.3V Analog
3.3V Digital
Audio signal
PLL
I/F
DSP
AK4113
3.3V for output
5V Analog
5V Digital
uP &
Others
Analog Digital
Control signal
AK4627
Figure 35. Power Supply Connection Example
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[AK4627]
PACKAGE
48pin LQFP(Unit: mm)
1.70Max
9.0
7.0
0.13 ± 0.13
1.40 ± 0.05
36
25
37
24
13
48
1
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10
M
0° ∼ 10°
S
0.10 S
0.30 ~ 0.75
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy
Cu
Lead frame surface treatment:
Solder (Pb free) plate
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[AK4627]
MARKING
AK4627VQ
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4627VQ
4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) Revision Reason
Page
7
Contents
11/01/26
11/08/29
00
01
First Edition
Specification
Change
ANALOG CHARACTERISTICS
ADC Analog Input Characteristics (Single-ended Inputs)
S/(N+D), fs=48kHz: 92 → 96dB (typ)
fs=96kHz: 86 → 92dB (typ)
DR, fs=96kHz: 96 → 99dB (typ)
fs=96kHz, A-weighted: 102 → 105dB (typ)
S/N: fs=96kHz: 96 → 99dB (typ)
fs=96kHz, A-wieghted: 102 → 105dB (typ)
ADC Analog Input Characteristics (Differential Inputs)
S/(N+D), fs=48kHz: 92 → 96dB (typ)
fs=96kHz: 86 → 94dB (typ)
DR, fs=96kHz: 97 → 100dB (typ)
fs=96kHz, A-weighted: 103 → 106dB (typ)
S/N: fs=96kHz: 97 → 100dB (typ)
fs=96kHz, A-wieghted: 103 → 106dB (typ)
DAC Analog Output Characteristics
S/(N+D), fs=48kHz: 90 → 98dB (typ)
fs=96kHz: 88 → 98dB (typ)
8
fs=192kHz: 88 → 98dB (typ)
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[AK4627]
Date (Y/M/D)
12/03/07
Revision Reason
Page
3
Contents
■ Ordering Guide
02
Error
Correction
AK4627 → AK4627VQ
9
DC CHARACTERISTICS
High-level Output Voltage Condition:
SDTO1-2, LRCK, BICK pins → SDTO1-2 pins
Low-level Output Voltage Condition:
SDTO1-2, LRCK, BICK, DZF1, DZF2 pins
→ SDTO1-2, DZF1, DZF2 pins
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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相关型号：
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