A4930GETTR-T [ALLEGRO]
PWM Based Peripheral Driver, 5 X 5 MM, 0.90 MM HEIGHT, MO-220VHHD-1, LEAD FREE, QFN-28;
| 型号： | A4930GETTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | PWM Based Peripheral Driver, 5 X 5 MM, 0.90 MM HEIGHT, MO-220VHHD-1, LEAD FREE, QFN-28 驱动 接口集成电路 |
| 文件： | 总10页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A4930
Single Phase Fan Pre-Driver
Features and Benefits
▪ Synchronous rectification for low power dissipation
▪ Drives four N-channel MOSFETs
▪ Internal UVLO and thermal shutdown circuitry
▪ Hall element input
▪ PWM current limiting
▪ Dead time protection
▪ FG output
▪ RD output
Description
Designed for pulse width modulated (PWM) current control
of single phase brushless fans, the A4930 minimizes external
component count and integrates all the key features required
forhigh-currentfans.Internalsynchronousrectificationcontrol
circuitry is provided to improve power dissipation in the
external MOSFETs during PWM operation. Internal circuit
protection includes thermal shutdown with hysteresis, rotor
lock, and dead time protection.
▪ Lock detect protection
▪ High VBB absolute maximum
▪ Soft start
▪ A4930GETTR-T AEC-Q100 qualified
The A4930 is supplied in a 0.90 nominal overall height,
5 mm × 5 mm, 28-pin QFN with exposed thermal pad, (suffix
ET). It is lead (Pb) free with 100% matte tin leadframe
plating.
Package: 28-pin QFN with exposed
thermal pad (suffix ET)
Approximate size
Functional Block Diagram
0.1 μF
0.1 μF
Hall
500 Ω
VREG5
CLD
5V
8V
0.1 μF
CHARGE PUMP
VCP
0.1 μF
0.1 μF
RD
Lock Detect
VBB
FGO
+12V
0.22 μF
Hall
Hall
HP
HN
10 μF
VCP
VREG8
GHA
3.5v
1.5v
VREG5 HP HN
SA
PWM
SIN
Hall
GATE
DRIVE
Fan
GHB
SB
VREG5
0.1 μF
GLB
Control
Logic
5
kΩ
GLA
SMIN
SENSE
VREF
100 mΩ
8.2 kΩ
5 kΩ
470 pF
vref
/5
CPWM
CDEL
VREG5
51 kΩ
1.24 kΩ
SS
0.47 μF
4930-DS, Rev. 3
A4930
Single Phase Fan Pre-Driver
Selection Guide
Part Number
Ambient Operating
Temperature, TA (°C)
Packing
A4930GETTR-T
A4930GETTR-C-T
–40 to 105
–20 to 105
1500 pieces per 7-in. reel
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
36
Units
V
Load Supply Voltage
Hall Input
VHx
–0.3 to 6
–0.3 to 6
–40 to 105
–20 to 105
150
V
Logic Input Voltage Range
VIN
V
A4930GETTR-T
ºC
ºC
ºC
ºC
Operating Temperature Range
TA
A4930GETTR-C-T
Junction Temperature
TJ(max)
Tstg
Storage Temperature Range
–55 to 150
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Symbol
Test Conditionsa
Value
Units
4-layer PCB based on JEDEC standard
32
ºC/W
Package Thermal Resistance
(Junction to Ambient)
RθJA
2-layer PCB with 0.7in.2 copper area
65
ºC/W
ºC/W
Package Thermal Resistance
(Junction to Case)
20b
RθJC
aAdditional thermal information available on Allegro™ website.
bEstimated.
Power Dissipation versus Ambient Temperature
4000
3750
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
25
50
75
100
125
150
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
ELECTRICAL CHARACTERISTICS1 valid at TA = 25°C, VBB = 12 V, unless noted otherwise
Characteristic
Load Supply Voltage Range
Motor Supply Current
VREG5
Symbol
VBB
Test Conditions
Min.
8
Typ.2
12
5
Max.
36
7
Units
V
Operating
IBB
fPWM < 30 kHz, Cload = 1000 pf
Iload = 10 mA
–
mA
V
V5
4.7
15
–
5
5.3
–
VREG5 Current Limit
VREG5 Load Regulation
Control Logic
IREG5
VREG5
–
mA
mV
IREG5 = 1 to 10 mA
12
30
VIN(1)
VIN(0)
IIN(0)
IIN(1)
2
–
–
–
–
–
–
0.8
–
V
Logic Input Voltage
V
PWM Pin Input Current
Other Logic Pin Input Current
Gate Drive
VIN = 0, 50 kΩ pull-up
–100
–34
μA
μA
VIN = 3.3
–
High Side Gate Drive Output
Low Side Gate Drive Output
Gate Drive Current Turn-on
Gate Drive Pulldown
Dead Time
VGHx
VGLx
IG
Relative to VBB, VBB = 12 V
GHx = GLx = 4 V
7
7
–
–
–
8.5
–
V
V
–
20
mA
Ω
RDS
tDEAD
–
40
–
700
1000
1300
ns
Control
Soft Start Time
tSS
fPWM
VPP
VLO
VHI
CLD = 0.47 ꢀF
CPWM = 470 pF
CPWM = 470 pF
–
15
–
300
21
–
27
–
ms
kHz
V
Internal PWM Frequency
CPWM Output Voltage
CPWM Low Threshold
CPWM High Threshold
SIN Input Impedance
Protection
2
–
1.5
3.5
200
–
V
–
–
V
ZIN
–
–
kΩ
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TJTSD
–
–
165
15
–
–
°C
°C
TJTSDhys
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
ELECTRICAL CHARACTERISTICS1 (continued) valid at TA = 25°C, VBB = 12 V, unless noted otherwise
Characteristic
VBB Undervoltage Lockout Enable Threshold
VBB Undervoltage Lockout Hysteresis
VCP Undervoltage Lockout Enable Threshold
Lock Detect On-Time
Symbol
VBBUV
VBBUVhys
VCPUV
tLDon
Test Conditions
Min.
–
Typ.2
7.5
0.8
5.4
1
Max.
Units
Rising VBB
7.85
V
V
V
s
0.3
–
–
–
–
–
Relative to VBB, VBB rising
CLD = 0.1 ꢀF
–
Lock Detect Off-Time
tLDoff
CLD = 0.1 ꢀF
–
15
s
Hall Logic
Hall Input Current
IHALL
VCMR
VHALL
Vth
VIN = 1.2 V
–1
0.2
60
–
0
–
1
3
ꢀA
V
Common Mode Input Range
AC Input Voltage Range
Hall Threshold
–
–
mVp-p
mV
mV
ꢀs
Difference in Halls at FG transition
RCDEL = 50 kΩ
10
20
2
–
Hysteresis Width
VHYS
tCD
5
35
3
Pulse Reject Filter
1
Commutation Delay
VPU
–
50
–
mV
FG and RD Outputs
Output Saturation Voltage
Leakage Current
VOL
VOH
I = 2 mA
V = 5 V
–
–
0.27
–
0.4
1
V
ꢀA
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
Functional Description
VREG5 This pin should be decoupled with a 0.1 μF capacitor
to ground. VREG5 can supply up to 15 mA, which can used to
power the external Hall element.
A soft start capacitor, CSS, can be connected to the SS pin to set
the rate for slowly ramping-up the load current to the maximum
value, according to the relationship:
VREG8 This pin should be decoupled with a 0.1 μF capacitor to
ground. VREG8 is used to power the low-side gate drive circuits.
t
SS = (CSS × VREF) / 3.3E–6
(4)
.
In this case the current limit will likely not be achieved and there
will be less demand on the input power supply. If this feature is
not utilized, the SS pin should be left open.
Charge Pump The charge pump is used to generate a supply
above VBB to drive the high-side MOSFETs. The VCP voltage
is internally monitored, and in the case of a fault condition, the
outputs of the device are disabled.
Synchronous Rectification When a PWM off-cycle is triggered,
load current recirculates. The A4930 synchronous rectification
feature turns on the appropriate MOSFETs during current decay,
and effectively shorts out the body diodes of the low RDS(on)
driver.
Lock Detect The IC detects a locked rotor condition by checking
to ensure that the FG output signal is continuously changing. The
length of time allowed for a stoppage before evaluating a locked
condition, tLD, is set by capacitor connected to CLD pin. CLD pro-
duces a triangle waveform with a frequency that is linearly related
to the capacitor value. The definition of tLD is defined as 8 cycles
of this triangle waveform, and its value can be calculated as:
TSD If the die temperature exceeds approximately 165°C, the
outputs will be disabled until the internal temperature falls below
a hysteresis level of 15°C.
tLD = CLD × (10 s /μF) .
(1)
Shutdown In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VBB, the outputs of
the device are disabled until the fault condition is removed. At
power-up the UVLO circuit disables the drivers until the UVLO
threshold is reached.
If an FG transition is not detected within tLD, the IC will disable
the appropriate source driver and hold both sink drivers on. The
circuit will automatically retry with a 15:1 ratio of off-time to on-
time. An RD pin logic high indicates this fault condition.
Current Limit and Soft Start To minimize demand on the
power supply, peak current is controlled. Initially, with the fan
at a stand-still, the turn-on of the bridge results in current rising
according to the L/R time constant of the motor. To prevent over-
stress, this peak current is regulated by an internal PWM control
circuit. When the outputs of the full-bridge are turned on, current
increases in the motor winding until it reaches a value given by:
CPWM This capacitor sets the frequency of the internal PWM
circuit. The value is typically from 15 to 30 kHz.
PWM The IC accepts a direct input PWM signal with a level in
the range from 0 to 6 V. The duty cycle, DC, of the input to this
pin is converted to an analog voltage that is output on the SIN
terminal as follows:
ITRIP = VREF / 5 × RSENSE
.
(2)
VSIN = 3.5 V –2 × DC .
(5)
The RSENSE value should be chosen to keep the peak sense voltage
within the range of 200 to 500 mV, according to the relationship:
If the PWM input is not used, then leave this pin open circuit.
Direct external PWM control can be utilized by applying the
signal to the SIN input (refer to the Applications Information sec-
tion). This can be implemented to create different PWM input to
PWM output transfer functions.
RSENSE < 500 mV / ITRIP
(3)
.
At the trip point, the sense comparator resets the source enable
latch, turning off the source driver. At this point, load inductance
causes the current to recirculate for 50 μs.
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
SIN An analog voltage input to this pin sets the duty cycle applied ever is set to a lower voltage. For 100% duty cycle applications,
to the fan winding. For temperature-based systems, connect SIN
to a thermistor output. For systems with direct input to the PWM
pin, the pin should be decoupled with a 0.1 μF capacitor. If vari-
able fan speed is not required, for 100% duty cycle, connect this
pin to GND. The input impedance is 200 kΩ (referenced to a
3.5 or 1.5 V rail).
connect this pin to GND.
CDEL A resistor connected between this pin and GND sets
the level at which the A4930 switches to slow decay mode in
advance of the Hall zero crossing as shown here:
V
CDEL = (2950 / RCDEL) – 7 mV (mV)
(6)
.
SMIN An analog voltage input to this pin sets the minimum speed
duty cycle to the fan winding. The PWM comparator chooses
either SIN or SMIN to determine the output duty cycle, which-
The resistor should be 25 to 100 kΩ. If this feature is not used,
the CDEL pin should be pulled up to VREG5 with a 5 kΩ resistor.
LD
FG
HP
Vth(1) = VHP – VHN = 10 mV (Typical)
Vth(2) = VHN – VHP = 10 mV (Typical)
VHYS = Vth(1) + Vth(2) = 20 mV (Typical)
VCDEL(1)
VCDEL(2)
0
Vth(1)
Vth(2)
HN
SA
SB
tCDEL
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
Applications Information
Overvoltage In a typical fan application, there is a blocking
diode that prevents currents from flowing back out of the fan
assembly to the 12 V supply. When the fan commutates before
the current has decayed to zero, the current charges up the VBB
bypass capacitor.
• Keep the sense connection to the power bridge as short as pos-
sible. This can be achieved by positioning the MOSFETs next to
each other, and by connecting the source of the sink side MOS-
FETs via a short trace, preferably on the surface of the PCB,
under the MOSFETs. A short trace here would minimize voltage
spikes due to inductance in the path, where currents switch at
high di/dt.
The larger the bypass capacitor, the less the voltage overshoot.
Typically, a clamp diode is required to dissipate energy from the
inductive kickback to avoid exceeding the maximum rating for
• Place the power traces from the MOSFETs to the motor con-
nector on the opposite side of the PCB. If possible, on that side
isolate the power traces by ground traces in order to minimize
interference with other signal traces due to the high dv/dt of the
power traces.
VBB , 36 V.
Layout Small form factor PCBs present a layout challenge for
the application. The layout would be restricted by the placement
of the Hall element, the location of the motor connectors, and the
common requirement that all components be placed on one side
of the PCB. For optimum results, consider the following recom-
mendations:
• Locate the A4930 to minimize the length of the GHx/GLx/Sx
traces to the power stage.
• Connect the GND pins of the A4930 to the exposed pad. Use
vias under the IC case to connect the exposed pad to the ground
plane on the opposite face of the PCB.
• Place the external MOSFET bridge close to the power connec-
tor. The bridge includes two dual N-channel MOSFETs, a sense
resistor, and a power supply capacitor. This will keep the large
current flows in one area of the PCB and avoid ground loop
problems.
External PWM Refering to the figure below, if external PWM
control is being used, the high voltage level is set by R1, R2, and
R3. The low voltage level is set by R1 and R3.
VREG5
0.1 μF
PWM
SIN
R1
10 kΩ
Control
Logic
0.47 μF
+
–
R2
PWM
Duty In
5 kΩ
R3
SMIN
CPWM
8.2 kΩ
PWM control using External PWM input
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
Pin-out Diagram
VREG5
CLD
FG
SA
1
2
3
4
5
6
7
21
20
19
18
17
16
15
GHB
SB
PAD
RD
VREG8
GLA
HP
HN
GLB
CDEL
SENSE
Terminal List
Number
Name
Description
Number
16
Name
GLB
Description
1
2
3
VREG5 Regulator decoupling terminal
Low-side drive for external N-channel MOSFET
Low-side drive for external N-channel MOSFET
CLD
FG
Capacitor to set Lock Detect Time
17
GLA
FG output, fan speed indicator (open drain)
18
VREG8 Gate drive supply
RD output, high for locked rotor condition (open
drain)
4
RD
19
SB
High-side source connection
5
6
HP
HN
Hall input positive
Hall input negative
20
21
22
23
24
25
26
27
28
GHB
SA
High-side drive for external N-channel MOSFET
High-side source connection
High-side drive for external N-channel MOSFET
Ground
7
CDEL Commutation delay
PWM PWM input
CPWM Capacitor to set internal frequency
GHA
GND
CP1
CP2
VCP
VBB
NC
8
9
Charge pump capacitor terminal
Charge pump capacitor terminal
Reservoir capacitor terminal
Supply voltage
10
11
12
13
14
15
SIN
SMIN
SS
Speed analog input/adjusted PWM output
Minimum speed analog input
Connection for soft start capacitor
Current limit setpoint
VREF
GND
Not connected
Ground
Thermal pad, connect to GND plane with vias to
bottom of PCB
–
Pad
SENSE Sense resistor connection
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
Package ET 28-Pin QFN with Exposed Thermal Pad
0.30
5.00 ±0.15
0.50
1.15
28
28
1
2
1
A
5.00 ±0.15
3.15 4.80
3.15
4.80
D
29X
C
SEATING
PLANE
0.08 C
C
PCB Layout Reference View
+0.05
–0.07
0.25
0.90 ±0.10
0.50
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
+0.20
–0.10
0.55
A
B
Terminal #1 mark area
3.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
2
1
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
28
3.15
D
Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4930
Single Phase Fan Pre-Driver
Revision
Change
Pages
Responsible
R. Fennelly
R. Fennelly
Date
2
3
Revised Operating Temperature Range
Revised Features and Benefits
2
1
February 26, 2014
March 12, 2014
Copyright ©2008-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
相关型号：
A4930METTR-T
PWM Based Peripheral Driver, 5 X 5 MM, 0.90 MM HEIGHT, MO-220VHHD-1, LEAD FREE, QFN-28
ALLEGRO
A4931METTR-T
Brushless DC Motor Controller, 5 X 5 MM, 0.90 MM HEIGHT, LEAD FREE, MO-220VHHD-1, QFN-28
ALLEGRO
A4933
The A4933 is a 3-phase controller for use with N-channel external power MOSFETs and is specifically designed for automotive applications.
ALLEGRO
A4935_12
The A4935 is a 3-phase controller for use with N-channel external power MOSFETs and is specifically designed for automotive applications.
ALLEGRO
©2020 ICPDF网 联系我们和版权申明