ARA05050S12-1 [ANADIGICS]
CATV Reverse Amplifier w/step Attenuator; CATV反向放大器W /步进衰减器
| 型号： | ARA05050S12-1 |
| 厂家： | 
ANADIGICS, INC |
| 描述： | CATV Reverse Amplifier w/step Attenuator |
| 文件： | 总12页 (文件大小：1466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ARA05050S12
CATV Reverse Amplifier w/ Step Attenuator
Advanced product information
Rev. 6
A
FEATURES
•
Integrated monolithic GaAs amplifier and step
attenuator.
•
•
•
•
•
•
•
•
•
•
Compatible with all digital and analog modulation types.
Frequency range: 5 - 100 MHz.
Gain: 0 - 30 dB, variable in 2 dB steps.
5 Volt operation.
Low noise figure.
Low distortion.
Amplifier shutdown capability.
Low cost.
High reliability.
S12C
Low signal to noise ratio at all gain levels.
28 Pin SSOP w/ Heat Slug
DESCRIPTION
levels. Both the input and output are
matched to 75 ohms. The precision
attenuator provides up to 30 dB of
attenuation in 2 dB increments. The
ARA05050 is supplied in a 28-pin SSOP
package featuring a thermal heat slug on
the bottom of the package. Soldering this
heat slug to the ground plane of the PC
board ensures the lowest possible thermal
resistance for the device resulting in a
long MTF.
The ARA05050 is a GaAs IC designed to perform the
reverse path amplification and output level control
functions in a CATV Set-Top Box or Cable Modem. It
incorporates a digitally controlled precision step
attenuator that is preceded by an ultra low noise amplifier
stage, and followed by an ultra-linear output driver
amplifier. It is capable of meeting the MCNS/DOCSIS
harmonic distortion specifications while only requiring a
single polarity +5V supply. This part is a single ended
design that does not require an output balun to achieve
-55 dBc 2nd harmonic performance at +58 dBmV output
Tx Enable/Disable
Gain Control
Upstream
ATTN
2/4/8/16 dB
QPSK/
16-QAM
Modulator
PA
PA
LPF
Balun
ARA05050 Reverse Amp
Clock
Clock
Data
Data
5-42 MHz
RAM
ROM
Coax
Microcontroller
w/Enet MAC
MAC
Connector
Diplex
Filter
45 MHz IF
Double
Conversion
Tuner
QAM
Receiver
w/FEC
54-860 MHz
10Base-T
Tranceiver
RJ45
Connector
SAW
Figure 1. Cable Modem or Interactive Set-Top Box Block Diagram
*See ANADIGICS ACU50751 and ACD0900
ARA05050S12
Advanced Product Information - Rev. 6
ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 °C)
Parameter
Gain 1
Min
30
-
Typ
32
Max
33
Unit
dB
Comments
At 0dB attenuation setting
5 to 100 MHz
1
Gain Flatness
0.75
1.5
dB
Attenuation Steps 1
2 dB
4 dB
1.6
3.8
1.85
4.0
2.2
4.2
dB
5 to 42 MHz 3
8 dB
8.0
8.3
8.5
16 dB
16.0
16.6
17.0
2nd Harmonic Distortion Level 2
3rd Harmonic Distortion Level 2
5 MHz
25 MHz
-
-
-60
-63
-55
-55
dBc
dBc
5 MHz
25 MHz
-
-
-63
-63
-60
-60
3rd Order Output Intercept Point
1dB Gain Compression Point
Noise Figure
78
-
-
-
dBmV
dBmV
dB
70
1.7
-
-
2.5
Output Noise Power
Any 3200 KHz bandwidth from
5 to 42 MHz
Active/No Signal/Min Attn. Setting
Active/No Signal/Max Attn. Setting
-
-
-
-
-24.6
-41.6
dBmV
dB
On/Off Isolation
Difference in output signal level
between active and standby
Shut Off Stage 2
-
30
53.5
-
-
Shut Off Stages 1 & 2
Input Impedance1
Input Return Loss1
Output Impedance1
-
-
75
-20
75
-20
5
-
-15
-
ohm
dB
ohm
dB
V
-
1
Ouput Return Loss
VDD1, VDD2
VDD Digital
V Shutdown
IDD1
-
-15
7
-
-
5
-
V
-2
-
-
-1.5
95
130
-
V
75
100
8
mA
mA
mA
W
IDD2
-
IDD Digital
-
Power Consumption
-
1
1.2
-
Attenuator Control Impedance
Attenuator Control Logic 4
-
5 K
ohm
-
-
VIL
VIH
0
2.8
0.5
6.5
Volts
Notes:
1. As measured in ANADIGICS test fixture
2. At +58 dBmV output level into 75 ohm load
3. For higher frequencies see figures 3 & 4.
4. With 470 ohm chip resistor from pin 2 to gnd (see test circuit).
2
A
ARA05050S12
Advanced Product Information - Rev. 6
ABSOLUTE MAXIMUM RATINGS
Parameter
Absolute Maximum
Unit
VDC
VDC
VDC
VDC
dBmV
°C
VDD (Pins 4,12, 18)
VRFIN (Pins 10, 24)
9
0 to -3
ATT (Pin 3) ATTOUT (Pin 26)
5
IN
VISET (Pins 11, 25)
2
+60
RF Input Voltage (Pins 10, 24)*
Storage Temperature
-55 to +200
260
Soldering Temperature
Soldering Time
°C
5
Sec
°C
Operating Case Temperature
* Blocking capacitors required
-40 to +85
ATTOUT RFIN2
RFOUT1
ATTIN
Shutdown
Shutdown
30 dB 2 dB step digital attenuator section
RF
IN
AMP
AMP
RFOUT
ISET1
16 dB
8 dB
2 dB
4 dB
ISET2
Figure 2
3
A
ARA05050S12
Advanced Product Information - Rev. 6
Figure 4
Figure 3
Figure 6
Figure 5
Figure 7
Figure 8
4
A
ARA05050S12
Advanced Product Information - Rev. 6
Figure 9
Figure 10. Attenuator Switching Speed 16 dB Step
Figure 11. Switching Speed of Output Disconnect Switch
5
A
ARA05050S12
Advanced Product Information - Rev. 6
TEST CIRCUIT
1
2
3
4
5
28
27
*
VDD1
0.1 uF
0.01 uF
1uF
10 uH
0.1 uF
3.3K
26
0.1 uF
25
20
W
24
1000
pF
1.8K
Shutdown
#2
0.01 uF
5K
5K
23
22
6
7
1 uF
0.01 uF
0.01 uF
1pF
620
W
1uF
620
ANADIGICS
0.01 uF
10uH
W
VDD2
ARA05050 21
Shutdown
#1
8
9
1 uF
5K
0.1 uF
3.3K
1.8K
20
19
18
17
16
15
5K
1 uF
RF IN
10
11
20
W
0.1 uF
1 uF
0.1 uF
0.1 uF
RFOUT
1 uF
3.9
W
12
13
14
0.01 uF
5V
digital
* = 470
W resistor for 3V attn. control
4
3
2
1
DIP SWITCH LOGIC TABLE
Attn (dB)
SW 1
2
4
6
8
10 12 14 16 18
20 22 24 26 28 30
X
O
O
O
O
X
O
O
X
X
O
O
O
O
X
X
O
X
O
X
X
O
X
X
X
O
O
O
O
X
X
O
O
X
O
X
O
X
X
X
O
X
O
O
X
X
X
O
X
X
O
X
X
X
X
X
X
X
SW 2
SW 3
SW4
O
O
O = Open
X = Closed
6
A
ARA05050S12
Advanced Product Information - Rev. 6
PIN DESCRIPTION
PIN
1
FUNCTION
DESCRIPTION
NC
Bypass
ATTIN
No Connection
2
Internal bypass. This pin must be externally ac decoupled (0.1uf cap)
Attenuator Input
3
4
RFOUT1+VDD1
VREF1
RF Output and +5v Supply for 1st Amplifier Stage
Reference voltage for 1st Amplifier
5
6,7,8,9
AC_GND
RFIN
AC Ground. These pins must be externally ac decoupled (1uF and 0.01uF cap)
RF Input to 1st Amplifier Stage
10
11
ISET1
Resistor set current for 1st Amplifier
12
5V digital
16 dB
5 volts digital supply voltage
13
16 dB Attenuator Control Parallel data input
8 dB Attenuator Control Parallel data input
4 dB Attenuator Control Parallel data input
2 dB Attenuator Control Parallel data input
Digital Ground
RF Output and +VDD2 V Supply for 2nd Amplifier Stage
Reference voltage for 2nd Amplifier
14
8 dB
15
4 dB
16
2 dB
17
Dig GND
RFOUT+VDD2
VREF2
18
19
20,21,22,23
AC_GND
AC Ground. These pins must be externally ac decoupled (1uF and 0.01uF cap)
RF Input to 2nd Amplifier Stage and Shutdown pin for 2nd Amplifier
Resistor set current for 2nd Amplifier (ground for max performance)
Attenuator Output
IN2
24
25
26
27
28
RF
ISET2
ATTOUT
NC
No Connection
NC
No Connection
7
A
PACKAGE OUTLINE
Application Note
LAYOUT CONSIDERATIONS
be +5V. When the switch is in the open state, it
is good general practice to set the program-
mable attenuator to its maximum attenuation
setting. This will increase the isolation between
the cm output and upstream modulator, and
provide the first stage amplifier with a 75 ohm
termination.
There are two issues that must be taken into
consideration when doing the PCB layout.
The first is thermal management, and the
second is RF related.
THERMAL LAYOUT CONSIDERATIONS
The ARA05050 will typically dissipate 0.9W,
and as high as 1.2W. Since the interior of
most set-top boxes, and cable modems as
Shutdown of the ARA05050:
In some applications it may be desirable to shut
the ARA05050 down for power saving. This can
be done by applying a negative voltage to pin 10
to shut down the input stage, and to pin 24 to
shut down output stage (see Figure 13). Shut-
ting down both amplifier stages will reduce the
current drawn from the +5V supply to typically
10 mA. If only one stage is shutdown, it is
recommended that the programmable attenuator
be set to a minimum of 16 dB to provide a good
impedance match to the remaining stage.
well typically are at +70°C, consideration
must be given to providing an adequate heat
sink for the die to obtain the maximum MTF
possible. To this end the ARA05050 incorpo-
rates a heat slug in the bottom of the pack-
age. This provides a low thermal resistance
path from the die to the outside of the pack-
age. The typical thermal rise from the heat
slug to the junction is 35°C/W. However, this
is only half of the equation. Adequate heat
sinking must be applied to the heat slug for
thermal dissipation. Providing a metalized pad
with via holes under the package will do this
(see Figure 14). The via holes should connect
to the ground plane of the PCB. The part is
then soldered to this pad during assembly.
RF LAYOUT CONSIDERATIONS
The ARA05050 is a power amplifier designed for
driving a 75ohm load. Since this part connects
the transmitter to the cable system, typically via
a diplexer, it is an analog device operating at RF
frequencies. This means that the layout of the
PCB will have an effect on the system perfor-
mance. The first consideration in RF layout are
the connections to ground. These must be low
impedance, and as short as possible. The best
way to do this is to use as large a via hole as
possible, located as close as possible to
connect to the ground plane. Specifically, care
should be given to the layout of the following
connections (the traces leading from the
EXTERNAL CIRCUITRY
Output Disconnect Switch:
For MCNS/DOCSIS applications an external
switch to disconnect the output of the
ARA05050 from the diplexer is required. This
switch is needed because of the output noise
requirement between bursts, and because of the
requirement that any shutdown transient not
exceed 7mV. The switch shown in Figure 12
meets these conditions because it does not
switch any current, or voltage, on the output
line. The series FET provides 35 dB of isolation,
while the shunt FET insures that the diplexer
remains terminated into a 75 ohm impedance.
Since the switch does not draw any current, it
may be driven directly from a low power CMOS
logic inverter; however the control voltages must
following pins to their respective components
should be as low as impedance as is practical.):
Pins 5 & 19: the 20 ohm chip resistor should be
as close as possible to the pins and the 1 uF
capacitor should be kept close to the 20 ohm
resistor.
ARA05050S12
Advanced Product Information - Rev. 6
Application Note
Pins 6–9 & 20–23: the capacitors should be
kept close to the pins.
The bypass capacitors on the Vdd lines should
be located as close as possible to the 10 uH
inductors.
Pin 11: the 1uF bypass capacitor should be
kept close to the pin.
The traces leading to the RF input, and leading
away from the RF output, should be 75 ohms.
Care should be taken to keep other traces,
which may have clock signals on them, as far
away as is practical to prevent unwanted
coupling onto the signal line.
Pin 12: the bypass capacitor at this node
should be reasonably close ot the pin.
The path leading between pins 4–10, and the
path between pins 18–24, should be kept as
short as possible.
10
A
ARA05050S12
Advanced Product Information - Rev. 6
+5V
+5V
.1uF
.1uF
10K
W
.1uF
.1uF
Q1
Q1/Q2 are
Input
Output
AF002C4 (Alpha)
(from rev. amp)
(to diplexer)
27
W
75W
Insertion Loss
@ 45 MHz: 0.1dB
10K
W
Q2
10K
W
3.3KW
+5V
Switch
Control
Isolation
@ 45 MHz: 38dB
3.3K
W
.1uF
.1uF
2nd Harmonic
@ +58 dBmV > 70dBc
Logic output levels
of 0 to +5V
Figure 12. Output Disconnect Switch
+3.3V
Pin 10/24
1st or 2nd stage of
Reverse Amplifier
Output
5KW
500
W
VCONT (0/3.3)
Q1
5K
W
Q2
3K
W
2.5K
W
Set IQ2 for ~ -2V at gate of
second stage of rev amp
-5V
Q1: 2N3906
Q2: 2N3904
Figure 13
11
A
ARA05050S12
Advanced Product Information - Rev. 6
ANADIGICS, Inc.
35 Technology Drive
Warren, New Jersey 07059
Tel: (908) 668-5000 / Fax: (908) 668-5132
Email: Mkg@anadigics.com
www.anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or discontinue any product at any time without notice.
The Advanced Product data sheets and product specifications contained in this data sheet are subject to change prior to a
products formal introduction. The information in this data sheet has been carefully checked and is assumed to be reliable.
However, ANADIGICS assumes no responsibility for inaccuracies. ANADIGICS strongly urges customers to verify that the
information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, device, or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
12
A
相关型号：
©2020 ICPDF网 联系我们和版权申明