APW7063KC-TRL [ANPEC]
Synchronous Buck PWM and Linear Controller; 同步降压PWM和线性控制器
| 型号： | APW7063KC-TRL |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM and Linear Controller |
| 文件： | 总21页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7063
Synchronous Buck PWM and Linear Controller
Features
General Description
The APW7063 integrates PWM and linear controller,
as well as themonitoring and protectionfunctions into
·
Provide Two Regulated Voltages
- Synchronous Rectified Buck PWM Controller
- Linear Controller
a single package. The synchronous PWM controller
which drives dualN-channel MOSFETs, which provides
one controlled power outputs with under-voltage and
over-current protections. Linear controller drives an
external N-channel MOSFET with under-voltage
protection.
·
·
Fast Transient Response
- 0~85% Duty Ratio
Excellent Output Voltage Regulation
- 0.8V Internal Reference
APW7063 provides excellent regulationfor output load
variation. An internal 0.8V temperature-compensated
reference voltage is designed to meet the various low
output voltage applications. APW7063 includes a
250kHz free-running triangle-wave oscillator that is
adjustable from below 70KHz to over 800KHz.
- ±1% Over Line Voltage and Temperature
Over Current Protection
·
- Sense Low-Side MOSFET’s RDS(ON)
Under Voltage Lockout
·
·
Small Converter Size
- 250KHz Free-Running Oscillator
- Programmable From 70kHz to 800kHz
14-Lead SOIC Package
A power-on-reset (POR)circuit limits the VCC minimum
opearting supply voltage to assure the controller
working well. Over current protection is achieved by
monitoring the voltage drop across the low side
MOSFET, eliminating the need for a current sensing
resistor and short circuit condition is detected through
the FB pin. The over-current protection triggers the
soft-start function until the fault events be removed,
but Under-voltage protection will shutdown IC directly.
·
·
Lead Free Available (RoHS Compliant)
Applications
·
Graphic Cards
·
·
·
·
Memory Power Supplies
DSL or Cable MODEMs
Set Top Boxes
Pull the COMP pin below 0.4V will shutdown the
controller, and both gate drive signals will be low.
Pinouts
Low-Voltage Distributed Power Supplies
1
2
3
4
5
6
7
RT
SS
FBL
14
13
12
DRIVE
VREG
VCC
11
10
9
LGATE
PGND
FB
COMP
BOOT
GND
PHASE
8
UGATE
ANPEC reserves the right to make changesto improve reliability or manufacturability without notice, and advise
customers to obtain the latest versionof relevant informationto verify before placingorders.
Copyright ã ANPECElectronicsCorp.
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Rev. A.7 - Nov., 2005
APW7063
Ordering and Marking Information
Package Code
APW7063
K : SOP - 14
Lead Free Code
Handling Code
Temp. Range
Package Code
Operating Ambient Temp. Range
°
C : 0 to 70 C
Handling Code
TU : Tube
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
XXXXX - Date Code
APW7063
XXXXX
APW7063 K :
Note:ANPEC lead-free products contain molding compounds/die attach m aterials and 100% matte tin plate
termination finish;which are fullycompliant with RoHSand compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Block Diagram
SS
VCC
vcc
BOOT
I
SS
5.8V
Power-On
Reset
10uA
GateControl
UGATE
vcc
SoftStart
and
FaultLogic
I
OCSET
GND
250uA
PHASE
VCC
U.V.P
Comparator
O.C.P
Comparator
50%VREF
:
2
LGATE
PGND
FBL
50%VREF
VCC
:
2
PWM
Comparator
ErrorAmp
VCC
DRIVE
VREF
Oscillator
Regulator
V
REF
Triangle
Wave
FB
COMP
RT
VREG
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Rev. A.7 - Nov., 2005
APW7063
Application Circuit
1. Boot-Strap - Use Internal Regulator
C1
12V
D1
5V
12V
1uF
1N4148
L1
VIN
R1
2R2
1uH
+
C2
470uF
6.3V
25mR
VIN
R2
R3
N C
N C
U1
APW7063
+
C5
470uF
16V
+
C6
470uF
16V
+
C7
470uF
16V
C 3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7
6
5
4.7uF
RT
SS
VREG
FB
COMP
GND
FBL
DRIVE
VCC
LGATE
PGND
BOOT
C 8
1uF
25mR
25mR
25mR
C 4
0.1uF
Q1
APM3055L
1
Q2
APM4220
R 4
3V3
8
4
PHASE UGATE
1
2
3
0R
C11
2.5V
/SHDN
L2
2.2uH
R6
C9
C10
4.7uF
R 5
0.1uF
+
470uF
6.3V
25mR
3.125KF
1%
820R
8
7
6
5
R 7
100R
C12
1000uF
6.3V
C13
+
1000uF
6.3V
+
D 2
C14
SR24
4.7uF
R 8
1KF
1%
Q3
APM4220
2A/40V
30mR
30mR
R 9
0R
C15
0.01uF
4
R10
2.32KF
1%
1
2
3
C16
56pF
C17
0.1uF
R11
20K
R12
1.07KF
1%
2. Boot-Strap - Use External Power
12V
C1
5V
C2
12V
1uF
1uF
L1
R2
VIN
2R2
1uH
+
C3
D1
VIN
470uF
R1
R3
N C
N C
U1
APW7063
1N4148
C5
470uF
16V
25mR
C9
470uF
16V
25mR
C6
470uF
16V
25mR
+
+
+
6.3V
25mR
C 4
4.7uF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
8
RT
SS
VREG
FB
COMP
GND
PHASE UGATE
FBL
DRIVE
VCC
LGATE
PGND
BOOT
C8
1uF
7
6
5
C 7
0.1uF
Q1
APM3055L
1
Q2
APM4220
R 4
0R
3V3
4
1
2
3
C12
2.5V
/SHDN
L2
2.2uH
R6
C10
470uF
C11
4.7uF
R 5
0.1uF
+
3.125KF
1%
620R
6.3V
25mR
8
7
6
5
R 8
100R
C13
1000uF
6.3V
C14
+
1000uF
6.3V
+
D 2
SR24
C15
4.7uF
R 7
Q3
APM4220
2A/40V
30mR
30mR
R 9
0R
1KF
C16
0.01uF
4
R10
2.32KF
1%
1%
1
2
3
C17
56pF
C18
0.1uF
R11
20K
R12
1.07KF
1%
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Rev. A.7 - Nov., 2005
APW7063
Absolute Maximum Ratings
Symbol
Parameter
Rating
30
Unit
V
VCC
VCC to GND
LGATE LGATE to GND
DRIVE DRIVE to GND
UGATE UGATE to GND
30
V
30
V
30
V
VBOOT
BOOT to GND
30
V
PHASE to GND
30
V
Operating Junction Temperature
Storage Temperature
0~150
-65 ~ 150
300
±2
oC
oC
oC
KV
TSTG
TSDR
VESD
Soldering Temperature (10 Seconds)
Minimum ESD Rating
Recommended Operating Conditions
Symbol
Parameter
Min.
Nom.
Max.
19
Unit
Supply Voltage
Boot Voltage
VCC
7
12
V
V
VBOOT
26
Thermal Characteristics
Symbol
Parameter
Junction to Ambient Resistance in free air (SOP-14)
Value
Unit
oC/W
160
qJA
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPEN and
TA = 0 ~ 70oC. Typlcal values are at TA = 25oC.
APW7063
Symbol
Parameter
Test Conditions
Unit
Min
Typ Max
SUPPLY CURRENT
ICC
POWER-ON-RESET
Rising VCC Threshold
Falling VCC Threshold
OSCILLATOR
VCC Nominal Supply
UGATE and LGATE Open
3
mA
7.0
6.6
7.2
6.8
7.4
7.0
V
V
Free Running Frequency
Total Variation
RT = OPEN, VCC = 12V
220
-15
250
280
+15
kHz
%
6KW < RT to GND < 200KW
Ramp Amplitude
RT = OPEN
1.7
VP-P
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Rev. A.7 - Nov., 2005
APW7063
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPEN and
TA = 0 ~ 70oC. Typlcal values are at TA = 25oC.
APW7063
Symbol
Parameter
Test Conditions
Unit
Min
-1
Typ
Max
REFERENCE
VREF
Reference Voltage
0.80
V
Reference Voltage Tolerance
+1
%
PWM EEEOR AMPLIFIER
DC Gain
75
dB
%
UGATE Duty Range
FB Input Current
0
85
0.1
uA
GATE DRIVERS
IUGATE Upper Gate Source
RUGATE Upper Gate Sink
ILGATE Lower Gate Source
RLGATE Lower Gate Sink
VBOOT = 12V, VUGATE = 6V
IUGATE = 0.3A
650
550
800
4
mA
W
8
8
VCC = 12V, VLGATE = 6V
ILGATE = 0.3A
700
4
mA
W
TD
LINEAR REGULATOR
Reference Voltage
Dead Time
50
nS
0.8
2
V
%
Regulation
Output Drive Current
VDRIVE = 4V
8
10
12
mA
PROTECTION
FB Under Voltage Level
FBL Under Voltage Level
OCSET Source Current
50
50
%
%
250
mA
VREG
VREG
IOUT
Output Voltage Accuracy
Output Current Capacity
VCC > 12V
VCC = 12V
5.5
6
6.5
12
V
20
mA
SOFT START and SHUTDOWN
TSS
ISS
Internal Soft-Start Interval
Soft-Start Charge Current
Shutdown Threshold
CSS = 0uF
2
mS
uA
V
8
10
0.4
50
COMP Falling
Shutdown Hysteresis
mV
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Rev. A.7 - Nov., 2005
APW7063
Functional Pin Description
RT (Pin 1)
VOLTAGE
V
SOFT START
This pin can adjust the switching frequency. Connect
a resistor from RT to VCC for decreasing the switching
frequency, Conversely, connect a resistor from RT to
GND for increasing the switching frequency (see
Typical Characteristics).
V
V
OUT2
OUT1
SS (Pin 2)
Connect a capacitor from this pin to GND to set the
soft-start interval of the converter. An internal 10mA
current source charges this capacitor to 5.2V. The SS
voltage clamps the reference voltage to theSS voltage,
and Figure1 shows the soft-start interval. At t0, the
internal source current starts to charge the capacitor
and the internal 0.8V reference also starts to rise and
follows the SS. Until the internal reference reaches to
0.8V at t2, the soft-start interval is completed. This
method provides a rapid and controlled output voltage
rise. The way of the Soft-Start of the output2 is the
same as the output1, but it starts from the SS at 2.2V
to 3.0V. The APW7063 also provides the internal
Soft-Start which is fixed to 2ms (t0 to t1). If the
FB
FBL
TIME
t0
t1
t2
t3
Figure 1. Soft-Start Interval
VREG (Pin 3)
An internal regulator will supply 6V for boost voltage,
a 1uF capacitor to GND is recommended for stability.
If the VREGvoltage has variation by other interference,
the IC can not work normally. When the VCC<8V,
don’t use the VREG for BOOST voltage.
external Soft-Start interval is slower than the internal FB (Pin 4)
Soft-Start interval (CSS<0.025uF) or no external
FB pinis the inverting input of the error amplifier, and it
capacitor, the Soft-Start will follow the internal Soft-
receives the feedback voltage from an external resistive
divider across the output (VOUT). The output voltage is
determined by :
Start.
C SS
´ 0.8V
Soft-Start
T
= t1 - t0 =
ISS
C SS
ROUT
RGND
æ
è
ö
÷
ø
´ 0.8V
+
t3 = t2
VOUT = 0.8V´ 1+
ç
ISS
where ROUT is the resistor connected from VOUT to FB,
and RGND is the resistor connected from FB to GND.
Where:
CSS = external Soft-Start capacitor
When the FB voltage is under 50% Vref, it will cause
the under voltage protection, and shutdown the device.
Remove the condition and restart the VCC voltage or
pull the COMP from low to high once, will enable the
device again.
ISS = Soft-Start current = 10mA
CSS ´ 2.2V
t2 =
ISS
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APW7063
Functional Pin Description (Cont.)
COMP (Pin 5)
PGND (Pin 10)
This pin is the output of the error amplifier. Add an
external resistor and capacitor network to provide the
loop compensation for the PWM converter (see
Application Information).
Power ground for the gate diver. Connect the lower
MOSFET source to this pin.
LGATE (Pin 11)
This pin provides the gate drive signal for the low side
MOSFET.
Pull this pin below 0.4V will shutdown the controller,
forcing the UGATE and LGATE signals to be 0V.A soft
start cycle will be initiated upon the release of this pin.
VCC (Pin 12)
GND (Pin 6)
This pin provides a supply voltagefor the device, when
VCC is above the rising threshold 4.2V, It turns on the
device is turned on, and conversely, VCC is below the
falling threshold 3.9V, the device is turned off. A 1uF
decoupling capacitor to GND is recommended.
Signal ground for the IC.
PHASE (Pin 7)
A resistor (ROCSET) is connected between this pin and
the drain of the low-side MOSFET will determine the
over current limit. An internally generated 250uA current
source will flow through this resistor, creating a voltage
drop. This voltage will be compared with the voltage
across the low-side MOSFET. The threshold of the
over current limit is therefore given by :
DRIVE (Pin 13)
Connect this pin to the gate of an external N-channel
MOSFET transistor. This pin provides the gate volt-
age for the linear regulator pass transistor. It also pro-
vides a means of compensating the linear controller
for applications where the user needs to optimize the
regulator transient response.
ILIMIT ´ RDS(ON)
ROCSET
=
250uA
FBL (Pin 14)
An over current condition will cycle the soft start
function until the over current condition is removed. Connect this pin to the output of the linear regulator
Because of the comparator delay time, so theon time via a proper sized resistor divider. The voltage at this
of the low-side MOSFETmust be longer than 800ns to pin is regulated to 0.8V and the output voltage is de-
termined using the following formula :
have the over current protection work.
UGATE (Pin 8)
ROUT
RGND
æ
è
ö
÷
ø
VOUT = 0.8V´ 1+
ç
This pin provides gate drive for the high-side MOSFET.
BOOT (Pin 9)
where ROUT is the resistorconnected from VOUT to FBL,
and RGND is the resistor connected from FBL to GND.
This pin provides the supply voltage to the high side
MOSFET driver. For driving logic level N-channel
MOSEFT, a bootstrap circuit can be use to create a
suitable driver’s supply.
This pin also monitores the under-voltage events, if
the linear regulator is not used, tie the FBL to VREG.
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APW7063
Typical Characteristics
Power Up
Power Down
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VCC(10V/div)
SS(5V/div)
VCC(10V/div)
SS(5V/div)
VOUT1(2V/div)
VOUT1(2V/div)
VOUT2(2V/div)
VOUT2(2V/div)
Time (10ms/div)
Time (10ms/div)
Enable (COMP is left open)
Shutdown (COMP is pulled to GND)
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VOUT2(2V/div)
VOUT2(2V/div)
VOUT1(2V/div)
VOUT1(2V/div)
COMP(1V/div)
COMP(1V/div)
SS(5V/div)
SS(5V/div)
Time (2ms/div)
Time (10ms/div)
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Rev. A.7 - Nov., 2005
APW7063
Typical Characteristics (Cont.)
UGATE Falling
UGATE Rising
VCC=2V, VIN=12V
VCC=2V, VIN=12V
LGATE(10V/div)
LGATE(10V/div)
PHASE(10V/div)
UGATE(10V/div)
PHASE(10V/div)
UGATE(10V/div)
Time (50ns/div)
Time (50ns/div)
Under Voltage Protection (PWM)
Under Voltage Protection (Linear)
VCC=12,VIN=12V
VOUT=3.3V, L=2.2mH
IL(10A/div)
SS(5V/div)
VCC=12V, VIN=5V
VOUT2=2.5V
SS(5V/div)
VOUT2(2V/div)
VOUT1 (2V/div)
UGATE (10V/div)
DRV(5V/div)
Time (5us/div)
Time (5us/div)
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Rev. A.7 - Nov., 2005
APW7063
Typical Characteristics (Cont.)
PWM Load Transient
Linear Load Transient
VCC=12V
VIN=12V
VCC=12V
VIN=12V
VOUT=2.5V
VOUT=3.3V
COUT=470mFx2
ESR=22.5mW
L=1.5mH
COUT=470mF
f=400kHz
VOUT2(100mV/div)
VOUT1(100mV/div)
IOUT2(1A/div)
IOUT1(5A/div)
Time (20us/div)
Time (10us/div)
UGATE Sink Current vs. UGATE Voltage
UGATE Source Current vs. UGATE Voltage
1.4
1.2
VBOOT=12V
VBOOT=12V
1.2
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
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Rev. A.7 - Nov., 2005
APW7063
Typical Characteristics (Cont.)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
1.4
1.2
1
VCC=12V
VCC=12V
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
Over Current Protection
VCC=12V,VIN=12V, VOUT=2.5V, ROCSET=1kW
RDS(ON)=16mW, L=2.2mH, IOUT=15A
Switching Frequence vs. RT Resistance
10000
1000
100
10
IL(10A/div)
SS(5V/div)
RT pull up to 12V
RT pull down to GND
UGATE(20V/div)
1
VOUT1(2V/div)
10
100
1000
Time (5us/div)
Switching Frequency (kHz)
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Rev. A.7 - Nov., 2005
APW7063
Typical Characteristics (Cont.)
Comp Source Current vs. Comp Voltage
Comp Sink Current vs. Comp Voltage
150
150
VCC=12V
VCC=12V
125
125
100
75
50
25
0
100
75
50
25
0
0
0.5
1
1.5
2
2.5
3
3.5
4
1
1.5
2
2.5
3
3.5
4
Comp Voltage (V)
Comp Voltage (V)
Drive Source Current vs. Drive Voltage
Drive Sink Current vs. Drive Voltage
10
8
40
30
20
10
0
VCC=12V
VCC=12V
6
4
2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Drive Voltage (V)
Drive Voltage (V)
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Rev. A.7 - Nov., 2005
APW7063
Typical Characteristics (Cont.)
VREG Voltage vs. Supply Voltage
6
VREG Voltage vs. Load Current
6.5
VCC=12V
5.5
5
6.25
6
4.5
4
5.75
5.5
0
2
4
6
8
10 12 14 16 18
0
5
10
15
20
Supply Voltage (V)
Load Current (mA)
Supply Current vs. Supply Voltage
Reference Voltage vs. Temperature
4
3.5
3
0.8
0.798
0.796
0.794
0.792
0.79
ICC
2.5
2
ICC(SHDN)
1.5
1
0.5
0
-40 -20
0
20 40 60 80 100 120
0
2
4
6
8
10
12
Supply Voltage (V)
Temperature (°C)
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Rev. A.7 - Nov., 2005
APW7063
Application Information
Component Selection Guidelines
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
current and vice versa. The maximum ripple current
occurs at the maximum input voltage. A good starting
point is to choose the ripple current tobe approximately
30% of the maximum output current.
Output Capacitor Selection
The selection of COUT is determined by the required
effective series resistance (ESR) and voltage rating
rather than the actual capacitance requirement.
Therefore select high performance low ESR capacitors
that are intended for switching regulator applications.
In some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
type of inductors, especially core that is make of
ferrite, the ripple current will increase abruptly when it
Input Capacitor Selection
The input capacitor is chosen based on the voltage saturates. This will result in a larger output ripple
ratingandthe RMS current rating. Forreliableoperation, voltage.
select the capacitor voltage rating to be at least 1.3
Compensation
times higher than the maximum input voltage. The
The output LC filter of a stepdown converter introduces
maximum RMS current ratingrequirement is approximately
a double pole, which contributes with –40dB/decade
IOUT/2 , where IOUT is the load current. During power up,
gain slope and 180 degrees phase shift in the control
the input capacitors have to handle large amount of
loop. A compensationnetwork betweenCOMP pin and
surge current. If tantalum capacitors are used, make
ground shouldbe added. The simplestloop compensation
sure they are surge tested by the manufactures. If in
network is shown in Fig. 5.
doubt, consult the capacitors manufacturer.
The output LC filter consists of the output inductor
For high frequency decoupling, a ceramic capacitor
and output capacitors. The transfer function of the LC
between 0.1uF to 1uF can be connected between VCC
filter is given by:
and ground pin.
1+ s´ ESR´ COUT
s2 ´ L´ COUT+ s´ ESR´ COUT+ 1
GAINLC
=
Inductor Selection
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will translate
into lower output ripple voltage. The ripple current and
ripple voltage can be approximated by:
The poles and zero of this transfer function are:
1
FLC
=
2´ p´ L´ COUT
1
FESR
=
2 ´ p ´ ESR ´ COUT
VIN - VOUT
VOUT
IRIPPLE
=
x
VIN
Fs x L
The FLC is the double poles ofthe LC filter, and FESR is
thezero introduced by the ESR of the output capacitor.
where Fs is the switching frequency of the regulator.
DVOUT = IRIPPLE x ESR
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APW7063
Application Information (Cont.)
Compensation (Cont.)
The compensation circuit is shown in Figure 5. R3
and C1 introduce a zero and C2 introduces a pole to
reduce the switching noise. The transfer function of
error amplifier is given by:
L
Output
PHASE
COUT
é
ù
1
1
æ
ö
gm´ Zo gm ´ R3 +
//
GAINAMP =
=
ç
÷
ê
ú
ESR
sC1 sC2
è
ë
ø
û
1
æ
ö
÷
s +
ç
R3 ´ C1
è
ø
gm ´
=
Figure 2. The Output LC Filter
C1+ C2
R3 ´ C1´ C2
æ
ö
÷
s´ s +
´ C2
ç
F
LC
è
ø
-40dB/dec
The pole and zero of the compensation network are:
1
F
ESR
FP =
C1´ C2
2´ p ´ R3´
C1+ C2
1
Gain
-20dB/dec
FZ
=
2´ p ´ R3 ´ C1
V
OUT
Frequency
Figure 3. The LC Filter Gain & Frequency
Error
R1
Amplifier
FB
-
COMP
The PWM modulator is shown in Figure. 4. The input
is the output of the error amplifierand the output is the
PHASE node. The transfer function of the PWM
modulator is given by:
R2
+
R3
C1
VREF
C2
VIN
GAINPWM =
DVOSC
VIN
Figure 5. Compensation Network
Driver
The closed loop gain of the converter can be written
PWM
Comparator
as:
R2
R1+R2
GAINLC x GAINPWM x
x GAINAMP
VOSC
Figure 6 shows the converter gain and the following
guidelines will help to design the compensation
network.
Output of
PHASE
Error
Amplifier
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
Driver
Use the following equation to calculate R3:
Figure 4. The PWM Modulator
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Rev. A.7 - Nov., 2005
APW7063
Application Information (Cont.)
losses inthe MOSFETs have twocomponents: conduction
Compensation (Cont.)
loss and transition loss. For the upper and lower
MOSFET, the losses are approximately given by the
following :
DVOSC
FESR
R1 + R2
FO
R3 =
´
´
´
2
VIN
R2
gm
FLC
Where:
PUPPER = Iou2t (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
PLOWER = Iou2t (1+ TC)(RDS(ON))(1-D)
gm = 900uA/V
2.Place the zero FZ before the LC filter double poles
FLC:
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tswis the switching interval
FZ = 0.75 x FLC
Calculate the C1 by the equation:
1
C1 =
D is the duty cycle
2´ p ´ R1´ 0.75 ´ FLC
Note that bothMOSFETs have conduction losses while
theupper MOSFETinclude anadditional transition loss.
The switching internal, tsw, is a function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the
switching waveform internal of the MOSFET.
3. Set the pole at the half the switching frequency:
FP = 0.5xFS
Calculate the C2 by the equation:
C1
C2 =
p ´ R3 ´ C1 ´ FS - 1
The (1+TC)term is tofactor in thetemperaturedependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs
Temperature” curve of the power MOSFET.
FZ=0.75FLC
F
P
=0.5F
S
LinearRegulator Input/OutputCapacitor Selection
20 ×log(gm×R3)
The input capacitor is chosen based on its voltage
rating. Underload transient condition, the input capacitor
will momentarily supply the required transient current.
A 1uF ceramic capacitor will be sufficient inmost
applications.
Compensation Gain
Gain
F
LC
F
O
VIN
? VOSC
20 ×log
Converter
Gain
F
ESR
PWM &
Filter Gain
The output capacitor for the linear regulator is chosen
to minimize any droop during load transient condition.
In addition, thecapacitor is chosen based on its voltage
rating.
Frequency
Figure 6. Converter Gain & Frequency
Linear Regulator MOSFET Selection
MOSFET Selection
Themaximum DRIVE voltage is determined by the VCC.
Since this pin drives an external N-channel MOSFET,
therefore the maximum output voltage of the linear
regulator is dependent upon the VGS.
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement.The
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APW7063
Application Information (Cont.)
MOSFET Selection (Cont.)
VOUT2MAX = VCC- VGS
VDS
Another criteria is its efficiency of heat removal. The
power dissipated by the MOSFET is given by:
Pdiss = Iout * (VIN - VOUT2
)
where Iout is the maximum load current
Vout2 is the nominal output voltage
In some applications, heatsink maybe required to help
maintain the junction temperature of the MOSFET
below its maximum rating.
t
Time
sw
Layout Considerations
Figure 7. Switching waveform across MOSFET
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be
minimized by using short, wide printed circuit traces.
Signal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 8 illustrates the layout,
with bold lines indicating high current paths. Components
along the bold lines should be placed close together.
Below is a checklist for your layout:
VIN
CIN
APW7063
+
11
PGND
12
LGATE
L
O
A
D
COUT
9
8
Q1
UGATE
PHASE
Q2
+
· Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore
keep traces to these nodes as short as possible.
L1
VOUT
Figure 8. Recommended Layout Diagram
· The groundreturn of CIN must return to the combine
COUT (-) terminal.
· Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
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Rev. A.7 - Nov., 2005
APW7063
Package Information
SOP – 14 (150mil)
A
D
Ee
B
L
Millimeters
Inches
Dim
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Max.
1.732
0.255
0.509
0.2496
8.762
3.999
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
A
A1
B
C
D
E
e
1.274
0.050
H
L
5.808
0.382
0°
6.215
1.274
8°
0.228
0.015
0°
0.244
0.050
8°
q°
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Rev. A.7 - Nov., 2005
APW7063
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to T P
Ramp-up
T L
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
°
°
3 C/second max.
3 C/second max.
Preheat
°
°
150 C
100 C
-
-
-
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (min to max) (ts)
°
°
150 C
200 C
60-120 seconds
60-180 seconds
Time maintained above:
°
°
183 C
217 C
-
-
Temperature (TL)
Time (tL)
60-150 seconds
60-150 seconds
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
°
Time within 5 C of actual
10-30 seconds
20-40 seconds
Peak Temperature (tp)
°
°
Ramp-down Rate
6 C/second max.
6 C/second max.
°
6 minutes max.
8 minutes max.
Time 25 C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
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Rev. A.7 - Nov., 2005
APW7063
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
°
°
225 +0/-5 C
240 +0/-5 C
³
°
°
225 +0/-5 C
2.5 mm
225 +0/-5 C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
°
°
°
260 +0 C*
260 +0 C*
260 +0 C*
°
°
°
1.6 mm – 2.5 mm
260 +0 C*
250 +0 C*
245 +0 C*
³
°
°
°
245 +0 C*
2.5 mm
250 +0 C*
shall
245 +0 C*
*Tolerance: The device manufacturer/supplier
assure process compatibility up to and including the
°
°
°
stated classification temperature (this means Peak reflow temperature +0 C. For example 260 C+0 C)
at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
Method
Description
245°C,5 SEC
1000 Hrs Bias @ 125°C
168 Hrs, 100% RH, 121°C
-65°C ~ 150°C, 200 Cycles
MIL-STD-883D-2003
MIL-STD 883D-1005.7
JESD-22-B, A102
MIL-STD 883D-1011.9
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
Ko
F
W
Ao
D1
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Rev. A.7 - Nov., 2005
APW7063
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
A
B
C
J
T1
T2
W
P
E
Application
13.0 + 0.5
- 0.2
16.0 ± 0.3
330REF 100REF
2 ± 0.5 16.5REF 2.5 ± 025
8
t
1.75
SOP-14
(150mil)
F
D
D1
Po
4.0
P1
Ao
Ko
f
f
0.50 +
0.1
1.50
(MIN)
±
0.3 0.05
7.5
2.0
6.5
2.10
(mm)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
Cover Tape Width
Devices Per Reel
24
21.3
2500
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ã ANPECElectronicsCorp.
Rev. A.7 - Nov., 2005
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