AOI4126 [AOS]
100V N-Channel MOSFET; 100V N沟道MOSFET型号: | AOI4126 |
厂家: | ALPHA & OMEGA SEMICONDUCTORS |
描述: | 100V N-Channel MOSFET |
文件: | 总7页 (文件大小:462K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AOD4126/AOI4126
100V N-Channel MOSFET
SDMOS TM
General Description
Product Summary
The AOD4126&AOI4126 are fabricated with SDMOSTM
trench technology that combines excellent RDS(ON) with
low gate charge.The result is outstanding efficiency with
controlled switching behavior. This universal technology is
well suited for PWM, load switching and general purpose
applications.
VDS
100V
ID (at VGS=10V)
RDS(ON) (at VGS=10V)
RDS(ON) (at VGS = 7V)
43A
< 24mΩ
< 30mΩ
100% UIS Tested
100% Rg Tested
TO252
DPAK
TO-251A
IPAK
D
Top View
Bottom View
Top View
Bottom View
D
D
D
G
S
G
S
G
S
D
D
S
G
G
S
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
Maximum
Units
Drain-Source Voltage
VDS
100
V
Gate-Source Voltage
VGS
±25
V
A
TC=25°C
43
Continuous Drain
Current B
ID
TC=100°C
30
Pulsed Drain Current C
IDM
100
TA=25°C
TA=70°C
7.5
Continuous Drain
Current A
IDSM
A
6
Avalanche Current C
IAS, IAR
28
A
Avalanche energy L=0.1mH C
EAS, EAR
39
mJ
TC=25°C
Power Dissipation B
TC=100°C
100
PD
W
50
3
TA=25°C
PDSM
W
°C
Power Dissipation A
1.9
TA=70°C
Junction and Storage Temperature Range
TJ, TSTG
-55 to 175
Thermal Characteristics
Parameter
Symbol
Typ
Max
10
Units
°C/W
°C/W
°C/W
Maximum Junction-to-Ambient A
Maximum Junction-to-Ambient A D
Maximum Junction-to-Case
t
≤ 10s
8
35
1
RθJA
Steady-State
Steady-State
42
RθJC
1.5
Rev1 : May 2012
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Page 1 of 7
AOD4126/AOI4126
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max Units
STATIC PARAMETERS
ID=250µA, VGS=0V
BVDSS
Drain-Source Breakdown Voltage
100
V
VDS=100V, VGS=0V
10
µA
50
IDSS
Zero Gate Voltage Drain Current
TJ=55°C
VDS=0V, VGS= ±25V
VDS=VGS ID=250µA
VGS=10V, VDS=5V
VGS=10V, ID=20A
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
100
4
nA
V
VGS(th)
ID(ON)
2
3.3
100
A
19
36
24
43
30
mΩ
RDS(ON)
Static Drain-Source On-Resistance
TJ=125°C
VGS=7V, ID=15A
23.5
34
mΩ
S
VDS=5V, ID=20A
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
IS=1A,VGS=0V
0.66
1
V
Maximum Body-Diode Continuous Current
40
A
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
1400 1770 2200
pF
pF
pF
Ω
VGS=0V, VDS=50V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
115
33
165
55
214
80
VGS=0V, VDS=0V, f=1MHz
VGS=10V, VDS=50V, ID=20A
0.3
0.65
1.0
SWITCHING PARAMETERS
Qg
Qgs
Qgd
tD(on)
tr
Total Gate Charge
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
14
4
28
9
42
14
14
nC
nC
nC
ns
ns
ns
ns
6
10
12
4
VGS=10V, VDS=50V, RL=2.5Ω,
RGEN=3Ω
tD(off)
tf
17
5
trr
IF=20A, dI/dt=500A/µs
IF=20A, dI/dt=500A/µs
12
60
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
20
82
26
ns
Qrr
nC
110
A. The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The
Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends
on the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and duty cycles to keep
initial TJ =25°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming
a maximum junction temperature of TJ(MAX)=175°C. The SOA curve provides a single pulse rating.
G. These tests are performed with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with TA=25°C.
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Rev 1 : May 2012
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Page 2 of 7
AOD4126/AOI4126
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
60
40
20
0
60
50
40
30
20
10
0
10V
8V
VDS=5V
7V
6.5V
125°C
VGS=6V
25°C
3
4
5
6
7
0
1
2
3
4
5
VGS(Volts)
VDS (Volts)
Fig 1: On-Region Characteristics (Note E)
Figure 2: Transfer Characteristics (Note E)
30
2.4
2.2
2
27
24
21
18
15
VGS=10V
ID=20A
VGS=7V
1.8
1.6
1.4
1.2
1
VGS=7V
ID=15A
VGS=10V
0.8
0
25
50
75
100 125 150 175 200
0
5
10
15
20
25
30
35
40
ID (A)
Temperature (°C)
Figure 4: On-Resistance vs. Junction Temperature
Figure 3: On-Resistance vs. Drain Current and Gate
Voltage (Note E)
50
1.0E+02
1.0E+01
ID=20A
40
30
20
10
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
125°C
125°C
25°C
25°C
0.0
0.2
0.4
VSD (Volts)
Figure 6: Body-Diode Characteristics (Note E)
0.6
0.8
1.0
1.2
6
7
8
9
10
VGS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
Rev 1: May 2012
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Page 3 of 7
AOD4126/AOI4126
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
10
2500
VDS=50V
ID=20A
8
2000
1500
1000
500
0
Ciss
6
4
Coss
Crss
2
0
0
5
10
15
20
25
30
0
20
40
60
80
100
Qg (nC)
VDS (Volts)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
1000
800
600
400
200
0
1000.0
100.0
10.0
1.0
TJ(Max)=175°C
TC=25°C
10µs
RDS(ON)
limited
100µs
1ms
10ms
DC
0.1
TJ(Max)=175°C
TC=25°C
0.0
0.01
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
VDS (Volts)
Pulse Width (s)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
Figure 10: Single Pulse Power Rating Junction-to-
Case (Note F)
10
1
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
D=Ton/T
TJ,PK=TC+PDM.ZθJC.RθJC
RθJC=1.5°C/W
0.1
0.01
PD
Single Pulse
Ton
T
0.00001
0.0001
0.001
0.01
0.1
1
10
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Rev 1: May 2012
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Page 4 of 7
AOD4126/AOI4126
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
100
120
90
60
30
0
TA=25°C
TA=100°C
TA=150°C
TA=125°C
10
0.000001
0
25
50
75
TCASE (°C)
Figure 13: Power De-rating (Note F)
100
125
150
175
0.00001
0.0001
0.001
Time in avalanche, tA (s)
Figure 12: Single Pulse Avalanche capability
(Note C)
1000
100
10
60
50
40
30
20
10
0
TA=25°C
1
100
0.01
1
0
25
50
75
100
125
150
175
Pulse Width (s)
TCASE (°C)
Figure 15: Single Pulse Power Rating Junction-to-
Ambient (Note H)
Figure 14: Current De-rating (Note F)
10
1
D=Ton/T
TJ,PK=TA+PDM.ZθJA.RθJA
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
RθJA=42°C/W
0.1
PD
0.01
Single Pulse
Ton
T
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)
Rev 1: May 2012
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Page 5 of 7
AOD4126/AOI4126
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
300
250
200
150
100
50
15
12
9
24
20
16
12
8
2
125ºC
1.8
1.6
1.4
1.2
1
di/dt=800A/µs
125ºC
di/dt=800A/µs
trr
25ºC
25ºC
125ºC
Irm
6
0.8
0.6
0.4
0.2
0
S
125ºC
3
4
Qrr
25ºC
20
25ºC
20
0
0
0
5
10
15
IS (A)
25
30
0
5
10
15
IS (A)
25
30
Figure 17: Diode Reverse Recovery Charge and Peak
Current vs. Conduction Current
Figure 18: Diode Reverse Recovery Time and
Softness Factor vs. Conduction Current
150
120
90
60
30
0
30
30
24
18
12
6
3
Is=20A
Is=20A
125ºC
26
125ºC
2.5
2
22
18
25ºC
trr
25ºC
14
1.5
1
Qrr
125ºC
25ºC
10
6
125ºC
Irm
0.5
2
S
25ºC
-2
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di/dt (A/µs)
di/dt (A/µs)
Figure 19: Diode Reverse Recovery Charge and Peak
Current vs. di/dt
Figure 20: Diode Reverse Recovery Time and
Softness Factor vs. di/dt
Rev 1: May 2012
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Page 6 of 7
AOD4126/AOI4126
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
-
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vgs
Vds
+
Vgs
Vdd
I AR
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Qrr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
Rev 1: May 2012
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Page 7 of 7
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