AON6450L [AOS]
N-Channel SDMOS TM Power Transistor; N沟道SDMOS TM功率晶体管
| 型号： | AON6450L |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | N-Channel SDMOS TM Power Transistor |
| 文件： | 总7页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AON6450L
N-Channel SDMOS TM Power Transistor
General Description
Product Summary
The AON6450L is fabricated with SDMOSTM trench
Parameter
VDS
100V
52A
technology that combines excellent RDS(ON) with low gate
charge.The result is outstanding efficiency with controlled
switching behavior. This universal technology is well suited
for PWM, load switching and general purpose applications.
ID (at VGS=10V)
< 14.5mΩ
< 17.5mΩ
RDS(ON) (at VGS=10V)
RDS(ON) (at VGS = 7V)
100% UIS Tested!
100% R g Tested!
- RoHS Compliant
- Halogen Free
D
Top View
Fits SOIC8
footprint !
G
S
DFN5X6
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
VDS
Maximum
100
Units
Drain-Source Voltage
V
V
VGS
ID
IDM
IDSM
Gate-Source Voltage
±25
TC=25°C
52
Continuous Drain
Current
Pulsed Drain Current C
TC=100°C
33
A
A
110
TA=25°C
TA=70°C
9
Continuous Drain
Current
Avalanche Current C
Repetitive avalanche energy L=0.1mH C
7
41
IAR
A
EAR
84
mJ
TC=25°C
Power Dissipation B
TC=100°C
83
PD
W
33
TA=25°C
2.3
PDSM
W
Power Dissipation A
TA=70°C
1.4
TJ, TSTG
Junction and Storage Temperature Range
-55 to 150
°C
Thermal Characteristics
Parameter
Symbol
Typ
14
40
1
Max
17
Units
°C/W
°C/W
°C/W
Maximum Junction-to-Ambient A
t ≤ 10s
RθJA
Maximum Junction-to-Ambient A D
Maximum Junction-to-Case
55
Steady-State
Steady-State
RθJC
1.5
Rev 0: January 2009
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Page 1 of 7
AON6450L
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max Units
STATIC PARAMETERS
BVDSS
Drain-Source Breakdown Voltage
ID=250µA, VGS=0V
100
V
VDS=100V, VGS=0V
10
µA
50
IDSS
Zero Gate Voltage Drain Current
TJ=55°C
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
VDS=0V, VGS= ±25V
VDS=VGS ID=250µA
VGS=10V, VDS=5V
100
4
nA
V
VGS(th)
ID(ON)
2.8
3.4
110
A
V
GS=10V, ID=20A
12.1
22.8
14
14.5
27.5
17.5
mΩ
mΩ
RDS(ON)
TJ=125°C
Static Drain-Source On-Resistance
VGS=7V, ID=20A
VDS=5V, ID=20A
IS=1A,VGS=0V
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
52
S
V
A
0.7
1
Maximum Body-Diode Continuous Current
52
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
2000 2570 3100
pF
pF
pF
Ω
VGS=0V, VDS=50V, f=1MHz
VGS=0V, VDS=0V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
170
50
250
80
330
120
1.2
0.4
0.8
SWITCHING PARAMETERS
Qg(10V)
Total Gate Charge
Total Gate Charge
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
34
9
43
11.5
14
52
14
17
19
nC
nC
nC
nC
ns
Qg(4.5V)
Qgs
Qgd
tD(on)
tr
V
GS=10V, VDS=50V, ID=20A
11
8
13.5
15
VGS=10V, VDS=50V, RL=2.5Ω,
GEN=3Ω
5
ns
R
tD(off)
tf
28.5
5
ns
ns
trr
IF=20A, dI/dt=500A/µs
IF=20A, dI/dt=500A/µs
17
75
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
24
31
ns
Qrr
nC
108
140
A. The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The
Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on
the user's specific board design, and the maximum temperature of 150°C may be used if the PCB allows it.
B. The power dissipation PD is based on TJ(MAX)=150°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initial
TJ =25°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming
a maximum junction temperature of TJ(MAX)=150°C. The SOA curve provides a single pulse rating.
G. These tests are performed with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with TA=25°C.
Rev 0: January 2009
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Rev 0: January 2009
www.aosmd.com
Page 2 of 7
AON6450L
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
10V
VDS=5V
7V
7.5V
6.5V
6V
125°C
VGS=5.5V
25°C
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
V
GS(Volts)
V
DS (Volts)
Figure 2: Transfer Characteristics (Note E)
Fig 1: On-Region Characteristics (Note E)
16
15
14
13
12
11
2.2
2
VGS=10V
ID=20A
VGS=7V
1.8
1.6
1.4
1.2
1
VGS=7V
ID=20A
VGS=10V
0.8
0
5
10
15
20
25
30
0
25
50
75
100
125
150
175
ID (A)
Temperature (°C)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage (Note E)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
30
25
20
15
10
5
1.0E+02
1.0E+01
ID=20A
125°C
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
125°
25°C
25°C
0.0
0.2
0.4
VSD (Volts)
Figure 6: Body-Diode Characteristics
0.6
0.8
1.0
5
6
7
8
9
10
VGS (Volts)
(Note E)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
Rev 0: January 2009
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Page 3 of 7
AON6450L
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
10
3500
3000
2500
2000
1500
1000
500
VDS=50V
ID=20A
8
Ciss
6
4
Coss
2
Crss
0
0
0
10
20
30
40
50
0
10
20
30
40
50
60
Qg (nC)
VDS (Volts)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
400
350
300
250
200
150
100
50
1000.0
100.0
10.0
1.0
TJ(Max)=150°C
TC=25°C
RDS(ON)
10µs
100µs
DC
1ms
TJ(Max)=150°C
TC=25°C
0.1
0.0
0
0.01
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
VDS (Volts)
Pulse Width (s)
Figure 9: Maximum Forward Biased
Safe Operating Area (Note F)
Figure 10: Single Pulse Power Rating Junction-to-
Case (Note F)
10
1
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
D=Ton/T
T
J,PK=TC+PDM.ZθJC.RθJC
RθJC=1.5°C/W
PD
0.1
Ton
T
Single Pulse
0.0001
0.01
0.00001
0.001
0.01
0.1
1
10
100
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Rev 0: January 2009
www.aosmd.com
Page 4 of 7
AON6450L
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
0
TA=25°C
TA=100°C
TA=150°C
TA=125°C
0
0
25
50
75
100
125
150
0.000001
0.00001
Time in avalanche, tA (s)
0.0001
T
CASE (°C)
Figure 12: Single Pulse Avalanche capability (Note
C)
Figure 13: Power De-rating (Note F)
10000
1000
100
10
60
50
40
30
20
10
0
TA=25°C
1
0.0001
0.01
1
100
10000
0
25
50
75
100
125
150
T
CASE (°C)
Pulse Width (s)
Figure 14: Current De-rating (Note F)
Figure 15: Single Pulse Power Rating Junction-to-
Ambient (Note G)
10
1
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
D=Ton/T
T
J,PK=TA+PDM.ZθJA.RθJA
RθJA=55°C/W
0.1
0.01
PD
Ton
Single Pulse
0.1
T
0.001
0.0001
0.001
0.01
1
10
100
1000
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note G)
Rev 0: January 2009
www.aosmd.com
Page 5 of 7
AON6450L
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
210
180
150
120
90
26
24
22
20
18
16
14
12
10
8
30
25
20
15
10
5
2
125ºC
di/dt=800A/µs
125ºC
25ºC
di/dt=800A/µs
1.6
1.2
0.8
0.4
0
trr
25ºC
125ºC
Qrr
60
25ºC
S
25ºC
30
125ºC
Irm
0
0
0
5
10
15
20
25
30
0
5
10
15
S (A)
20
25
30
IS (A)
I
Figure 17: Diode Reverse Recovery Charge and
Peak Current vs. Conduction Current
Figure 18: Diode Reverse Recovery Time and
Softness Factor vs. Conduction Current
210
180
150
120
90
26
22
18
14
10
6
40
35
30
25
20
15
10
5
2
Is=20A
125ºC
Is=20A
125ºC
1.5
1
trr
25ºC
25ºC
Qrr
125ºC
60
25ºC
0.5
0
S
25ºC
30
125º
Irm
0
2
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di/dt (A/µs)
di/dt (A/µs)
Figure 19: Diode Reverse Recovery Charge and
Peak Current vs. di/dt
Figure 20: Diode Reverse Recovery Time and
Softness Factor vs. di/dt
Rev 0: January 2009
www.aosmd.com
Page 6 of 7
AON6450L
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
-
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vgs
Vds
+
Vgs
Vdd
I AR
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Q rr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
Rev 0: January 2009
www.aosmd.com
Page 7 of 7
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