AOZ1051PI [AOS]
EZBuck⢠3 A Synchronous Buck Regulator; EZBuckâ ?? ¢ 3同步降压稳压器
| 型号： | AOZ1051PI |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⢠3 A Synchronous Buck Regulator |
| 文件： | 总14页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1051PI
EZBuck™ 3 A Synchronous Buck Regulator
General Description
Features
The AOZ1051PI is a high efficiency, easy to use, 3 A
synchronous buck regulator. The AOZ1051PI works from
4.5 V to 18 V input voltage range, and provides up to 3 A
of continuous output current with an output voltage
adjustable down to 0.8 V.
z 4.5 V to 18 V operating input voltage range
z Synchronous Buck: 70 mΩ internal high-side switch
and 40 mΩ internal low-side switch (at 12 V)
z Up to 95 % efficiency
z External soft start
The AOZ1051PI comes in an exposed pad SO-8
package and is rated over a -40 °C to +85 °C operating
ambient temperature range.
z Output voltage adjustable to 0.8 V
z 3 A continuous output current
z 500 kHz PWM operation
z Cycle-by-cycle current limit
z Pre-bias start-up
z Short-circuit protection
z Thermal shutdown
z Exposed pad SO-8 package
Applications
z Point of load DC/DC converters
z LCD TV
z Set top boxes
z DVD and Blu-ray players/recorders
z Cable modems
Typical Application
VIN
C1
C
SS
10µF
VIN
EN
SS
L1 4.7µH
VOUT
LX
AOZ1051PI
R1
R2
COMP
C2, C3
22µF
R
C
C
C
FB
AGND
PGND
Figure 1. 3.3 V 3 A Synchronous Buck Regulator, Fs = 500 kHz
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Page 1 of 14
AOZ1051PI
Ordering Information
Part Number
Ambient Temperature Range
-40 °C to +85 °C
Package
Environmental
Green Product
AOZ1051PI
EPAD SO-8
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
1
2
3
4
8
7
6
5
PGND
VIN
NC
SS
PAD
(LX)
AGND
FB
EN
COMP
Exposed Pad SO-8
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1
2
PGND
VIN
Power ground. PGND needs to be electrically connected to AGND.
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,
the device starts up.
3
4
5
6
AGND
FB
Analog ground. AGND is the reference point for controller section. AGND needs to be
electrically connected to PGND.
Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
COMP
EN
External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. If on/off control in not needed, connect EN to VIN and do not leave it open.
7
8
SS
NC
Soft-start pin. 5 µA current charging current.
No Connect Pin. Pin 8 is not internally connected. Connect this pin externally to LX and
use it for better thermal performance.
Exposed pad
LX
Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of the
power stage.
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AOZ1051PI
Block Diagram
VIN
Internal
+5V
UVLO
& POR
5V LDO
Regulator
OTP
EN
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
SS
SS
5µA
+
–
+
Level
Shifter
+
FET
Driver
+
–
PWM
Control
Logic
0.8V
PWM
Comp
EAmp
FB
LX
Q2
COMP
500kHz
Oscillator
PGND
AGND
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
Recommended Operating Conditions
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Rating
Parameter
Supply Voltage (VIN)
Rating
Supply Voltage (VIN)
LX to AGND
20 V
4.5 V to 18 V
0.8 V to 0.85 • VIN
-40 °C to +85 °C
-0.7 V to VIN+0.3 V
-5 V to 22 V
Output Voltage Range
LX to AGND (20 ns)
EN to AGND
Ambient Temperature (TA)
-0.3 V to VIN+0.3 V
-0.3 V to 6.0 V
-0.3 V to +0.3 V
+150 °C
Package Thermal Resistance
(2)
Exposed Pad SO-8 (ΘJA
)
50 °C/W
FB, SS, COMP to AGND
PGND to AGND
Note:
2. The value of ΘJA is measured with the device mounted on a 1-in2
FR-4 board with 2 oz. Copper, in a still air environment with
TA = 25 °C. The value in any given application depends on the
user’s specific board design.
Junction Temperature (TJ)
Storage Temperature (TS)
ESD Rating(1)
-65 °C to +150 °C
2.0 kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 kΩ in series with 100 pF.
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Page 3 of 14
AOZ1051PI
Electrical Characteristics
)
TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified(3
Symbol
Parameter
Supply Voltage
Conditions
Min.
4.5
Typ. Max. Units
VIN
18
V
VUVLO
Input Under-Voltage Lockout
Threshold
VIN Rising
VIN Falling
4.1
3.7
1.6
1
V
IIN
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
IOUT = 0, VFB = 1.2 V, VEN > 2 V
VEN = 0 V
2.5
10
mA
µA
V
IOFF
VFB
TA = 25 °C
0.788
0.8
0.5
1
0.812
Load Regulation
%
Line Regulation
%
IFB
Feedback Voltage Input Current
EN Input Threshold
200
nA
VEN
Off Threshold
On Threshold
0.6
V
2
VHYS
EN Input Hysteresis
EN Leakage Current
SS Time
100
2
mV
µA
1
CSS = 16 nF
ms
MODULATOR
fO
Frequency
400
85
500
600
150
kHz
%
DMAX
TMIN
Maximum Duty Cycle
Controllable Minimum On Time
Current Sense Transconductance
Error Amplifier Transconductance
ns
8
A/ V
µA/V
200
PROTECTION
ILIM Current Limit
Over-Temperature Shutdown Limit
3.5
4.5
150
100
A
TJ Rising
TJ Falling
°C
OUTPUT STAGE
High-Side Switch On-Resistance
VIN = 12 V
VIN = 5 V
VIN = 12 V
VIN = 5 V
70
110
40
mΩ
mΩ
Low-Side Switch On-Resistance
50
Note:
3. Specification in BOLD indicate an ambient temperature range of -40 °C to +85 °C. These specifications are guaranteed by design.
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Page 4 of 14
AOZ1051PI
Typical Performance Characteristics
Circuit of Figure 1. T = 25 °C, V = V = 12 V, V
= 3.3 V unless otherwise specified.
A
IN
EN
OUT
Light Load Operation
Full Load Operation
Vin ripple
0.5V/div
Vin ripple
0.1V/div
Vo ripple
0.1V/div
Vo ripple
0.1V/div
IL
2A/div
IL
2A/div
VLX
10V/div
VLX
10V/div
2µs/div
2µs/div
Start Up to Full Load
Short Circuit Protection
Vin
5V/div
LVX
10V/div
Vo
2V/div
Vo
2V/div
IL
2A/div
lin
2A/div
2ms/div
20ms/div
50% to 100% Load Transient
Short Circuit Recovery
VLX
10V/div
Vo
0.1V/div
Vo
2V/div
Io
2A/div
IL
2A/div
100µs/div
20ms/div
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AOZ1051PI
Efficiency
Efficiency (VIN = 12V) vs. Load Current
100
95
90
85
80
75
70
65
60
5V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
1.2V OUTPUT
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
Load Current (A)
Detailed Description
The AOZ1051PI is a current-mode step down regulator
with an integrated high-side PMOS switch and a low-side
NMOS switch. The AOZ1051PI operates from a 4.5 V to
18 V input voltage range and supplies up to 3 A of load
current. Features include enable control, power-on reset,
input under voltage lockout, output over voltage
Steady-State Operation
Under heavy load steady-state conditions, the converter
operates in fixed frequency and Continuous-Conduction
Mode (CCM).
The AOZ1051PI integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference voltage is amplified
by the internal transconductance error amplifier. The
error voltage, which shows on the COMP pin, is
compared against the current signal, which is the sum of
inductor current signal and ramp compensation signal, at
the PWM comparator input. If the current signal is less
than the error voltage, the internal high-side switch is on.
The inductor current flows from the input through the
inductor to the output. When the current signal exceeds
the error voltage, the high-side switch is off. The inductor
current is freewheeling through the internal low-side
N-MOSFET switch to output. The internal adaptive FET
driver guarantees no turn on overlap of both the
protection, external soft-start and thermal shut down.
The AOZ1051PI is available in an exposed pad SO-8
package.
Enable and Soft Start
The AOZ1051PI has an external soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. The soft start process
begins when the input voltage rises to 4.1 V and voltage
on the EN pin is HIGH. In the soft start process, the
FB voltage is ramped to follow the voltage of the soft start
pin until it reaches 0.8 V. The voltage of the soft-start pin
is charged by an internal 5 µA current.
The EN pin of the AOZ1051PI is active high. Connect the
EN pin to VIN if the enable function is not used. Pulling
EN to ground will disable the AOZ1051PI. Do not leave
EN open. The voltage on the EN pin must be above 2 V
to enable the AOZ1051PI. When the EN pin voltage falls
below 0.6 V, the AOZ1051PI is disabled.
high-side and the low-side switch.
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AOZ1051PI
Compared with regulators using freewheeling Schottky
diodes, the AOZ1051PI uses a freewheeling NMOSFET
to realize synchronous rectification. This greatly
improves the converter efficiency and reduces power
loss in the low-side switch.
Since the switch duty cycle can be as high as 100 %, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on the upper PMOS and
the inductor.
Protection Features
The AOZ1051PI uses a P-Channel MOSFET as the
high-side switch. This saves the bootstrap capacitor
normally seen in a circuit using an NMOS switch. It also
allows 100 % turn-on of the high-side switch to achieve
linear regulation mode of operation. The minimum
The AOZ1051PI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
Over Current Protection (OCP)
voltage drop from V to V is the load current times DC
IN
O
The sensed inductor current signal is also used for over
current protection. Since the AOZ1051PI employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4 V and 2.5 V internally.
The peak inductor current is automatically limited
cycle-by-cycle.
resistance of the MOSFET plus DC resistance of the
buck inductor. It can be calculated by equation below:
V
= V – I × R
IN O DS(ON)
O_MAX
where;
V
O_MAX is the maximum output voltage,
IN is the input voltage from 4.5 V to 18 V,
V
When the output is shorted to ground under fault
conditions, the inductor current slowly decays during a
switching cycle because the output voltage is 0 V.
To prevent catastrophic failure, a secondary current limit
is designed inside the AOZ1051PI. The measured
inductor current is compared against a preset voltage
which represents the current limit, between 3.5 A and 5.0
A. When the output current is greater than the current
limit, the high side switch will be turned off. The converter
will initiate a soft start once the over-current condition is
resolved.
IO is the output current from 0 A to 3 A, and
RDS(ON) is the on resistance of the internal MOSFET.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin using a resistor divider network as shown in
Figure 1. The resistor divider network includes R and
1
R . Usually, a design is started by picking a fixed R
2
2
value and calculating the required R with the equation
1
below:
R
⎛
⎞
⎟
⎠
1
Power-On Reset (POR)
V
= 0.8 × 1 + ------
⎜
O
R
⎝
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4.1 V, the converter starts
operation. When input voltage falls below 3.7 V, the
converter will be shut down.
2
Some standard value of R and R for the most common
output voltages are listed in Table 1.
1
2
Thermal Protection
Table 1.
An internal temperature sensor monitors the junction
temperature. The sensor shuts down the internal control
circuit and high side PMOS if the junction temperature
exceeds 150 ºC. The regulator will restart automatically
under the control of the soft-start circuit when the junction
temperature decreases to 100 ºC.
V (V)
R (kΩ)
R (kΩ)
O
1
2
0.8
1.2
1.5
1.8
2.5
3.3
5.0
1.0
4.99
10
Open
10
11.5
10.2
10
12.7
21.5
31.1
52.3
10
10
The combination of R and R should be large enough to
1
2
avoid drawing excessive current from the output, which
will cause power loss.
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AOZ1051PI
For reliable operation and best performance, the input
capacitors must have a current rating higher than
Application Information
The basic AOZ1051PI application circuit is show in
Figure 1. Component selection is explained below.
I
at the worst operating conditions. Ceramic
CIN_RMS
capacitors are preferred for input capacitors because of
their low ESR and high current rating. Depending on the
application circuits, other low ESR tantalum capacitors
may be used. When selecting ceramic capacitors, X5R or
X7R type dielectric ceramic capacitors should be used
for their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
manufactures are based on a certain operating life time.
Further de-rating may need to be considered for long
term reliability.
Input Capacitor
The input capacitor must be connected to the V pin and
IN
the PGND pin of AOZ1051PI to maintain steady input
voltage and filter out the pulsing input current. The
voltage rating of input capacitor must be greater than
maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
Inductor
I
V
O
V
⎛
⎞
O
O
-----------------
--------
ΔV
=
× 1 – -------- ×
⎜
⎝
⎟
⎠
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For a given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
IN
f × C
V
V
IN
IN
IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
V
⎛
⎞
⎟
⎠
V
O
O
----------
× 1 – --------
⎜
ΔI
=
L
f × L
⎝
V
IN
V
⎛
⎜
⎝
⎞
⎟
⎠
V
O
The peak inductor current is:
O
--------
I
= I ×
1 – --------
CIN_RMS
O
V
V
IN
IN
ΔI
L
I
= I + --------
Lpeak
O
2
if we let m equal the conversion ratio:
V
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on the inductor is designed to be
20 % to 40 % of output current.
O
-------- = m
V
IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 below. It can be seen that when V is
O
half of V , C is under the worst current stress. The
IN
IN
worst current stress on C is 0.5 x I .
When selecting the inductor, confirm it is able to handle
the peak current without saturation at the highest
operating temperature.
IN
O
0.5
0.4
0.3
0.2
0.1
0
The inductor takes the highest current in a buck circuit.
The conduction loss on the inductor needs to be checked
for thermal and efficiency requirements.
ICIN_RMS(m)
IO
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. However,
they cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
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Page 8 of 14
AOZ1051PI
Output Capacitor
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Loop Compensation
The AOZ1051PI employs peak current mode control for
ease of use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It also greatly simplifies the
compensation loop design.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
1
⎛
⎞
⎠
ΔV = ΔI × ESR
+ -------------------------
O
L
CO
⎝
1
8 × f × C
f
= ----------------------------------
O
P1
2π ×
×
R
C
O
L
where,
CO is output capacitor value, and
The zero is a ESR zero due to the output capacitor and
its ESR. It is can be calculated by:
ESRCO is the equivalent series resistance of the output
capacitor.
1
f
= ------------------------------------------------
Z1
2π × C × ESR
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
O
CO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
1
-------------------------
ΔV = ΔI ×
O
L
8 × f × C
O
The compensation design shapes the converter control
loop transfer function for the desired gain and phase.
Several different types of compensation networks can be
used with the AOZ1051PI. For most cases, a series
capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV = ΔI × ESR
CO
O
L
In the AOZ1051PI, FB and COMP are the inverting input
and the output of the internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitors are
recommended as output capacitors.
G
EA
f
= ------------------------------------------
P2
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
2π × C × G
C
VEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
ΔI
L
I
= ----------
CO_RMS
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor in Figure 1.
12
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Page 9 of 14
AOZ1051PI
The zero given by the external compensation network,
capacitor C and resistor R , is located at:
Thermal Management and Layout
Considerations
C
C
In the AOZ1051PI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pad, to the filter inductor, to the output capacitor and
load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from the inductor,
to the output capacitors and load, to the low side
NMOSFET. Current flows in the second loop when the
low side NMOSFET is on.
1
f
= -----------------------------------
Z2
2π × C × R
C
C
To design the compensation circuit, a target crossover
frequency f to close the loop must be selected. The
C
system crossover frequency is where the control loop
has unity gain. The crossover is the also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transients. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
loop, converter stability under all line and load condition
must be considered.
In PCB layout, minimizing the area of the two loops will
reduce the noise of the circuit and improves efficiency.
A ground plane is strongly recommended to connect the
input capacitor, the output capacitor, and the PGND pin
of the AOZ1051PI.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of the switching frequency.
In the AOZ1051PI buck regulator circuit, the major power
dissipating components are the AOZ1051PI and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power:
The strategy for choosing R and C is to set the cross
C
C
over frequency with R and set the compensator zero
C
with C . Using selected crossover frequency, f , to
C
C
calculate R :
C
V
2π × C
P
= V × I – V × I
IN IN O O
O
C
total_loss
---------- -----------------------------
R
= f ×
×
C
C
V
G
× G
EA CS
FB
The power dissipation of the inductor can be
approximately calculated by the output current and DCR
value of the inductor:
where;
fC is the desired crossover frequency. For best performance,
fC is set to be about 1/10 of the switching frequency;
2
P
= I × R
× 1.1
inductor
inductor_loss
O
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V, and
The actual junction temperature can be calculated by the
power dissipation in the AOZ1051PI and the thermal
impedance from junction to ambient:
GCS is the current sense circuit transconductance, which is
8 A/V
T
= (P
–P
) × Θ
inductor_loss
JA
junction
total_loss
The compensation capacitor C and resistor R together
C
C
make a zero. This zero is put somewhere close to the
dominate pole f but lower than 1/5 of the selected
The maximum junction temperature of the AOZ1051PI is
150 ºC, which limits the maximum load current capability.
p1
crossover frequency. C can is selected by:
C
The thermal performance of the AOZ1051PI is strongly
affected by the PCB layout. Care should be taken during
the design process to ensure that the IC will operate
under the recommended environmental conditions.
1.5
C
= -----------------------------------
C
2π × R × f
C
P1
The above equation can be simplified to:
C × R
O
L
C
= ---------------------
C
R
C
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
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Page 10 of 14
AOZ1051PI
Layout Considerations
The AOZ1051PI is an exposed pad SO-8 package.
Several layout tips are listed for the best electric and
thermal performance.
1. The exposed pad (LX) is connected to the internal
PFET and NFET drains. Connected a large copper
plane to the LX pin to help thermal dissipation.
2. Do not use a thermal relief connection to the VIN pin
or the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
3. The input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and only connect
them at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current trace from the LX pad to L to Co to
the PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace away from the LX pad.
Rev. 1.0 June 2011
www.aosmd.com
Page 11 of 14
AOZ1051PI
Package Dimensions, SO-8 EP1
Gauge plane
0.2500
D0
C
L
L1
E1
E
E2
E3
L1'
D1
D
Note 5
θ
7 (4x)
A2
A1
A
e
B
Dimensions in millimeters
Dimensions in inches
Symbols Min.
Nom. Max.
Symbols Min.
Nom. Max.
A
A1
A2
B
C
D
D0
D1
E
1.40
0.00
1.40
0.31
0.17
4.80
3.20
3.10
5.80
—
1.55
0.05
1.50
0.406
—
4.96
3.40
3.30
6.00
1.27
3.90
2.41
0.40 REF
0.95
—
1.70
0.10
1.60
0.51
0.25
5.00
3.60
3.50
6.20
—
A
A1
A2
B
C
D
D0
D1
E
0.055 0.061 0.067
RECOMMENDED LAND PATTERN
0.000 0.002 0.004
0.055 0.059 0.063
0.012 0.016 0.020
3.70
0.007
—
0.010
0.189 0.195 0.197
0.126 0.134 0.142
0.122 0.130 0.138
0.228 0.236 0.244
2.20
5.74
2.71
e
e
—
0.050
—
E1
E2
E3
L
y
θ
3.80
2.21
4.00
2.61
E1
E2
E3
L
y
θ
0.150 0.153 0.157
0.087 0.095 0.103
0.016 REF
2.87
0.40
—
0°
1.27
0.10
8°
0.016 0.037 0.050
—
0°
—
—
3°
0.004
8°
0.80
UNIT: mm
1.27
3°
0.635
|
L1–L1'
L1
|
—
0.04
1.04 REF
0.12
|
L1–L1'
L1
|
0.002 0.005
0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Rev. 1.0 June 2011
www.aosmd.com
Page 12 of 14
AOZ1051PI
Tape and Reel Dimensions, SO-8 EP1
Carrier Tape
P1
P2
D1
T
E1
E2
E
B0
K0
D0
P0
A0
Feeding Direction
UNIT: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
SO-8
(12mm)
6.40
0.10
5.20
0.10
2.10
0.10
1.60
0.10
1.50
0.10
12.00 1.75
0.10 0.10
5.50
0.10
8.00
0.10
4.00
0.10
2.00
0.10
0.25
0.10
Reel
W1
S
G
V
N
K
M
R
H
W
UNIT: mm
Tape Size Reel Size
12mm ø330
M
N
W
W1
ø330.00 ø97.00 13.00 17.40
0.50 0.10 0.30 1.00 +0.50/-0.20
H
K
S
G
R
V
ø13.00
10.60
2.00
0.50
—
—
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
Rev. 1.0 June 2011
www.aosmd.com
Page 13 of 14
AOZ1051PI
Part Marking
Z1051PI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.0 June 2011
www.aosmd.com
Page 14 of 14
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