T6816-TIQ [ATMEL]

40-V Dual Hex Output Driver with Serial Input Control; 带串行输入控制40 -V双六角输出驱动器


型号：	T6816-TIQ
厂家：	ATMEL
描述：	40-V Dual Hex Output Driver with Serial Input Control 带串行输入控制40 -V双六角输出驱动器驱动器
文件：	总15页 (文件大小：173K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Features

• Six High-side and Six Low-side Drivers

• Outputs Freely Configurable as Switch, Half Bridge or H–bridge

• Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors

and Inductors

• 0.6 A Continuous Current per Switch

• Low-side: R_DSon< 1.5 ꢀ versus Total Temperature Range

• High-side: R_DSon< 2.0 ꢀ versus Total Temperature Range

• Very Low Quiescent Current Is < 20 µA in Standby Mode

• Outputs Short-circuit Protected

• Overtemperature Prewarning and Protection

• Undervoltage Protection

• Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature

and Power Supply Fail

• Serial Data Interface

• Operation Voltage up to 40 V

40-V Dual Hex

Output Driver

with Serial Input

Control

• Daisy Chaining Possible

• SO28 Power Package

Description

T6816

The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technol-

ogy. It is especially suitable for truck or bus applications and the industrial 24-V supply.

It controls up to 12 different loads via a 16-bit dataword.

Each of the six high-side and six low-side drivers is capable to drive currents up to

600 mA. The drivers are freely configurable and can be controlled separately from a

standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,

capacitors and inductors can be combined. The IC is also designed to easily build H-

bridges to drive DC motors in motion-control applications.

Protection is guaranteed in terms of short-circuit conditions, overtemperature and

undervoltage. Various diagnosis functions and a very low quiescent current in standby

mode open a wide range of applications.

Overvoltage protection is matched to the requirements of the 24-V industrial voltage

and the 24-V automotive supply. Automotive qualification referring to conducted inter-

ferences, EMC protection and 2 kV ESD protection gives added value and enhanced

quality for the exacting requirements of automotive applications.

Rev. 4595B–BCD–05/03

Figure 1. Block Diagram

HS3

HS5

HS6

HS1

HS2

HS4

Fault

Detect

Fault

Detect

Fault

Detect

Fault

Detect

Fault

Detect

GND

Osc

GND

CLK

UV -

protection

Control

logic

Input Register

Output Register

GND

Thermal

protection

INH

Power-on

reset

Vcc

Fault

Detect

Fault

Detect

Fault

Detect

Fault

Detect

Fault

Detect

Fault

Detect

GND

Vcc

LS1

LS2

LS3

LS6

LS4

LS5

T6816

4595B–BCD–05/03

T6816

Pin Configuration

Figure 2. Pinning SO28

HS6 LS6

28 27

CLK

CS GND GND GND GND VCC DO INH

LS1 HS1

16 15

T6816

Lead frame

GND GND GND GND

LS5 HS5 HS4 LS4 VS

VS LS3 HS3 HS2 LS2

Pin Description

Symbol

Function

Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for

short and open load

LS5

High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for

short and open load

HS5

HS4

LS4

High-side driver output 4; see Pin 2

Low-side driver output 4; see Pin 1

Power supply output stages HS4, HS5, HS6, internal supply; external connection to Pin 10 necessary

Ground; reference potential; internal connection to Pin 20 - 23; cooling tab

Power supply output stages HS1, HS2 and HS3

Low-side driver output 3; see Pin 1

6, 7, 8, 9

GND

LS3

HS3

HS2

LS2

HS1

LS1

High-side driver output 3; see Pin 2

High-side driver output 2; see Pin 2

Low-side driver output 2; see Pin 1

High-side driver output 1; see Pin 2

Low-side driver output 1; see Pin 1

Inhibit input; 5 V logic input with internal pull down; low = standby,

high = normal operating

INH

Serial data output; 5 V CMOS logic level tri-state output for output (status) register data; sends 16-bit status

information to the QC (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low,

therefore, several ICs can operate on one data output line only.

VCC

GND

Logic supply voltage (5 V)

20, 21, 22,

Ground; see Pin 6 – 9

Chip select input; 5 V CMOS logic level input with internal pull up;

low = serial communication is enabled, high = disabled

Serial clock input; 5 V CMOS logic level input with internal pull down;

controls serial data input interface and internal shift register (f_max= 2 MHz)

CLK

Serial data input; 5 V CMOS logic level input with internal pull down; receives serial data from the control device; DI

expects a 16-bit control word with LSB being transferred first

Low-side driver output 6; see Pin 1

High-side driver output 6; see Pin 2

LS6

HS6

4595B–BCD–05/03

Functional Description

Serial Interface

Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-

chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,

SRR) has to be transferred first. Execution of new input data is enabled on the rising

edge of the CS signal. When CS is high, Pin DO is in tri-state condition. This output is

enabled on the falling edge of CS. Output data will change their state with the rising

edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is

transferred first.

Figure 3. Data Transfer Input Data Protocol

SRR

LS1

HS1

LS2

HS2

LS3

HS3

LS4

HS4

LS5

HS5

LS6

HS6 OLD SCT

12 13 14

CLK

SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD

INH

PSF

Table 1. Input Data Protocol

Bit

Input Register

Function

Status register reset (high = reset; the bits PSF, SCD and

overtemperature shutdown in the output data register are set to

low)

SRR

LS1

HS1

LS2

HS2

LS3

HS3

LS4

HS4

LS5

HS5

LS6

HS6

Controls output LS1 (high = switch output LS1 on)

Controls output HS1 (high = switch output HS1 on)

See LS1

See HS1

See LS1

See HS1

See LS1

See HS1

See LS1

See HS1

See LS1

See HS1

T6816

4595B–BCD–05/03

T6816

Table 1. Input Data Protocol (Continued)

Bit

Input Register

Function

OLD

Open load detection (low = on)

Programmable time delay for short circuit (shutdown delay high/

low = 12 ms/1.5 ms

SCT

Software inhibit; low = standby, high = normal operation

(data transfer is not affected by standby function because the

digital part is still powered)

Table 2. Output Data Protocol

Output (Status)

Bit

Function

Temperature prewarning: high = warning (overtemperature shut-

down see remark below)

Normal operation: high = output is on, low = output is off

Open-load detection: high = open load, low = no open load

(correct load condition is detected if the corresponding output is

switched off)

Status LS1

Status HS1

Normal operation: high = output is on, low = output is off

Open-load detection: high = open load, low = no open load

(correct load condition is detected if the corresponding output is

switched off)

Status LS2

Status HS2

Status LS3

Status HS3

Status LS4

Status HS4

Status LS5

Status HS5

Status LS6

Status HS6

Description see LS1

Description see HS1

Description see LS1

Description see HS1

Description see LS1

Description see HS1

Description see LS1

Description see HS1

Description see LS1

Description see HS1

Short circuit detected: set high, when at least one output is

switched off by a short circuit condition

SCD

Inhibit: this bit is controlled by software (bit SI in input register)

and hardware inhibit (Pin 17). High = standby, low = normal

operation

INH

PSF

Power supply fail: undervoltage at Pin VS detected

Note:

Bit 0 to 15 = high: overtemperature shutdown

Table 3. Status of the Input Register after Power on Reset

Bit 15

(SI)

Bit 14

(SCT)

Bit 13

(OLD)

Bit 12

(HS6)

Bit 11

(LS6)

Bit 10

(HS5)

Bit 9

(LS5)

Bit 8

(HS4)

Bit 7

(LS4)

Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

4595B–BCD–05/03

Power Supply Fail

In case of undervoltage at Pin VS, an internal timer is started. When the undervoltage

delay time (t_dUV) programmed by the SCT bit is reached, the power supply fail bit (PSF)

in the output register is set and all outputs are disabled. When normal voltage is present

again, the outputs are enabled immediately. The PSF bit remains high until it is reset by

the SRR bit in the input register.

Open-load Detection

If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side

switch and a pull-down current for each low-side switch is turned on (open-load detec-

tion current I_HS1-6, I_LS1-6). If V_VS–V_HS1-6or V_LS1-6is lower than the open-load detection

threshold (open-load condition), the corresponding bit of the output in the output register

is set to high. Switching on an output stage with OLD bit set to low disables the open-

load function for this output.

Overtemperature

Protection

If the junction temperature exceeds the thermal prewarning threshold, T_{jPW set}, the tem-

perature prewarning bit (TP) in the output register is set. When the temperature falls

below the thermal prewarning threshold, T_{jPW reset}, the bit TP is reset. The TP bit can be

read without transferring a complete 16-bit data word: with CS = high to low, the state of

TP appears at Pin DO. After the microcontroller has read this information, CS is set high

and the data transfer is interrupted without affecting the state of the input and output

registers.

If the junction temperature exceeds the thermal shutdown threshold, T_{j switch off}, the out-

puts are disabled and all bits in the output register are set high. The outputs can be

enabled again when the temperature falls below the thermal shutdown threshold,

T _{j switch on}, and when a high has been written to the SRR bit in the input register. Ther-

mal prewarning and shutdown threshold have hysteresis.

Short-circuit Protection

The output currents are limited by a current regulator. Current limitation takes place

when the overcurrent limitation and shutdown threshold (I_HS1-6, I_LS1-6) are reached.

Simultaneously, an internal timer is started. The shorted output is disabled when during

a permanent short the delay time (t_dSd) programmed by the short-circuit timer bit (SCT)

is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature

prewarning bit TP in the output register is set during a short, the shorted output is dis-

abled immediately and SCD bit is set. By writing a high to the SRR bit in the input

Inhibit

There are two ways to inhibit the T6816:

1. Set bit SI in the input register to zero

2. Switch Pin 17 (INH) to 0 V

In both cases, all output stages are turned off but the serial interface stays active. The

output stages can be activated again by bit SI = 1 or by Pin 17 (INH) switched back to

5 V.

T6816

4595B–BCD–05/03

T6816

Absolute Maximum Ratings

All values refer to GND pins

Parameter

Symbol

Value

-0.3 to +40

-1

Unit

Supply voltage Pins 5, 10

Supply voltage tt0.5 s; I_Su-2 A Pins 5, 10

V_VS

Supply voltage difference |V_{S_Pin5}- V_{S_Pin10}

Supply current Pins 5, 10

DV_VS

150

I_VS

1.4

Supply current t < 200 ms Pins 5, 10

Logic supply voltage Pin 19

Input voltage Pin 17

2.6

V_VCC

-0.3 to +7

-0.3 to +17

-0.3 to V_VCC+0.3

-10 to +10

V_INH

Logic input voltage Pins 24 to 26

Logic output voltage Pin 18

Input current Pins 17, 24 to 26

Output current Pin 18

V_DI,V_CLK,V_CS

V_DO

I_INH,I_DI,I_CLK,I_CS

I_DO

I_{LS1 to}I_LS6

I_{HS1 to}I_HS6

Output current Pins 1 to 4, 11 to 16,

Pins 27 and 28

Internal limited, see

output specification

Reverse conducting current Pins 2, 3, 12, 13,

15, (t_Pulse= 150 ms) 28 towards Pins 5, 10

I_{HS1 to}I_HS6

Junction temperature range

Storage temperature range

T_j

-40 to +150

-55 to +150

T_STG

Thermal Resistance

All values refer to GND pins

Parameter

Test Conditions

Measured to GND

Symbol

Min.

Typ.

Max.

Unit

Junction - pin

R_thJP

K/W

Pins 6 to 9 and 20 to 23

Junction ambient

R_thJA

K/W

Operating Range

All values refer to GND pins

Parameter

Test Conditions

Pins 5, 10

Symbol

V_VS

Min.

Typ.

Max.

Unit

(1)

Supply voltage

V_UV

4.5

Logic supply voltage

Logic input voltage

Pin 19

V_VCC

5.5

Pin 17, 24 to 26

V_INH,V_DI,

V_CLK,V_CS

-0.3

V_VCC

Serial interface clock frequency

Junction temperature range

Pin 25

f_CLK

T_j

MHz

-40

150

Note:

1. Threshold for undervoltage detection.

4595B–BCD–05/03

Noise and Surge Immunity

Parameter

Test Conditions

Value

Level 4 ⁽¹⁾

Level 5

2 kV

Conducted interferences

Interference Suppression

ESD (Human Body Model)

ESD (Machine Model)

ISO 7637-1

VDE 0879 Part 2

MIL-STD-883D Method 3015.7

EOS/ESD - S 5.2

150 V

Note:

1. Test pulse 5: V_Smax= 40 V

Electrical Characteristics

7.5 V < V_VS< 40 V; 4.5 V < V_VCC< 5.5 V; INH = High; -40°C < T_j< 150°C; unless otherwise specified,

all values refer to GND pins.

No.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Current Consumption

1.1

Quiescent current

(VS)

V_VS< 28 V, INH or

bit SI = lo

5, 10

I_VS

µA

1.2

1.3

Quiescent current

(VCC)

4.5 V < V_VCC< 5.5 V,

INH or bit SI = low

I_VCC

V_VS< 28 V normal

operating, all output

stages off,

Supply current (VS)

5, 10

I_VS

0.8

1.2

1.4

1.5

V_VS< 28 V normal

operating, all output

stages on, no load

Supply current (VS)

Supply current (VCC)

5, 10

I_VS

µA

4.5 V < V_VCC< 5.5 V,

normal operating Pin

I_VCC

150

2.1

Internal Oscillator Frequency

Frequency (timebase

for delay timers)

f_OSC

kHz

Undervoltage Detection, Power-on Reset

Power–on reset

threshold

3.1

V_VCC

t_dPor

V_UV

3.4

3.9

4.4

160

7.0

µs

Power–on reset delay

time

After switching on

V_VCC

3.2

3.3

3.4

3.5

Undervoltage

detection threshold

5, 10

5.5

Undervoltage

detection hysteresis

ꢁV_UV

t_dUV

0.4

Undervoltage

detection delay

Thermal Prewarning and Shutdown

Thermal prewarning

4.1

4.2

T_jPWset

125

105

145

125

165

145

Thermal prewarning

T_jPWreset

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

T6816

4595B–BCD–05/03

T6816

Electrical Characteristics (Continued)

7.5 V < V_VS< 40 V; 4.5 V < V_VCC< 5.5 V; INH = High; -40°C < T_j< 150°C; unless otherwise specified,

all values refer to GND pins.

No.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

4.3

Thermal prewarning

hysteresis

DT_jPW

4.4

4.5

4.6

Thermal shutdown

T_{j switch off}

T_{j switch on}

150

130

170

150

190

170

Thermal shutdown

hysteresis

DT_{j switch off}

4.7

4.8

Ratio thermal

shutdown/thermal

prewarning

T_{j switch off/}

T_{jPW set}

1.05

1.17

Ratio thermal

shutdown/thermal

prewarning

T_{j switch on/}

T_{jPW reset}

1.2

Output Specification (LS1 - LS6, HS1 - HS6) 7.5 V < V_VS< 40 V

5.1

1, 4,

11,

14,

16, 27

R_{DS OnL}

1.5

ꢀ

On resistance

I_Out= 600 mA

5.2

5.3

5.4

5.5

2, 3,

12,

13,

R_{DS OnH}

2.0

ꢀ

I_Out= -600 mA

15, 28

1, 4,

11,

14,

V_LS1-6

Output clamping

voltage

I_LS1-6= 50 mA

16, 27

1, 4,

11,

14,

Output leakage

current

_LS1–6= 40 V

I_LS1–6

µA

all output stages off

16, 27

2, 3,

12,

13,

Output leakage

current

_HS1-6= 0 V

I_HS1–6

-10

µA

all output stages off

15, 28

5.7

5.8

5.9

1-4,

11-16

27, 28

W_outx

Inductive shutdown

energy

1-4,

11-16

27, 28

dV_LS1–6/dt

dV_HS1–6/dt

200

950

400

mV/µs

Output voltage edge

steepness

Overcurrent limitation

and shutdown

threshold

1, 4,

11,14

16, 27

I_LS1–6

650

1250

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

4595B–BCD–05/03

Electrical Characteristics (Continued)

7.5 V < V_VS< 40 V; 4.5 V < V_VCC< 5.5 V; INH = High; -40°C < T_j< 150°C; unless otherwise specified,

all values refer to GND pins.

No.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

5.10

Overcurrent limitation

and shutdown

threshold

2, 3,

12,13

15, 28

I_HS1–6

-1250

-950

-650

5.11

5.12

Overcurrent

shutdown delay time

Input register

bit 14 (SCT) = low

t_dSd

1.0

1.5

2.0

µA

1, 4,

11,14

16, 27

Open load detection

current

Input register bit 13

(OLD) =low, output off

I_LS1–6

200

5.13

2, 3,

12,13

15, 28

Open load detection

current

Input register bit 13

(OLD) =low, output off

I_HS1–6

-150

1.2

-30

µA

5.14

5.15

Open load detection

current ratio

_LS1–6/I_HS1–

1, 4,

11,14

16, 27

Open load detection

threshold

Input register bit 13

(OLD) =low, output off

V_LS1–6

0.6

5.16

2, 3,

12,13

15, 28

Open load detection

threshold

Input register bit 13

(OLD) =low, output off

V_VS–

V_HS1–6

0.6

5.17

5.18

Output switch on

delay ¹⁾

R_Load= 1 kꢀ

t_don

t_doff

0.5

Output switch off

delay ¹⁾

Inhibit Input

6.1

Input voltage low level

threshold

0.3-

V_VCC

V_IL

V_IH

6.2

6.3

Input voltage high

level threshold

0.7-

V_VCC

Hysteresis of input

voltage

ꢁV_I

100

700

µA

6.4

Pull-down current

V_INH= V_VCC

I_PD

Serial Interface - Logic Inputs DI, CLK, CS

7.1

Input voltage low-

level threshold

0.3-

V_VCC

24-26

25, 26

V_IL

V_IH

7.2

7.3

7.4

7.5

Input voltage high-

level threshold

0.7-

V_VCC

Hysteresis of input

voltage

DV_I

I_PDSI

I_PUSI

500

µA

Pull-down current Pin

V_DI, V_CLK= V_VCC

DI, CLK

Pull-up current

Pin CS

V_CS= 0 V

-50

-2

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

T6816

4595B–BCD–05/03

T6816

Electrical Characteristics (Continued)

7.5 V < V_VS< 40 V; 4.5 V < V_VCC< 5.5 V; INH = High; -40°C < T_j< 150°C; unless otherwise specified,

all values refer to GND pins.

No.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Serial Interface - Logic Output DO

8.1

Output voltage low

I_OL= 3 mA

level

V_DOL

V_DOH

I_DO

0.5

8.2

8.3

Output voltage high

I_OL= -2 mA

level

V_VCC

0.7 V

Leakage current

(tri-state)

V_CS= V_VCC,

0 V < V_DO< V_VCC

-10

µA

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

Serial Interface — Timing

Parameters

Test Conditions

C_DO= 100 pF

Timing Chart No.

Symbol

t_ENDO

t_DISDO

t_DOf

Min.

Typ.

Max.

200

100

200

Unit

DO enable after CS falling edge

DO disable after CS rising edge

DO fall time

–

DO rise time

–

t_DOr

DO valid time

t_DOVal

t_CSSethl

t_CSSetlh

CS setup time

225

CS setup time

Input register Bit 14

(SCT) = high

CS high time

t_CSh

Input register Bit 14

(SCT) = low

CLK high time

CLK low time

CLK period time

CLK setup time

DI setup time

DI hold time

t_CLKh

t_CLKl

225

500

225

–

t_CLKp

t_CLKSethl

t_CLKSetlh

t_DIset

t_DIHold

4595B–BCD–05/03

Figure 4. Serial Interface Timing with Chart Numbers

CLK

Inputs DI, CLK, CS: High level = 0.7 x V_CC,low level = 0.3 x V_CC

Output DO: High level = 0.8 x V_CC, low level = 0.2 x V_CC

T6816

4595B–BCD–05/03

T6816

Figure 5. Application Circuit

Vcc

U5021M

Enable

WATCHDOG

HS1

HS2

HS3

HS4

HS5

HS6

BYT41

V_BAT

V_S

Fault

Detect

24V

GND

Osc

GND

CLK

Control

logic

UV -

Input Register

Output Register

ꢀC

INH

protection

GND

Thermal

protection

Power-on

Reset

GND

Vcc

Fault

Detect

Fault

Detect

Fault

Detect

Fault

Detect

Vcc

5 V

LS1

LS2

LS3

LS4

LS5

LS6

Application Notes

It is strongly recommended to connect the blocking capacitors at V_CCand V_Sas close as

possible to the power supply and GND pins.

Recommended value for capacitors at V_S:

electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value

for electrolytic capacitor depends on external loads, conducted interferences and

reverse conducting current I_HSX(see: Absolut Maximum Ratings).

Recommended value for capacitors at V_CC

electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.

To reduce thermal resistance it is recommended to place cooling areas on the PCB as

close as possible to GND pins.

4595B–BCD–05/03

Ordering Information

Extended Type Number

Package

Remarks

T6816-TIQ

SO28

Power package, taped and reeled

Package Information

9.15

8.65

Package SO28

Dimensions in mm

18.05

17.80

7.5

7.3

2.35

0.25

0.10

0.4

10.50

10.20

1.27

16.51

technical drawings

according to DIN

specifications

T6816

4595B–BCD–05/03

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Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

Europe

Microcontrollers

Atmel Sarl

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

FAX 1(719) 540-1759

TEL (41) 26-426-5555

FAX (41) 26-426-5500

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

ASIC/ASSP/Smart Cards

Zone Industrielle

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

Japan

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

FAX 1(719) 540-1759

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

Atmel^®is the registered trademark of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4595B–BCD–05/03

T6816-TIQ [ATMEL]

相关型号：

T6816-TIQY

T6816_05

T6816_08

T6816_09

T6817

T6817-FP

T6817-TKQ

T6817-TKQY

T6817-TKS

T6817-TKSY

T6817_05

T6817_07