T6816_05 [ATMEL]
40-V Dual Hex Output Driver with Serial Input Control; 带串行输入控制40 -V双六角输出驱动器
| 型号： | T6816_05 |
| 厂家： | 
ATMEL |
| 描述： | 40-V Dual Hex Output Driver with Serial Input Control |
| 文件： | 总16页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
Six High-side and Six Low-side Drivers
Outputs Freely Configurable as Switch, Half Bridge or H-bridge
Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
•
•
•
•
•
•
•
•
0.6A Continuous Current per Switch
Low-side: RDSon < 1.5Ωversus Total Temperature Range
High-side: RDSon < 2.0Ω versus Total Temperature Range
Very Low Quiescent Current Is < 20 µA in Standby Mode
Outputs Short-circuit Protected
40-V Dual Hex
Output Driver
with Serial Input
Control
Overtemperature Prewarning and Protection
Undervoltage Protection
Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
•
•
•
•
Serial Data Interface
Operation Voltage up to 40V
T6816
Daisy Chaining Possible
SO28 Power Package
1. Description
The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technol-
ogy. It is especially suitable for truck or bus applications and the industrial 24-V
supply. It controls up to 12 different loads via a 16-bit dataword.
Each of the six high-side and six low-side drivers is capable to drive currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC is also designed to easily build
H-bridges to drive DC motors in motion-control applications.
Protection is guaranteed in terms of short-circuit conditions, overtemperature and
undervoltage. Various diagnosis functions and a very low quiescent current in standby
mode open a wide range of applications.
Automotive qualification referring to conducted interferences, EMC protection and
2 kV ESD protection gives added value and enhanced quality for the exacting require-
ments of automotive applications.
Rev. 4595E–BCD–09/05
Figure 1-1. Block Diagram
HS3
HS5
HS6
HS1
HS2
HS4
15
3
2
13
12
28
5
10
6
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
VS
VS
Fault
Fault
Detect
Detect
26
DI
GND
Osc
7
25
24
S
C
T
O
L
H
S
6
H
S
5
H
S
4
H
S
2
L
S
2
H
L
S
6
L
L
S
4
H
S
3
L
S
3
L
S
1
S
R
R
GND
GND
CLK
S
I
S
5
S
1
D
VS
8
Control
logic
UV -
protection
Input Register
Output Register
CS
9
GND
GND
GND
GND
Thermal
protection
17
18
L
S
6
P
S
F
S
C
D
H
S
6
H
S
5
H
S
4
H
L
S
2
H
S
1
T
P
L
S
5
L
S
4
H
S
3
L
S
3
L
S
1
I
INH
20
N
H
S
2
Power-on
reset
21
22
23
19
DO
VCC
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
GND
VCC
VCC
4
1
16
LS1
14
LS2
11
LS3
27
LS6
LS4
LS5
2
T6816
4595E–BCD–09/05
T6816
2. Pin Configuration
Figure 2-1. Pinning SO28
HS6 LS6
DI
CLK
25
CS GND GND GND GND VCC DO INH
24
22
LS1 HS1
16 15
26
28
27
23
21
20
19
18
17
T6816
Lead frame
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND GND GND GND
LS5 HS5 HS4 LS4 VS
VS LS3 HS3 HS2 LS2
Table 2-1.
Pin
Pin Description
Symbol
Function
Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection;
diagnosis for short and open load
1
2
LS5
High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection;
diagnosis for short and open load
HS5
3
4
HS4
LS4
VS
High-side driver output 4; see pin 2
Low-side driver output 4; see pin 1
5
Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary
Ground; reference potential; internal connection to pin 20-23; cooling tab
Power supply output stages HS1, HS2 and HS3
Low-side driver output 3; see pin 1
6, 7, 8, 9
10
GND
VS
11
LS3
HS3
HS2
LS2
HS1
LS1
INH
12
High-side driver output 3; see pin 2
13
High-side driver output 2; see pin 2
14
Low-side driver output 2; see pin 1
15
High-side driver output 1; see pin 2
16
Low-side driver output 1; see pin 1
17
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operating
Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status
information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is
selected by CS = low, therefore, several ICs can operate on one data output line only.
18
DO
19
VCC
GND
Logic supply voltage (5V)
Ground; see pin 6-9
20-23
Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
24
25
26
CS
CLK
DI
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
27
28
LS6
HS6
Low-side driver output 6; see pin 1
High-side driver output 6; see pin 2
3
4595E–BCD–09/05
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
CS
DI
SRR
0
LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT SI
10 11 12 13 14 15
1
2
3
4
5
6
7
8
9
CLK
DO
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH
PSF
Table 3-1.
Bit
Input Data Protocol
Input Register
Function
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
LS4
HS4
LS5
HS5
LS6
HS6
OLD
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
See LS1
8
See HS1
9
See LS1
10
11
12
13
See HS1
See LS1
See HS1
Open load detection (low = on)
Programmable time delay for short circuit
(shutdown delay high/low = 12 ms/1.5 ms)
14
SCT
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part
is still powered)
15
SI
4
T6816
4595E–BCD–09/05
T6816
Table 3-2.
Output Data Protocol
Output (Status)
Register
Bit
Function
Temperature prewarning: high = warning
(overtemperature shutdown see remark below)
0
TP
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
1
2
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
Status HS1
3
4
Status LS2
Status HS2
Status LS3
Status HS3
Status LS4
Status HS4
Status LS5
Status HS5
Status LS6
Status HS6
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
5
6
7
8
9
10
11
12
Short circuit detected: set high, when at least one output is switched off by a
short circuit condition
13
SCD
Inhibit: this bit is controlled by software (bit SI in input register) and hardware
inhibit (pin 17). High = standby, low = normal operation
14
15
INH
PSF
Power supply fail: undervoltage at pin VS detected
Note:
Bit 0 to 15 = high: overtemperature shutdown
Table 3-3.
Status of the Input Register after Power on Reset
Bit 15
(SI)
Bit 14
Bit 13
(OLD)
Bit 12
(HS6)
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(SCT)
(LS6)
(HS5)
(LS5) (HS4) (LS4)
(HS3)
(LS3)
(HS2)
(LS2) (HS1) (LS1)
(SRR)
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
5
4595E–BCD–09/05
3.2
3.3
3.4
Power Supply Fail
In case of undervoltage at pin VS, an internal timer is started. When the undervoltage delay time
(tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output regis-
ter is set and all outputs are disabled. When normal voltage is present again, the outputs are
enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input
register.
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6
LS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condi-
,
I
tion), the corresponding bit of the output in the output register is set to high. Switching on an
output stage with OLD bit set to low disables the open-load function for this output.
Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature
prewarning bit (TP) in the output register is set. When the temperature falls below the thermal
prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a
complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the
microcontroller has read this information, CS is set high and the data transfer is interrupted with-
out affecting the state of the input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are
disabled and all bits in the output register are set high. The outputs can be enabled again when
the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has
been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold
have hysteresis.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the
overcurrent limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an
internal timer is started. The shorted output is disabled when during a permanent short the delay
time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-cir-
cuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set
during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to
the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.
3.6
Inhibit
There are two ways to inhibit the T6816:
1. Set bit SI in the input register to zero
2. Switch pin 17 (INH) to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output
stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V.
6
T6816
4595E–BCD–09/05
T6816
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins
Parameter
Pin
Symbol
Value
–0.3 to +40
–1
Unit
V
Supply voltage
5, 10
5, 10
VVS
Supply voltage t < 0.5 s; IS ≥ –2 A
VVS
V
Supply voltage difference
Supply current
VS_pin5 – VS_pin10
∆VVS
150
mV
A
5, 10
5, 10
19
IVS
IVS
1.4
Supply current t < 200 ms
Logic supply voltage
Input voltage
2.6
A
VVCC
–0.3 to +7
–0.3 to +17
–0.3 to VVCC +0.3
–0.3 to VVCC +0.3
–10 to +10
–10 to +10
V
17
VINH
V
Logic input voltage
Logic output voltage
Input current
24 to 26
18
VDI, VCLK, VCS
VDO
IINH, IDI, ICLK, ICS
IDO
LS1 to ILS6
IHS1 to IHS6
V
V
17, 24 to 26
18
mA
mA
Output current
1 to 4, 11 to 16,
27 and 28
I
Internal limited, see
output specification
Output current
Reverse conducting current
(tPulse = 150 µs)
2, 3, 12, 13, 15,
28 towards 5, 10
I
HS1 to IHS6
17
A
Junction temperature range
Storage temperature range
Tj
–40 to +150
–55 to +150
°C
°C
TSTG
5. Thermal Resistance
All values refer to GND pins
Parameter
Test Conditions
Pin
Symbol
RthJP
Min.
Typ.
Max.
Unit
K/W
K/W
Junction pin
Measured to GND
6 to 9, 20 to 23
25
65
Junction ambient
RthJA
6. Operating Range
All values refer to GND pins
Parameter
Test Conditions
Pin
5, 10
19
Symbol
VVS
Min.
Typ.
Max.
40
Unit
V
(1)
Supply voltage
Logic supply voltage
VUV
4.5
VVCC
5
5.5
V
VINH, VDI, VCLK,
VCS
Logic input voltage
17, 24 to 26
25
–0.3
–40
VVCC
2
V
Serial interface clock
frequency
fCLK
Tj
MHz
°C
Junction
temperature range
150
Note:
1. Threshold for undervoltage detection.
7
4595E–BCD–09/05
7. Noise and Surge Immunity
Parameter
Test Conditions
Value
Level 4(1)
Level 5
2 kV
Conducted interferences
Interference Suppression
ESD (Human Body Model)
ESD (Machine Model)
ISO 7637-1
VDE 0879 Part 2
MIL-STD-883D Method 3015.7
EOS/ESD - S 5.2
150V
Note:
1. Test pulse 5: VSmax = 40V
8. Electrical Characteristics
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
VVS < 28V,
INH or bit SI = low
1.1
Quiescent current (VS)
5, 10
19
IVS
40
20
µA
µA
A
A
Quiescent current
(VCC)
4.5V < VVCC < 5.5V,
INH or bit SI = low
1.2
1.3
IVCC
V
VS < 28V normal
Supply current (VS)
operating, all output
stages off
5, 10
IVS
0.8
1.2
mA
A
V
VS < 28V normal
1.4
Supply current (VS)
Supply current (VCC)
operating, all output
stages on, no load
5, 10
19
IVS
10
mA
µA
A
A
4.5V < VVCC < 5.5V,
normal operating pin
1.5
2
IVCC
150
Internal Oscillator Frequency
Frequency (timebase
for delay timers)
2.1
3
fOSC
19
45
kHz
A
Undervoltage Detection, Power-on Reset
Power-on reset
threshold
3.1
19
VVCC
tdPor
VUV
3.4
30
3.9
95
4.4
160
7.0
V
µs
V
A
A
A
A
A
Power-on reset delay
After switching on VVCC
time
3.2
3.3
3.4
3.5
19
Undervoltage detection
threshold
5, 10
5, 10
5, 10
5.5
Undervoltage detection
hysteresis
∆VUV
tdUV
0.4
V
Undervoltage detection
delay
7
21
ms
4
Thermal Prewarning and Shutdown
Thermal prewarning
4.1
4.2
17
17
TjPWset
125
105
145
125
165
145
°C
°C
A
A
Thermal prewarning
TjPWreset
Thermal prewarning
hysteresis
4.3
∆TjPW
20
K
A
A
4.4
Thermal shutdown
17
Tj switch off
150
170
190
°C
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
8
T6816
4595E–BCD–09/05
T6816
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
4.5
Thermal shutdown
17
Tj switch on
130
150
170
°C
A
Thermal shutdown
hysteresis
4.6
∆Tj switch off
20
K
A
Ratio thermal
shutdown/thermal
prewarning
Tj switch off/
TjPW set
4.7
1.05
1.05
1.17
A
Ratio thermal
shutdown/thermal
prewarning
Tj switch on/
TjPW reset
4.8
5
1.2
A
Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < 40V
1, 4, 11,
5.1
On resistance
On resistance
I
Out = 600 mA
14, 16,
27
RDS OnL
RDS OnH
VLS1-6
ILS1-6
1.5
2.0
60
Ω
Ω
A
A
A
A
A
D
A
A
2, 3, 12,
13, 15,
28
5.2
5.3
5.4
5.5
5.7
5.8
5.9
IOut = –600 mA
ILS1-6 = 50 mA
1, 4, 11,
14, 16,
27
Output clamping
voltage
40
V
1, 4, 11,
14, 16,
27
V
LS1–6 = 40V
Output leakage current
Output leakage current
10
µA
all output stages off
2, 3, 12,
13, 15,
28
VHS1-6 = 0V
IHS1-6
–10
µA
all output stages off
1-4,
11-16,
27, 28
Inductive shutdown
energy
Woutx
15
mJ
mV/µs
mA
1-4,
11-16,
27, 28
Output voltage edge
steepness
dVLS1-6/dt
dVHS1-6/dt
50
200
950
400
1-4,
11-16,
27
Overcurrent limitation
and shutdown threshold
ILS1-6
650
1250
2, 3,
12,13,
15, 28
Overcurrent limitation
and shutdown threshold
5.10
5.11
5.12
IHS1-6
–1250
1.0
–950
1.5
–650
2.0
mA
ms
µA
A
A
A
Overcurrent shutdown Input register
tdSd
delay time
bit 14 (SCT) = low
1, 4,
11,14,
16, 27
Open load detection
current
Input register bit 13
(OLD) = low, output off
ILS1-6
60
200
2, 3, 12,
13 15,
28
Open load detection
current
Input register bit 13
(OLD) = low, output off
5.13
IHS1-6
–150
–30
µA
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
9
4595E–BCD–09/05
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Open load detection
current ratio
5.14
ILS1-6/IHS1-6
1.2
A
1, 4,
11,14,
16, 27
Open load detection
threshold
Input register bit 13
(OLD) = low, output off
5.15
VLS1-6
0.6
0.6
2
2
V
V
A
A
2, 3,
12, 13
15, 28
Open load detection
threshold
Input register bit 13
(OLD) = low, output off
VVS
–
5.16
5.17
VHS1-6
Output switch on
delay(1)
RLoad = 1 kΩ
RLoad = 1 kΩ
tdon
0.5
1
ms
ms
A
A
Output switch off
delay(1)
5.18
6
tdoff
Inhibit Input
Input voltage low level
threshold
0.3 ×
VVCC
6.1
17
17
VIL
VIH
V
V
A
A
Input voltage high level
threshold
0.7 ×
VVCC
6.2
6.3
Hysteresis of input
voltage
17
17
∆VI
100
10
700
80
mV
µA
A
A
6.4
Pull-down current
V
INH = VVCC
IPD
7
Serial Interface - Logic Inputs DI, CLK, CS
Input voltage low-level
threshold
0.3 ×
VVCC
7.1
7.2
7.3
7.4
24-26
24-26
24-26
VIL
VIH
∆VI
V
V
A
A
A
Input voltage high-level
threshold
0.7 ×
VVCC
Hysteresis of input
voltage
50
500
mV
Pull-down current pin
VDI, VCLK = VVCC
DI, CLK
25, 26
24
IPDSI
IPUSI
2
50
–2
µA
µA
A
A
7.5
8
Pull-up current pin CS
V
CS= 0V
–50
Serial Interface - Logic Output DO
Output voltage low level IOL = 3 mA
Output voltage high
8.1
18
18
VDOL
VDOH
0.5
V
V
A
A
VVCC
–
8.2
8.3
IOL = –2 mA
level
0.7V
Leakage current
(tri-state)
VCS = VVCC,
0V < VDO < VVCC
18
IDO
–10
10
µA
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
10
T6816
4595E–BCD–09/05
T6816
9. Serial Interface - Timing
Parameters
Test Conditions
Timing Chart No.
Symbol
tENDO
tDISDO
tDOf
Min.
Typ.
Max.
200
200
100
100
200
Unit
ns
DO enable after CS falling edge
DO disable after CS rising edge
DO fall time
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
1
2
ns
–
ns
DO rise time
–
tDOr
ns
DO valid time
10
4
tDOVal
tCSSethl
tCSSetlh
ns
CS setup time
225
225
ns
CS setup time
8
ns
Input register bit 14
(SCT) = high
CS high time
CS high time
9
9
tCSh
tCSh
16
2
ms
ms
Input register bit 14
(SCT) = low
CLK high time
CLK low time
CLK period time
CLK setup time
CLK setup time
DI setup time
DI hold time
5
6
tCLKh
tCLKl
225
225
500
225
225
40
ns
ns
ns
ns
ns
ns
ns
–
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
11
4595E–BCD–09/05
Figure 9-1. Serial Interface Timing with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCC
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
12
T6816
4595E–BCD–09/05
T6816
10. Application
Figure 10-1. Application Circuit
VCC
U5021M
Enable
WATCHDOG
HS1
HS2
HS3
HS4
HS5
HS6
15
13
12
3
2
28
VS
BYT41D
VBatt
24V
5
10
6
VS
VS
Fault
Fault
Fault
Fault
Fault
Fault
Detect
Detect
Detect
Detect
Detect
Detect
+
26
25
DI
GND
GND
GND
GND
GND
GND
GND
GND
VCC
Osc
7
S
C
T
O
L
H
S
6
L
S
6
H
S
5
L
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
CLK
S
I
S
5
R
R
VS
D
8
UV -
Control
logic
24
Input Register
Output Register
CS
INH
protection
9
Thermal
17
18
L
S
6
P
S
F
S
C
D
H
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
H
S
2
L
H
S
1
L
T
P
I
protection
20
21
22
23
19
N
H
S
S
S
3
2
1
Power-on
Reset
DO
VCC
Fault
Fault
Detect
Fault
Fault
Fault
Detect
Fault
Detect
Detect
Detect
Detect
VCC
5 V
VCC
VCC
+
VCC
16
LS1
14
LS2
11
LS3
4
1
27
LS6
LS4
LS5
VS
VS
10.1 Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec-
trolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IHSX (see: Absolute Maximum Ratings).
Recommended value for capacitors at VCC
:
electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as
possible to GND pins.
13
4595E–BCD–09/05
11. Ordering Information
Extended Type Number
Package
Remarks
T6816-TIQY
SO28
Power package, taped and reeled, Pb-free
12. Package Information
9.15
8.65
Package SO28
Dimensions in mm
18.05
17.80
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
16.51
28
15
technical drawings
according to DIN
specifications
1
14
14
T6816
4595E–BCD–09/05
T6816
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Pb-free logo on page 1 added
4595E-BCD-09/05
• Section 1 “Description” on page 1 changed
• Ordering Information on page 14 changed
• Put datasheet in a new template
4595D-BCD-05/05
4595C-BCD-04/04
• Table “Electrical Characteristics” rows 5.15 and 5.16 changed
• Put datasheet in a new template
• Table “Absolute Maximum Ratings” on page 7 changed
• Table “Electrical Characteristics” on page 10 changed
15
4595E–BCD–09/05
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