T6817-FP [TEMIC]
Peripheral Driver, 6 Driver, BCDMOS, PDSO20,;
| 型号： | T6817-FP |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Peripheral Driver, 6 Driver, BCDMOS, PDSO20, 驱动 CD 光电二极管 驱动器 |
| 文件： | 总14页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T6817
Dual Triple DMOS Output Driver with Serial Input Control
Description
The T6817 is a fully protected driver interface designed Protection is guaranteed in terms of short-circuit condi-
in 0.8-µm BCDMOS technology. It is used to control up tions, overtemperature, under- and overvoltage. Various
to 6 different loads by a microcontroller in automotive diagnosis functions and a very low quiescent current in
and industrial applications.
standby mode open a wide range of applications. Auto-
motive qualification referring to conducted interferences,
EMC protection and 2 kV ESD protection gives added
value and enhanced quality for the exacting requirements
of automotive applications.
Each of the 3 high-side and 3 Low-side drivers is capable
to drive currents up to 600 mA. The drivers are freely con-
figurable and can be controlled separately from a standard
serial data interface. Therefore, all kinds of loads such as
bulbs, resistors, capacitors and inductors can be com-
bined. The IC design especially supports the applications
of H-bridges to drive DC motors.
FD eTahtrueerehisgh-side and three low-side drivers
D Outputs short-circuit protected
D Outputs freely configurable as switch, half bridge or
D Overtemperature prewarning and protection
D Undervoltage and overvoltage protection
H-bridge
D Capable to switch all kinds of loads such as DC
D Various diagnosis functions such as shorted output,
motors, bulbs, resistors, capacitors and inductors
open load, overtemperature and power supply fail
D 0.6 A continuous current per switch
D Serial data interface
D Daisy chaining possible
D Loss of ground protection
D SSO20 package
D Low-side: R
< 1.5 Ω vs. total temperature range
< 2.0 Ω vs. total temperature range
DSon
D High-side: R
DSon
D Very low quiescent current Is < 20 µA in standby
mode
Ordering Information
Extended Type Number
Package
Remarks
T6817-FP
SSO20 Power package
Rev. A2, 10-Jul-01
1 (14)
Preliminary Information
T6817
Block Diagram
HS3
HS2
HS1
12
14
16
Osc
Vs
Vs
Fault
Detect
Fault
Detect
Fault
Detect
6
7
DI
VS
2
4
OV
–
S
C
T
O
H
S
3
L
S
3
H
S
2
L
S
2
H
L
S
1
S
protection
n. n. n. n. n. n.
CLK
L
S
R
R
S
I
u. u. u. u. u.
u.
D
1
Vcc
VS
Control
logic
Vcc
Input Register
Output Register
19
CS
Serial interface
3
5
–
UV
protection
INH
n. n. n. n. n. n.
P
S
F
I
N
H
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
T
P
u. u. u. u. u. u.
S
GND
GND
GND
1
1
P ower-on
Reset
DO
10
18
Vcc
11
13
20
Fault
Detect
Fault
Detect
Fault
Detect
Thermal
protection
GND
GND
8
15
17
LS3
LS2
LS1
Figure 1. Block diagram
2 (14)
Rev. A2, 10-Jul-01
Preliminary Information
T6817
Pin Description
GND VCC DO LS1 HS1 LS2 HS2 GND HS3 GND
16
20
19
18
15
14
13
12
11
17
Leadframe
T6817
2
1
4
6
7
9
3
5
8
10
GND
CLK INH VS VS LS3 n.c. GND
Figure 2. Pinning
DI
CS
Pin Description
Pin
Symbol
GND
DI
Function
1
Ground; reference potential; internal connection to Pin 10, 11, 13 and 20; cooling tab
2
Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the
control device, DI expects a 16-bit control word with LSB being transferred first
3
4
5
CS
Chip-select input; 5-V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
CLK
INH
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
Inhibit input; 5-V logic input with internal pull-down; low = standby,
high = normal operating
6, 7
8
VS
Power supply output stages HS1, HS2 and HS3
LS3
Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
9
n.c.
GND
GND
HS3
Not connected
10
11
12
Ground, see Pin 1
Ground, see Pin 1
High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
13
14
15
16
17
18
GND
HS2
LS2
HS1
LS1
DO
Ground, see Pin 1
High-side driver output 2; see Pin 12
Low-side driver output 2; see Pin 8
High-side driver output 1; see Pin 12
Low-side driver output 1; see Pin 8
Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit sta-
tus information to the mC (LSB is transferred first); output will remain tristated unless device is selected by
CS = low, therefore, several ICs can operate on one data output line only.
19
20
VCC
GND
Logic supply voltage (5 V)
Ground, see Pin 1
Rev. A2, 10-Jul-01
3 (14)
Preliminary Information
T6817
Functional Description
Serial Interface
CS
DI
CLK
DO
SRR LS1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
n.u.
n.u.
n.u.
n.u.
10
n.u.
11
n.u.
12
OLD SCT
13 14
SI
15
0
1
7
8
9
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 n.u.
n.u.
n.u.
n.u.
n.u.
n.u. SCD
INH PSF
Figure 3. Data transfer
Data transfer starts with the falling edge of the CS signal. When CS is high, Pin DO is in tristate condition. This
Data must appear at DI synchronized to CLK and are output is enabled on the falling edge of CS. Output data
accepted on the falling edge of the CLK signal. LSB will change their state with the rising edge of CLK and
(bit 0, SRR) has to be transferred first. Execution of new stay stable until the next rising edge of CLK appears. LSB
input data is enabled on the rising edge of the CS signal. (bit 0, TP) is transferred first.
Input Data Protocol
Bit
Input Register
Function
0
SRR
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the
output data register are set to low)
1
2
LS1
HS1
LS2
HS2
LS3
HS3
n.u.
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Not used
8
n.u.
Not used
9
n.u.
Not used
10
11
12
13
14
n.u.
Not used
n.u.
Not used
n.u.
Not used
OLD
SCT
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown
delay high / low = 100 ms / 12.5 ms, overvoltage shutdown delay high / low = 14 ms / 3.5 ms
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digitalpart is still powered)
After power-on reset, the input register has the following status:
4 (14)
Rev. A2, 10-Jul-01
Preliminary Information
T6817
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(SI)
(SCT) (OLD)
(HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
H
H
H
n.u. n.u. n.u. n.u. n.u. n.u.
L
L
L
L
L
L
L
Output Data Protocol
Bit Output (Status) Register
Function
0
1
TP
Temperature prewarning: high = warning (overtemperature shut down see remark below)
Normal operation: high = output is on, low = output is off
Status LS1
Open-load detection: high = open load, low = no open load (correct load condition is detected
if the corresponding output is switched off)
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct load condition is detected
if the corresponding output is switched off)
3
4
Status LS2
Status HS2
Status LS3
Status HS3
n.u.
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
5
6
7
8
n.u.
Not used
9
n.u.
Not used
10
11
12
13
n.u.
Not used
n.u.
Not used
n.u.
Not used
SCD
Short circuit detected: set high, when at least one output is switched off by a short circuit
condition
14
15
INH
PSF
Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit
(Pin 17). High = standby, low = normal operation
Power supply fail: over- or undervoltage at Pin VS detected
Remark: Bit 0 to 15 = high: overtemperature shutdown
function for this output. If bit SI is set to low, the open-
load function is also switched off.
Power Supply Fail
In case of over- or undervoltage at Pin VS, an internal
timer is started. When the over- or undervoltage delay
Overtemperature Protection
time (t
/t
) programmed by the SCT bit is reached,
dOV dUV
If the junction temperature exceeds the thermal
the power supply fail bit (PSF) in the output register is set
and all outputs are disabled. When normal voltage is pres-
ent again the outputs are enabled immediately. The PSF
bit remains high until it is reset by the SRR bit in the input
register.
prewarning threshold,
prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning
T
,
the temperature
jPW set
threshold, T , the bit TP is reset. The TP bit can be
jPW reset
read without transferring a complete 16-bit data word:
with CS = high to low, the state of TP appears at Pin DO.
After the mC has read this information, CS is set high and
the data transfer is interrupted without affecting the state
of input and output registers.
Open-Load Detection
If the open-load detection bit (OLD) is set to low, a
pull-up current for each high-side switch and a pull-down
current for each low-side switch is turned on (open-load If the junction temperature exceeds the thermal shutdown
detection current I , I ). If V –V or threshold, T , the outputs are disabled and all bits
HS1–3
LS1–3
VS
HS1–3
j switch off
V
LS1–3
is lower than the open-load detection threshold in the output register are set high. The outputs can be
(open-load condition), the corresponding bit of the output enabled again when the temperature falls below the
in the output register is set to high. Switching on an output thermal shutdown threshold, T , and when a high
j switch on
stage with OLD bit set to low disables the open-load has been written to the SRR bit in the input register.
Rev. A2, 10-Jul-01 5 (14)
Preliminary Information
T6817
Thermal prewarning and shutdown threshold have shorted output is disabled immediately and SCD bit is set.
hysteresis.
By writing a high to the SRR bit in the input register, the
SCD bit is reset and the disabled outputs are enabled.
Short-Circuit Protection
Inhibit
The output currents are limited by a current regulator.
Current limitation takes place when the overcurrent
limitation and shutdown threshold (I
, I
) are There are two ways to inhibit the T6817:
HS1–3 LS1–3
reached. Simultaneously, an internal timer is started. The 1.
shorted output is disabled when during a permanent short 2.
Set bit SI in the input register to zero
Switch Pin 5 (INH) to 0 V
the delay time (t ) programmed by the short-circuit In both cases, all output stages are turned off but the serial
dSd
timer bit (SCT) is reached. Additionally, the short-circuit interface stays active. The output stages can be activated
detection bit (SCD) is set. If the temperature prewarning again by bit SI = 1 and by Pin 5 (INH) switched back to
bit TP in the output register is set during a short, the 5 V.
Absolute Maximum Ratings
All values refer to GND pins
Parameters
Pins 6, 7
Symbol
Value
– 0.3 to 40
– 1
Unit
V
Supply voltage
V
VS
V
VS
Supply voltage tt0.5 s; I u–2 A Pins 6, 7
V
S
Supply voltage difference
Supply current
|V
S_Pin6
– V
|
DV
VS
150
mV
A
S_Pin7
Pins 6, 7
Pins 6,7
Pin 19
I
I
1.4
VS
VS
Supply current t < 200 ms
Logic supply voltage
Input voltage
2.6
A
V
VCC
–0.3 to 7
–0.3 to 17
V
Pin 5
V
INH
V
Logic input voltage
Logic output voltage
Input current
Pins 2 to 4
Pin 18
V
V
V
–0.3 to V
+ 0.3
V
DI, CS, CLK
VCC
VCC
V
–0.3 to V
+ 0.3
V
DO
Pins 5, 2 to 4
Pin 18
I
I
I
I
–10 to +10
–10 to +10
mA
mA
INH, DI, CS, CLK
Output current
I
DO
Output current
Pins 8, 12, 14 to 17
I
I
I
Internal limited, see
output specification
LS1 to LS3
I
HS1 to HS3
Reverse conducting current
Pins 12, 14, 16,
I
I
17
A
HS1 to HS3
(t
= 150 ms)
towards Pins 6, 7
Pulse
Junction temperature range
Storage temperature range
T
–40 to 150
–55 to 150
°C
°C
j
T
STG
Operating Range
All values refer to GND pins
Parameters
Test Conditions /
Pins
Symbol
Min. Typ. Max.
Unit
1)
2)
Supply voltage
Pins 6, 7
Pin 19
V
V
40
5.5
V
V
VS
UV
Logic supply voltage
Logic input voltage
V
VCC
4.5
5
Pin 2 to 4 and 5
Pin 4
V
V
V
V
–0.3
V
V
INH, DI, CLK, CS
VCC
Serial interface clock frequency
Junction temperature range
f
2
MHz
°C
CLK
T
–40
150
j
1)
2)
Threshold for undervoltage detection
Outputs disabled for V > V (threshold for overvoltage detection)
VS OV
6 (14)
Rev. A2, 10-Jul-01
Preliminary Information
T6817
Thermal Resistance
All values refer to GND pins
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Junction – pin
Measured to GND
R
25
K/W
thJP
Pins 1, 10, 11, 13 and 20
Junction ambient
R
65
K/W
thJA
Noise and Surge Immunity
Parameters
Conducted interferences
Interference Suppression
ESD (Human Body Model)
Test Conditions
Value
1)
ISO 7637-1
Level 4
VDE 0879 Part 2
Level 5
2 kV
ESD STM 5.1 – 1998
ESD (Machine Model)
1)
JEDEC EIA / JESD 22 – A115-A
150 V
Test pulse 5: V
= 40 V
Smax
Electrical Characteristics
7.5 V < V < V ; 4.5 V < V
< 5.5 V; INH = High; –40°C < T < 150°C; unless otherwise specified,
VS
OV
VCC
j
all values refer to GND pins.
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Current Consumption
Quiescent current (VS)
V
t16 V, INH or
I
40
20
mA
mA
mA
VS
VS
bit SI = low
Pins 6, 7
Quiescent current (VCC)
Supply current (VS)
4.5 VtV
t5.5 V,
I
VCC
VCC
INH or bit SI = low Pin 19
V
VS
t16 V normal operat-
I
0.8
1.2
VS
ing, all output stages off,
Pins 6, 7
Supply current (VS)
Supply current (VCC)
V
< 16 V normal operat-
I
10
mA
VS
VS
ing, all output stages on, no
load
Pins 6, 7
4.5 V < V
< 5.5 V,
I
150
mA
VCC
VCC
normal operating
Pin 19
Internal Oscillator Frequency
Frequency (time-base for delay
timers)
f
19
45
kHz
OSC
Over- and Undervoltage Detection, Power-On Reset
Power-on reset threshold
Pin 19
V
3.4
30
3.9
95
4.4
160
7.0
V
ms
V
VCC
Power-on reset delay time
After switching on V
t
VCC
dPor
Undervoltage detection thresh-
old
Pins 6, 7
V
5.5
UV
Rev. A2, 10-Jul-01
7 (14)
Preliminary Information
T6817
Electrical Characteristics (continued)
7.5 V < V < V ; 4.5 V < V
< 5.5 V; INH = High; –40°C < T < 150°C; unless otherwise specified,
VS
OV
VCC
j
all values refer to GND pins.
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Undervoltage detection hyste-
resis
Pins 6, 7
DV
0.4
V
UV
Undervoltage detection delay
t
7
21
ms
V
dUV
Overvoltage detection threshold
Overvoltage detection hysteresis
Overvoltage detection delay
Pins 6, 7
Pins 6, 7
V
18.0
22.5
OV
DV
1
V
OV
Input register
bit 14 (SCT) = high
bit 14 (SCT) = low
t
t
7
1.75
21
5.25
ms
ms
dOV
dOV
Thermal Prewarning and Shutdown
Thermal prewarning
T
125
105
3
145
125
20
165
145
°C
°C
K
jPWset
Thermal prewarning
TjPWreset
DT
Thermal prewarning hysteresis
Thermal shutdown
jPW
T
150
130
3
170
150
20
190
170
°C
°C
K
j switch off
Thermal shutdown
T
j switch on
Thermal shutdown hysteresis
DT
j switch
T
j switch off/
Ratio thermal shutdown / ther-
mal prewarning
1.05
1.17
T
jPW set
T
T
j switch on/
Ratio thermal shutdown / ther-
mal prewarning
1.05
1.2
jPW reset
Output Specification (LS1 – LS3, HS1 – HS3)
7.5 V < V < V
VS OV
On resistance
I
I
I
= 600 mA
Out
Pins 8, 15 and 17
R
1.5
W
DS OnL
On resistance
= –600 mA
Out
Pins 12, 14 and 16
= 50 mA
R
2.0
60
W
DS OnH
Output clamping voltage
Output leakage current
V
40
V
LS1–3
LS1–3
LS1-3
HS1-3
Pins 8, 15 and 17
V
= 40 V
LS1-3
all output stages off
Pins 8, 15 and 17
I
10
mA
mA
Output leakage current
V
HS1–3
= 0 V
all output stages off
Pins 12, 14 and 16
I
–10
Inductive shutdown energy
Pins 8, 12, 14 to 17
W
outx
15
mJ
Output voltage edge steepness
Pins 8, 12, 14 to 17 dV
dV
/dt
/dt
50
200
950
400
mV/ms
LS1-3
HS1-3
Overcurrent limitation and shut-
down threshold
Pins 8, 15 and 17
I
650
1250
mA
LS1-3
8 (14)
Rev. A2, 10-Jul-01
Preliminary Information
T6817
Electrical Characteristics (continued)
7.5 V < V < V ; 4.5 V < V
< 5.5 V; INH = High; –40°C < T < 150°C; unless otherwise specified,
VS
OV
VCC
j
all values refer to GND pins.
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Overcurrent limitation and shut-
down threshold
Pins 12, 14 and 16
I
–1250
–950
–650
mA
HS1-3
Overcurrent shutdown delay
time
Input register
bit 14 (SCT) = high
bit 14 (SCT) = low
t
t
70
8.75
100
12.5
140
17.5
ms
ms
dSd
dSd
Open load detection current
Open load detection current
Input register bit 13 (OLD)
=low, output off
I
60
200
mA
LS1-3
Pins 8, 15 and 17
Input register bit 13 (OLD)
=low, output off
I
–150
–30
mA
HS1-3
Pins 12, 14 and 16
Open load detection current ra-
tio
I
I
1.2
0.6
LS1-3 /
HS1-3
Open load detection threshold
Input register bit 13 (OLD)
=low, output off
V
4
4
V
V
LS1-3
Pins 8, 15 and 17
Open load detection threshold
Input register bit 13 (OLD)
=low, output off
V
0.6
VS-
V
HS1-3
Pins 12, 14 and 16
1)
Output Switch on delay
R
R
= 1 kW
= 1 kW
t
0.5
1
ms
ms
Load
Load
don
1)
Output Switch off delay
t
doff
Inhibit Input
Input voltage low level thresh-
old
Pin 5
Pin 5
V
0.3
V
V
IL
V
VCC
Input voltage high level thresh-
old
V
IH
0.7
V
VCC
Hysteresis of input voltage
Pull-down current
Pin 5
Pin 5
∆V
100
10
700
80
mV
I
V
INH
= V
I
PD
mA
VCC
Serial Interface – Logic Inputs DI, CLK, CS
Input voltage low level thresh-
old
Pins 2–4
V
V
0.3
V
V
IL
V
VCC
Input voltage high level thresh-
old
Pins 2–4
Pins 2–4
0.7
IH
V
VCC
Hysteresis of input voltage
∆V
50
2
500
50
mV
I
Pull-down current Pin DI, CLK V , V
= V
I
mA
DI
CLK
VCC
PDSI
Pins 2 and 4
Pull-up current Pin CS
V = 0 V
CS
Pin 3
I
–50
–2
mA
PUSI
1)
Delay time between rising edge of CS after data transmision and switch on/off output stages to 90% of final level
Rev. A2, 10-Jul-01
9 (14)
Preliminary Information
T6817
Electrical Characteristics (continued)
7.5 V < V < V ; 4.5 V < V
< 5.5 V; INH = High; –40°C < T < 150°C; unless otherwise specified,
VS
OV
VCC
j
all values refer to GND pins.
Parameter
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
0.5
Unit
Serial Interface – Logic Output DO
Output voltage low level
Output voltage high level
I
I
= 3 mA
Pin 18
Pin 18
V
DOL
V
V
OL
OL
V
–1V
VCC
= –2 mA
V
DOH
Leakage current
(tristate)
VCS = VVCC, 0 VtVDOtVVCC
I
–10
10
mA
DO
Pin 18
Parameters
Test
Timing
Symbol Min.
Typ.
Max.
Unit
Conditions
Chart No.
Serial Interface – timing
DO enable after CS falling edge
DO disable after CS rising edge
DO fall time
C
C
C
C
C
= 100 pF
= 100 pF
= 100 pF
= 100 pF
= 100 pF
1
2
t
200
200
100
100
200
ns
ns
ns
ns
ns
ns
ns
ms
DO
DO
DO
DO
DO
ENDO
t
DISDO
–
t
t
DOf
DOr
DO rise time
–
DO valid time
10
4
t
DOVal
CS setup time
t
t
225
225
140
CSSethl
CSSetlh
CS setup time
8
CS high time
Input register
Bit 14 (SCT) =
high
9
t
CSh
CS high time
Input register
Bit 14 (SCT) =
low
9
t
17.5
ms
CSh
CLK high time
CLK low time
CLK period time
CLK setup time
CLK setup time
DI setup time
5
6
t
t
225
225
500
225
225
40
ns
ns
ns
ns
ns
ns
ns
CLKh
t
CLKl
–
CLKp
7
t
t
CLKSethl
CLKSetlh
3
11
12
t
DIset
DI hold time
t
40
DIHold
10 (14)
Rev. A2, 10-Jul-01
Preliminary Information
T6817
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × V , Low level = 0.3 × V
CC
CC
Output DO: High level = 0.8 × V , Low level = 0.2 × V
CC
CC
Figure 4. Serial interface timing diagram with chart numbers
Rev. A2, 10-Jul-01
11 (14)
Preliminary Information
T6817
Application Circuit
Vcc
U5021M
WATCHDOG
Enable
HS3
HS2
HS1
12
14
16
Vs
BYT41D
V
Osc
Vs
Vs
Fault
Fault
Fault
Detect
Detect
Detect
6
7
BATT
+
13V
DI
VS
2
4
–
OV
S
O
L
D
H
3
L
S
3
H
S
2
L
S
2
H
1
L
S
1
S
R
protection
CLK
n. n. n. n. n. n.
S
C
T
S
R
S
I
u. u. u. u. u. u.
Vcc
Vcc
Control
logic
VS
Input Register
Output Register
Vcc
CS
19
Serial interface
mC
3
5
–
Vcc
5V
UV
protection
+
n. n. n. n. n. n.
P
S
F
I
S
H
S
3
L
S
3
H
S
2
L
S
2
H L T
INH
u. u. u. u. u. u.
P
S S
N
H
C
D
GND
GND
1
1
1
P ower-on
Reset
DO
10
18
Vcc
GND
11
Fault
Fault
Fault
Detect
Detect
Detect
Thermal
protection
GND
13
GND
20
8
15
17
LS3
LS2
LS1
Vcc
Figure 5. Application circuit
Application Notes
It is strongly recommended to connect the blocking Recommended value for capacitors at V
:
CC
capacitors at V and V as close as possible to the power electrolythic capacitor C > 10 µF in parallel with a
CC
S
supply and GND pins.
ceramic capacitor C = 100 nF.
Recommended value for capacitors at V :
S
To reduce thermal resistance it is recommended to place
cooling areas on the PCB as close as possible to GND
pins.
electrolythic capacitor C > 22 µF in parallel with a
ceramic capacitor C = 100 nF. Value for electrolytic
capacitor depends on external loads, conducted interfer-
ences and reverse conducting current I
Maximum Ratings).
(see: Absolut
HSX
12 (14)
Rev. A2, 10-Jul-01
Preliminary Information
T6817
Package Information
Package SSO20
Dimensions in mm
5.7
5.3
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
1
10
Rev. A2, 10-Jul-01
13 (14)
Preliminary Information
T6817
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
14 (14)
Rev. A2, 10-Jul-01
Preliminary Information
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