T6817-TKS [ATMEL]
Dual Triple DMOS Output Driver with Serial Input Control; 带串行输入控制三双DMOS输出驱动器
| 型号： | T6817-TKS |
| 厂家： | 
ATMEL |
| 描述： | Dual Triple DMOS Output Driver with Serial Input Control |
| 文件： | 总15页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Three High-side and Three Low-side Drivers
• Outputs Freely Configurable as Switch, Half Bridge or H-bridge
• Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors,
Capacitors and Inductors
• 0.6 A Continuous Current Per Switch
• Low-side: RDSon < 1.5 ꢀ Versus Total Temperature Range
• High-side: RDSon < 2.0 ꢀ Versus Total Temperature Range
• Very Low Quiescent Current IS < 20 µA in Standby Mode
• Outputs Short-circuit Protected
• Overtemperature Prewarning and Protection
• Undervoltage and Overvoltage Protection
• Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
• Serial Data Interface
• Daisy Chaining Possible
Dual Triple
DMOS Output
Driver with
Serial Input
Control
• SSO20 Package
Description
T6817
The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technol-
ogy. It can be used to control up to 6 different loads by a microcontroller in automotive
and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design is especially supportive of
H-bridges applications to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, under-
and overvoltage. Various diagnosis functions and a very low quiescent current in
standby mode open a wide range of applications. Meeting automotive qualifications in
the area of conducted interferences, EMC protection and 2 kV ESD protection provide
added value and enhanced quality for the exacting requirements of automotive
applications.
Rev. 4670A–BCD–02/03
Figure 1. Block Diagram
HS3
HS2
HS1
12
14
16
Osc
VS
VS
Fault
detect
Fault
detect
Fault
detect
6
7
DI
2
VS
OV -
protection
S
C
T
O
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
CLK
L
n.
n. n. n. n. n.
S
I
4
u. u. u. u. u. u.
D
VS
UV
Vcc
VCC
Input register
Control
logic
CS
19
Serial interface
3
5
protection
-
Output register
INH
n. n. n. n. n. n.
u. u. u. u. u. u.
P
S
F
I
N
H
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
GND
GND
Power-on
reset
1
DO
Vcc
10
18
GND
GND
GND
11
13
20
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
8
15
17
LS3
LS2
LS1
2
T6817
4670A–BCD–02/03
T6817
Pin Configuration
Figure 2. Pinning SSO20
GND
DI
1
2
3
4
5
6
7
8
9
20 GND
19 VCC
18 DO
CS
CLK
INH
VS
17 LS1
16 HS1
15 LS2
14 HS2
13 GND
12 HS3
11 GND
VS
LS3
n.c.
GND 10
Pin Description
Pin
Symbol
Function
Ground; reference potential; internal connection to Pin 10, 11, 13 and 20; cooling tab
1
GND
Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control
device, DI expects a 16-bit control word with LSB being transferred first
2
3
4
DI
CS
Chip-select input; 5-V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
CLK
Inhibit input; 5-V logic input with internal pull-down; low = standby,
high = normal operating
5
6, 7
8
INH
VS
Power supply output stages HS1, HS2 and HS3
Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
LS3
9
n.c.
Not connected
10
11
GND
GND
Ground (see Pin 1) be consistant
Ground (see Pin 1)
High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
12
HS3
13
14
15
16
17
GND
HS2
LS2
HS1
LS1
Ground (see Pin 1)
High-side driver output 2 (see Pin 12) be consistant
Low-side driver output 2 (see Pin 8)
High-side driver output 1 (see Pin 12)
Low-side driver output 1 (see Pin 8)
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
18
DO
19
20
VCC
GND
Logic supply voltage (5 V)
Ground (see Pin 1)
3
4670A–BCD–02/03
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI
synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, Pin DO is in tri-state condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data Transfer Input Data Protocol
CS
DI
CLK
DO
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
HS3
6
n.u.
n.u.
n.u.
n.u.
10
n.u.
11
n.u.
12
OLD
13
SCT
14
SI
15
5
7
8
9
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
SCD
INH
PSF
Table 1. Input Data Protocol
Bit
Input Register
Function
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
OLD
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Not used
8
Not used
9
Not used
10
11
12
13
Not used
Not used
Not used
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown
(short circuit shutdown delay high/low = 100 ms/12.5 ms,
overvoltage shutdown delay high/low = 14 ms/3.5 ms
14
15
SCT
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital
part is still powered)
4
T6817
4670A–BCD–02/03
T6817
Table 2. Output Data Protocol
Output (Status)
Bit
Register
Function
Temperature prewarning: high = warning (overtemperature shut-
down, see remark below)
0
TP
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)
1
2
Status LS1
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)
3
4
Status LS2
Status HS2
Status LS3
Status HS3
n.u.
Description, see LS1
Description, see HS1
Description, see LS1
Description, see HS1
Not used
5
6
7
8
n.u.
Not used
9
n.u.
Not used
10
11
12
n.u.
Not used
n.u.
Not used
n.u.
Not used
Short circuit detected: set high, when at least one output is
switched off by a short circuit condition
13
SCD
Inhibit: this bit is controlled by software (bit SI in input register)
and hardware inhibit (Pin 17). High = standby, low = normal
operation
14
INH
15
PSF
Power supply fail: over- or undervoltage at Pin VS detected
Note:
Bit 0 to 15 = high: overtemperature shutdown
After power-on reset, the input register has the following status:
Bit 15
(SI)
Bit 14
(SCT)
Bit 13
(OLD)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
n.u.
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
H
H
H
n.u.
n.u.
n.u.
n.u.
n.u.
L
L
L
L
L
L
L
Power-supply Fail
In case of over- or undervoltage at Pin VS, an internal timer is started. When the under-
voltage delay time (tdUV, tdOV) programmed by the SCT bit is reached, the power supply
fail bit (PSF) in the output register is set and all outputs are disabled. When normal volt-
age is present again, the outputs are enabled immediately. The PSF bit remains high
until it is reset by the SRR bit in the input register.
5
4670A–BCD–02/03
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side
switch and a pull-down current for each low-side switch is turned on (open-load detec-
tion current IHS1-3, ILS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection
threshold (open-load condition), the corresponding bit of the output in the output register
is set to high. Switching on an output stage with the OLD bit set to low disables the
open-load function for this output. If bit SI is set to low, the open-load function is also
switched off.
Overtemperature
Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the tem-
perature prewarning bit (TP) in the output register is set. When the temperature falls
below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be
read without transferring a complete 16-bit data word: with CS = high to low, the state of
TP appears at Pin DO. After the microcontroller has read this information, CS is set high
and the data transfer is interrupted without affecting the state of the input and output
registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the out-
puts are disabled and all bits in the output register are set high. The outputs can be
enabled again when the temperature falls below the thermal shutdown threshold,
Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal
prewarning and shutdown threshold have hysteresis.
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place
when the overcurrent limitation and shutdown threshold (IHS1-3, ILS1-3) are reached.
Simultaneously, an internal timer is started. The shorted output is disabled when during
a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT)
is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature
prewarning bit TP in the output register is set during a short, the shorted output is dis-
abled immediately and SCD bit is set. By writing a high to the SRR bit in the input
register, the SCD bit is reset and the disabled outputs are enabled.
Inhibit
There are two ways to inhibit the T6817:
1. Set bit SI in the input register to zero
2. Switch Pin 5 (INH) to 0 V
In both cases, all output stages are turned off but the serial interface stays active. The
output stages can be activated again by bit SI = 1 and by Pin 5 (INH) switched back to
5 V.
6
T6817
4670A–BCD–02/03
T6817
Absolute Maximum Ratings
All values refer to GND pins
Parameter
Pin
6, 7
6, 7
Symbol
Value
- 0.3 to +40
- 1
Unit
V
Supply voltage
VVS
Supply voltage t < 0.5 s; IS > -2 A
VVS
V
Supply voltage difference |VS_Pin6 - VS_Pin7
|
ꢁVVS
150
mV
A
Supply current
6, 7
6, 7
19
IVS
IVS
1.4
Supply current t < 200 ms
Logic supply voltage
Input voltage
2.6
A
VVCC
-0.3 to 7
-0.3 to 17
-0.3 to VVCC +0.3
-0.3 to VVCC +0.3
-10 to +10
-10 to +10
V
5
VINH
V
Logic input voltage
Logic output voltage
Input current
2 to 4
18
VDI, VCLK, VCS
VDO
IINH, IDI, ICLK, ICS
IDO
ILS1 to ILS3
IHS1 to IHS3
V
V
5, 2 to 4
18
mA
mA
Output current
Output current
Internal limited, see
output specification
8, 12, 14 to 17
Reverse conducting current (tPulse = 150 µs)
12, 14, 16
towards 6, 7
I
HS1 to IHS3
17
A
Junction temperature range
Storage temperature range
Tj
-40 to +150
-55 to +150
LC
LC
TSTG
Thermal Resistance
All values refer to GND pins
Parameter
Test Conditions
Measured to GND
Symbol
Value
Unit
Junction - pin
RthJP
25
K/W
Pins 1, 10, 11, 13 and 20
Junction ambient
RthJA
65
K/W
Operating Range
All values refer to GND pins
Parameter
Test Conditions
Pins 6, 7
Symbol
VVS
Min.
Typ.
Max.
40 (2)
5.5
Unit
V
(1)
Supply voltage
VUV
4.5
Logic supply voltage
Logic input voltage
Pin 19
VVCC
5
V
Pin 2 to 4 and 5
Pin 4
VINH, VDI, VCLK, VCS
fCLK
-0.3
VVCC
2
V
Serial interface clock
frequency
MHz
Junction temperature range
Tj
-40
150
LC
Notes: 1. Threshold for undervoltage detection
2. Outputs disabled for VVS > VOV (threshold for overvoltage detection)
7
4670A–BCD–02/03
Noise and Surge Immunity
Parameter
Test Conditions
Value
Level 4 1)
Level 5
2 kV
Conducted interferences
Interference Suppression
ESD (Human Body Model)
ESD (Machine Model)
ISO 7637–1
VDE 0879 Part 2
MIL-STM 5.1 – 1998
JEDEC EIA / JESD 22 – A115-A
150 V
Note:
1. Test pulse 5: VSmax = 40 V
Electrical Characteristics
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current Consumption
1.1
Quiescent current
(VS)
VVS ꢂꢃ16 V, INH or
bit SI = lo
6, 7
19
IVS
40
20
ꢄA
ꢄA
A
A
1.2
1.3
Quiescent current
(VCC)
4.5 V < VVCC < 5.5 V,
INH or bit SI = low
IVCC
VVS < 16 V normal
operating, all output
stages off,
Supply current (VS)
6, 7
IVS
0.8
1.2
mA
A
1.4
1.5
VVS < 16 V normal
operating, all output
stages on, no load
Supply current (VS)
Supply current (VCC)
6, 7
19
IVS
10
mA
A
A
4.5 V < VVCC < 5.5 V,
normal operating Pin
IVCC
150
ꢄA
2
Internal Oscillator Frequency
2.1
Frequency (time base
for delay timers)
A
fOSC
19
45
kHz
3
Over- and Undervoltage Detection, Power-on Reset
3.1
Power-on reset
threshold
19
A
A
A
A
A
A
A
VVCC
tdPor
VUV
3.4
30
3.9
95
4.4
160
7.0
V
ꢄs
V
3.2
3.3
3.4
3.6
3.7
38
Power-on reset delay
time
After switching on
VVCC
19
Undervoltage
detection threshold
6, 7
6, 7
6, 7
6, 7
6, 7
5.5
Undervoltage
detection hysteresis
ꢁVUV
tdUV
0.4
V
Undervoltage
detection delay
7
21
ms
V
Overvoltagedetection
threshold
VOV
18.0
22.5
Overvoltagedetection
hysteresis
ꢁVOV
1
V
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
8
T6817
4670A–BCD–02/03
T6817
Electrical Characteristics (Continued)
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
3.9
Input register
A
Undervoltage
detection delay
bit 14 (SCT) = high
bit 14 (SCT) = low
tdOV
tdOV
7
21
ms
ms
1.75
5.25
4
Thermal Prewarning and Shutdown
Thermal prewarning
4.1
4.2
4.3
TjPWset
125
105
145
125
165
145
LC
LC
A
A
Thermal prewarning
TjPWreset
Thermal prewarning
hysteresis
ꢁTjPW
3
20
K
A
4.4
4.5
4.6
Thermal shutdown
Thermal shutdown
Tj switch off
Tj switch on
150
130
170
150
190
170
LC
LC
A
A
Thermal shutdown
hysteresis
ꢁTj switch off
3
20
K
A
4.7
4.8
Ratio thermal
shutdown / thermal
prewarning
Tj switch off/
TjPW set
1.05
1.17
A
Ratio thermal
shutdown / thermal
prewarning
Tj switch on/
TjPW reset
1.05
1.2
A
5
Output Specification (LS1 - LS6, HS1 - HS6) 7.5 V < VVS < VOV
5.1
8, 15,
17
A
A
A
A
A
On resistance
On resistance
I
I
Out = 600 mA
Out = -600 mA
RDS OnL
1.5
ꢀ
5.2
5.3
5.4
5.5
12,
14, 16
RDS OnH
VLS1-3
2.0
60
ꢀ
Output clamping
voltage
8, 15,
17
40
V
ILS1-3= 50 mA
LS1–3 = 40 V
Output leakage
current
V
8, 15,
17
all output stages off
ILS1–3
IHS1–3
10
µA
µA
2, 3,
12,
13,
Output leakage
current
VHS1-3 = 0 V
all output stages off
-10
15, 28
5.7
5.8
8, 12,
14 to
17
Woutx
15
mJ
D
Inductive shutdown
energy
8, 12,
14 to
17
dVLS1–3/dt
dVHS1–3/dt
50
200
400
mV/µs
A
A
A
Output voltage edge
steepness
5.9
Overcurrent limitation
and shutdown
threshold
8, 15,
17
ILS1–3
650
950
1250
-650
mA
mA
5.10
Overcurrent limitation
and shutdown
threshold
12,
14, 16
IHS1–3
-1250
-950
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
9
4670A–BCD–02/03
Electrical Characteristics (Continued)
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
5.11
Input register
Overcurrent
shutdown delay time
bit 14 (SCT) = high
bit 14 (SCT) = low
tdSd
tdSd
8
12
16
ms
ms
A
A
1.0
1.5
2.0
5.12
5.13
5.14
Open load detection
current
Input register bit 13
(OLD) =low, output off
8, 15,
17
A
ILS1–3
IHS1–3
60
-150
1.2
200
-30
ꢄA
ꢄA
Open load detection
current
Input register bit 13
(OLD) =low, output off 14, 16
12,
A
A
A
A
A
A
ILS1–3 /
IHS1–3
Open load detection
current ratio
5.15
5.16
5.17
5.18
Open load detection
threshold
Input register bit 13
(OLD) =low, output off
8, 15,
17
VLS1–3
0.6
4
4
V
V
Open load detection
threshold
Input register bit 13
(OLD) =low, output off 14, 16
12,
VVS–
VHS1–3
0.6
Output switch on
delay 1)
RLoad = 1 kꢀ
tdon
tdoff
0.5
1
ms
ms
Output switch off
delay 1)
RLoad = 1 kꢀ
6
Inhibit Input
6.1
Input voltage low level
threshold
5
5
5
0.3 P
VVCC
A
A
A
A
VIL
VIH
V
V
6.2
6.3
Input voltage high
level threshold
0.7 P
VVCC
Hysteresis of input
voltage
ꢁVI
100
10
700
80
mV
6.4
7
Pull-down current
VINH = VVCC
5
IPD
ꢄA
Serial Interface – Logic Inputs DI, CLK, CS
7.1
Input voltage low-
level threshold
0.3 P
VVCC
2-4
2-4
2-4
2, 4
3
VIL
VIH
V
V
A
A
A
A
A
7.2
7.3
7.4
7.5
Input voltage high-
level threshold
0.7 P
VVCC
Hysteresis of input
voltage
ꢁVI
50
2
500
50
mV
ꢄA
ꢄA
Pull-down current Pin
VDI, VCLK = VVCC
DI, CLK
IPDSI
IPUSI
Pull-up current
Pin CS
VCS= 0 V
-50
-2
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
10
T6817
4670A–BCD–02/03
T6817
Electrical Characteristics (Continued)
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
8
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Serial Interface - Logic Output DO
8.1
Output voltage low
level
I
OL = 3 mA
18
18
18
VDOL
VDOH
IDO
0.5
V
V
A
A
A
8.2
8.3
Output voltage high
level
VVCC
1 V
-
IOL = -2 mA
Leakage current
(tri-state)
VCS = VVCC,
0 V < VDO < VVCC
-10
10
ꢄA
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
Serial Interface – Timing
Timing
Parameters
Test Conditions
Chart No.
Symbol
tENDO
tDISDO
tDOf
Min.
Typ.
Max.
200
200
100
100
200
Unit
ns
DO enable after CS falling edge
DO disable after CS rising edge
DO fall time
C
DO = 100 pF
DO = 100 pF
1
2
C
ns
CDO = 100 pF
-
ns
DO rise time
C
DO = 100 pF
DO = 100 pF
-
tDOr
ns
DO valid time
C
10
4
tDOVal
tCSSethl
tCSSetlh
ns
CS setup time
225
225
ns
CS setup time
8
ns
Input register Bit 14
(SCT) = high
CS high time
CS high time
9
9
tCSh
tCSh
140
ms
ms
Input register Bit 14
(SCT) = low
17.5
CLK high time
CLK low time
CLK period time
CLK setup time
CLK setup time
DI setup time
DI hold time
5
6
tCLKh
tCLKl
225
225
500
225
225
40
ns
ns
ns
ns
ns
ns
ns
-
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
11
4670A–BCD–02/03
Figure 4. Serial Interface Timing with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC
Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12
T6817
4670A–BCD–02/03
T6817
Figure 5. Application Circuit
Vcc
Enable
U5021M
Watchdog
M
M
HS3
HS2
HS1
Vs
12
14
16
BYT41D
Osc
Fault
detect
Fault
detect
Fault
detect
VS
VS
6
7
V
Batt
13 V
+
DI
V
S
2
4
OV-
protection
S
O
H
S
3
L
S
3
H
S
2
L
S
2
H
L
S
1
S
R
R
n. n. n. n. n. n.
u. u. u. u. u. u.
CLK
C
T
L
S
S
I
D
1
Vcc
5 V
Vcc
19
V
S
VCC
Input register
Control
logic
UV-
+
CS
Serial interface
protection
3
5
Output register
µC
INH
n. n. n. n. n. n.
P
S
F
I
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
L
T
P
u. u. u. u. u. u.
N
H
S
S
GND
GND
Power-on
reset
1
1
1
DO
Vcc
10
18
GND
GND
GND
11
13
20
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
8
15
17
LS3
LS2
LS1
Application Notes
It is strongly recommended that the blocking capacitors at VCC and VS be connected as
close as possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolythic capacitor C > 22 ꢀF in parallel with a ceramic capacitor C = 100 nF. Value
for electrolytic capacitor depends on external loads, conducted interferences and
reverse conducting current IHSX (see: Absolut Maximum Ratings).
Recommended value for capacitors at VCC
:
Electrolythic capacitor C > 10 ꢀF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended that cooling areas be placed on the
PCB as close as possible to GND pins.
13
4670A–BCD–02/03
Ordering Information
Extended Type Number
Package
SSO20
SSO20
Remarks
T6817-TKS
Power package, tube
Power package, taped and reeled
T6817-TKQ
Package Information
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
1
10
14
T6817
4670A–BCD–02/03
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4670A–BCD–02/03
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