U3600BM-MFN [ATMEL]
RF and Baseband Circuit, Bipolar, PDSO44, SSO-44;
| 型号： | U3600BM-MFN |
| 厂家： | 
ATMEL |
| 描述： | RF and Baseband Circuit, Bipolar, PDSO44, SSO-44 无绳电话集成电路 电信集成电路 电信电路 光电二极管 无绳技术 异步传输模式 ATM |
| 文件： | 总44页 (文件大小：742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
All Functions and Channel Selections are Controlled by Serial Bus
RF Part
•
•
•
•
All Oscillators and PLL Integrated
IF Converter
Single-chip
Cordless
FM Demodulator
RSSI
Telephone IC
Low Frequency Part
•
•
•
•
•
Asymmetrical Input of Microphone Amplifier
Asymmetrical Output of Earpiece Amplifier
Compander
U3600BM
Power Supply Management
Serial Bus
Application
•
•
CT0 Standard
Narrowband Voice and Data Transmitting/Receiving Systems
1. Description
The programmable single-chip multichannel cordless phone IC includes all necessary
low frequency parts such as microphone- and earphone amplifier, compander, power-
supply management as well as all RF parts such as IF converter, FM demodulator,
RSSI, oscillators and PLL. Several gains and mutes in transmit and receive direction
are controlled by the serial bus. The compander can be bypassed.
Rev. 4516D–CT0–10/05
Figure 1-1. Block Diagram
MIX2IN
33
MIX2O
VAF
OSCGND
MIX1O
MIX1IN2
MIX1IN1
XCK
MIX2GND
IFIN1
32
EXIN
29
IFIN2
31
ETC
30
41
40
39
37
36
34
38
35
28
IF
Amp
RSSI
42
Mixer1
Mixer2
RECO
Crystal
Oscillator
Ear
Amp
Expander
GNDLO
RECO2
27
26
MUXDA
D
A
f
LO
Serial
Bus
43
44
Demo-
dulator
f
f
RXO
DAIN
LO2
LO1
Ref3
LO
:K
:N
VCO3
:2
-
+
Bias
Bat low
Detector
f
LO
sin
(3)
Phase
Comparator
25
cos
+
1
1
PCLO
DATRX
-
1.5V
24
MIC
-
Mic
+
MixerT
+45
-45
VRMIC
23
:D2
MICO
COIN
:D3
(1)
:D1
:10
:M
:2
:M12
Ref2
22
f
Compressor
Mod
:M12
f
21
(2)
:2
CTC
20
Phase
Comparator
COUT
f
2
3
4
Ref1
12
RFOGND
RFO
+
Spl
19
Loop
Filter
1.5V
Phase
Comparator
VCO1
9
VCO2
Limiter
LIMIN
Amp
-
RFOVB
10
15
14
13
VSS
16
7
11
18
TXO
5
8
17
6
VDD
AGND
D
C
OPOUT
VBIAS
MODIN
VRF
LFGND
MLF
OPIN
(3): PLL3: Local oscillator (LO) PLL
DACO
(1): PLL1: Modulator PLL
(2): PLL2: Mixer PLL
2
U3600BM
4516D–CT0–10/05
U3600BM
2. Pin Configuration
Figure 2-1. Pinning SSO44
1
2
44
43
42
41
40
39
38
37
36
35
34
33
PCLO
RFOGND
RFO
LO1
LO2
3
GNDLO
MIX1IN2
4
RFOVB
AGND
5
MIX1IN1
MIX1O
OSCGND
XCK
6
VBIAS
7
VRF
MLF
8
LFGND
9
VAF
MODIN
10
MIX2O
MIX2GND
11
VDD
VSS
12
13
14
15
16
17
18
MIX2IN
IFIN1
IFIN2
ETC
32
31
D
C
DACO
30
29
28
27
26
25
OPOUT
OPIN
TXO
EXIN
RECO1
RECO2
RXO
LIMIN
COUT
19
20
DAIN
MIC
CTC
21
22
24
23
COIN
MICO
3
4516D–CT0–10/05
Table 2-1.
Pin
1
Pin Description
Symbol
Function
Phase comparator local oscillator
PCLO
2
RFOGND RF transmit output ground
3
RFO
RFOVB
AGND
VBIAS
VRF
RF transmit output
4
Power supply input of RF transmit output buffer
Analog ground for RF part
5
6
Decoupling capacitor of current reference
Supply voltage for RF part
7
8
MLF
Modulator loop filter
9
LFGND
MODIN
VDD
Modulator loop filter ground
Modulator input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Supply voltage output for peripherals and internal supply of digital part
Ground for LF analog and digital
Data input of serial bus
VSS
D
C
Clock input of serial bus
DACO
OPOUT
OPIN
TXO
D/A and data comparator output
Operational amplifier output
Operational amplifier input (inverting)
Output of limiter amplifier
LIMIN
COUT
CTC
Limiter input
Compressor output
Compressor time constant control analog output
Compressor input
COIN
MICO
MIC
Microphone amplifier output
Inverting input of microphone amplifier
Data comparator input
DAIN
RXO
Output of demodulator
RECO2
RECO1
EXIN
ETC
Symmetrical output of receive amplifier
Expander input
Expander time constant control analog output
IFIN2
IFIN1
MIX2IN
Symmetrical input of IF amplifier
Input of Mixer2
MIX2GND IF amplifier and Mixer2 ground
MIX2O
VAF
Mixer2 output
Supply voltage for AF/IF parts
Crystal oscillator input 11.15 MHz
XCK
OSCGND Oscillator ground
MIX1O
MIX1IN1
MIX1IN2
GNDLO
Output of Mixer1
Symmetrical input of MIxer1
Ground of LO
43
44
LO2
LO1
Tank elements for LO are connected to these pins
4
U3600BM
4516D–CT0–10/05
U3600BM
3. System Description
Radio frequency IC for analog cordless telephone application in 26/50 MHz band (CTO stan-
dard). The IC performs full duplex communication. The transmitting and receiving frequency are
depending on whether the IC is used in the handset or in the base station.
Frequency converter comprise an FM transmitter with switchable output power and first receiver
mixer in the same unit. A two-wire bus interface can be used for the frequency control as well as
for switching the transmitter power amplifier and the receiver. Fine frequency adjust of reference
quartz oscillator is programmable.
The receive part is designed for a double conversion architecture. The incoming radio frequency
signal will be filtered and amplified before reaching the first mixer. At this stage the RF signal will
be converted down to the first intermediate frequency (10.7 MHz) by using a crystal oscillator
(LO1).
The transmit part contains two PLL controlled VCOs. The frequency modulation is accomplished
by super-posing the incoming audio signal on the PLL control voltage. Final frequency is a prod-
uct of mixing VCO1 with first local oscillator of receiver part (VCO3). The FM modulated carrier
is amplified by externals power amplifier before entering the output filter and the antenna
connector.
3.1
Adjustments for VCO1 and VCO2
To be able to use a wide frequency range for the VCOs (i.e., VCO2 26.3 MHz to 49.9 MHz) the
two internal VCOs (VCO1 and VCO2, i.e., the VCOs of the transmit part) have a rough adjust
and a fine adjust to increase the frequency range given by the phase comparator.
The rough adjusts for these VCOs are correlated with the country setting. For every country
there are two sets of VCO rough adjust settings, one for the base and one for the handset. See
tables at channels frequencies and dividers.
To compensate the variation in production there is a fine adjust for each of the VCOs. The fine
adjusts of the internal VCOs could be set manually (for test purposes) or set by the automatic
mode. Theoretically the sign of the changing (increase/ decrease when the voltage of the phase
comparator is to high) is selectable, but we need value 1 () in all cases.
Setting VCO1 (VCO2) under normal conditions:
EAFA1 (EAFA2) = 1, automatic fine adjust VCO1(VCO2) enabled
SAFA1 (SAFA2) = 1, sign of auto fine adjustment of VCO1 (VCO2) = 1.
3.2
Adjustment for VCO3
In order to increase the adjustment range of VCO3 with fixed external tank elements and/or for
“band switching”, especially for US frequencies, VCO3 has programmable capacitors inside.
These capacitors can be added by serial bus (FA3 [4:0]) between LO1 and LO2. There are 31
steps available, every step adding a capacitor of 0.5 pF.
5
4516D–CT0–10/05
3.3
Speed-up of the Loop Filter of PLL1 (“Modulator PLL”)
To have a fast locking time for the modulator loop there is a precharge and a speed-up mode for
the external loop filter.
During receive mode (VCO3 enabled, VCO1 disabled) the modulator loop filter is precharged to
about half of the internally regulated 2.5V charge-pump voltage.
During the first 30 ms after enabling VCO1 the modulator phase comparator is in speed-up
mode. In this mode the current of the pase comparator which charges the loop filter is much
larger than in normal mode. Additionally to the automatically switched 30 ms speed-up mode,
the speed-up can be activated for any time by setting the bit SU1.
3.4
3.5
Speed-up of the Loop Filter of PLL3 (“1st. LO.”)
Similiar to PLL1, there is also a possibility to increase the locking speed of PLL3. This can be
done by setting the bit SU3. Having done this, the charge pump at the output of the phase com-
parator has a bigger current capability and therefore charges the external capacitors faster.
Adjustment of the Modulator Gain
To fulfil the different requirements of the different countries three conversion gains of the modu-
lator are selectable by the bits GMOD [1:0] (R6: D2, D3).
Country settings see tables at channel frequencies and dividers. Ranges see electrical charac-
teristics at RF transmitter.
3.6
Modulator PLL
The fractional divider has been chosen to increase the reference frequency of the modulator
PLL.
Q
1
557.5 kHz = f
/ P + ---------
Mod
1
223
P1: integer part of the fractional divider (M = 1)
Q1: fractional part of the fractional divider (M = 1)
f
Mod
Q
= 223 × -------------------------- – P
1
1
557.5 kHz
557.5 kHz
223 = --------------------------
2.5 kHz
The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz.
In fact, the fractional divider divides Q1 times by (P1 + 1) and (223 – Q1) times by P1
during 223 cycles.
Q × (P + 1) + (223 – Q )P
1
Q
1
1
1
1
-----------------------------------------------------------------------------
→
= P + ---------
1
223
223
For each comparison cycle (fRef1 = 557.5 kHz), the accumulator content is incremented by the
Q1 value and the divider divides by the P1 value. When the accumulator value reaches or
exceeds 223, the divider divides by the value (P1 + 1). Then, the accumulator holds the excess
value (accumulator value - 223). After 223 cycles, the correct division is executed.
6
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4516D–CT0–10/05
U3600BM
3.7
Serial Bus Interface
The circuit is remoted by an external microcontroller through the serial bus.
The data is a 12-bit word:
A0 - A3: address of the destination register (0 to 15)
D7 - D0: contents of register
The data line must be stable when the clock is high and data must be serially shifted.
After 12 clock periods, the transfer to the destination register is (internally) generated by a low to
high transition of the data line when the clock is high.
Figure 3-1. Serial Bus
Data
D
Micro-
processor
Clock
C
Figure 3-2.
Serial Bus Transmission
Data
(D)
D0
D1
D2
A0
A1
A2
A3
Clock
(C)
1st word
2nd word
Word transmission
Transfer condition
Figure 3-3. Serial Bus Structure
Data
8
4
Clock
0
128
Address
Decoder
Latches
15
Commands
7
4516D–CT0–10/05
Figure 3-4. Serial Bus Timing Diagram
Data
(D)
A1
A2
A3
D0
Clock
(C)
teon
teh
teoff
tcl
tsud
thd
tch
3.8
Content of Internal Registers
The registers have the following structure
D7
R0: Reference for D/A converter
MUXDA DA6 DA5
D6
D5
D4
D3
D2
D1
D0
DA4
DA3
DA2
DA1
DA0
MUXDA: D/A multiplexing VBAT/RSSI
DA(0:6): Reference voltage D/A
R1: Gain of earpeace amplifier and demodulator
GEA4 GEA3 GEA2 GEA1 GEA0
GDEM
free
free
GEA[0:4]: Gain of earpeace amplifier; “0” is LSB, “4” is MSB
GDEM: Demodulator gain (1 = low gain)
R2: Switches and mutes for receive and data reception
DATRX
BEXP
EEA
ERXO
ERX1
ERXHF
MRX
ERX2
DATRX:
BEXP:
EEA:
Switch data comparator output to “DACO”-pin
Bypass expander
Enable earpiece amplifier
ERXO:
ERX1:
ERXHF:
MRX:
Enable RXO output driver
Enable RX low frequency part 1
Enable Mixer2 and IF-amplifier
Mute RX low frequency path (expander) keeping circuit enabled
Enable RX low frequency part 2 (expander)
ERX2:
8
U3600BM
4516D–CT0–10/05
U3600BM
R3: Switches and mutes for transmit and power managemant
PDVDD
RBAT
free
free
free
free
MTX
ETX
PDVDD:
RBAT:
MTX:
Enable pull-down transistor in power-down mode
Battery detection high/low range
Mute TX low frequency path (compressor) keeping circuit enabled
Enable TX low frequency part
ETX:
R4: free (not used, for future extensions )
free
free
free
free
free
free
free
free
free
free
R5: Gain VCO2
free free
KV23
KV22
KV21
M12
KV2[1:3]: Gain of VCO2
M12: Double phase comparator frequency of PLL2
R6: Miscellaneus settings in synthesizer part
ETXO M1CP FRMT IMIXI
ETXO: Enable HF-transmit output
GMOD1
GMOD0
SU1
(TM)
M1CP:
Changes 1 dB compression point and current consumption of Mixer1
(“0” –> high, “1” –> low)
FRMT:
IMIXI:
Output frequency range of MixerT
Invert inputs of phase comparator in PLL2
GMOD[0:1]: Modulation gain of VCO1
SU1:
(TM):
Speed-up phase comparator for PLL1
Enable the internal test mode. It is mandatory that TM is kept to “0”!
(if not 0, the circuit will not work as expected or described here in this paper)
R7: PLL1 setting
DR1I1 DR1I0
RA11
RA10
DV1I3
DV1I2
DV1I1
DV1I0
DR1I[0:1]: Additional divider reference frequency PLL1
RA1[0:1]: Rough adjustment VCO1
DV1I[0:3]: Divider setting PLL1 integer part; “0” is LSB, “3” is MSB
R8: Divider PLL1 fractional part
DV1F7
DV1F6
DV1F5
DV1F4
DV1F3
DV1F2
DV1F1
DV1F0
DV1F[0:7]: Divider setting PLL1 fractional part; “0” is LSB, “7” is MSB
9
4516D–CT0–10/05
R9: Divider PLL3 LSBs
DV3I7 DV3I6
DV3I5
DV3I4
DV3I3
DV3I2
DV3I1
DV3I9
DV3I0
DV3I8
R10: Divider PLL3 MSBs and MSB of VCO3 fine adjustment
FA34 DV3I14 DV3I13 DV3I12 DV3I11 DV3I10
FA34: Fine adjustment VCO3 (frequency reduction) MSB
DV1I[0:14]: Divider setting PLL3 integer part; “0” is LSB, “14” is MSB
R11: Setting PLL2 and VCO3
FA33
FA32
FA31
FA30
AMIX2
AMIX1
RA21
RA20
FA3[0:4]: Fine adjustment of VCO3 (frequency reduction); “0” is LSB, “4” is MSB
AMIX[1:2]: Lengthening antibacklash signal PLL2
RA2[1:0]: Rough adjustment VCO2
R12: Divider for country setting, fine adjustment oscillator
FAOS2
FAOS1
FAOS0
D31
D30
D20
D11
D10
FAOS[0:2]: Fine adjustment of crystal oscillator (frequency reduction);
“0” is LSB, “2” is MSB
D3[0:1]:
D20:
D1[0:1]:
Setting divider D3
Setting divider D2
Setting divider D1
R13: VCO1 enable and fine adjustment
EVCO1
SAFA1
EAFA1
FA14
FA13
FA12
FA11
FA10
EVCO1:
SAFA1:
EAFA1:
Enable VCO1
Sign for automatic fine adjustment of VCO1
Enable automatic fine adjustment of VCO1
FA1(0:4): Manual fine adjustment of VCO1 (frequency reduction);
“0” is LSB, “4” is MSB
R14: VCO2 enable and fine adjustment
EVCO2
SAFA2
EAFA2
FA24
FA23
FA22
FA21
FA20
EVCO2:
SAFA2:
EAFA2:
Enable VCO2 and MixerT
Sign for automatic fine adjustment of VCO2
Enable automatic fine adjustment of VCO2
FA2(0:4): Manual fine adjustment of VCO2 (frtequency reduction);
“0” is LSB, “4” is MSB
10
U3600BM
4516D–CT0–10/05
U3600BM
R15: VCO3 enable, speed-up and referencq frequency, crystal oscillator enable
EVCO3
EOSC
SU3
E25K
E12K5
E10K
E6K25
E5K
EVCO3:
EOSC:
SU3:
Enable VCO3 and Mixer1
Enable crystal oscillator (11.15 MHz)
Speed-up phase comparator for PLL3
E25K:
E12K5:
E10K:
E6K25:
E5K:
Selection phase comparator frequency for PLL3: fRef3 = 25 kHz
Selection phase comparator frequency for PLL3: fRef3 = 12.5 kHz
Selection phase comparator frequency for PLL3: fRef3 = 10 kHz
Selection phase comparator frequency for PLL3: fRef3 = 6.25 kHz
Selection phase comparator frequency for PLL3: fRef3 = 5 kHz
E5K, E6K25, E10K, E15K5, E25K = 0:
Selection phase comparator frequency for PLL3: fRef3 = 2.5 kHz
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VBatt, VDD
Tj
Value
5.5
Unit
V
Supply voltage
Junction temperature
Ambient temperature
Storage temperature
Power dissipation Tamb = 60°C
+125
°C
°C
°C
W
Tamb
–25 to +75
–50 to +125
0.9
Tstg
Ptot
5. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient SSO44
RthJA
70
K/W
11
4516D–CT0–10/05
6. Electrical Characteristics
Tamb = +25°C, VRF = VAF = RFOVB = 3.6V, all bits set to “0”, unless otherwise specified.
Test circuit, see Figure 8-1 on page 18. Crystal specifications, see table “Crystal Specifications”.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Power Supply
Operating voltage range
3.1
3.6
5.2
V
Current Consumption
Operating current in inactive
mode (low voltage)
VRF = VAF = RFOVB = 2.9V
VDD = 0V
30
30
65
100
7.5
8.5
85
µA
µA
Operating current in standby
mode
VRF = VAF = RFOVB = 3.6V
ERXHF = EVCO3 = EOSC = 1
350
10.4
11.5
Operating current in RX mode
“waiting for RSSI”
mA
mA
Operating current in RX mode
“receiving data”
ERXHF = EVCO3 = EOSC = ERX1
= ERXO = 1
Operating current in
conversation mode: all blocks
enabled
ERXHF = EVCO3 = EOSC = ERX1 = ERXO
= ERX2 = EEA = EVCO2 = ETXO = 1
no load at RFO pin 3
20
29
mA
Charge Pump of LL1
Charge pump output voltage
Output high
2.38
1.15
2.5
1.4
2.63
1.65
V
V
Precharge voltage at the loop
filter
SB127 = 1, SB119 = 0
VMLF = 1.25V, output low
VMLF = 1.25V, output high
VMLF = 1.25V, output low
VMLF = 1.25V, output high
VMLF = 1.25V, output tristate
190
–400
4.3
400
–190
8
µA
µA
µA
µA
nA
Charge pump output current
in speed-up mode
6.2
Charge pump output current
–8
–6.2
–4.3
+150
Charge pump leakage current
Charge Pump of PLL3
–150
Charge pump output voltage
Output high
2.38
220
–420
80
2.5
2.63
420
V
VPCLO = 1.25V, output low
VPCLO = 1.25V, output high
VPCLO = 1.25V, output low
VPCLO = 1.25V, output high
VPCLO = 1.25V, output tristate
µA
µA
µA
µA
nA
Charge pump output current
in speed-up mode
–220
160
Charge pump output current
Charge pump leakage current
–160
–50
–80
+50
Receiver Input Mixer (Mixer1), EVCO3 = EOSC = 1
Input frequency range
20
50
MHz
MHz
kΩ
Output frequency
10.7
3.0
Input resistance
Input capacitance
Output impedance
MIX1IN1/MIX1IN2 to GND
MIX1IN1/MIX1IN2 to GND
MIX1O
3.5
pF
210
330
390
Ω
MIX1IN1/2 -> MIX1O
Voltage gain
“Loaded” (330 Ω with serial capacitance)
“Unloaded”
11.5
17.5
dB
dB
Input noise voltage
9
nV Hz–1/2
12
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U3600BM
6. Electrical Characteristics (Continued)
Tamb = +25°C, VRF = VAF = RFOVB = 3.6V, all bits set to “0”, unless otherwise specified.
Test circuit, see Figure 8-1 on page 18. Crystal specifications, see table “Crystal Specifications”.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
“Loaded” (330Ωwith serial capacitance)
M1CP=0
M1CP=1
“unloaded”
M1CP=1
140
40
mV
mV
Input 1-dB compression point
100
430
mV
mV
Third order input intercept
point
“Loaded” (330Ωwith seial capacitance)
M1CP=0
IF Mixer (Mixer2), EOSC = ERXHF = 1; Input Frequency: 10.7 MHz
Input resistance
Input capacitance
Output impedance
MIX2IN to GND
MIX2IN to GND
MIX2O
2.0
2.5
3.0
3
4.0
3.5
kΩ
pF
Ω
1200
1500
1800
MIX2IN -> MIX2O
“Loaded” (1500Ω with serial capacitance)
Voltage gain
13
32
80
15
17
dB
mV
mV
Input 1-dB compression point
“Loaded” (1500Ω with serial capacitance)
Third order input intercept
point
“Loaded” (1500Ω with serial capcitance)
IF Amplifier and Demodulator, ERXHF=1, ERX1=1, ERXO=1; Input Signal: 450 kHz, 500 µV, FM-modulation Frequency = 1 kHz
Recovered audio at RXO,
demodulator gain
GDEM=0
GDEM=1
180
90
mV/kHz
mV/kHz
AM rejection ratio
30% AM, 2.5 kHz FM
35
dB
Expander, ERX2 = 1; 470 nF from ETC to GND (VSS)
Gain reference level = G.R.L.
(gain = 0 dB)
70
80
90
mVrms
VEXIN = 10 dB less than G.R.L.
VEXIN = 20 dB less than G.R.L.
VEXIN = 30 dB less than G.R.L.
–11
–21
–35
–10
–20
–30
–9
–19
–25
dB
dB
dB
Gain versus input signal level
(“gain tracking”)
VEXIN = step 25 mV –> 50 mV
Attack time
measure time after step, when output
voltage has 0.75 times of final value
16
16
ms
VEXIN = step 50 mV –> 25 mV
measure time after step, when output
voltage has 1.5 times of final value
Release time
ms
Input resistance
9.5
15
kΩ
Earpiece Amplifier, EEA = 1, ERX2 = 1, BEXP = 1; Apply Input Voltage to EXIN; Measure Differentially at RECO1/2
Minimum gain
Medium gain
GEA[4:0]=0
GEA[4:0]=16
GEA[4:0]=31
0
1
17
32
1
2
dB
dB
dB
dB
16
31
0.8
18
33
1.2
Maximum gain
Gain adjust step
Maximum gain; 1 kΩ load; increase input
voltage until distortion ≈ 5%
Output voltage swing
Input resistance
4.8
7.3
5
Vpp
12.5
kΩ
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6. Electrical Characteristics (Continued)
Tamb = +25°C, VRF = VAF = RFOVB = 3.6V, all bits set to “0”, unless otherwise specified.
Test circuit, see Figure 8-1 on page 18. Crystal specifications, see table “Crystal Specifications”.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
IF Amplifier: RSSI
Input frequency
Input resistance
ERXHF=1
450
2.0
kHz
1.6
2.5
kΩ
VIF = 0 µV
starting from 0 increase RSSI-level until
mean of sampled signal at DACO is ≥ 0.5.
RSSI-level = ION0
RSSI sensitivity
1
VIF = 25.4 µV, f = 450 kHz
increase RSSI level again until mean of
sampled signal at DACO is ≥ 0.5.
RSSI-level = ION1
RSSI-sensitivity = ION1-ION0
RSSI input voltage dynamic
range
65
dB
dB
dB
RSSI level number of
programmable steps (see
folowing table “RSSI Level
Programming (Typical Values)
127
0.46
RSSI level step size in the
logarithmic region
0.35
0.6
Table 6-1.
RSSI Level Programming (Typical Values)
Input Voltage VIF (µV)
RSSI Level (Decimal)
0
5
8
25.4
42.4
424
14
54
97
111
4240
42400
14
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7. Electrical Characteristics
Tamb = +25°C, VRF = VAF = RFOVB = 3.6V, all bits set to “0”, unless otherwise specified. Test circuit, see Figure 8-1 on page 18.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Data Comparator, ERX1 = DATRX = 1
Hysteresis
50
1.5
100
mV
V
Threshold voltage
Input impedance
DAIN
kΩ
DACO, without load
(CMOS-output –> full swing)
Output high voltage
3.5
V
DACO, without load
(CMOS-output –> full swing)
Output low voltage
0.1
6
V
Output impedance
DACO
kΩ
Battery Switch
Decrease VBAT until internal switch
between VBAT and VDD becomes high
ohmic (“off”)
“Off” threshold
“On” threshold
2.85
3.1
2.95
3.1
V
V
Increase VBAT until internal switch
between VBAT and VDD becomes low
ohmic (“on”)
3.2
3.35
Hysteresis
Difference between on and off threshold
250
mV
µA
Ω
“Off”-leakage current
Switch “On”-resistance
10
50
Battery Management, MUXDA = 1
Maximum bat low
DA[6:0] = 127, RBAT = 1
3.7
3.05
4.75
3.83
3.5
3.95
3.2
4.1
3.35
V
V
Minimum bat low over switch
Maximum bat high
DA[6:0] = 27, RBAT = 1
DA[6:0] = 127, RBAT = 0
DA[6:0] = 0, RBAT = 0
5.05
4.1
5.25
V
Minimum bat high
4.27
V
Adjust step
7.5
11.5
mV
mV
Maximum - Minimum
Microphone Amplifier, ETX=1
Open loop gain
852.5
952.5
1052.5
80
3
dB
Gain bandwidth product
MHz
Input noise voltage,
BW = 300 Hz to 3.4 kHz,
psophometrically weighted
0.8
2
µVrmsp
Compressor, ETX = 1; 470 nF from CTC to GND (VSS)
Gain reference level = G.R.L.
(gain = 0 dB)
298
316
340
mVrms
dB
VCOIN = 20 dB less than G.R.L.
10
20
25
30
9
19
22
11
21
28
Gain versus input signal level
(“gain tracking”)
VCOIN = 40 dB less than G.R.L.
VCOIN = 50 dB less than G.R.L.
VCOIN = 60 dB less than G.R.L
VCOIN = step 31.6 mV –> 126 mV,
(-30 dBV –> –18 dBV)
measure time after step, when output
voltage has 1.5 times of final value
Attack time
3.5
ms
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7. Electrical Characteristics (Continued)
Tamb = +25°C, VRF = VAF = RFOVB = 3.6V, all bits set to “0”, unless otherwise specified. Test circuit, see Figure 8-1 on page 18.
Parameters
Test Conditions
Symbol
Min.
Typ.
14.4
19.5
Max.
Unit
VCOIN = step 126 mV –> 31.6 mV
(–18 dBV –> –30 dBV)
measure time after step, when output
voltage has 0.75 times of final value
Release time
ms
Input resistance
14
26
kΩ
Splatter Amplifier, ETX = 1
Open loop gain
90
dB
Gain bandwidth product
150
kHz
Maximum output voltage
swing
2.4
Vpp
Limiter Amplifier, ETX = 1, Tj = 25°C
Gain for signals below
limitation
LIMIN –> TXO,
20 mVRMS applied to LIMIN (AC coupled)
26
dB
%
Distortion for signals below
limitation
LIMIN –> TXO,
20 mVRMS applied to LIMIN (AC coupled)
2
Maximum output voltage
swing (above limitation,
clipping)
1.8
15
2.1
20
2.35
25
Vpp
Input resistance at LIMIN
kΩ
Note:
The gain and maximum output voltage swing of the limiter amplifier changes with temperature to compensate the tempera-
ture dependancy of MODIN (“tx conversion gain” of RF transmit part), fundamentally determined by the structure of the
circuitry.
RF Transmitter, ETXO = EVCO1 = EVCO2 = EVCO3 = EOSC = 1; Tj = 25°C
MODIN input impedance
70
100
300
130
390
0.3
kΩ
Ω
RFO output impedance
RFO output voltage level
Load = 200 ø
230
ETXO = 0; no load
V
49.99
00
Highest operating frequency
USA Base Channel 9 (US1b9)
MHz
For the complete programming see
“Channel Frequencies, Dividers and
Country Settings” on page 20“
USA1:
GMOD[1:0] = 00; fMod = ~7.6 MHz
5.2
5.2
kHz/V
kHz/V
TX conversion gain
MODIN - RFO
USA2:
GMOD[1:0] = 01; fMod = ~5.7 MHz
France:
GMOD[1:0] = 01; fMod = 4.3 MHz
GMOD[1:0] = 00; fMod = 4.3 MHz
3.8
2.7
kHz/V
kHz/V
Spain/Netherlands:
GMOD[1:0] = 10; fMod = 1.8 MHz
7.9
1.5
kHz/V
%
Modulation frequency: 1 kHz
Demodulated distortion THD
MODIN - RFO
US:
∆F = 4.0 kHz
5
France: ∆F = 2.5 kHz
16
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7. Electrical Characteristics (Continued)
Tamb = +25°C, VRF = VAF = RFOVB = 3.6V, all bits set to “0”, unless otherwise specified. Test circuit, see Figure 8-1 on page 18.
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Note:
The tx conversion gain of the RF transmitter is somehow dependent on temperature. This is determined by the fundamental
principle of this circuitry. Means have been taken inside the limiter amplifier, being in the signal path before MODIN, which are
able to completely compensate this temperature behavior.
Logical Part
Inputs: C, D
Low voltage input
High voltage input
Vil
Vih
0.2 × VDD
0.8 × VD
D
Input leakage current
(0 < VI < VDD)
Ii
+5
+5
µA
µA
–1
–5
Input leakage current
Pin XCK (0 < VI < VDD)
Serial bus (Figure 8-2)
Data set-up time
Data hold time
Clock low time
Clock high time
tsud
thd
tcl
tch
teon
0.1
0
2
2
0.1
µs
µs
µs
µs
µs
Hold time before transfer
condition
Data low pulse on transfer
condition
Data high pulse on transfer
condition
teh
0.2
0.2
µs
µs
teoff
8. Fine Adjustment of the Oscillator Frequency
To set the frequency of the oscillator exact to 11.15 MHz, the frequency is adjustable in 8 steps, by adding 3 different internal capacities
the frequency could be reduced.
Parameters
Test Conditions/Pins
FAOS (0:2) = 0
Min.
Typ.
Max.
Unit
Oscillator frequency without
reduction
11.15
+∆
MHz
FAOS2 FAOS1 FAOS0
0
0
1
1
0
1
0
0
1
0
0
1
140
280
560
700
Changing of oscillator frequency
with FOSC reduction
Hz
17
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Figure 8-1. Test Circuit
BZT55C51
56K
MIX1IN2
MIX1IN1
10N
10N
24K
5P
MIX1O
PCLO
RFOGND
RFO
LO1
LO2
330
1
0
GNDLO
MIX1IN2
MIX1IN1
MIX1O
OSCGND
XCK
TX-/Modulator-
Loop Filter
RFOVB
AGND
VBIAS
VRF
10N
MODIN
5.6K
1U 100N
VRF
2
1
MLF
VAF
470N
LFGND
MODIN
VDD
VAF
MIX2O
MIX2GND
MIX2IN
IFIN1
MIX2O
DATA
VSS
470N
DATA
1500
CLOCK
DACO
IFIN2
ETC
470N
CLOCK
OPOUT
EIN
OPIN
TXO
RECO1
RECO2
RXO
MIX2IN
10N
LIMIN
COUT
CTC
DACO
DAIN
MIC
CIN
MICO
IFIN1
IFIN2
10N
10N
850
EIN
220N
RECO1
RECO2
RXO
DAIN
This schematics is only a basic(simplified)
NOTE:
representation of the current production tes
t circuit
18
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Figure 8-2. Application Circuit
e t l r i F e l x p u D
n e n t a A n
19
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9. Channel Frequencies, Dividers and Country Settings
To meet all requirements of various countries – France (F), Spain (E), Netherlands (NL), USA,
Portugal (P), Taiwan, New Zealand and Korea – and modes – base (b), handset (h) – several
bits have to be set which do not change for the different channels. These settings are called
country settings.
• The country-setting bits contain:
• Rough adjustments for 2 VCOs
• Setting three integer divider in the mixer PLL and modulator PLL
• Conversion gain adjustment of mixer PLL
• Modulator gain
• Setting of the pulling direction of PLL2 (value dependent, if TX frequency is higher or lower
than LO frequency)
• Demodulator gain
Number of
Name Register
RA1[1:0]
RA2[1:0]
D1[1:0]
Function
Notes
Positions
Rough adjust VCO1
Rough adjust VCO2
Integer divider D1
Integer divider D2
00: is the highest frequency
00: is the highest frequency
Division by 2, 4, 6, 8
Division by 6, 8
3
4
4
2
D20
Doubles reference frequency
of PLL2 when set to “1”
M12
Integer divider M12
2
D3[1:0]
KV[3:1]
Integer divider D3
Conversion gain VCO2
Modulator gain
Division by 1, 2, 4
3
6
3
GMOD[1:0]
00: gain minimal
Reverse inputs of PC of
PLL
IMIXI
0: if fVCO2 lower than fVCO3
2
“0” means no reduction, >0
only necessary in E, NL,
Portugal
Additional divider M for
reference frequency fRef1
DR1[1:0]
4
Frequency range
Mixer T
FRMT
GDEM
0: output frequency < 5 MHz
2
2
0: high gain
1: low gain
Demodulator gain
Note:
Setting the fractional dividers:
For N, QM, send the binary equivalent of the numbers given below.
For PM (integer part of modulator PLL), send the D2 complement (16 – PM)
i.e., Fb1 (PM = 7, QM = 159 => integer: send 16 – PM = 9, fractional: send 159)
20
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10. Tables for Programming of the Dividers (Refer to Block Diagram)
Table 10-1. Divider D1 for PLL2
D11 (bit)
D10 (bit)
Decimally
D1 (Block Diagram),if M12 = 0
D1 (Block Diagram),if M12 = 1
0
0
1
1
0
1
0
1
0
1
2
3
2
8
6
4
1
4
3
2
Table 10-2. Divider D2 between PLL1 and PLL2
D20 (bit)
Decimally
D2 (Block Diagram),if M12 = 0
D2 (Block Diagram),if M12 = 1
0
0
0
1
6
8
3
4
Table 10-3. Divider D3 for PLL1
D31 (bit)
D30 (bit)
Decimally
D3 (Block Diagram)
0
0
1
1
0
1
0
1
0
1
2
3
1
2
6
4
10.1 Divider M for Reference Frequency of PLL1
There are several countries like Spain, the Netherlands and Portugal with relatively low modula-
tor frequencies fMod. In case of modulation there will be a big maximum time shift between
pulses coming from fractional divider and pulses coming from reference frequency divider. As a
consequence the phase comparator enters an undesired operation mode. To avoid entering this
operation mode the reference frequency fRef1 has to be reduced by a factor M. Simultaneously,
keeping fMod constant, the factors of fractional dividers have to be changed as well.
The connection between the additional reference frequency divider M and the factors PM and QM
of fractional divider is given below. The subscript M denotes which value of M refers to the fac-
tors PM and QM of fractional divider. The formulas take into account that the numerator of the
fraction QM/223 must not exceed 223.
PM = P1 × M + integer (Q × M/223)
QM = Q1 × M - 223 × integer (Q1 × M/223)
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10.2 France Base
Table 10-4. Country Setting
Name
RA1[1:0] RA2[1:0] D1[1:0]
D20
D3[1:0] KV2[3:1]
GMOD[1:0]
IMIXI DR1I[1:0] FRMT GDEM
Setting
00
11
11
1
01
100
01 (1)
0
00
0
0
high
gain
Value
max
min
D1 = 4
D2 = 8
D3 = 2
supra
M = 1
low
Note:
Alternatively, GMOD[1:0] could be set to “00”. This reduces the TX conversion gain (MODIN –> RFO) from
about 3.8 kHz/V to about 2.7 kHz/V, a value, which should be still sufficient for a maximum ∆f of 2.5 kHz
that is useful in the French case.
Table 10-5. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel
(MHz)
Rx Channel Frequency
(MHz)
fLO = 1/2 fVCO3
(MHz)
DV3I[14:0] = N
4898
1
2
26.3125
26.3250
26.3375
26.3500
26.3625
26.3750
26.3875
26.400
41.3125
41.3250
41.3375
41.3500
41.3625
41.3750
41.3875
41.4000
41.4125
41.4250
41.4375
41.4500
41.4625
41.4750
41.4875
30.6125
30.6250
30.6375
30.6500
30.6625
30.6750
30.6875
30.7000
30.7125
30.7250
30.7375
30.7500
30.7625
30.7750
30.7875
4900
3
4902
4
4904
5
4906
6
4908
7
4910
8
4912
9
26.4125
26.4250
26.4375
26.4500
26.4625
26.4750
26.4875
4914
10
11
12
13
14
15
4916
4918
4920
4922
4924
4926
10.2.1
France Modulation Loop Frequency and Divider
f
Mod = 4.3 MHz, PM = 7, QM = 159, M = 1
22
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10.3 France Hand
Table 10-6. Country Setting
Name
RA1[1:0] RA2[1:0] D1[1:0]
D20
D3[1:0] KV2[3:1]
GMOD[1:0]
IMIXI DR1I[1:0] FRMT GDEM
Setting
00
01
11
1
01
101
01 (1)
1
00
0
0
high
gain
Value
max
D1 = 4
D2 = 8
D3 = 2
infra
M = 1
low
Note:
Alternatively, GMOD[1:0] could be set to “00”. This reduces the TX conversion gain (MODIN –> RFO) from
about 3.8 kHz/V to about 2.7 kHz/V, a value, which should be still sufficient for a maximum ∆f of 2.5 kHz
that is useful in the French case.
Table 10-7. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
(MHz)
fLO = 1/2 fVCO3
(MHz)
DV3I[14:0] = N
5922
1
2
41.3125
41.3250
41.3375
41.3500
41.3625
41.3750
41.3875
41.4000
41.4125
41.4250
41.4375
41.4500
41.4625
41.4750
41.4875
26.3125
26.3250
26.3375
26.3500
26.3625
26.3750
26.3875
26.4000
26.4125
26.4250
26.4375
26.4500
26.4625
26.4750
26.4875
37.0125
37.0250
37.0375
37.0500
37.0625
37.0750
37.0875
37.1000
37.1125
37.1250
37.1375
37.1500
37.1625
37.1750
37.1875
5924
3
5926
4
5928
5
5930
6
5932
7
5934
8
5936
9
5938
10
11
12
13
14
15
5940
5942
5944
5946
5948
5950
10.3.1
France Modulation Loop Frequency and Divider
f
Mod = 4.3 MHz, PM = 7, QM = 159, M = 1
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10.4 Spain Base
Table 10-8. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
10
10
00
001
10
11
1
1
D1 = 2
D2 = 8
D3 = 4
infra
M = 4
high
low gain
Table 10-9. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
39.925
39.950
39.975
40.000
40.025
40.050
40.075
40.100
40.150
40.175
40.200
40.225
DV3I[14:0] = N
4676
1
2
31.025
31.050
31.075
31.100
31.125
31.150
31.175
31.200
31.250
31.275
31.300
31.325
29.225
29.250
29.275
29.300
29.325
29.350
29.375
29.400
29.450
29.475
29.500
29.525
4680
3
4684
4
4688
5
4692
6
4696
7
4700
8
4704
9
4712
10
11
12
4716
4720
4724
10.4.1
Spain Modulation Loop Frequency and Divider
f
Ref1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
24
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10.5 Spain Hand
Table 10-10. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
10
IMIXI
0
DR1I[1:0] FRMT GDEM
10
01
00
100
11
1
1
high
D1 = 2
D2 = 8
D3 = 4
high
supra
M = 4
high
low gain
Table 10-11. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
31.025
31.050
31.075
31.100
31.125
31.150
31.175
31.200
31.250
31.275
31.300
31.325
DV3I[14:0] = N
6676
1
2
39.925
39.950
39.975
40.000
40.025
40.050
40.075
40.100
40.150
40.175
40.200
40.225
41.725
41.750
41.775
41.800
41.825
41.850
41.875
41.900
41.950
41.975
42.000
42.025
6680
3
6684
4
6688
5
6692
6
6696
7
6700
8
6704
9
6712
10
11
12
6716
6720
6724
10.5.1
Spain Modulation Loop Frequency and Divider
f
Ref1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
25
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10.6 Netherlands Base
Table 10-12. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
10
IMIXI
1
DR1I[1:0] FRMT GDEM
10
10
00
001
11
1
1
low
D1 = 2
D2 = 8
D3 = 4
high
infra
M = 4
high
low gain
Table 10-13. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
4678
1
2
31.0375
31.0625
31.0875
31.1125
31.1375
31.1625
31.1875
31.2125
31.2375
31.2625
31.2875
31.3125
39.9375
39.9625
39.9875
40.0125
40.0375
40.0625
40.0875
40.1125
40.1375
40.1625
40.1875
40.2125
29.2375
29.2625
29.2875
29.3125
29.3375
29.3625
29.3875
29.4125
29.4375
29.4625
29.4875
29.5125
4682
3
4686
4
4690
5
4694
6
4698
7
4702
8
4706
9
4710
10
11
12
4714
4718
4722
10.6.1
Netherlands Modulation Loop Frequency and Divider
f
Ref1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
26
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10.7 Netherlands Hand
Table 10-14. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
10
IMIXI
0
DR1I[1:0] FRMT GDEM
10
01
00
001
11
1
1
high
D1 = 2
D2 = 8
D3 = 4
high
supra
M = 4
high
low gain
Table 10-15. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
6678
1
2
39.9375
39.9625
39.9875
40.0125
40.0375
40.0625
40.0875
40.1125
40.1375
40.1625
40.1875
40.2125
31.0375
31.0625
31.0875
31.1125
31.1375
31.1625
31.1875
31.2125
31.2375
31.2625
31.2875
31.3125
41.7375
41.7625
41.7875
41.8125
41.8375
41.8625
41.8875
41.9125
41.9375
41.9625
41.9875
42.0125
6682
3
6686
4
6690
5
6694
6
6698
7
6702
8
6706
9
6710
10
11
12
6714
6718
6722
10.7.1
Netherlands Modulation Loop Frequency and Divider
f
Ref1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
27
4516D–CT0–10/05
10.8 U.K. Base
Table 10-16. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
10
IMIXI
1
DR1I[1:0] FRMT GDEM
10
10
00
001
11
1
1
low
D1 = 2
D2 = 8
D3 = 4
high
infra
M = 4
high
low gain
Table 10-17. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
DV3I[14:0] = N
(MHz)
1
2
3
4
31.0375
31.0625
31.0875
31.1125
39.9375
39.9625
39.9875
40.0125
29.2375
29.2625
29.2875
29.3125
4678
4682
4686
4690
10.8.1
U.K. Modulation Loop Frequency and Divider
f
Ref1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
10.9 U.K. Handset
Table 10-18. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
10
IMIXI
0
DR1I[1:0] FRMT GDEM
10
01
00
001
11
1
1
high
D1 = 2
D2 = 8
D3 = 4
high
supra
M = 4
high
low gain
Table 10-19. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
DV3I[14:0] = N
(MHz)
1
2
3
4
39.9375
39.9625
39.9875
40.0125
31.0375
31.0625
31.0875
31.1125
41.7375
41.7625
41.7875
41.8125
6678
6682
6686
6690
10.9.1
U.K. Modulation Loop Frequency and Divider
f
Ref1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
28
U3600BM
4516D–CT0–10/05
U3600BM
10.10 USA Base
Table 10-20. Country Setting Channels (Channel 1 – 10, USA1)
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
10
00
01
100
00
00
1
1
max
D1 = 8
D2 = 8
D3 = 1
low
infra
M = 1
high
low gain
Table 10-21. Country Setting New Channels (Channel 11 – 25, USA2)
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
0
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
01
01
10
110
01
00
0
1
high
D1 = 6
D2 = &
D3 = 1
infra
M = 1
low
low gain
Table 10-22. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
DV3I[14:0] = N
(MHz)
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
1
2
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
38.970
39.145
39.160
39.070
39.175
39.130
39.190
39.230
39.290
39.270
7794
7829
7832
7814
7835
7826
7838
7846
7858
7854
3
4
5
6
7
8
9
10
Table 10-23. New Channel
Channel
Number
TX Channel Frequency
RX Channel Frequency
(MHz)
fLO = 1/2 fVCO3
(MHz)
(MHz)
43.720
43.740
43.820
43.840
43.920
43.960
44.120
44.160
44.180
44.200
44.320
44.360
44.400
44.460
44.480
DV3I[14:0] = N
7612
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
48.760
48.840
48.860
48.920
49.020
49.080
49.100
49.160
49.200
49.240
49.280
49.360
49.400
49.460
49.500
38.06
38.14
38.16
38.22
38.32
38.38
38.40
38.46
38.50
38.54
38.58
38.66
38.70
38.76
38.80
7628
7632
7644
7664
7676
7680
7692
7700
7708
7716
7732
7740
7752
7760
29
4516D–CT0–10/05
10.11 USA Hand
Table 10-24. Country Setting Channels (Channel 1 – 10, USA1):
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
0
DR1I[1:0] FRMT GDEM
10
00
01
100
00
00
1
1
max
D1 = 8
D2 = 8
D3 = 1
supra
M = 1
high
low gain
Table 10-25. Country Setting New Channels (Channel 11 – 25, USA2):
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
0
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
0
DR1I[1:0] FRMT GDEM
01
00
10
110
01
00
0
1
high
D1 = 6
D2 = &
D3 = 1
supra
M = 1
low
low gain
Table 10-26. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
DV3I[14:0] = N
11462
1
2
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
57.31
57.33
57.37
57.41
57.43
57.47
57.53
57.57
57.63
57.67
11466
3
11474
4
11482
5
11486
6
11494
7
11506
8
11514
9
11526
10
11534
Table 10-27. New channel
Channel
Number
TX Channel Frequency
RX Channel Frequency
(MHz)
fLO = 1/2 fVCO3
(MHz)
(MHz)
48.760
48.840
48.860
48.920
49.020
49.080
49.100
49.160
49.200
49.240
49.260
49.360
49.400
49.460
49.500
DV3I[14:0] = N
10884
10888
10904
10908
10924
10932
10964
10972
10976
10980
11004
11012
11020
11032
11036
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
43.720
43.740
43.820
43.840
43.920
43.960
44.120
44.160
44.180
44.200
44.320
44.360
44.400
44.460
44.480
54.42
54.44
54.52
54.54
54.62
54.66
54.82
54.86
54.88
54.90
55.02
55.06
55.10
55.16
55.18
30
U3600BM
4516D–CT0–10/05
U3600BM
Table 10-28. USA Modulation Loop Frequencies and Dividers
N Channel
PM
13
13
13
13
13
13
13
13
13
13
QM
157
95
fMod (MHz)
7.640
7.485
7.510
7.640
7.555
7.640
7.640
7.640
7.640
7.700
1
2
3
105
157
123
157
157
157
157
181
4
5
6
7
8
9
10
Table 10-29. New Channel
N Channel
PM
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
QM
34
10
34
18
10
2
fMod (MHz)
5.66
5.60
5.66
5.62
5.60
5.58
5.72
5.70
5.68
5.66
5.74
5.70
5.70
5.70
5.68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
58
50
42
34
66
50
50
50
42
31
4516D–CT0–10/05
10.12 Portugal Base
Table 10-30. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
01
10
00
001
10
11
1
1
D1 = 2
D2 = 8
D3 = 4
infra
M = 4
high
low gain
Table 10-31. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
37.000
37.025
37.050
37.075
37.100
37.125
37.150
37.175
37.200
37.225
37.250
37.275
DV3I[14:0] = N
4208
1
2
27.550
27.575
27.600
27.625
27.650
27.675
27.700
27.725
27.750
27.775
27.800
27.825
26.300
26.325
26.350
26.375
26.400
26.425
26.450
26.475
26.500
26.525
26.550
26.575
4212
3
4216
4
4220
5
4224
6
4228
7
4232
8
4236
9
4240
10
11
12
4244
4248
4252
10.12.1 Portugal Modulation Loop Frequency and Divider
Ref1 = 557.5 kHz/4, fMod = 1.25 MHz/4,PM = 8,QM = 216, M = 4
f
32
U3600BM
4516D–CT0–10/05
U3600BM
10.13 Portugal Hand
Table 10-32. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
11
KV2[3:1]
GMOD[1:0]
IMIXI
0
DR1I[1:0] FRMT GDEM
01
01
00
001
10
11
1
1
D1 = 2
D2 = 8
D3 = 4
supra
M = 4
high
low gain
Table 10-33. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
27.550
27.575
27.600
27.625
27.650
27.675
27.700
27.725
27.750
27.775
27.800
27.825
DV3I[14:0] = N
6120
1
2
37.000
37.025
37.050
37.075
37.100
37.125
37.150
37.175
37.200
37.225
37.250
37.275
38.250
38.275
38.300
38.325
38.350
38.375
38.400
38.425
38.450
38.475
38.500
38.525
6124
3
6128
4
6132
5
6136
6
6140
7
6144
8
6148
9
6152
10
11
12
6156
6160
6164
10.13.1 Portugal Modulation Loop Frequency and Divider
Ref1 = 557.5 kHz/4, fMod = 1.25 MHz/4,PM = 8,QM = 216, M = 4
f
33
4516D–CT0–10/05
10.14 Taiwan Base
Table 10-34. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
10
00
01
110
01
00
1
1
max
D1 = 8
D2 = 8
D3 = 1
infra
M = 1
high
low gain
Table 10-35. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
6008
1
2
45.2500
45.2750
45.3000
45.3250
45.3500
45.3750
45.4000
45.4250
45.4500
45.4750
48.2500
48.2750
48.3000
48.3250
48.3500
48.3750
48.4000
48.4250
48.4500
48.4750
37.5500
37.5750
37.6000
37.6250
37.6500
37.6750
37.7000
37.7250
37.7500
37.7750
6012
3
6016
4
6020
5
6024
6
6028
7
6032
8
6036
9
6040
10
6044
10.14.1 Taiwan Modulation Loop Frequency and Divider
Mod = 7.7 MHz, PM = 13,QM = 181, M = 1
f
34
U3600BM
4516D–CT0–10/05
U3600BM
10.15 Taiwan Hand
Table 10-36. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
0
DR1I[1:0] FRMT GDEM
10
00
01
110
00
00
1
1
max
D1 = 8
D2 = 8
D3 = 1
supra
M = 1
high
low gain
Table 10-37. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
8952
1
2
48.2500
48.2750
48.3000
48.3250
48.3500
48.3750
48.4000
48.4250
48.4500
48.4750
45.2500
45.2750
45.3000
45.3250
45.3500
45.3750
45.4000
45.4250
45.4500
45.4750
55.9500
55.9750
56.0000
56.0250
56.0500
56.0750
56.1000
56.1250
56.1500
56.1750
8956
3
8960
4
8964
5
8968
6
8972
7
8976
8
8980
9
8984
10
8988
10.15.1 Taiwan Modulation Loop Frequency and Divider
Mod = 7.7 MHz, PM = 13,QM = 181, M = 1
f
35
4516D–CT0–10/05
10.16 China Base
Table 10-38. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
10
00
01
110
01
00
1
1
max
D1 = 8
D2 = 8
D3 = 1
infra
M = 1
high
low gain
Table 10-39. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
5968
5972
5976
5980
5984
5988
5992
5996
6000
6004
6008
6012
6016
6020
6024
6028
6032
6036
6040
6044
1
2
45.0000
45.0250
45.0500
45.0750
45.1000
45.1250
45.1500
45.1750
45.2000
45.2250
45.2500
45.2750
45.3000
45.3250
45.3500
45.3750
45.4000
45.4250
45.4500
45.4750
48.0000
48.0250
48.0500
48.0750
48.1000
48.1250
48.1500
48.1750
48.2000
48.2250
48.2500
48.2750
48.3000
48.3250
48.3500
48.3750
48.4000
48.4250
48.4500
48.4750
37.3000
37.3250
37.3500
37.3750
37.4000
37.4250
37.4500
37.4750
37.5000
37.5250
37.5500
37.5750
37.6000
37.6250
37.6500
37.6750
37.7000
37.7250
37.7500
37.7750
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10.16.1 China Modulation Loop Frequency and Divider
Mod = 7.7 MHz, PM = 13,QM = 181, M = 1
f
36
U3600BM
4516D–CT0–10/05
U3600BM
10.17 China Hand
Table 10-40. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
00
KV2[3:1]
GMOD[1:0]
IMIXI
0
DR1I[1:0] FRMT GDEM
10
00
01
110
00
00
1
1
max
D1 = 8
D2 = 8
D3 = 1
supra
M = 1
high
low gain
Table 10-41. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
8912
8916
8920
8924
8928
8932
8936
8940
8944
8948
8952
8956
8960
8964
8968
8972
8976
8980
8984
8988
1
2
48.000
48.0250
48.0500
48.0750
48.1000
48.1250
48.1500
48.1750
48.2000
48.2250
48.2500
48.2750
48.3000
48.3250
48.3500
48.3750
48.4000
48.4250
48.4500
48.4750
45.0000
45.0250
450500
450750
45.1000
45.1250
45.1500
45.1750
45.2000
45.2250
45.2500
45.2750
45.3000
45.3250
45.3500
45.3750
45.4000
45.4250
45.4500
45.4750
55.7000
55.7250
55.7500
55.7750
55.8000
55.8250
55.8500
55.8750
55.9000
55.9250
55.9500
55.9750
56.0000
56.0250
56.0500
56.0750
56.1000
56.1250
56.1500
56.1750
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10.17.1 China Modulation Loop Frequency and Divider
Mod = 7.7 MHz, PM = 13,QM = 181, M = 1
f
37
4516D–CT0–10/05
10.18 New Zealand Base
Table 10-42. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
01
KV2[3:1]
GMOD[1:0]
IMIXI
1
DR1I[1:0] FRMT GDEM
00
01
11
110
01
00
0
1
D1 = 4
D2 = 8
D3 = 2
infra
M = 1
low
low gain
Table 10-43. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
4728
11
12
13
14
15
16
17
18
19
20
34.2500
34.2750
34.3000
34.3250
34.3500
34.3750
34.4000
34.4250
34.4500
34.4750
40.2500
40.2750
40.3000
40.3250
40.3500
40.3750
40.4000
40.4250
40.4500
40.4750
29.5500
29.5750
29.6000
29.6250
29.6500
29.6750
29.7000
29.7250
29.7500
29.7750
4732
4736
4740
4744
4748
4752
4756
4760
4764
10.18.1 New Zealand Modulation Loop Frequency and Divider
Mod = 4.7 MHz/4, PM = 8,QM = 96, M = 1
f
38
U3600BM
4516D–CT0–10/05
U3600BM
10.19 New Zealand Hand
Table 10-44. Country Setting
Name
Setting
Value
RA1[1:0] RA2[1:0] D1[1:0]
D20
1
D3[1:0]
01
KV2[3:1]
GMOD[1:0]
IMIXI
0
DR1I[1:0] FRMT GDEM
00
01
11
101
01
00
0
1
max
min
D1 = 4
D2 = 8
D3 = 2
supra
M = 1
low
low gain
Table 10-45. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
7192
11
12
13
14
15
16
17
18
19
20
40.2500
40.2750
40.3000
40.3250
40.3500
40.3750
40.4000
40.4250
40.4500
40.4750
34.2500
34.2750
34.3000
34.3250
34.3500
34.3750
34.4000
34.4250
34.4500
34.4750
44.9500
44.9750
45.0000
45.0250
45.0500
45.0750
45.1000
45.1250
45.1500
45.1750
7196
7200
7204
7208
7212
7216
7220
7224
7228
10.19.1 New Zealand Modulation Loop Frequency and Divider
Mod = 4.7 MHz/4, PM = 8,QM = 96, M = 1
f
39
4516D–CT0–10/05
10.20 Korea Base
Table 10-46. Country Setting
Name
RA1[1:0] RA2[1:0] D1[1:0]
D20
D3[1:0]
KV2[3:1]
GMOD[1:0]
IMIXI
DR1I[1:0] FRMT GDEM
Setting
10
00
01
1
00
100
00
1
00
1
1
high
gain
Value
max
D1 = 8
D2 = 8
D3 = 1
infra
M = 1
high
Table 10-47. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
7794
1
2
46.6100
46.6300
46.6700
46.7100
46.7300
46.7700
46.8300
46.8700
46.9300
46.9700
46.5100
46.5300
46.5500
46.5700
46.5900
49.6700
49.8450
49.8600
49.7700
49.8750
49.8300
49.8900
49.9300
49.9900
49.9700
49.6950
49.7100
49.7250
49.7400
49.7550
38.9700
39.1450
39.1600
39.0700
39.1750
39.1300
39.1900
39.2300
39.2900
39.2700
39.9950
39.0100
39.0250
39.0400
39.0550
7829
3
7832
4
7814
5
7835
6
7826
7
7838
8
7846
9
7858
10
11
12
13
14
15
7854
7799
7802
7805
7808
7811
40
U3600BM
4516D–CT0–10/05
U3600BM
10.21 Korea Hand
Table 10-48. Country Setting
Name
RA1[1:0] RA2[1:0] D1[1:0]
D20
D3[1:0]
KV2[3:1]
GMOD[1:0]
IMIXI
DR1I[1:0] FRMT GDEM
Setting
10
00
01
1
00
100
00
0
00
1
1
high
gain
Value
max
D1 = 8
D2 = 8
D3 = 1
supra
M = 1
high
Table 10-49. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel
Number
TX Channel Frequency
(MHz)
RX Channel Frequency
fLO = 1/2 fVCO3
(MHz)
(MHz)
DV3I[14:0] = N
11462
11466
11474
11482
11486
11494
11506
11514
11526
11534
11442
11446
11450
11454
11458
1
2
49.6700
49.8450
49.8600
49.7700
49.8750
49.8300
49.8900
49.9300
49.9900
49.9700
49.6950
49.7100
49.7250
49.7400
49.7550
46.6100
46.6300
46.6700
46.7100
46.7300
46.7700
46.8300
46.8700
46.9300
46.9700
46.5100
46.5300
46.5500
46.5700
46.5900
57.3100
57.3300
57.3700
57.4100
57.4300
57.4700
57.5300
57.5700
57.6300
57.6700
57.2100
57.2300
57.2500
57.2700
57.2900
3
4
5
6
7
8
9
10
11
12
13
14
15
41
4516D–CT0–10/05
Table 10-50. Korea Modulation Loop Frequencies and Dividers
N Channel
PM
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
QM
157
95
fMod (MHz)
7.640
7.485
7.510
7.640
7.555
7.640
7.640
7.640
7.640
7.700
7.515
7.520
7.525
7.530
7.535
1
2
3
105
157
123
157
157
157
157
181
107
109
111
113
115
4
5
6
7
8
9
10
11
12
13
14
15
Table 10-51. Crystal Specifications
Drive level < 0.01 µW
Parameters
Symbol
Min.
Typ.
11.15
14
Max.
Unit
MHz
pF
Load resonance frequency with 14 pF load capacitance
Load capacitance
Frequency tolerance
–30
9.2
+30
3.1
ppm
Shunt capacitance
pF
Motional capacitance
fF (1)
Ω
Series resistance
20
Note:
(1) Necessary to stay within adjustment range of oscillator FAOS (0:2) = 0 ... 5
42
U3600BM
4516D–CT0–10/05
U3600BM
11. Ordering Information
Extended Type Number
Package
SSO44
SSO44
Remarks
U3600BM-NFNY
Tube, Pb-free
U3600BM-NFNG3Y
Taped and reeled, Pb-free
12. Package Information
9.15
8.65
Package SSO44
Dimensions in mm
18.05
17.80
7.50
7.30
2.35
0.3
0.8
0.25
0.10
0.25
10.50
10.20
16.8
44
23
technical drawings
according to DIN
specifications
1
22
43
4516D–CT0–10/05
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