首页 |元器件品牌

HFBR-5984L [AVAGO]

FIBER OPTIC TRANSCEIVER, 1280-1380nm, 200Mbps(Tx), 200Mbps(Rx), BOARD/PANEL MOUNT, LC CONNECTOR;
HFBR-5984L
型号： HFBR-5984L
厂家： AVAGO TECHNOLOGIES LIMITED    AVAGO TECHNOLOGIES LIMITED
描述：

FIBER OPTIC TRANSCEIVER, 1280-1380nm, 200Mbps(Tx), 200Mbps(Rx), BOARD/PANEL MOUNT, LC CONNECTOR

放大器 光纤
文件： 总12页 (文件大小：364K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
HFBR-5984L  
200 MBd Low-Cost SBCON Transceivers  
in 2 x 5 SFF Package Style  
Data Sheet  
Description  
Features  
•
Multisour­ed 2 x 5 SFF pa­kage style with LC re­ep-  
The HFBR-5984L trans­eiver from Agilent provides the  
system designer with a produ­t to implement the SBCON  
spe­ifi­ation and to be ­ompatible with IBM ESCON ar-  
­hite­ture.  
ta­le  
•
•
Single +3.3 V power supply  
Wave solder and aqueous wash pro­ess ­ompatibil-  
ity  
This trans­eiver is supplied in the industry standard 2 x 5  
SFF with an LC fiber ­onne­tor interfa­e.  
•
•
Manufa­tured in an ISO 9001 ­ertified fa­ility  
SBCON 200 MBd spe­ifi­ation  
Transmitter Sections  
The transmitter se­tion of the HFBR-5984L utilizes a 1300  
nm InGaAsP LED. This LED is pa­kaged in the opti­al sub-  
assembly portion of the transmitter se­tion. It is driven by  
a ­ustom sili­on IC whi­h ­onverts differential PECL logi­  
signals, ECL referen­ed (shifted) to a +3.3 V supply, into  
an analog LED drive ­urrent.  
Applications  
®
•
Inter­onne­tion with IBM ­ompatible pro­essors,  
dire­tors and ­hannel atta­hment units  
– Disk and tape drives  
– Communi­ation ­ontrollers  
•
Data ­ommuni­ation equipment  
– Lo­al area networks  
Receiver Sections  
– Point-to-point ­ommuni­ation  
The re­eiver se­tion of the HFBR-5984L utilizes an InGaAs  
PINphotodiode­oupledto a ­ustom sili­on transimpedan­e  
preamplifier IC. It is pa­kaged in the opti­al subassembly  
portion of the re­eiver.  
This PIN/preamplifier ­ombination is ­oupled to a ­ustom  
quantizer IC whi­h provides the final pulse shaping for  
the logi­ output and the Signal Dete­t fun­tion. The Data  
output is differential. The Signal Dete­t output is single-  
ended. Both Data and Signal Dete­t outputs are PECL  
­ompatible, ECL referen­ed (shifted) to a +3.3 V power  
supply. The re­eiver outputs, Data Out and Data Out Bar,  
are squel­hed at Signal Dete­t Deassert.  
Package  
The overall pa­kage ­on­ept for the Agilent trans­eiver The ele­tri­al subassembly ­onsists of a high volume  
­onsists of three basi­ elements; the two opti­al subas- multilayer printed ­ir­uit board on whi­h the ICs and  
semblies, an ele­tri­al subassembly, and the housing as various surfa­e-mounted passive ­ir­uit elements are  
illustrated in the blo­k diagram in Figure1.  
atta­hed.  
The pa­kage outline drawing and pin out are shown in  
Figures 2 and 5. The details of this pa­kage outline and  
Both the re­eiver and transmitter se­tions in­lude an  
internal shield for the ele­tri­al and opti­al subassemblies  
pin out are ­ompliant with the multisour­e definition of to ensure high immunity to external EMI fields.  
the 2 x 5 SFF. The low profile of the Agilent trans­eiver  
The solder posts of the Agilent design are isolated from  
design ­omplies with the maximum height allowed for  
the internal ­ir­uit of the trans­eiver.  
the LC ­onne­tor over the entire length of the pa­kage.  
The trans­eiver is atta­hed to a printed ­ir­uit board with  
the ten signal pins and the two solder posts whi­h exit  
the bottom of the housing. The two solder posts provide  
the primary me­hani­al strength to withstand the loads  
The opti­al subassemblies utilize a high-volume assembly  
pro­ess together with low-­ost lens elements whi­h  
result in a ­ost-effe­tive building blo­k.  
imposed on the trans­eiver by mating with the LC ­on-  
ne­tored fiber ­ables.  
RX SUPPLY  
DATA OUT  
QUANTIZER IC  
PIN PHOTODIODE  
PRE-AMPLIFIER  
SUBASSEMBLY  
DATA OUT  
RX GROUND  
TX GROUND  
SIGNAL  
DETECT  
LC  
RECEPTACLE  
LED  
OPTICAL  
SUBASSEMBLY  
DATA IN  
LED DRIVER IC  
DATA IN  
TX SUPPLY  
Figure 1. Block Diagram.  
2
RX  
TX  
Mounting  
Studs/Solder  
Posts  
Top  
View  
o
o
o
o
o
RECEIVER SIGNAL GROUND  
RECEIVER POWER SUPPLY  
SIGNAL DETECT  
RECEIVER DATA OUT BAR  
RECEIVER DATA OUT  
o 1  
o 2  
10  
9
8
7
6
TRANSMITTER DATA IN BAR  
TRANSMITTER DATA IN  
TRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY)  
TRANSMITTER SIGNAL GROUND  
TRANSMITTER POWER SUPPLY  
o
o
o
3
4
5
Figure 2. Pin Out Diagram.  
Pin Descriptions:  
Pin 7 Transmitter Signal Ground V TX:  
Pin 1 Receiver Signal Ground V RX:  
EE  
EE  
Dire­tly ­onne­t this pin to the transmitter ground  
plane.  
Dire­tly ­onne­t this pin to the re­eiver ground plane.  
Pin 2 Receiver Power Supply V RX:  
CC  
Pin 8 Transmitter Disable T  
:
DIS  
Provide +3.3 V d­ via the re­ommended re­eiver power  
supply filter ­ir­uit. Lo­ate the power supply filter ­ir­uit  
No internal ­onne­tion. Optional feature for laser based  
produ­ts only.  
as ­lose as possible to the V RX pin.  
CC  
Pin 9 Transmitter Data In TD+:  
Pin 3 Signal Detect SD:  
No internal terminations are provided. See re­ommend-  
ed ­ir­uit s­hemati­.  
Normal opti­al input levels to the re­eiver result in a logi­  
“1”output.  
Pin 10 Transmitter Data In Bar TD-:  
No internal terminations are provided. See re­ommend-  
ed ­ir­uit s­hemati­.  
Low opti­al input levels to the re­eiver result in a fault  
­ondition indi­ated by a logi­ “0”output.  
This Signal Dete­t output ­an be used to drive a PECL  
input on an upstream ­ir­uit, su­h as Signal Dete­t input  
or Loss of Signal-bar.  
Mounting Studs/Solder Posts  
The mounting studs are provided for trans­eiver me-  
­hani­al atta­hment to the ­ir­uit board. It is re­om-  
mended that the holes in the ­ir­uit board be ­onne­ted  
to ­hassis ground.  
Pin 4 Receiver Data Out Bar RD-:  
No internal terminations are provided. See re­ommended  
­ir­uit s­hemati­.  
Pin 5 Receiver Data Out RD+:  
No internal terminations are provided. See re­ommended  
­ir­uit s­hemati­.  
Pin 6 Transmitter Power Supply V TX:  
CC  
Provide +3.3 V d­ via the re­ommended transmitter  
power supply filter ­ir­uit. Lo­ate the power supply filter  
­ir­uit as ­lose as possible to the V TX pin.  
CC  
3
Care should be used to avoid shorting the re­eiver data  
or signal dete­t outputs dire­tly to ground without  
proper ­urrent limiting impedan­e.  
Application Information  
The Appli­ations Engineering group is available to assist  
you with the te­hni­al understanding and design trade-  
offs asso­iated with these trans­eivers. You ­an ­onta­t  
them through your Agilent sales representative.  
Solder and Wash Process Compatibility  
The trans­eivers are delivered with prote­tive pro­ess  
plugs inserted into the LC re­epta­le. This pro­ess plug  
prote­ts the opti­al subassemblies during wave solder  
and aqueous wash pro­essing and a­ts as a dust ­over  
during shipping.  
The following information is provided to answer some  
of the most ­ommon questions about the use of these  
parts.  
Transceiver Optical Power Budget versus Link Length  
These trans­eivers are ­ompatible with either industry  
standard wave or hand solder pro­esses.  
Opti­al Power Budget (OPB) is the available opti­al power  
for a fiber opti­ link to a­­ommodate fiber ­able losses  
plus losses due to in-line ­onne­tors, spli­es, opti­al  
swit­hes, and to provide margin for link aging and  
unplanned losses due to ­able plant re­onfiguration or  
repair.  
Shipping Container  
The trans­eiver is pa­kaged in a shipping ­ontainer  
designed to prote­t it from me­hani­al and ESD damage  
during shipment or storage.  
Board Layout - Decoupling Circuit, Ground Planes and Termi-  
nation Circuits  
Agilent LED te­hnology has produ­ed 1300 nm LED  
devi­es with lower aging ­hara­teristi­s than normally  
asso­iated with these te­hnologies in the industry. The  
industry ­onvention is 1.5 dB aging for 1300 nm LEDs.  
It is important to take ­are in the layout of your ­ir­uit  
board to a­hieve optimum performan­e from these  
trans­eivers. Figure 4 provides a good example of a  
s­hemati­ for a power supply de­oupling ­ir­uit that  
works well with these parts. It is further re­ommended  
that a ­ontiguous ground plane be provided in the  
­ir­uit board dire­tly under the trans­eiver to provide  
a low indu­tan­e ground for signal return ­urrent. This  
re­ommendation is in keeping with good high frequen­y  
board layout pra­ti­es. Figures 3 and 4 show two re­om-  
mended termination s­hemes.  
The 1300 nm Agilent LEDs are spe­ified to experien­e  
less than 1dB of aging over normal ­ommer­ial equip-  
ment mission life periods. Conta­t your Agilent sales  
representative for additional details.  
Recommended Handling Precautions  
Agilent re­ommends that normal stati­ pre­autions be  
taken in the handling and assembly of these trans­eivers  
to prevent damage whi­h may be indu­ed by ele­trostati­  
dis­harge (ESD). The HFBR-5984L series of trans­eivers  
meet MIL-STD-883C Method 3015.4 Class 2 produ­ts.  
PHY DEVICE  
VCC (+3.3 V)  
TERMINATE AT  
TRANSCEIVER INPUTS  
Z = 50  
Z = 50  
Ω
Ω
TD-  
LVPECL  
100 Ω  
TD+  
130 Ω  
130 Ω  
10  
9
8
7
6
VCC (+3.3 V)  
1 µH  
10 µF  
TX  
C2  
C3  
VCC (+3.3 V)  
RX  
1 µH  
C1  
RD+  
1
2
3
4
5
Z = 50  
Ω
Ω
100 Ω  
LVPECL  
RD-  
Z = 50  
Z = 50  
VCC (+3.3 V)  
130 Ω  
130 Ω  
130 Ω  
Ω
SD  
82 Ω  
TERMINATE AT  
DEVICE INPUTS  
Note: C1 = C2 = C3 = 10 nF or 100 nF  
Figure 3. Recommended Decoupling and Termination Circuits  
4
Board Layout - Hole Pattern  
Regulatory Compliance  
The Agilent trans­eiver ­omplies with the ­ir­uit board  
These trans­eiver produ­ts are intended to enable  
“Common Trans­eiver Footprint”hole pattern defined in ­ommer­ial system designers to develop equipment  
the original multisour­e announ­ement whi­h defined that ­omplies with the various international regula-  
the 2 x 5 SFF pa­kage style. This drawing is reprodu­ed  
in Figure 6 with the addition of ANSI Y14.5M ­ompliant  
tions governing ­ertifi­ation of Information Te­hnology  
Equipment. See the Regulatory Complian­e Table for  
dimensioning to be used as a guide in the me­hani­al details. Additional information is available from your  
layout of your ­ir­uit board. Figure 6 illustrates the re­- Agilent sales representative.  
ommended panel opening and the position of the ­ir­uit  
board with respe­t to this panel.  
Board Layout - Art Work  
The Appli­ations Engineering group has developed a  
Gerber file artwork for a multilayer printed ­ir­uit board  
layout in­orporating the re­ommendations above.  
Conta­t your lo­al Agilent sales representative for details.  
TERMINATE AT  
TRANSCEIVER INPUTS  
PHY DEVICE  
VCC (+3.3 V)  
VCC (+3.3 V)  
10 nF  
130 W  
130 W  
Z = 50 W  
Z = 50 W  
TD-  
LVPECL  
TD+  
82 W  
82 W  
10  
9
8
7
6
VCC (+3.3 V)  
VCC (+3.3 V)  
1 µH  
C2  
TX  
VCC (+3.3 V)  
10 nF  
10 µF  
C3  
RX  
130 W  
130 W  
RD+  
RD-  
1 µH  
C1  
1
2
3
4
5
LVPECL  
Z = 50 W  
VCC (+3.3 V)  
10 nF  
Z = 50 W  
Z = 50 W  
82 W  
82 W  
130 W  
SD  
82 W  
TERMINATE AT DEVICE INPUTS  
Note: C1 = C2 = C3 = 10 nF or 100 nF  
Figure 4. Alternative Termination Circuits  
5
Figure 5. Package Outline Drawing  
6
Figure 6. Recommended Board Layout Hole Pattern and Panel Opening  
ꢀ
For additional information regarding EMI, sus­eptibility,  
ESD and ­ondu­ted noise testing pro­edures and results.  
Refer to Appli­ation Note 1166 Minimizing Radiated  
Emissions of High-Speed Data Communications Systems.  
Electrostatic Discharge (ESD)  
There are two design ­ases in whi­h immunity to ESD  
damage is important.  
The first ­ase is during handling of the trans­eiver prior  
to mounting it on the ­ir­uit board. It is important to  
use normal ESD handling pre­autions for ESD sensitive  
devi­es. These pre-­autions in­lude using grounded wrist  
straps, work ben­hes, and floor mats in ESD ­ontrolled  
areas.  
Transceiver Reliability and Performance Qualification Data  
The 2 x 5 SFF trans­eivers have passed Agilent reliability  
and performan­e qualifi­ation testing and are undergo-  
ing ongoing quality and reliability monitoring. Details are  
available from your Agilent sales representative.  
These trans­eivers are manufa­tured at the Agilent  
Singapore lo­ation whi­h is an ISO 9001 ­ertified  
fa­ility.  
The se­ond ­ase to ­onsider is stati­ dis­harges to  
the exterior of the equipment ­hassis ­ontaining the  
trans­eiver parts. To the extent that the LC ­onne­tor is  
exposed to the outside of the equipment ­hassis it may  
be subje­t to whatever ESD system level test ­riteria that  
the equipment is intended to meet.  
Ordering Information  
The HFBR-5984L 1300 nm produ­t is available for produ­-  
tion orders through the Agilent Component Field Sales  
Offi­es and Authorized Distributors world wide.  
Electromagnetic Interference (EMI)  
Most equipment designs utilizing this high speed trans-  
­eiver from Agilent will be required to meet the require-  
ments of FCC in the United States, CENELEC EN55022  
(CISPR 22) in Europe and VCCI in Japan.  
For te­hni­al information regarding this produ­t, please  
visit Agilent Semi­ondu­tor Produ­ts website at www.  
agilent.com/view/fiber. Use the qui­k sear­h feature to  
sear­h for this part number. You may also ­onta­t Agilent  
Semi­ondu­tor Produ­ts Customer Response Center at  
1-800-235-0312.  
This produ­t is suitable for use in designs ranging  
from a desktop ­omputer with a single trans­eiver to a  
­on­entrator or swit­h produ­t with a large number of  
trans­eivers.  
Applications Support Materials  
Conta­t your lo­al Agilent Component Field Sales Offi­e  
for information on how to obtain PCB layouts and evalu-  
ation boards for the 2 x 5 SFF trans­eivers.  
Immunity  
Equipment utilizing these trans­eivers will be subje­t to  
radio-frequen­y ele­tromagneti­ fields in some environ-  
ments. These trans­eivers have a high immunity to su­h  
fields.  
Regulatory Compliance Table  
Feature  
Test Method  
Performance  
Ele­trostati­ Dis­harge(ESD) to the JEDEC/EIAJESD22-A114-A  
Meets Class 2 (2000 to 3999 Volts).  
Ele­tri­al Pins  
andMIL-STD-883 Method  
3015(Human Body Model)  
Withstand up to 3000 V applied between ele­tri­al pins.  
Ele­trostati­ Dis­harge (ESD) to the Variation of  
LC Re­epta­le IEC 61000-4-2  
Typi­ally withstand at least 25 kV without damage when the LC Conne­tor  
Re­epta­le is ­onta­ted by a Human Body Model probe.  
Ele­tromagneti­ Interferen­e (EMI) FCC Class B  
CENELEC CEN55022 VCCI  
Trans­eivers typi­ally provide a 10 dB margin to the noted standard limits  
when tested at a ­ertified test range with the trans­eiver mounted to a  
­ir­uit ­ard without a ­hassis en­losure.  
Class 2  
Immunity  
Eye Safety  
Variation ofIEC 61000-4-3  
Typi­ally show no measurable effe­t from a 10 V/m field swept from 80  
to 450 MHz applied to the trans­eiver when mounted to a ­ir­uit ­ard  
without a ­hassis en­losure.  
AEL Class 1  
EN60825-1 (+A11)  
Compliant per Agilent testing under single fault ­onditions.  
TUV Certifi­ation #: E9ꢀꢀ1332-13UL File #: E1ꢀ38ꢀ4  
8
Absolute Maximum Ratings  
Stresses in ex­ess of the absolute maximum ratings ­an ­ause ­atastrophi­ damage to the devi­e. Limits apply to ea­h parameter  
in isolation, all other parameters having values within the re­ommended operating ­onditions. It should not be assumed that  
limiting values of more than one parameter ­an be applied to the produ­t at the same time. Exposure to the absolute maximum  
ratings for extended periods ­an adversely affe­t devi­e reliability.  
Parameter  
Symbol  
Minimum  
-40  
Typical  
Maximum  
+100  
+260  
10  
Unit  
°C  
Reference  
Storage Temperature  
Lead Soldering Temperature  
Lead Soldering Time  
Supply Voltage  
T
S
T
°C  
SOLD  
SOLD  
t
Se­.  
V
V
V
V
-0.5  
-0.5  
3.6  
CC  
I
Data Input Voltage  
Differential Input Voltage  
V
V
CC  
2.0  
50  
V
Note 1  
D
Output Current  
I
mA  
O
Recommended Operating Conditions  
Parameter  
Case Operating Temperature  
Symbol  
T
C
Minimum  
-20  
Typical  
Maximum  
+85  
Unit  
°C  
V
Reference  
Note 2  
Supply Voltage  
V
V
V
2.9ꢀ  
3.63  
CC  
Data Input Voltage - Low  
Data Input Voltage - High  
- V  
-1.81  
-1.4ꢀ5  
-0.880  
V
IL  
CC  
- V  
CC  
-1.165  
V
IH  
W
Data and Signal Dete­t Output Load  
R
L
50  
PCB Assembly Process Compatibility  
Parameter  
Symbol  
Minimum  
Typical  
Maximum  
Unit  
Reference  
Hand Lead Soldering Temperature  
Time  
t
t
+26010  
°Cse­  
solder time  
Wave Soldering and Aqueous Wash  
Temperature Time  
t
t
+26010  
110  
°Cse­  
psi  
11  
solder time  
Aqueous Wash Pressure  
Transmitter Electrical Characteristics  
(T = -20°C to +85°C, V = 2.9ꢀ V to 3.63 V)  
C
CC  
Parameter  
Symbol  
Minimum  
Typical  
133  
0.45  
-2  
Maximum  
1ꢀ5  
Unit  
mA  
W
Reference  
Note 3  
Note 4  
Supply Current  
Power Dissipation  
I
CC  
P
0.64  
DISS  
Data Input Current - Low  
Data Input Current - High  
I
I
-350  
µA  
µA  
IL  
IH  
18  
350  
9
Receiver Electrical Characteristics  
(T = -20°C to +85°C, V = 2.9ꢀ V to 3.63 V)  
C
CC  
Parameter  
Supply Current  
Symbol  
I
CC  
Minimum  
Typical  
65  
Maximum  
125  
Unit  
mA  
W
V
Reference  
Note 5  
Note 4  
Note 6  
Note 6  
Note ꢀ  
Note ꢀ  
Note 6  
Note 6  
Note ꢀ  
Note ꢀ  
Power Dissipation  
Data Output Voltage - Low  
Data Output Voltage - High  
Data Output Rise Time  
Data Output Fall Time  
P
V
V
0.25  
0.46  
-1.62  
-0.86  
1.3  
DISS  
- V  
-1.86  
-1.10  
0.35  
0.35  
-1.86  
-1.10  
0.35  
0.35  
OL  
CC  
- V  
V
OH  
CC  
t
t
ns  
ns  
V
r
1.3  
f
Signal Dete­t Output Voltage - Low  
Signal Dete­t Output Voltage - High  
Signal Dete­t Output Rise Time  
Signal Dete­t Output Fall Time  
V
V
- V  
-1.62  
-0.86  
2.2  
OL  
CC  
- V  
V
OH  
CC  
t
t
ns  
ns  
r
2.2  
f
Transmitter Optical Characteristics  
(T = -20°C to +85°C, V = 2.9ꢀ V to 3.63 V)  
C
CC  
Parameter  
Symbol  
Minimum  
Typical  
Maximum  
Unit  
Reference  
Output Opti­al Power  
BOL62.5/125  
P
-19.5-20.5  
-16.0-16.0  
-14.0-14.0  
dBm avg.  
Note 8  
O
µm, NA = 0.2ꢀ5 Fiber EOL  
Opti­al Extin­tion Ratio  
Center Wavelength  
8
dB  
Note 9  
l
1280  
1380  
1ꢀ5  
nm  
nm  
Figure ꢀ  
­
Spe­tral Width - FWHM  
Dl  
14ꢀ  
1
Note 10  
Figure ꢀ  
Opti­al Rise Time  
Opti­al Fall Time  
Total Jitter  
t
t
1.ꢀ  
1.ꢀ  
0.8  
ns  
ns  
ns  
Note 11, 12  
Figure ꢀ  
r
1.2  
0.2  
Note 11, 12  
Figure ꢀ  
f
Tj  
Note 13  
Receiver Optical Characteristics  
(T = -20°C to +85°C, V = 2.9ꢀ V to 3.63 V)  
C
CC  
Parameter  
Symbol  
Minimum  
Typical  
Maximum  
Unit  
Reference  
Input Opti­al PowerMinimum at Window  
Edge  
P
(W)  
Pin Min (C)+1 dBm avg.  
dB  
Note 14  
Figure 8  
IN Min.  
IN Min.  
IN Max.  
Input Opti­al PowerMinimum at Eye Center  
P
(C)  
-29  
dBm avg.  
Note 15  
Figure 8  
Input Opti­al Power Maximum  
Operating Wavelength  
Systemati­ Jitter  
P
l
-14  
dBm avg.  
nm  
Note 14  
1280  
1380  
1.0  
SJ  
0.2  
ns  
Note 16  
Note 1ꢀ  
Note 18  
Note 19  
Eyewidth  
t
ew  
1.4  
-44.5  
-45  
0.5  
0
ns  
Signal Dete­t - Asserted  
Signal Dete­t - Deasserted  
Signal Dete­t - Hysteresis  
Signal Dete­t Assert Time(off to on)  
P
A
-35.5  
-36  
dBm avg.  
dBm avg.  
dB  
P
D
P
A
- P  
D
4.0  
t
A
500  
µs  
Note 20  
Note 21  
Signal Dete­t Deassert Time(on to off)  
t
D
0
500  
µs  
10  
Notes:  
1. This is the maximum voltage that ­an be applied a­ross the Differential Transmitter Data Inputs to prevent damage to the input ESD prote­-  
tion ­ir­uit.  
2. The outputs are terminated with 50 W ­onne­ted to V –2 V.  
CC  
3. The power supply ­urrent needed to operate the transmitter is provided to differential ECL ­ir­uitry. This ­ir­uitry maintains a nearly ­onstant  
­urrent flow from the power supply. Constant ­urrent operation helps to prevent unwanted ele­tri­al noise from being generated and ­on-  
du­ted or emitted to neighboring ­ir­uitry.  
4. The power dissipation value is the power dissipated in the re­eiver itself. Power dissipation is ­al­ulated as the sum of the produ­ts of supply  
voltage and ­urrents, minus the sum of the produ­ts of the output voltages and ­urrents.  
5. This value is measured with the outputs terminated into 50 W ­onne­ted to V –2 V and an Input Opti­al Power Level of –14.5 dBm average.  
CC  
6. This value is measured with respe­t to V with the output terminated into 50 W ­onne­ted to V –2 V.  
CC  
CC  
ꢀ. The output rise time and fall times are measured between 20% and 80% levels with the output ­onne­ted to V – 2 V through 50 W.  
CC  
8. These opti­al power values are measured with the following ­onditions:  
• The Beginning of Life (BOL) to the End of Life (EOL) opti­al power degradation is assumed to be 1.5 dB per the industry ­onvention for long  
wavelength LEDs. The a­tual degradation observed in normal ­ommer­ial environments will be <1.0 dB with Agilent’s 1300 nm LED prod-  
u­ts.  
• Over the spe­ified operating voltage and temperature ranges.  
• Input Signal: 1010 data pattern, 200 Mb/s NRZ ­ode.  
9. The Extin­tion Ratio is a measure of the modulation depth of the opti­al signal. The data “0”output opti­al power is ­ompared to the data “1”  
peak output opti­al and expressed in de­ibels. With the transmitter driven by a HALT Line State (12.5 Mhz square-wave) signal, the average  
opti­al power is measured. The data “1”peak power is then ­al­ulated by adding 3 dB to the measured average opti­al power. The data “0”  
output opti­al power is found by measuring the opti­al power when the transmitter is driven by a logi­ “0”input. The Extin­tion Ratio is the  
ratio of the opti­al power at the “0”level ­ompared to the opti­al power at the “1”level expressed in de­ibels.  
10. From an assumed Gaussian-shaped wavelength distribution, the relationship between FWHM and RMS values for Spe­tral Width is 2.35 x  
RMS = FWHM.  
11. Input ­onditions: 100 MHz, square wave signal, input voltages are in the range spe­ified for V and V  
IL  
IH .  
12. Measured with ele­tri­al input signal rise and fall time of 0.35 to 1.3 ns (20-80%) at the transmitter input pins. Opti­al output rise and fall  
times are measured between 20% and 80% levels.  
13. Transmitter Systemati­ Jitter is equal to the sum of Duty Cy­le Distortion (DCD) and Data Dependent Jitter (DDJ). DCD is equivalent to Pulse-  
ꢀ
Width Distortion (PWD). Systemati­ Jitter is measured at the 50% signal level with 200 MBd, PRBS 2 –1 ele­tri­al input data pattern.  
14. This spe­ifi­ation is intended to indi­ate the performan­e of the re­eiver se­tion of the trans­eiver when Input Opti­al Power signal ­har-  
a­teristi­s are present per the following ­onditions. The Input Opti­al Power dynami­ range from the minimum level (with a window time-  
width) to the maximum level is the range over whi­h the re­eiver is guaranteed to provide output data with a Bit Error Ratio (BER) better than  
–12  
or equal to 10  
.
• At the Beginning of Life (BOL).  
• Over the spe­ified operating temperature and voltage ranges.  
• Re­eiver data window time-width is 1.4 ns or greater and ­entered at mid-symbol.  
ꢀ
• Input signal is 200 MBd, Pseudo Random-Bit-Stream 2 –1 data pattern.  
• Transmitter ­ross-talk effe­ts have been in­luded in Re­eiver sensitivity. Transmitter should be running at 50% duty ­y­le (nominal) be-  
tween 8 - 200 Mb/s, while Re­eiver sensitivity is measured.  
15. All ­onditions of note 14 apply ex­ept that the measurement is made at the ­enter of the symbol with no window time-width and with a BER  
-15  
better than or equal to 10  
.
16. The re­eiver systemati­ jitter spe­ifi­ation applies to opti­al powers between –14.5 dBm avg. to –2ꢀ.0 dBm avg. at the re­eiver. Re­eiver Sys-  
temati­ Jitter is equal to the sum of Duty Cy­le Distortion (DCD) and Data Dependent Jitter (DDJ). DCD is equivalent to Pulse-Width Distor-  
ꢀ
tion (PWD). Systemati­ Jitter is measured at the 50% signal level with 200 MBd, PRBS 2 –1 ele­tri­al output data pattern.  
200  
180  
160  
140  
120  
100  
6
5
4
3
2
1
0
3.0  
1.0  
1.5  
2.0  
tr/f – TRANSMITTER  
OUTPUT OPTICAL  
RISE/FALL TIMES –  
2.5  
3.0  
ns  
1260  
1280  
1300  
1320  
1340  
1360  
-3  
-2  
-1  
0
1
2
3
l
C – TRANSMITTER OUTPUT OPTICAL RISE/  
FALL TIMES – ns  
EYE SAMPLING TIME POSITION (ns)  
CONDITIONS:  
1. TA = +25 C  
2. VCC = 3.3 V dc  
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/1.2 ns.  
4. INPUT OPTICAL POWER IS NORMALIZED TO  
CENTER OF DATA SYMBOL.  
5. NOTE 15 AND 16 APPLY.  
HFBR-5930 TRANSMITTER TEST RESULTS  
OF λC, ∆λ AND t r/f ARE CORRELATED AND  
COMPLY WITH THE ALLOWED SPECTRAL WIDTH  
AS A FUNCTION OF CENTER WAVELENGTH FOR  
VARIOUS RISE AND FALL TIMES.  
Figure 7. Transmitter Output Optical Spectral Width  
(FWHM) vs. Transmitter Output Optical Center Wave-  
length and Rise/Fall Times.  
Figure 8. Relative Input Optical Power vs. Eye Sam-  
pling Time Position.  
1ꢀ. Eye-width spe­ified defines the minimum ­lo­k time-position range, ­entered around the ­enter of the 5 ns baud interval, at whi­h the BER  
–12  
ꢀ
must be 10 or better. Test data pattern is PRBS 2 –1. The typi­al ­hange in input opti­al power to open the eye to 1.4 nse­ from a ­losed  
eye is less than 1.0 dB.  
18. Status Flag swit­hing thresholds:  
Dire­tion of de­reasing opti­al power:  
If Power >–36.0 dBm avg., then SF = 1 (high)  
If Power <–45.0 dBm avg., then SF = 0 (low)  
Dire­tion of in­reasing opti­al power:  
If Power <–45.5 dBm avg., then SF = 0 (low)  
If Power >–35.5 dBm avg., then SF = 1 (high)  
19. Status Flag Hysteresis is the differen­e in low-to-high and high-to-low swit­hing thresholds. Thresholds must lie within opti­al power limits  
spe­ified. The Hysteresis is desired to avoid Status Flag ­hatter when the opti­al input is near the threshold.  
20. The Status Flag output shall be asserted within 500 µs after a step in­rease of the Input Opti­al Power. The step will be  
from a low Input Opti­al Power <–45.5 dBm avg., to >–35.5 dBm avg.  
21. Status Flag output shall be de-asserted within 500 µs after a step de­rease in the Input Opti­al Power. The Step will be from a high Input Op-  
ti­al Power >–36.0 dBm avg. to <–45.0 dBm avg.  
For product information and a complete list of distributors, please go to our web site: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.  
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.  
AV02-xxxxEN - March 21, 2007  
12  

相关型号：

HFBR-5984LZ

 FIBER OPTIC TRANSCEIVER, 1280-1380nm, 200Mbps(Tx), 200Mbps(Rx), BOARD/PANEL MOUNT, LC CONNECTOR, ROHS COMPLIANT PACKAGE-10
AVAGO

HFBR-59L1AGEZ

 1.25 GBd Ethernet and 1.0625 GBd Fibre Channel 850 nm SFF Low Voltage (3.3 V) Optical Transceiver
AVAGO

HFBR-59L1AL

 Agilent HFBR-59L1AL 1.25 GBd Ethernet and 1.0625 GBd Fibre Channel 850 nm SFF Low Voltage (3.3 V) Optical Transceiver
AGILENT

HFBR-59L1AL

 Agilent HFBR-59L1AL 1.25 GBd Ethernet and 1.0625 GBd Fibre Channel 850 nm SFF Low Voltage (3.3 V) Optical Transceiver
HP

HFBR-59L1AL

 1.25 GBd Ethernet and 1.0625 GBd Fibre Channel 850 nm SFF Low Voltage (3.3 V) Optical Transceiver
AVAGO

HFBR-59L1ALZ

 暂无描述
AVAGO

HFBR-707X2DEM

 10 Gb Ethernet, 1310 nm, 10GBASE-LRM, X2 Transceiver
AVAGO

HFBR-712BP

 Telecomm/Datacomm
ETC

HFBR-772BEHZ

 Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver
AVAGO

HFBR-772BEPWZ

 Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver Low cost per Gb/s
AVAGO

HFBR-772BEWZ

 Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver Low cost per Gb/s
AVAGO

HFBR-772BEZ

 Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver
AVAGO
©2020 ICPDF网 联系我们和版权申明