ADS5271IPFPT [BB]
8-Channel, 12-Bit, 50MSPS ADC with Serial LVDS Interface; 8通道， 12位， 50MSPS ADC，具有串行LVDS接口
| 型号： | ADS5271IPFPT |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 8-Channel, 12-Bit, 50MSPS ADC with Serial LVDS Interface |
| 文件： | 总19页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5271
SBAS313A − JUNE 2004 − REVISED JUNE 2004
8-Channel, 12-Bit, 50MSPS ADC
with Serial LVDS Interface
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
FD EATURES
Maximum Sample Rate: 50MSPS
D
D
D
D
D
D
D
D
D
D
D
D
D
D
12-Bit Resolution
The ADS5271 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
No Missing Codes
Power Dissipation: 957mW
CMOS Technology
The device is available in a PowerPAD TQFP-80 package and
is specified over a −40°C to +85°C operating range.
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
Internal and External References
3.3V Digital/Analog Supply
Serialized LVDS Outputs
LCLKP
LCLKN
6X ADCLK
1X ADCLK
PLL
ADCLKP
ADCLKN
Integrated Frame and Synch Patterns
MSB and LSB First Modes
Option to Double LVDS Clock Output Currents
Pin- and Format-Compatible Family
TQFP-80 PowerPAD Package
ADCLK
IN1P
IN1N
OUT1P
OUT1N
12−Bit
ADC
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
IN2P
IN2N
OUT2P
OUT2N
12−Bit
ADC
AD PPLICATIONS
IN3P
IN3N
OUT3P
OUT3N
Portable Ultrasound Systems
12−Bit
ADC
D
D
D
Tape Drives
Test Equipment
Optical Networking
IN4P
IN4N
OUT4P
OUT4N
12−Bit
ADC
IN5P
IN5N
OUT5P
OUT5N
12−Bit
ADC
DESCRIPTION
The ADS5271 is a high-performance, 50MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
IN6P
IN6N
OUT6P
OUT6N
12−Bit
ADC
IN7P
IN7N
OUT7P
OUT7N
12−Bit
ADC
IN8P
IN8N
OUT8P
OUT8N
12−Bit
ADC
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
Serializer
Control
Registers
Reference
INT/EXT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2004, Texas Instruments Incorporated
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(1)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Voltage Between AVSS and LVSS . . . . . . . . . . . . . . . . . . −0.3V to 0.3V
Voltage Between AVDD and LVDD . . . . . . . . . . . . . . . . . −0.3V to 0.3V
Voltages Applied to External REF Pins . . . . . . . . . . . . . . −0.3V to 2.4V
All LVDS Data and Clock Outputs . . . . . . . . . . . . . . . . . . −0.3V to 2.4V
Analog Input Pins
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Clock Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 2.7V
Clock Not Running . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.15V to 2.7V
Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . . . . −30mA
Operating Free-Air Temperature Range, T . . . . . . . . . −40°C to 85°C
A
Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . . . . 220°C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
ADS5271
HTQFP-80
PFP
−40°C to +85°C
ADS5271IPFP
ADS5271IPFP
ADS5271IPFPT
Tray, 96
″
″
″
″
″
Tape and Reel, 250
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 4.69mm x 4.69mm (min), 6.20mm x 6.20mm (max).
RELATED PRODUCTS
MODEL
RESOLUTION (BITS)
SAMPLE RATE (MSPS)
CHANNELS
ADS5270
ADS5272
ADS5273
ADS5275
ADS5276
ADS5277
12
12
12
10
10
10
40
65
70
40
50
65
8
8
8
8
8
8
RECOMMENDED OPERATING CONDITIONS
ADS5271
TYP
MIN
MAX
UNIT
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
Low Level Voltage Clock Input
20
50
MSPS
V
High Level Voltage Clock Input
V
ADCLK and ADCLK Outputs (LVDS)
20
50
MHz
MHz
°C
P
N
(1)
LCLK and LCLK Outputs (LVDS)
120
−40
300
+85
P
N
Operating Free-Air Temperature, T
A
Thermal Characteristics
q
21
68
°C/W
°C/W
JA
q
JC
(1)
6 × ADCLK.
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
Default with internal pull-up.
2.0V
Internal Reference
1
0
PP
Internal reference is powered down. Common mode of external reference should be within 50mV of
. V is derived from the internal bandgap voltage.
External Reference
V
CM
CM
2
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS
T
= −40°C, and T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5271
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNITS
DC ACCURACY
No Missing Codes
Assured
0.5
0.6
0.2
14
DNL Differential Nonlinearity
INL Integral Nonlinearity
f
f
= 5MHz
= 5MHz
−0.9
−2.0
0.9
2.0
LSB
LSB
IN
IN
(1)
Offset Error
−0.75
0.75
%FS
Offset Temperature Coefficient
ppm/°C
%FS
(2)
Fixed Attenuation in Channel
1
(3)
Variable Attenuation in Channel
0.2
1.0
44
%FS
(4)
Gain Error
−2.5
2.5
%FS
(5)
Gain Temperature Coefficient
ppm/°C
POWER SUPPLY
Total Supply Current
I(AVDD) Analog Supply Current
I
V
V
= FS, F = 5MHz
290
232
58
mA
mA
mA
mW
mW
CC
IN
IN
= FS, F = 5MHz
IN
IN
I(LVDD) Digital Output Driver Supply Current
Power Dissipation
V
IN
= FS, F = 5MHz, LVDS Into 100Ω Load
IN
957
90
1000
Power Down
Clock Running
REFERENCE VOLTAGES
VREF Reference Top (internal)
1.95
0.95
1.45
2.0
1.0
1.5
2.0
2.05
1.05
1.55
V
V
T
VREF
Reference Bottom (internal)
B
V
CM
Common-Mode Voltage
(6)
V
V
Output Current
50mV Change in Voltage
mA
V
CM
VREF
Reference Top (external)
1.875
T
VREF
Reference Bottom (external)
1.125
V
B
(7)
Reference Input Resistance
2.5
7.0
mA
ANALOG INPUT
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
pF
V
V
0.05
CM
1.5
2.02
600
V
PP
Differential Input Signal at 4V
Recovery to Within 1% of Code
PP
Voltage Overload Recovery Time
Input Bandwidth
4.0
300
CLK Cycles
MHz
−3dBFS
DIGITAL DATA OUTPUTS
Data Bit Rate
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
240
MBPS
20
0.6
MHz
V
V
IN
LOW Input Low Voltage
HIGH Input High Voltage
Input Current
0
V
IN
2.1
VDD
10
V
µA
pF
Input Pin Capacitance
5.0
(1)
(2)
Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full scale.
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are
changed from −V to +V , the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation.
REF
REF
NOTE: V
is defined as (REF − REF ).
T B
REF
(3)
(4)
(5)
Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
The reference voltages are trimmed at production so that (VREF − VREF ) is within 25mV of the ideal value of 1V. It does not include fixed attenuation.
T
B
The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with
temperature.
(6)
(7)
V
provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The V
output current specified is the additional drive of
CM
CM
the V
buffer if loaded externally.
CM
Average current drawn from the reference pins in the external reference mode.
3
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
AC CHARACTERISTICS
T
= −40°C, T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5271
PARAMETER
DYNAMIC CHARACTERISTICS
CONDITIONS
MIN
TYP
MAX
UNITS
f
f
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 5MHz
87
85
dBc
dBc
IN
IN
78
SFDR Spurious-Free Dynamic Range
f
f
84
dBc
IN
IN
82
dBc
f
90
dBc
IN
IN
f
85
78
90
dBc
HD
HD
2nd-Order Harmonic Distortion
3rd-Order Harmonic Distortion
2
f
f
87
dBc
IN
IN
85
dBc
f
87
dBc
IN
IN
f
85
dBc
3
f
f
84
dBc
IN
82
dBc
IN
f
f
70.5
70.5
70.5
70.5
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
68
SNR Signal-to-Noise Ratio
f
f
IN
IN
f
IN
IN
f
67.5
70
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
f
f
70
IN
IN
70
f
11.3
IN
Signal Applied to 7 Channels;
Measurement Taken on the Channel with
No Input Signal
Crosstalk
−90
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at I = 3.5mA, R
LOAD
= 100Ω, and C
= 9pF. I refers to the current setting for the LVDS buffer. R
is the differential load resistance
O
LOAD
O
LOAD
between the differential LVDS pair. C
is the effective single-ended load capacitance between the differential LVDS pins and ground. C includes the
LOAD
LOAD
receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100Ω differential impedance between the device and
the load. All LVDS specifications are functionally tested, but not parametrically tested.
PARAMETER
(1)
CONDITIONS
MIN
TYP MAX UNITS
DC SPECIFICATIONS
Output Voltage High, OUT or OUT
V
R
R
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1375 1500
1025
mV
mV
mV
mV
pF
OH
P
N
LOAD
V
Output Voltage Low, OUT or OUT
R
= 100Ω 1%
= 100Ω 1%
900
300
OL
P
N
LOAD
LOAD
V
V
Output Differential Voltage, OUT or OUT
Output Offset Voltage
R
350
400
OD
P
N
(2)
= 100Ω 1%; See LVDS Timing Diagram, Page 7
= 1.0V and 1.4V
1100 1200 1300
OS
LOAD
(3)
C
Output Capacitance
V
4
O
CM
∆V
∆V
Change in V Between 0 and 1
Change Between 0 and 1
R
R
= 100Ω 1%
= 100Ω 1%
25
25
40
12
mV
mV
mA
mA
OD
OD
LOAD
OS
LOAD
ISOUT Output Short-Circuit Current
ISOUT Output Current
Drivers Shorted to Ground
Drivers Shorted Together
NP
DRIVER AC SPECIFICATIONS
Clock Clock Signal Duty Cycle
Minimum Data Setup Time
6 × ADCLK
45
50
55
%
ps
ps
(4, 5)
400
400
400
250
200
150
(4, 5)
Minimum Data Hold Time
Rise Time or V Fall Time
t
/t
V
I
I
I
= 2.5mA
= 3.5mA
= 4.5mA
RISE FALL
OD
OD
O
O
O
ps
ps
ps
I
= 6mA
O
(1)
(2)
(3)
(4)
(5)
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
refers to the common-mode of OUT and OUT
V
.
N
OS
P
Output capacitance inside the device, from either OUT or OUT to ground.
P
N
Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock
paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.
4
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
SWITCHING CHARACTERISTICS
T
= −40°C, T = +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5271
MIN
TYP
MAX
PARAMETER
CONDITIONS
UNITS
SWITCHING SPECIFICATIONS
t
20
50
ns
ns
SAMPLE
t (A) Aperture Delay
2.5
1
D
Aperture Jitter (uncertainty)
t (pipeline) Latency
ps
6.5
5
cycles
ns
D
t
Propagation Delay
PROP
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
Start Sequence
CS
t1
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
SDATA
MSB
D6
D5
D4
D3
D2
D1
D0
t4
t5
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
ns
t
1
t
2
t
3
t
4
t
5
Serial CLK Period
50
Serial CLK High Time
Serial CLK Low Time
13
13
5
ns
ns
Minimum Data Setup Time
Minimum Data Hold Time
ns
5
ns
5
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
SERIAL INTERFACE TIMING
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0. LVDS BUFFERS
0
0
1
1
0
1
0
1
Normal ADC Output
Deskew Pattern
Patterns Get Reversed in MSB First
Mode of LVDS
Sync Pattern
Custom Pattern
0
0
1
1
0
1
0
1
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
0
0
0
1
1. LSB/MSB MODE
Default LVDS Clock Output Current
2X LVDS Clock Output Current
LSB Mode
D3
0
D2
X
D1
X
D0
1
0
0
X
X
0
1
X
X
MSB Mode
0
0
0
0
1
1
0
1
2. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
X
X
X
X
3. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
X
X
X
X
CUSTOM PATTERN (registers 4-6)
D3
MSB
X
D2
X
D1
X
D0
X
0
0
0
1
1
1
0
0
1
0
1
0
X
X
X
Bits for Custom Pattern
X
X
X
LSB
(1)
TEST PATTERNS
Deskew
101010101010
000000111111
Sync
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1)
Default is LSB first. If MSB is selected the above patterns will be reversed.
6
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LVDS TIMING DIAGRAM (PER ADC CHANNEL)
Sample n
Sample n+6
Input
1
tSAMPLE
ADCLK
tS
2
LCLKP
6X ADCLK
LCLKN
OUTP
D10 D11
D0 D1
SERIAL DATA
OUTN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Sample n data
ADCLKP
1X ADCLK
ADCLKN
tD(A)
tPROP
6.5 Clock Cycles
RESET TIMING
t1
+AVDD
Power
Supply
t1 > 10ms
t2 > 100ns
0V
+AVDD
0V
RESET
t2
POWER-DOWN TIMING
µ
10 s
Device Fully
Powers Down
PD
Device Fully
Powers Up
µ
1 s
7
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
PIN CONFIGURATION
Top View
TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
60
59
AVDD
IN1P
AVDD
IN8N
IN1N
3
58 IN8P
57
4
AVSS
IN2P
AVSS
5
56 IN7N
55 IN7P
IN2N
6
7
54
AVDD
AVSS
IN3P
AVDD
8
53 AVSS
9
52
51
50
IN6N
IN6P
10
11
IN3N
ADS5271
AVSS
AVSS
IN4P 12
13
49 IN5N
48
IN4N
IN5P
AVDD 14
LVSS 15
47 AVDD
46 LVSS
16
45
PD
RESET
LVSS 17
44 LVSS
18
19
20
43
42
41
LVSS
LCLKP
LCLKN
LVSS
ADCLKN
ADCLKP
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
PIN DESCRIPTIONS
NUMBER
OF PINS
NAME
PIN #
I/O
DESCRIPTION
AVDD
AVSS
LVDD
LVSS
1, 7, 14, 47, 54, 60, 63, 70, 75
8
14
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
Analog Power Supply
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
Analog Ground
25, 35
I
LVDS Power Supply
15, 17, 18, 26, 36, 43, 44, 46
I
LVDS Ground
IN1
2
I
Channel 1 Differential Analog Input High
Channel 1 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 8 Differential Analog Input High
Channel 8 Differential Analog Input Low
Reference Top Voltage
P
N
IN1
IN2
3
I
5
I
P
N
IN2
IN3
6
I
9
I
P
N
IN3
IN4
10
12
13
48
49
51
52
55
56
58
59
67
66
65
69
16
19
20
71
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
64
45
76
77
78
I
I
P
N
IN4
IN5
I
I
P
N
IN5
IN6
I
I
P
N
IN6
IN7
I
I
P
N
IN7
IN8
I
I
P
N
IN8
I
REFT
I/O
I/O
O
I
REFB
Reference Bottom Voltage
V
CM
Common-Mode Output Voltage
INT/EXT
PD
Internal/External Reference Select; 0 = External, 1 = Internal
Power-Down; 0 = Normal, 1 = Power-Down
Positive LVDS Clock
I
LCLK
O
O
I
P
LCLK
Negative LVDS Clock
N
ADCLK
Data Converter Clock Input
OUT1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I
Channel 1 Positive LVDS Data Output
Channel 1 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Positive LVDS ADC Clock Output
Negative LVDS ADC Clock Output
Bias Current Setting Resistor of 56kΩ to Ground
Reset to Default; 0 = Reset, 1 = Normal
Chip Select; 0 = Select, 1 = No Select
Serial Data Input
P
N
OUT1
OUT2
P
N
OUT2
OUT3
P
N
OUT3
OUT4
P
N
OUT4
OUT5
P
N
OUT5
OUT6
P
N
OUT6
OUT7
P
N
OUT7
OUT8
P
N
OUT8
ADCLK
P
ADCLK
N
ISET
RESET
CS
I
SDA
I
SCLK
I
Serial Data Clock
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS, internal
A
voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
20
40
60
80
0
20
40
60
80
−
−
fIN = 1MHz ( 1dBFS)
SNR = 71.1dBFS
SINAD = 70.9dBFS
SFDR = 87.7dBc
fIN = 5MHz ( 1dBFS)
SNR = 70.9dBFS
SINAD = 70.8dBFS
SFDR = 89dBc
−
−
−
−
−
−
−
−
−
−
−
−
100
120
100
120
0
0
0
5
10
15
20
25
0
5
10
15
20
25
Input Frequency (MHz)
Input Frequency (MHz)
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
−
−
fIN = 10MHz ( 1dBFS)
SNR = 70.9dBFS
SINAD = 70.7dBFS
SFDR = 95.4dBc
fIN = 20MHz ( 1dBFS)
SNR = 70.5dBFS
SINAD = 70.4dBFS
SFDR = 85.6dBc
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
100
120
100
120
5
10
15
20
25
0
5
10
15
20
25
Input Frequency (MHz)
Input Frequency (MHz)
INPUT FREQUENCY vs AMPLITUDE
DIFFERENTIAL NONLINEARITY
0
0.5
0.4
0.3
0.2
0.1
0
fIN = 5MHz
−
−
f1 = 9.5MHz ( 7dBFS)
f2 = 10.2MHz ( 7dBFS)
−
−
−
−
20
40
60
80
IMD(3) − 85
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
−
100
120
5
10
15
20
25
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Input Frequency (MHz)
10
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TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS, internal
A
voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
INTEGRAL NONLINEARITY
SWEPT INPUT POWER
SNR (dBFS)
1.0
0.8
0.6
0.4
0.2
0
90
80
70
60
50
40
30
20
10
0
fIN = 5MHz
fIN = 5MHz
SFDR (dBc)
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
SNR (dBc)
−
−
−
−
−
−
−
10
0
512 1024 1536 2048 2560 3072 3584 4096
Code
70
60
50
40
30
20
0
80
60
Input Amplitude (dBFS)
SWEPT INPUT POWER
DYNAMIC PERFORMANCE vs DUTY CYCLE
fIN = 5MHz
90
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
60
fIN = 10MHz
SNR (dBFS)
SFDR
SFDR (dBc)
SNR
SNR (dBc)
SINAD
−
−
−
−
−
−
−
10
70
60
50
40
30
20
0
20
30
40
50
Duty Cycle (%)
60
70
Input Amplitude (dBFS)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
DYNAMIC PERFORMANCE vs CLOCK FREQUENCY
fIN = 5MHz
SFDR
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
55
50
SFDR
SNR
SINAD
SNR
0
5
10
15
20
25
30
35
40
45
50
15
20
25
30
35
40
45
50
55
Input Frequency (MHz)
Clock Frequency (MHz)
11
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TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS, internal
A
voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
DYNAMIC PERFORMANCE vs CLOCK FREQUENCY
SFDR
SUPPLY CURRENT vs CLOCK FREQUENCY
95
90
85
80
75
70
65
60
55
50
0.30
0.25
0.20
0.15
0.10
0.05
0
IAVDD
SNR
SINAD
IDVDD
15
20
25
30
35
40
45
50
55
60
15
20
25
30
35
40
45
50
55
60
Clock Frequency (MHz)
Clock Frequency (MHz)
POWER DISSIPATION vs TEMPERATURE
975
970
965
960
955
950
945
940
−
−
−
−
−
45 35 25 15 5
5
15 25 35 45 55 65 75
_
Temperature ( C)
12
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SBAS313A − JUNE 2004 − REVISED JUNE 2004
pins (saving routing space on the board), reduced power
consumption, and reduced effects of digital noise coupling
to the analog circuit inside the ADS5271.
THEORY OF OPERATION
OVERVIEW
The ADS5271 is an 8-channel, high-speed, CMOS ADC.
It consists of a high-performance sample-and-hold circuit
at the input, followed by a 12-bit ADC. The 12 bits given out
by each channel are serialized and sent out on a single pair
of pins in LVDS format. All eight channels of the ADS5271
operates from a single clock referred to as ADCLK. The
sampling clocks for each of the eight channels are
generated from the input clock using a carefully matched
clock buffer tree. The 12X clock required for the serializer
is generated internally from ADCLK using a phase lock
loop (PLL). A 6X and a 1X clock are also output in LVDS
format along with the data to enable easy data capture.
The ADS5271 operate from internally generated reference
voltages that are trimmed to ensure matching across
multiple devices on a board. This feature eliminates the
need for external routing of reference lines and also
improves matching of the gain across devices. The
nominal values of REFT and REFB are 2V and 1V,
respectively. These values imply that a differential input of
−1V corresponds to the zero code of the ADC, and a
differential input of +1V corresponds to the full-scale code
(4095 LSB). VCM (common-mode voltage of REFT and
REFB) is also made available externally through a pin, and
is nominally 1.5V.
The ADS5271 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
DRIVING THE ANALOG INPUTS
The analog input biasing is shown in Figure 1. The
recommended method to drive the inputs is through AC
coupling. AC coupling removes the worry of setting the
common-mode of the driving circuit, since the inputs are
biased internally using two 600Ω resistors.
ADS5271
IN+
Ω
600
Input
Circuitry
Ω
600
−
IN
CM Buffer 1
CM Buffer 2
Internal
Voltage
Reference
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the digital
error correction logic, ensuring excellent differential
linearity and no missing codes at the 12-bit level. The
pipeline architecture results in a data latency of 6.5 clock
cycles.
VCM
Figure 1. Analog Input Bias Circuitry
The sampling capacitor used to sample the inputs is 4pF.
The choice of the external AC coupling capacitor is
dictated by the attenuation at the lowest desired input
frequency of operation. The attenuation resulting from
using a 10nF AC coupling capacitor is 0.04%.
The output of the ADC goes to a serializer that operates
from a 12X clock generated by the PLL. The 12 data bits
from each channel are serialized and sent LSB first. In
addition to serializing the data, the serializer also
generates a 1X clock and a 6X clock. These clocks are
generated in the same way the serialized data is
generated, so these clocks maintain perfect synchroniza-
tion with the data. The data and clock outputs of the
serializer are buffered externally using LVDS buffers.
Using LVDS buffers to transmit data externally has
multiple advantages, such as reduced number of output
If the input is DC coupled, then the output common-mode
voltage of the circuit driving the ADS5271 should match
the VCM (which is provided as an output pin) to within
50mV. It is recommended that the output common-mode
of the driving circuit be derived from VCM provided by the
device.
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The sampling circuit consists of a low-pass RC filter at the
input to filter out noise components that might be getting
differentially coupled on the input pins. The inputs are
sampled on two 4pF capacitors. The sampling on the
capacitors is done with respect to an internally generated
common-mode voltage (INCM). The switches connecting
the sampling capacitors to the INCM are opened out first
(before the switches connecting them to the analog
inputs). This ensures that the charge injection arising out
of the switches opening is independent of the input signal
amplitude to a first-order of approximation. SP refers to a
sampling clock whose falling edge comes an instant
before the SAMPLE clock. The falling edge of SP
determines the sampling instant.
All bias currents required for the internal operation of the
device are set using an external resistor to ground at pin
ISET. Using a 56kΩ resistor on ISET generates an internal
reference current of 20µA. This current is mirrored
internally to generate the bias current for the internal
blocks. Using a larger external resistor at ISET reduces the
reference bias current and thereby scales down the device
operating power. However, it is recommended that the
external resistor be within 10% of the specified value of
56k so that the internal bias margins for the various blocks
are proper.
Buffering the internal bandgap voltage also generates a
voltage called VCM, which is set to the midlevel of REFT
and REFB, and is accessible on a pin. The internal buffer
driving VCM has a drive of 2mA. It is meant as a reference
voltage to derive the input common-mode in case the input
is directly coupled.
INCM
(internally generated voltage)
When using the internal reference mode, a resistor greater
than 2Ω should be added between the reference pins
(REFT and REFB) and the decoupling capacitor, as shown
in Figure 3.
SP
Sample
(defines sampling instant)
4pF
4pF
Ω
Ω
15
IN+
1.5pF
1.7pF
SP
SP
ADS5271
15
−
IN
Sample
REFT
REFB
1.5pF
INCM
Ω
> 2
Ω
> 2
Figure 2. Input Circuitry
µ
µ
µ
µ
0.1 F
0.1 F
2.2 F
2.2 F
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale input peak-to-peak supported by
the ADS5271 is 2V. For a nominal value of VCM (1.5V), INP
and INN can swing from 1V to 2V. The ADS5271 is
specially designed to handle an over-voltage differential
peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP
and INN). If the input common-mode is not considerably off
from VCM during overload (less than 300mV), recovery
from an over-voltage input condition is expected to be
within 4 clock cycles. All of the amplifiers in the SHA and
ADC are specially designed for excellent recovery from an
overload signal.
Figure 3. Internal Refernce Mode
The device also supports the use of external reference
voltages. This mode involves forcing REFT and REFB
externally. In this mode, the internal reference buffer is
tri-stated. Since the switching current for the eight ADCs
come from the externally forced references, it is possible
for the performance to be slightly less than when the
internal references are used. It should be noted that in this
mode, VCM and ISET continue to be generated from the
internal bandgap voltage, as in the internal reference
mode. It is therefore important to ensure that the
common-mode voltage of the externally forced reference
REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies heavily on gain
matching across all receiver channels. A typical system
would have about 12 octal ADCs on the board. In such a
case, it is critical to ensure that the gain is matched,
essentially requiring the reference voltages seen by all the
ADCs to be the same. Matching references within the eight
channels of a chip is done by using a single internal
reference voltage buffer. Trimming the reference voltages
on each chip during production ensures the reference
voltages are well matched across different chips.
voltages matches to within 50mV of VCM
.
CLOCKING
The eight channels on the chip run off a single ADCLK
input. To ensure that the aperture delay and jitter are same
for all the channels, a clock tree network is used to
generate individual sampling clocks to each channel. The
14
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clock paths for all the channels are matched from the
source point all the way to the sample-and-hold. This
ensures that the performance and timing for all the
channels are identical. The use of the clock tree for
matching introduces an aperture delay, which is defined as
the delay between the rising edge of ADCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched, and vary between 2.5ns to 4.5ns
across devices. Another critical specification is the
aperture jitter that is defined as the uncertainty of the
sampling instant. The gates in the clock path are designed
so as to give an rms jitter of about 1ps.
data rate output by the serializer is 480 MBPS. The data
comes out LSB first, with a register programmability to
revert to MSB first. The serializer also gives out a 1X clock
and a 6X clock. The 6X clock (denoted as LCLKP/ LCLKN)
is meant to synchronize the capture of the LVDS data. The
deskew mode can be enabled as well, using a register
setting. This mode gives out a data stream of alternate 0s
and 1s and can be used determine the relative delay
between the 6X clock and the output data for optimum
capture. A 1X clock is also generated by the serializer and
transmitted by the LVDS buffer. The 1X clock (referred to
as ADCLKP/ADCLKN) is used to determine the start of the
12-bit data frame. The sync mode (enabled through a
register setting) gives out a data of six 0s followed by six
1s. Using this mode, the 1X clock can be used to determine
the start of the data frame. In addition to the deskew mode
pattern and the sync pattern, a custom pattern can be
defined by the user and output from the LVDS buffer.
The input ADCLK should ideally have a 50% duty cycle.
However, while routing ADCLK to different components on
board, the duty cycle of the ADCLK reaching the ADS5271
could deviate from 50%. A smaller (or larger) duty cycle
eats into the time available for sample or hold phases of
each circuit, and is therefore not optimal. For this reason,
the internal PLL is used to generate an internal clock that
has 50% duty cycle.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various types of
noise coupling. One of the main sources of noise is the
switching noise from the serializer and the output buffers.
Maximum care is taken to isolate these noise sources from
the sensitive analog blocks. As a starting point, the analog
and digital domains of the chip are clearly demarcated.
AVDD and AVSS are used to denote the supplies for the
analog sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there is
minimal interaction between the supply sets within the
device. The extent of noise coupled and transmitted from
the digital to the analog sections depends on the following:
The use of the PLL automatically dictates the lower
frequency of operation to be about 20MHz.
LVDS BUFFERS
The LVDS buffer has two current sources, as shown in
Figure 4. OUTP and OUTN are loaded externally by a
resistive load that is ideally about 100Ω. Depending on the
data being 0 or 1, the currents are directed in one or the
other direction through the resistor. The LVDS buffer has
four current settings. The default current setting is 3.5mA,
and gives a differential drop of about 350mV across the
100Ω resistor.
1. The effective inductances of each of the supply/ground
sets.
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground pins
leads to better suppression of the noise. For this reason,
multiple pins are used to drive each supply/ground. It is
also critical to ensure that the impedances of the supply
and ground lines on board are kept to the minimum
possible values. Use of ground planes in the board as well
as large decoupling capacitors between the supply and
ground lines are necessary to get the best possible SNR
from the device.
External
Termination
Resistor
High
Low
OUTP
OUTN
Low
High
It is recommended that the isolation be maintained on
board by using separate supplies to drive AVDD and
LVDD, as well as separate ground planes for AVSS and
LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The current in
the LVDS buffer is independent of the direction of
switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in low-noise
coupling.
Figure 4. LVDS Buffer
The LVDS buffer gets data from a serializer that takes the
output data from each channel and serializes it into a
single data stream. For a clock frequency of 40MHz, the
15
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After the supplies have stabilized, it is required to give the
device an active RESET pulse. This results in all internal
registers getting reset to their default value of 0 (inactive).
Without RESET, it is possible that some registers might be
in their non-default state on power-up. This could cause
the device to malfunction.
POWER-DOWN MODE
The ADS5271 has a power-down pin, PD. Pulling PD high
causes the devices to enter the power-down mode. In this
mode, the reference and clock circuitry as well as all the
channels are powered down. Device power consumption
drops to less than 100mW in this mode. Individual
channels can also be selectively powered down by
programming registers.
LAYOUT OF PCB WITH
POWERPAD THERMALLY
ENHANCED PACKAGES
The ADS5271 also has an internal circuit that monitors the
state of stopped clocks. If ADCLK is stopped (or if it runs
at a speed < 3MHz), this monitoring circuit generates a
logic signal that puts the device in a power-down state. As
a result, the power consumption of the device goes to less
than 100mW when ADCLK is stopped. This circuit can
also be disabled using register options.
The ADS5271 is housed in an 80-lead PowerPAD
thermally enhanced package. To make optimum use of the
thermal efficiencies designed into the PowerPAD
package, the PCB must be designed with this technology
in mind. Please refer to SLMA004 PowerPAD brief
PowerPAD Made Easy (refer to our web site at
www.ti.com), which addresses the specific considerations
required when integrating a PowerPAD package into a
PCB design. For more detailed information, including
thermal modeling and repair procedures, please see
SLMA002 technical brief PowerPAD Thermally Enhanced
Package (www.ti.com).
SUPPLY SEQUENCE
The following supply sequence is recommended for
powering up the device:
1. AVDD is powered up.
2. LVDD is powered up.
16
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ADS5271IPFP
ADS5271IPFPT
ACTIVE
ACTIVE
HTQFP
HTQFP
PFP
80
80
96
None
None
CU NIPDAU Level-3-220C-168 HR
CU NIPDAU Level-3-220C-168 HR
PFP
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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