ADS5521IPAPR [BB]
12-Bit, 105MSPS Analog-toDigital Converter; 12位，105Msps模数转换器
| 型号： | ADS5521IPAPR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 12-Bit, 105MSPS Analog-toDigital Converter |
| 文件： | 总20页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS309 − MAY 2004
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D
Pin-Compatible with:
FEATURES
− ADS5500 (14-Bit, 125MSPS)
− ADS5541 (14-Bit, 105MSPS)
− ADS5542 (14-Bit, 80MSPS)
− ADS5520 (12-Bit, 125MSPS)
− ADS5522 (12-Bit, 80MSPS)
D
D
D
D
D
D
D
D
12-Bit Resolution
105MSPS Sample Rate
High SNR: 69.4dB at 100MHz f
IN
High SFDR: 85.0dB at 100MHz f
IN
APPLICATIONS
D
2.3V Differential Input Voltage
PP
Wireless Communication
− Communication Receivers
− Base Station Infrastructure
Internal Voltage Reference
3.3V Single-Supply Voltage
D
D
D
D
D
D
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Analog Power Dissipation: 564mW
− Total Power Dissipation: 700mW
Communication Instrumentation
− Radar, Infrared
D
D
TQFP-64 PowerPADE Package
Recommended Op Amps:
THS3202, THS3201, THS4503,
OPA695, OPA847
Video and Imaging
Medical Equipment
Military Equipment
DESCRIPTION
The ADS5521 is a high-performance, 12-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed
for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5521
has excellent power consumption of 700mW at 3.3V single-supply voltage. This allows an even higher system
integration density. The provided internal reference simplifies system design requirements. Parallel CMOS
compatible output ensures seamless interfacing with common logic.
The ADS5521 is available in a 64-pin TQFP PowerPAD package and is pin-compatible with the ADS5500, ADS5541,
ADS5542, ADS5520, and ADS5522. This device is specified over the full temperature range of −40°C to +85°C.
AVDD
DRVDD
CLK+
CLK
CLKOUT
Timing Circuitry
−
D0
V +
12−Bit
Pipeline
ADC Core
Digital
Error
Correction
IN
.
.
.
Output
Control
S&H
V
−
IN
D11
OVR
DFS
Control Logic
Internal
Reference
CM
Serial Programming Register
ADS5521
AGND
DRGND
SCLK
SEN
SDATA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
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Copyright 2004, Texas Instruments Incorporated
ꢣꢦ ꢎ ꢢ ꢕ ꢐꢟ ꢤꢕ ꢔ ꢕ ꢏ ꢐꢣ ꢠꢕ ꢍ ꢅꢧ ꢓ ꢦꢎ ꢖꢎ ꢡꢅ ꢕꢖ ꢄꢢ ꢅꢄꢡ ꢤꢎ ꢅꢎ ꢎꢍ ꢤ ꢐꢅꢦ ꢕꢖ ꢢꢣ ꢕꢡ ꢄꢟꢄꢡ ꢎꢅꢄ ꢐꢍꢢ ꢎꢖ ꢕ ꢤꢕ ꢢꢄꢑ ꢍ
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SBAS309 − MAY 2004
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
(2)
HTQFP-64
PowerPAD
ADS5521IPAP
Tray, 160
ADS5521
PAP
−40°C to +85°C
ADS5521I
ADS5521IPAPR
Tape and Reel, 1000
(1)
(2)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max).
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(1)
over operating free-air temperature range unless otherwise noted
MIN TYP MAX
UNIT
PARAMETER
ADS5521
UNIT
Supplies
AV
DD
to A
to DR
GND
,
GND
−0.3 to +3.7
V
Analog supply voltage, AV
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Supply
Voltage
DD
DRV
DD
Output driver supply voltage, DRV
DD
A
GND
to DR
0.1
V
V
V
V
GND
Analog Input
Analog input to A
GND
−0.15 to +2.5
Differential input range
2.3
10
V
PP
V
Logic input to DR
GND
−0.3 to DRV
+ 0.3
DD
(1)
CM
Input common-mode voltage, V
Digital Output
1.5
1.6
Digital data output to DR
Input current (any input)
−0.3 to DRV
30
+ 0.3
GND
DD
mA
°C
°C
°C
Maximum output load
Clock Input
pF
Operating temperature range
Junction temperature
−40 to +85
+105
DLL ON
60
10
105 MSPS
80 MSPS
ADCLK input sample
rate (sine wave) 1/t
C
Storage temperature range
−65 to +150
DLL OFF
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
Clock amplitude, sine wave,
(2)
3
V
PP
differential
Clock duty cycle
Open free-air temperature range
(3)
50
%
−40
+85
°C
(1)
(2)
(3)
Input common-mode should be connected to CM.
See Figure 13 for more information.
See Figure 12 for more information.
2
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SBAS309 − MAY 2004
ELECTRICAL CHARACTERISTICS
Typ, min, and max values at T = +25°C, full temperature range is T
= −40°C to t
MAX
PP
= +85°C, sampling rate = 105MSPS, 50% clock duty
differential clock, unless otherwise noted.
A
MIN
cycle, AV
= DRV
= 3.3V, DLL On, −1dBFS differential input, and 3V
DD
DD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12 (tested)
Bits
Analog Inputs
Differential input range
2.3
6.6
4
V
PP
kΩ
pF
Differential input impedance
Differential input capacitance
Total analog input common-mode current
Analog input bandwidth
See Figure 4
See Figure 4
(1)
3.36
mA
MHz
Source impedance = 50Ω
750
Conversion Characteristics
Maximum sample rate
See Note 2
1.5
+4
MSPS
Data latency
See timing diagram, Figure 1
16.5
Clock Cycles
Internal Reference Voltages
Reference bottom voltage, V
REFM
0.97
2.11
V
V
Reference top voltage, V
REFP
Reference error
−4
0.9
%
V
Common-mode voltage output, V
CM
1.55 0.05
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
0.2
Differential linearity error, DNL
Integral linearity error, INL
Offset error
f
IN
f
IN
= 10MHz
= 10MHz
−0.3
−1
+0.3
+1.5
LSB
LSB
0.9
TBD
TBD
TBD
TBD
mV
Offset temperature coefficient
Gain error
%/°C
%FS
∆%/°C
Gain temperature coefficient
Dynamic AC Characteristics
Room temp
70.6
70.5
70.4
70.1
69.8
69.7
69.4
68.8
67.4
1.1
85
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
LSB
f
= 10MHz
IN
Full temp range
f
IN
f
IN
= 30MHz
= 55MHz
Room temp
Signal-to-noise ratio, SNR
RMS Output noise
f
IN
= 70MHz
Full temp range
f
IN
f
IN
f
IN
= 100MHz
= 150MHz
= 225MHz
Input tied to common-mode
Room temp
dBc
f
IN
= 10MHz
Full temp range
85
dBc
f
IN
f
IN
= 30MHz
= 55MHz
84
dBc
83
dBc
Room temp
80
dBc
Spurious-free dynamic range, SFDR
f
IN
= 70MHz
Full temp range
80
dBc
f
IN
f
IN
f
IN
= 100MHz
= 150MHz
= 225MHz
85
dBc
75
dBc
76
dBc
(1)
(2)
1.68mA per input.
See Recommended Operating Conditions on page 2.
3
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SBAS309 − MAY 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at T = +25°C, full temperature range is T
= −40°C to t
MAX
PP
= +85°C, sampling rate = 105MSPS, 50% clock duty
differential clock, unless otherwise noted.
A
MIN
cycle, AV
= DRV
= 3.3V, DLL On, −1dBFS differential input, and 3V
DD
DD
PARAMETER
CONDITIONS
MIN
TYP
102
101
93
MAX
UNIT
dBc
Room temp
f
= 10MHz
IN
Full temp range
dBc
f
IN
f
IN
= 30MHz
= 55MHz
dBc
88
dBc
Room temp
82
dBc
Second-harmonic, HD2
f
IN
= 70MHz
Full temp range
82
dBc
f
IN
f
IN
f
IN
= 100MHz
= 150MHz
= 225MHz
86
dBc
80
dBc
78
dBc
Room temp
85
dBc
f
IN
= 10MHz
Full temp range
85
dBc
f
IN
f
IN
= 30MHz
= 55MHz
84
dBc
83
dBc
Room temp
80
dBc
Third-harmonic, HD3
f
IN
= 70MHz
Full temp range
80
dBc
f
IN
f
IN
f
IN
f
IN
f
IN
= 100MHz
= 150MHz
= 225MHz
91
dBc
76
dBc
78
dBc
= 10MHz Room temp
= 70MHz Room temp
92
dBc
Worst-harmonic/spur
(other than HD2 and HD3)
89
dBc
Room temp
= 10MHz
70.4
70.3
70.1
69.8
69.2
69.2
69.2
67.8
66.6
83.7
83.6
81.5
80.7
77.2
77.2
82.5
74.1
74.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
f
IN
Full temp range
f
IN
f
IN
= 30MHz
= 55MHz
Room temp
Signal-to-noise + distortion, SINAD
f
IN
= 70MHz
Full temp range
f
IN
f
IN
f
IN
= 100MHz
= 150MHz
= 225MHz
Room temp
f
IN
= 10MHz
Full temp range
dBc
f
IN
f
IN
= 30MHz
= 55MHz
dBc
dBc
Room temp
dBc
Total harmonic distortion, THD
f
IN
= 70MHz
Full temp range
dBc
f
IN
f
IN
f
IN
= 100MHz
= 150MHz
= 225MHz
dBc
dBc
dBc
4
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SBAS309 − MAY 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at T = +25°C, full temperature range is T
= −40°C to t
MAX
PP
= +85°C, sampling rate = 105MSPS, 50% clock duty
differential clock, unless otherwise noted.
A
MIN
cycle, AV
= DRV
= 3.3V, DLL On, −1dBFS differential input, and 3V
DD
DD
PARAMETER
CONDITIONS
= 70MHz
MIN
TYP
MAX
UNIT
Effective number of bits, ENOB
Two-tone intermodulation distortion, IMD
Power Supply
f
IN
11.2
Bits
f = 10.1MHz, 15.1MHz
(−7dBFS each tone)
TBD
TBD
TBD
dBc
dBc
dBc
f = 30.1MHz, 35.1MHz
(−7dBFS each tone)
f = 50.1MHz, 55.1MHz
(−7dBFS each tone)
V
= full-scale, f = 55MHz
IN
IN
AV
Total supply current, I
CC
212
171
TBD
TBD
mA
mA
= DRV
= 3.3V
DD
DD
V
IN
AV
= full-scale, f = 55MHz
IN
= 3.3V
Analog supply current, I
AVDD
= DRV
DD
DD
V
= full-scale, f = 55MHz
= DRV
DD
IN
AV
IN
= 3.3V
Output buffer supply current, I
41
TBD
TBD
TBD
TBD
mA
mW
mW
mW
DRVDD
DD
Analog only
564
700
TBD
Power dissipation
Standby power
Total power with 10pF load on
digital output to ground
With clocks running
DIGITAL CHARACTERISTICS
Typ, min, and max values at T = +25°C, full temperature range is T
= −40°C to t
PP
= +85°C, sampling rate = 105MSPS, 50% clock duty
differential clock, unless otherwise noted.
A
MIN MAX
cycle, AV
= DRV
= 3.3V, DLL On, −1dBFS differential input, and 3V
DD
DD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input current for RESET
Input capacitance
2.4
V
0.8
10
10
V
µA
µA
µA
pF
−20
4
(1)
Digital Outputs
(2)
= 10pF , f = 105MSPS
Low-level output voltage
High-level output voltage
Output capacitance
C
LOAD
C
LOAD
0.3
3.0
3
V
V
S
(2)
= 10pF , f = 105MSPS
S
pF
(1)
(2)
For optimal performance, all digital output lines (D0:D11), including the output clock, should see a similar load.
Equivalent capacitance to ground of (load + parasitics of transmission lines).
5
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SBAS309 − MAY 2004
TIMING CHARACTERISTCS
N + 4
N + 3
N + 2
Analog
Input
Signal
Sample
N
N + 1
N + 17
N + 16
N + 15
tPDI
tA
Input Clock
tSETUP
Output Clock
tHOLD
−
−
−
−
−
−
−
N 1
N
17
N
16
N
15
N
13
N
3
N
2
N
Data Out
(D0−D11)
Data Invalid
16.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
Typ, min, and max values at T = +25°C, full temperature range is T
= −40°C to t
PP
= +85°C, sampling rate = 105MSPS, 50% clock duty
differential clock, unless otherwise noted.
A
MIN
MAX
cycle, AV
= DRV
= 3.3V, DLL On, −1dBFS differential input, and 3V
DD
DD
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Aperture delay, t
Input CLK falling edge to data sampling point
1
ns
fs
A
Aperture jitter (uncertainty) Uncertainty in sampling instant
300
TBD
TBD
Data setup time, t
Data valid to 50% of CLKOUT rising edge
CLKOUT rising edge to data becoming invalid
ns
ns
SETUP
HOLD
Data hold time, t
Input clock falling edge (on which sampling
takes place) to input clock rising edge (on
which the corresponding data is given out)
Data latency, t (Pipe)
16.5
Clock Cycles
D
Propagation delay, t
Data rise time
Input clock rising edge to data valid
Data out 20% to 80%
TBD
2.5
ns
ns
ns
PDI
Data fall time
Data out 80% to 20%
2.5
Output enable (OE) to
output stable delay
2
ms
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D
D
D
Data is loaded at every 16th SCLK falling edge
while SEN is low.
In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D
D
Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
Minimum width of data stream for a valid loading is
16 clocks.
6
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SBAS309 − MAY 2004
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 2. DATA Communication is 2-Byte, MSB First
tSLOADS
tSLOADH
SEN
tWSCLK
tWSCLK
tSCLK
SCLK
tOS
tOH
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 3. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
(1)
MIN
(1)
TYP
(1)
MAX
SYMBOL
PARAMETER
SCLK Period
UNIT
ns
t
50
25
8
SCLK
t
SCLK Duty Cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data Setup Time
50
75
%
WSCLK
t
ns
SLOADS
SLOADH
t
6
ns
t
8
ns
DS
DH
t
Data Hold Time
6
ns
(1)
Typ, min, and max values are characterized, but not production tested.
Table 2. Serial Register Table
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
1
1
0
1
0
0
0
0
0
0
0
0
0
0
DLL
OFF
0
DLL OFF = 0 : internal DLL is on, recommended for
60−105MSPS clock speed
DLL OFF = 1 : internal DLL is off, recommended for
10−80MSPS clock speed
1
1
1
0
0
TP<1> TP<0>
0
0
0
0
0
0
0
0
0
0
0
TP<1:0> − Test modes for output data capture
TP<1> = 0, TP<0> = 0 : Normal mode of operation,
TP<1> = 0
TP<0> = 1 : All output lines are pulled to ’0’, TP<1> = 1
TP<0> = 0 : All output lines are pulled to ’1’, TP<1> = 1
TP<0> = 1 : A continuous stream of ’10’ comes out on
all output lines
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
PDN = 0 : Normal mode of operation, PDN = 1 :
Device is put in power down (low current) mode
7
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SBAS309 − MAY 2004
Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (V
)
DATA FORMAT
CLOCK OUTPUT POLARITY
DFS
1
6
Straight Binary
Data valid on rising edge
V
t
AV
DD
1
DFS
5
12
Two’s Complement
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
AV
u V
u
AV
DD
DD
DFS
3
2
3
7
12
Straight Binary
AV
u V
u
AV
DD
DD
DFS
5
6
Two’s Complement
V
u
AV
DD
DFS
PIN CONFIGURATION
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
DRGND
Reserved
Reserved
Reserved
AVDD
DRGND
47 D1
3
46
45
44
D0 (LSB)
NC
4
NC
5
AGND
6
43 CLKOUT
42 DRGND
AVDD
7
ADS5521
8
41
40
39
AGND
OE
PowerPAD
(Connected to Analog Ground)
9
AVDD
DFS
AVDD
10
CLKP
CLKM 11
38 AGND
12
13
37
36
AGND
AGND
AVDD
AGND
AGND 14
AVDD 15
35 RESET
34 AVDD
16
33
AVDD
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
8
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SBAS309 − MAY 2004
PIN ASSIGNMENTS
TERMINAL
NAME
NO.
OF PINS
12
NO.
I/O
DESCRIPTION
AV
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
I
Analog power supply
Analog ground
DD
A
GND
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
14
I
DRV
49, 58
2
6
I
I
Output driver power supply
Output driver ground
DD
DR
1, 42, 48,
50, 57, 59
GND
NC
44, 45
19
2
1
1
1
—
I
Not connected
INP
Differential analog input (positive)
Differential analog input (negative)
INM
20
I
REFP
29
O
Reference voltage (positive); 0.1µF capacitor in series with a 1Ω
resistor to GND
REFM
30
1
O
Reference voltage (negative); 0.1µF capacitor in series with a 1Ω
resistor to GND
IREF
31
1
1
I
O
I
Current set; 56kΩ resistor to GND; do not connect capacitors
CM
17
Common-mode output voltage
RESET
OE
35
1
Reset (active high), 200kΩ resistor to AV
DD
41
1
I
Output enable (active high)
(1)
Data format and clock out polarity select
DFS
40
1
I
CLKP
10
1
I
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select
CLKM
SEN
11
1
I
4
1
I
SDATA
SCLK
3
1
I
Serial interface data
2
1
I
Serial interface clock
D0 (LSB)−D11 (MSB)
OVR
46, 47, 51−56, 60−63
12
1
O
O
O
Parallel data output
64
43
Over-range indicator bit
CLKOUT
1
CMOS clock out in sync with data
:
NOTE PowerPAD is connected to analog ground.
(1)
The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AV , 5/8 AV , and AV . The thresholds are centered. More details are
DD DD DD
listed in Table 3 on page 8.
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Integral Nonlinearity (INL)
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by FFT
analysis) is reduced by 3dB.
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a “best
straight line” or “best fit” determined by a least square
curve fit. INL is independent from effects of offset, gain or
quantization errors.
Aperture Delay
The delay in time between the falling edge of the input
sampling clock and the actual time at which the sampling
occurs.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
This is the maximum sampling rate where certified
operation is given.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Minimum Conversion Rate
Clock Pulse Width/Duty Cycle
This is the minimum sampling rate where the ADC still
works.
A perfect differential sine wave clock results in a 50% clock
duty cycle on the internal conversion clock. Pulse width
high is the minimum amount of time that the ENCODE
pulse should be left in logic ‘1’ state to achieve rated
performance. Pulse width low is the minimum time that the
ENCODE pulse should be left in a low state (logic ‘0’). At
a given clock rate, these specifications define an
acceptable clock duty cycle.
Nyquist Sampling
When the sampled frequencies of the analog input signal
are below fCLOCK/2, it is called Nyquist sampling. The
Nyquist frequency is fCLOCK/2, which can vary depending
on the sample rate (fCLOCK).
Offset Error
Differential Nonlinearity (DNL)
Offset error is the deviation of output code from
mid-code when both inputs are tied to common-mode.
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation of any single LSB
transition at the digital output from an ideal 1 LSB step at
the analog input. If a device claims to have no missing
codes, it means that all possible codes (for a 14-bit
converter, 16384 codes) are present over the full operating
range.
Propagation Delay
This is the delay between the input clock rising edge and
the time when all data bits are within valid logic levels.
Signal-to-Noise and Distortion (SINAD)
The RMS value of the sine wave fIN (input sine wave for an
ADC) to the RMS value of the noise of the converter from
DC to the Nyquist frequency, including harmonic content.
It is typically expressed in decibels (dB). SINAD includes
harmonics, but excludes DC.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its
measured SINAD using the following formula:
Input(VS )
SINAD + 20Log
SINAD * 1.76
(10) Noise ) Harmonics
ENOB +
6.02
If SINAD is not known, SNR can be used exceptionally to
calculate ENOB (ENOBSNR).
Signal-to-Noise Ratio (without harmonics)
SNR is a measure of signal strength relative to background
noise. The ratio is usually measured in dB. If the incoming
signal strength in µV is VS, and the noise level (also in µV)
is VN, then the SNR in dB is given by the formula:
Effective Resolution Bandwidth
The highest input frequency where the SNR (dB) is
dropped by 3dB for a full-scale input amplitude.
VS
Gain Error
SNR + 20Log
(10) VN
The amount of deviation between the ideal transfer
function and the measured transfer function (with the offset
error removed) when a full-scale analog input voltage is
applied to the ADC, resulting in all 1s in the digital code.
Gain error is usually given in LSB or as a percent of
full-scale range (%FSR).
This is the ratio of the RMS signal amplitude, VS (set 1dB
below full-scale), to the RMS value of the sum of all other
spectral components, VN, excluding harmonics and DC.
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Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
The ratio of the RMS value of the analog input sine wave
to the RMS value of the peak spur observed in the
frequency domain. It may be reported in dBc (that is, it
degrades as signal levels are lowered), or in dBFS (always
related back to converter full-scale). The peak spurious
component may or may not be a harmonic.
THD is the ratio of the RMS signal amplitude of the input
sine wave to the RMS value of distortion appearing at
multiples (harmonics) of the input, typically given in dBc.
Two-Tone Intermodulation Distortion Rejection
The ratio of the RMS value of either input tone (f1, f2) to the
RMS value of the worst third-order intermodulation
product (2f1 − f2; 2f2 − f1). It is reported in dBc.
Temperature Drift
Temperature drift (for offset error and gain error) specifies
the maximum change from the initial temperature value to
the value at TMIN or TMAX
.
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APPLICATION INFORMATION
in a data latency of 16.5 clock cycles, after which the
output data is available as a 12-bit parallel word, coded
in either straight offset binary or binary two’s
complement format.
THEORY OF OPERATION
The ADS5521 is a low-power, 12-bit, 105MSPS,
CMOS, switched capacitor, pipeline ADC that operates
from a single 3.3V supply. The conversion process is
initiated by a falling edge of the external input clock.
Once the signal is captured by the input S&H, the input
sample is sequentially converted by a series of small
resolution stages, with the outputs combined in a digital
correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through
the pipeline every half clock cycle. This process results
INPUT CONFIGURATION
The analog input for the ADS5521 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique, shown in
Figure 4.
SAMPLE
W3a
SAMPLE
PHASE
PHASE
W1a
L1
R1a
C1a
INP
CP1
CP3
R3
SAMPLE
PHASE
W2
CACROSS
SWITCH
L2
R1b
C1b
VINCM
1V
INM
CP2
W1b
CP4
SAMPLE
PHASE
SAMPLE
PHASE
W3a
L1, L2 : 6nh to 10nh effective
Ω
Ω
R1a, R1b : 25 to 35
C1a, C1b : 2.2pF to 2.6pF
CP1, CP2 : 2.5pF to 3.5pF
CP3, CP4, : 1.2pF to 1.8pF
CACROSS : 0.8pF to 1.2pF
Ω
Ω
R3 : 80 to 120
Switches:
Ω
Ω
Ω
Ω
Ω
W1a, W1b : On Resistance: 25 to 35
W2 : On Resistance: 7.5 to 15
3a, W3b : On Resistance: 40 to 60
1a, W1b, W2, W3a, W3b : Off Resistance: 1e10
Ω
W
W
All switches are on in sample phase.
Approximately half of every clock period is a sample phase.
Figure 4. Analog Input Stage
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This differential input topology produces a high level of
AC performance for high sampling rates. It also results
in a very high usable input bandwidth, especially
important for high intermediate-frequency (IF) or
undersampling applications. The ADS5521 requires
each of the analog inputs (INP, INM) to be externally
biased around the common-mode level of the internal
circuitry (CM, pin 17). For a full-scale differential input,
each of the differential lines of the input signal (pins 19
and 20) swings symmetrically between CM + 0.575V
and CM – 0.575V. This means that each input is driven
with a signal of up to CM 0.575V, so that each input
4mA fs
125MSPS
(1)
Where:
f > 60MSPS.
S
This equation helps to design the output capability and
impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of the
ADS5521. TI offers a wide selection of single-ended
operational amplifiers (including the THS3201,
THS3202, OPA847, and OPA695) that can be selected
depending on the application. An RF gain block
amplifier, such as TI’s THS9001, can also be used with
an RF transformer for very high input frequency
has a maximum differential signal of 1.15V for a total
PP
differential input signal swing of 2.3V . The maximum
PP
swing is determined by the two reference voltages, the
top reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
The ADS5521 obtains optimum performance when the
analog inputs are driven differentially. The circuit shown
in Figure 5 shows one possible configuration using an
RF transformer.
applications. The THS4503 is
differential input/output amplifier. Table 4 lists the
recommended amplifiers.
a recommended
When using single-ended operational amplifiers (such
as the THS3201, THS3202, OPA847, or OPA695) to
provide gain, a three-amplifier circuit is recommended
with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the
secondary driving the two differential inputs of the
ADS5521. These three amplifier circuits minimize
even-order harmonics. For very high frequency inputs,
an RF gain block amplifier can be used to drive a
transformer primary; in this case, the transformer
secondary connections can drive the input of the
ADS5521 directly, as shown in Figure 5, or with the
addition of the filter circuit shown in Figure 6.
R0
Z0
Ω
50
Ω
50
INP
1:1
R
50
AC Signal
Source
ADS5521
INM
Ω
CM
ADT1−1WT
Ω
10
µ
0.1 F
1nF
Figure 6 illustrates how RIN and CIN can be placed to
isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the
input noise in the ADC. It is recommended that these
components be included in the ADS5521 circuit layout
when any of the amplifier circuits discussed previously
are used. The components allow fine-tuning of the
circuit performance. Any mismatch between the
differential lines of the ADS5521 input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even-order
harmonics. In this case, special care should be taken to
keep as much electrical symmetry as possible between
both inputs.
Figure 5. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of
an RF transformer. Since the input signal must be
biased around the common-mode voltage of the
internal circuitry, the common-mode voltage (V ) from
CM
the ADS5521 is connected to the center-tap of the
secondary winding. To ensure a steady low-noise V
reference, best performance is obtained when the CM
(pin 17) output is filtered to ground with 0.1µF and
0.01µF low-inductance capacitors.
CM
Output V
(pin 17) is designed to directly drive the
CM
Another possible configuration for lower-frequency sig-
nals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring
DC coupling of the input. Flexible in their configurations
(see Figure 7), such amplifiers can be used for single-
ended-to-differential conversion, signal amplification.
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 4mA (2mA per
input). Equation (1) describes the dependency of the
common-mode current and the sampling frequency:
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Table 4. Recommended Amplifiers to Drive the Input of the ADS5521
INPUT SIGNAL FREQUENCY
DC to 20MHz
RECOMMENDED AMPLIFIER
THS4503
TYPE OF AMPLIFIER
Differential In/Out Amp
Operational Amp
Operational Amp
Operational Amp
Operational Amp
RF Gain Block
USE WITH TRANSFORMER?
No
Yes
Yes
Yes
Yes
Yes
DC to 50MHz
OPA847
OPA695
THS3201
10MHz to 120MHz
Over 100MHz
THS3202
THS9001
−
+5V 5V
RS
RIN
Ω
100
µ
0.1 F
VIN
1:1
INP
OPA695
RT
100
CIN
ADS5521
1000pF
RIN
Ω
R1
INM
Ω
400
CM
AV = 8V/V
(18dB)
R2
57.5
Ω
10
Ω
µ
0.1 F
Figure 6. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
RS
RG
RF
+5V
RT
+3.3V
µ
µ
0.1 F
10 F
RIN
RIN
INP
ADS5521
12-Bit/105MSPS
VOCM
INM
µ
1 F
THS4503
CM
µ
µ
0.1 F
10 F
Ω
10
−
5V
RG
RF
µ
0.1 F
Figure 7. Using the THS4503 with the ADS5521
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POWER SUPPLY SEQUENCE
CLOCK INPUT
The ADS5521 requires a power-up sequence where the
The ADS5521 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5kΩ
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17), as shown in Figure 9.
DRV
supply must be at least 0.4V by the time the
DD
AV
supply reaches 3.0V. Powering up both supplies
DD
at the same time will work without any problem. If this
sequence is not followed, the device may stay in
power-down mode.
POWER DOWN
The device will enter power-down in one of two ways:
either by reducing the clock speed to between DC and
1MHz, or by setting a bit through the serial
programming interface. Using the reduced clock speed,
the power-down may be initiated for clock frequencies
below 10MHz. For clock frequencies between 1MHz
and 10Mhz, this can vary from device to device, but will
power-down for clock speeds below 1MHz.
CM
CM
Ω
Ω
5k
5k
CLKP
CLKM
The device can be powered down by programming the
internal register (see Serial Programming Interface
section). The outputs become tri-stated and only the
internal reference is powered up to shorten the
power-up time. The Power-Down mode reduces power
dissipation to a minimum of 180mW.
6pF
3pF
3pF
REFERENCE CIRCUIT
Figure 9. Clock Inputs
The ADS5521 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1µF
decoupling capacitor in series with a 1Ω resistor, as
shown in Figure 8. In addition, an external 56.2kΩ
resistor should be connected from IREF (pin 31) to
AGND to set the proper current for the operation of the
ADC, as shown in Figure 8. No capacitor should be
connected between pin 31 and ground; only the 56.2kΩ
resistor should be used.
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01µF capacitor, while CLKP is AC-coupled with a
0.01µF capacitor to the clock source, as shown in
Figure 10.
µ
0.01 F
Square Wave
or Sine Wave
CLKP
ADS5521
CLKM
(3VPP
)
µ
0.01 F
Ω
Ω
1
REFP
REFM
29
30
µ
1 F
1
Figure 10. AC-Coupled, Single-Ended Clock Input
µ
1 F
The ADS5521 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01µF
capacitors, as shown in Figure 11.
31 IREF
Ω
56k
Figure 8. REFP, REFM, and IREF Connections for
Optimum Performance
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SBAS309 − MAY 2004
amplitudes without exceeding the supply rails and
absolute maximum ratings of the ADC clock input.
Figure 13 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, refer to the ADS5521EVM User’s Guide,
available for download from www.ti.com.
µ
0.01 F
CLKP
ADS5521
CLKM
Differential Square Wave
or Sine Wave
(3VPP
)
µ
0.01 F
Figure 11. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 50%
duty cycle should be provided. Figure 12 shows the
performance variation of the ADC versus clock duty
cycle.
TBD
Figure 13. AC Performance vs Clock Amplitude
INTERNAL DLL
TBD
In order to obtain the fastest sampling rates achievable
with the ADS5521, the device uses an internal digital
phase lock loop (DLL). Nevertheless, the limited
frequency range of operation of DLL degrades the
performance at clock frequencies below 60MSPS. In
order to operate the device below 60MSPS, the internal
DLL must be shut off using the DLL OFF mode
described in the Serial Interface Programming section.
The Typical Performance Curves show the
performance obtained in both modes of operation: DLL
ON (default), and DLL OFF. In either of the two modes,
the device will enter power down mode if no clock or
slow clock is provided. The limit of the clock frequency
where the device will function properly is ensured to be
over 10MHz.
Figure 12. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter will further
improve as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
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OUTPUT INFORMATION
SERIAL PROGRAMMING INTERFACE
The ADC provides 12 data outputs (D11 to D0, with D11
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
The ADS5521 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power-up by applying a 2µs (minimum) high pulse on
RESET (pin 35); this also resets the entire ADC and
sets the data outputs to low. This pin has a 200kΩ
Two different output formats (straight offset binary or
two’s complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to tri-state the outputs.
internal pull-up resistor to AV . The programming is
DD
done through a three-wire interface. The timing diagram
and serial register setting in the Serial Programing
Interface section describe the programming of this
register.
Table 2 shows the different modes and the bit values to
be written on the register to enable them.
The output circuitry of the ADS5521 has being designed
to minimize the noise produced by the transients of the
data switching, and in particular its coupling to the ADC
analog circuitry. Output D2 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
rate described in the timing diagram of Figure 1, as long
as all outputs (including CLKOUT) have a similar load
as the one at D2 (pin 51). This circuit also reduces the
sensitivity of the output timing versus supply voltage or
temperature. External series resistors with the output
are not necessary.
Note that some of these modes may modify the
standard operation of the device and possibly vary the
performance with respect to the typical data shown in
this data sheet.
17
PACKAGE OPTION ADDENDUM
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25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ADS5521IPAP
PREVIEW
PREVIEW
HTQFP
HTQFP
PAP
64
64
160
None
None
Call TI
Call TI
Call TI
Call TI
ADS5521IPAPR
PAP
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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相关型号：
ADS5525IRGZ25
1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN-48
TI
ADS5525IRGZRG4
12-bit, 170 MSPS ADC with User selectable DDR LVDS or Parallel CMOS outputs 48-VQFN -40 to 85
TI
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