DAC2904Y/250 [BB]
Dual, 14-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER; 双通道， 14位， 125MSPS数位类比转换器
| 型号： | DAC2904Y/250 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Dual, 14-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总19页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC2904
DAC2904
SBAS198B – NOVEMBER 2003
Dual, 14-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● 125MSPS UPDATE RATE
APPLICATIONS
● COMMUNICATIONS:
Base Stations, WLL, WLAN
Baseband I/Q Modulation
●
SINGLE SUPPLY: +3.3V or +5V
● HIGH SFDR: 78dB at fOUT = 10MHz
● LOW GLITCH: 2pVs
● MEDICAL/TEST INSTRUMENTATION
● ARBITRARY WAVEFORM GENERATORS (ARB)
● DIRECT DIGITAL SYNTHESIS (DDS)
● LOW POWER: 310mW
● INTERNAL REFERENCE
● POWER-DOWN MODE: 23mW
The DAC2904 combines high dynamic performance with a
high update rate to create a cost-effective solution for a wide
variety of waveform-synthesis applications:
DESCRIPTION
The DAC2904 is a monolithic, 14-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is opti-
mized to provide high dynamic performance while dissipating
only 310mW.
• Pin compatibility between family members provides 10-bit
(DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904)
resolution.
Operating with high update rates of up to 125MSPS, the
DAC2904 offers exceptional dynamic performance, and
enables the generation of very-high output frequencies suit-
able for “Direct IF” applications. The DAC2904 has been
optimized for communications applications in which sepa-
rate I and Q data are processed while maintaining tight-gain
and offset matching.
• Pin compatible to the AD9767 dual DAC.
• Gain matching is typically 0.5% of full-scale, and offset
matching is specified at 0.02% max.
• The DAC2904 utilizes an advanced CMOS process; the
segmented architecture minimizes output-glitch energy,
and maximizes the dynamic performance.
• All digital inputs are +3.3V and +5V logic compatible. The
DAC2904 has an internal reference circuit, and allows use
in a multiplying configuration.
Each DAC has a high-impedance differential-current output,
suitable for single-ended or differential analog-output con-
figurations.
• The DAC2904 is available in a TQFP-48 package, and is
specified over the extended industrial temperature range of
–40°C to +85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002-2003, Texas Instruments
Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VA to AGND ........................................................................ –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD ............................................................................... –6V to +6V
CLK, PD to DGND ...................................................... –0.3V to VD + 0.3V
D0-D9 to DGND .......................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND ........................................................ –1V to VA + 0.3V
BW, BYP to AGND ..................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND ................................................. –0.3V to VA + 0.3V
INT/EXT to AGND ...................................................... –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature ..................................................................... +125°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
SPECIFIED
DRAWING
NUMBER
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DAC2904Y
TQFP-48
355
PFB
–40°C to +85°C
DAC2904Y
DAC2904Y/250
DAC2904Y/1K
Tape and Reel
Tape and Reel
"
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC2904Y/1K” will get a single 1000-piece Tape and Reel.
PRODUCT
EVM ORDERING NUMBER
COMMENT
DAC2904
DAC2904-EVM
Fully populated evaluation board. See user manual for details.
ELECTRICAL CHARACTERISTICS
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, 50ý doubly-terminated, unless otherwise noted. Independant Gain Mode.
DAC2904Y
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
14
Bits
Output Update Rate (fCLOCK
)
125
MSPS
STATIC ACCURACY(1)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TA = +25°C
TA = +25°C
±4.0
±5.0
LSB
LSB
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
fOUT = 1MHz, fCLOCK = 50MSPS
To Nyquist
0dBFS Output
–6dBFS Output
–12dBFS Output
71
82
77
72
82
81
81
78
72
80
69
69
64
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fOUT = 1MHz, fCLOCK = 26MSPS
fOUT = 2.18MHz, fCLOCK = 52MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 10.4MHz, fCLOCK = 78MSPS
fOUT = 15.7MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 20.1MHz, fCLOCK = 125MSPS
fOUT = 40.2MHz, fCLOCK = 125MSPS
Spurious-Free Dynamic Range within a Window
fOUT = 1.0MHz, fCLOCK = 50MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 5.26MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 125MSPS
Total Harmonic Distortion (THD)
fOUT = 1MHz, fCLOCK = 50MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 5.26MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 125MSPS
Multitone Power Ratio
fOUT = 2.0MHz to 2.99MHz, fCLOCK = 65MSPS
Signal-to-Noise Ratio (SNR)
fOUT = 5.02MHz, fCLOCK = 50MHz
Signal-to-Noise and Distortion (SINAD)
fOUT = 5.02MHz, fCLOCK = 50MHz
2MHz Span
10MHz Span
10MHz Span
10MHz Span
80
90
88
88
88
dBc
dBc
dBc
dBc
–79
–77
–76
–75
–70
dBc
dBc
dBc
dBc
8 Tone with 110kHz Spacing
0dBFS Output
80
68
67
dBc
dBc
dBc
0dBFS Output
0dBFS Output
DAC2904
SBAS198B
2
ELECTRICAL CHARACTERISTICS (Cont.)
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, 50ý doubly terminated, unless otherwise noted. Independant Gain Mode.
DAC2904Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (Cont.)
Channel Isolation
fOUT = 1MHz, fCLOCK = 52MSPS
fOUT = 20MHz, fCLOCK = 125MSPS
Output Settling Time(2)
Output Rise Time(2)
85
77
30
2
dBc
dBc
ns
to 0.1%
10% to 90%
10% to 90%
ns
Output Fall Time(2)
2
ns
Glitch Impulse
2
pV-s
DC ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error—Full-Scale
Gain Error
All Bits HIGH, IOUT
2
20
+1.25
+5
mA
V
–1.0
–5
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
With Internal Reference
+5V, ±10%
±1
±1
%FSR
%FSR
%FSR
ppmFSR/°C
%FSR
ppmFSR/°C
%FSR/V
%FSR/V
pA/ Hz
pA/šHz
kΩ
–2.5
–2.0
+2.5
+2.0
Gain Matching
0.5
±50
Gain Drift
Offset Error
–0.02
+0.02
Offset Drift
±0.2
Power-Supply Rejection, +VA
Power-Supply Rejection, +VD
Output Noise
–0.2
+0.2
+3.3V, ±10%
–0.025
+0.025
IOUT = 20mA, RLOAD = 50Ω
IOUT = 2mA
50
30
200
6
Output Resistance
Output Capacitance
I
OUT, IOUT to Ground
pF
REFERENCE/CONTROL AMP
Reference Voltage
+1.18
+0.5
+1.25
±50
100
0.3
+1.31
+1.25
V
Reference Voltage Drift
ppmFSR/°C
Reference Output Current
Reference Multiplying Bandwidth
Input Compliance Range
nA
MHz
V
DIGITAL INPUTS
Logic Coding
Straight Binary
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Voltage, VIH
Logic Low Voltage, VIL
+VD = +5V
+VD = +5V
+VD = 3.3V
+VD = 3.3V
+VD = 3.3V
+VD = 3.3V
3.5
2
5
0
V
V
1.2
0.8
3
V
0
V
(4)
Logic High Current, IIH
±10
±10
5
µA
µA
pF
Logic Low Current
Input Capacitance
POWER SUPPLY
Supply Voltages
+VA
+3.0
+3.0
+5
+5.5
+5.5
V
V
+VD
+3.3
Supply Current
(5)
IVA
+VA = +5V, lOUT = 20mA
Power-Down Mode
58
1.7
4.2
17
65
3
mA
mA
(5)
IVA
(5)
IVD
7
mA
(6)
IVD
19.5
350
390
mA
Power Dissipation(5)
Power Dissipation(6)
Power Dissipation(5)
Power Dissipation
Thermal Resistance, TQFP-48
θJA
+VA = +5V, +VD = 3.3V, lOUT = 20mA
+VA = +5V, +VD = 3.3V, lOUT = 20mA
+VA = +5V, +VD = 3.3V, lOUT = 2mA
Power-Down Mode
310
348
130
23
mW
mW
mW
mW
38
60
13
°C/W
°C/W
θJC
TEMPERATURE RANGE
Specified
Ambient
Ambient
–40
–40
+85
+85
°C
°C
Operating
NOTES: (1) At output lOUT, while driving a virtual ground. (2) Measured single-ended into 50ý load. (3) Nominal full-scale output current is 32 • IREF; see Application
section for details. (4) Typically 45µA for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz. (6) Measured
at fCLOCK = 100MSPS and fOUT = 40MHz.
DAC2904
SBAS198B
3
PIN CONFIGURATION
Top View
TQFP-48
48 47 46 45 44 43 42 41 40 39 38 37
D13_1 (MSB)
1
2
3
4
5
6
7
8
9
36 D0-2
35 D1-2
34 D2_2
33 D3_2
32 D4_2
31 D5_2
30 D6_2
29 D7_2
28 D8_2
27 D9_2
26 D10_2
25 D11_2
D12_1
D11_1
D10_1
D9_1
D8_1
D7_1
D6_1
D5_1
DAC2904
D4_1 10
D3_1 11
D2_1 12
13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTIONS
PIN
DESIGNATOR
DESCRIPTION
1-14
15
D[13:0]_1
DGND
+VD
Data Port DAC1, Data Bit 13 (MSB) to Bit 0 (LSB).
Digital Ground
16
Digital Supply, +3.0V to +5.5V
DAC1 Input Latches Write Signal
Clock Input DAC1
17
WRT1
CLK1
18
19
CLK2
Clock Input DAC2
20
WRT2
DGND
+VD
DAC2 Input Latches Write Signal
Digital Ground
21
22
Digital Supply, +3.0V to +5.5V
Data Port DAC2, Data Bit 13 (MSB) to Bit 0 (LSB).
23-36
37
D[13:0]_2
PD
Power-Down Function Control Input; “H” = DAC in power-down mode; “L” = DAC in normal operation (Internal pull-down for default “L”).
Analog Ground
38
AGND
39
IOUT
IOUT
2
2
Current Output DAC2. Full-scale with all bits of data port 2 high.
Complementary Current Output DAC2. Full-scale with all bits of data port 2 low.
Full-Scale Adjust, DAC2. Connect External RSET Resistor
40
41
FSA2
GSET
REFIN
42
Gain-Setting Mode (H = 1 Resistor, L = 2 Resistors)
43
Internal Reference Voltage output; External Reference Voltage input. Bypass with 0.1µF to AGND for internal reference
operation.
44
45
46
47
48
FSA1
Full-Scale Adjust, DAC1. Connect External RSET Resistor
IOUT
IOUT
1
1
Complementary Current Output DAC1. Full-scale with all bits of data port 1 low.
Current Output DAC1. Full-scale with all bits of data port 1 high.
Analog Supply, +3.0V to +5.5V
+VA
NC
No Connection
DAC2904
SBAS198B
4
TIMING DIAGRAM
tS
tH
DATA IN
D[13:0](n)
D[13:0](n + 1)
tLPW
WRT1
WRT2
tCPW
CLK1
CLK2
tSET
IOUT
1
IOUT
IOUT
50%
(n)
(n + 1)
I
OUT2
tPD
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tS
tH
Input Setup Time
Input Hold Time
Latch/Clock Pulsewidth
Delay Rising CLK Edge to
Rising WRT Edge
2
1.5
3.5
0
ns
ns
ns
ns
t
LPW, tCPW
4
tCW
tPW – 2
tPD
tSET
Propagation Delay
Settling Time (0.1%)
1
30
ns
ns
DIGITAL INPUTS AND TIMING
The two converter channels within the DAC2904 consist of
two independent, 14-bit, parallel data ports. Each DAC-
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2904 results in a defined sequence for the WRT and
CLK signals, expressed by parameter ‘tCW’. A correct tim-
ing is observed when the rising edge of CLK occurs at the
same time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.
The data input ports of the DAC2904 accepts a standard
positive coding with data bit D13 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetric duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the set-up and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2904 are CMOS compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage; Vth = +VD/2 (±20% tolerance). The DAC2904
is designed to operate with a digital supply (+VD) of +3.0V
to +5.5V.
DAC2904
SBAS198B
5
TYPICAL CHARACTERISTICS
TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted.
TYPICAL DNL
TYPICAL INL
6
5
4
3
4
2
3
1
2
0
1
0
–1
–2
–3
–4
–1
–2
–3
–4
0
0
0
2k
4k
6k
8k
10k
12k
14k
16k
0
2k
4k
6k
8k
10k
12k
14k
16k
Code
Code
SFDR vs fOUT AT 52MSPS
SFDR vs fOUT AT 26MSPS
90
85
80
75
70
65
60
90
85
80
75
70
65
60
–6dBFS
0dBFS
0dBFS
–6dBFS
–12dBFS
–12dBFS
5
10
15
20
25
0
2
4
6
8
10
12
fOUT (MHz)
f
OUT (MHz)
SFDR vs fOUT AT 100MSPS
SFDR vs fOUT AT 78MSPS
85
80
75
70
65
60
55
50
85
80
75
70
65
60
55
0dBFS
–6dBFS
–6dBFS
–12dBFS
–12dBFS
0dBFS
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
fOUT (MHz)
f
OUT (MHz)
DAC2904
SBAS198B
6
TYPICAL CHARACTERISTICS (Cont.)
TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted.
SFDR vs IOUTFS and fOUT at 78MSPS, 0dBFS
SFDR vs fOUT AT 125MHz
85
80
75
70
65
60
55
50
82
80
78
76
74
72
70
68
66
64
62
20mA
10mA
–6dBFS
–12dBFS
5mA
0dBFS
0
10
20
30
OUT (MHz)
40
50
60
0
5
10
15
OUT (MHz)
20
25
f
f
SFDR AT 125MSPS vs TEMPERATURE
2MHz
GAIN AND OFFSET DRIFT
Offset Error
0.8
0.6
0.004
0.003
0.002
0.001
0
90
85
80
75
70
65
60
55
50
0.4
10MHz
0.2
20MHz
40MHz
0
–0.2
–0.4
–0.6
–0.8
–0.001
–0.002
–0.003
–0.004
Gain Error
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80 85
Temperature (°C)
Temperature (°C)
IVD vs RATIO AT +VD = +3.3V
125MSPS
IVA vs IOUTFS
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
100MSPS
78MSPS
52MSPS
26MSPS
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
0
5
10
15
20
25
Ratio (FOUT/FCLK
)
I
OUTFS (mA)
DAC2904
SBAS198B
7
TYPICAL CHARACTERISTICS (Cont.)
TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted.
SINGLE-TONE SFDR
SINGLE-TONE SFDR
10
0
10
0
fCLOCK = 100MSPS
OUT = 20.2MHz
Amplitude = 0dBFS
fCLOCK = 52MSPS
OUT = 5.23MHz
Amplitude = 0dBFS
f
f
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
5.2
10.4
15.6
20.8
26
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
DUAL-TONE SFDR
FOUR-TONE SFDR
10
0
10
0
fCLOCK = 78MSPS
fCLOCK = 50MSPS
f
OUT1 = 9.44MHz
OUT2 = 10.44MHz
Amplitude = 0dBFS
f
f
f
f
OUT1 = 6.25MHz
OUT2 = 6.75MHz
OUT3 = 7.25MHz
OUT4 = 7.75MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
f
–20
–30
–40
–50
–60
–70
–80
–90
Amplitude = 0dBFS
0
7.8
15.6
23.4
31.2
39
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
WCDMA-ACPR
–30
–40
–50
–60
–70
–80
–90
fCLOCK = 61.44MSPS
PCHANNEL = –13dBm
ACPR = –69.2dB
–100
–110
–120
–130
Center 15.36MHz; Span 14MHz
DAC2904
SBAS198B
8
DAC TRANSFER FUNCTION
APPLICATION INFORMATION
THEORY OF OPERATION
Each of the DACs in the DAC2904 has a set of complemen-
tary current output, IOUT1 and IOUT2. The full-scale output
current, IOUTFS, is the summation of the two complementary
output currents:
The architecture of the DAC2904 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a full-
scale output current of up to 20mA, as shown in Figure 1. An
internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output
summing node, IOUT or IOUT. The complementary outputs
deliver a differential output signal, which improves the
dynamic performance through reduction of even-order har-
monics, common-mode signals (noise), and double the peak-
to-peak output signal swing by a factor of two, compared to
single-ended operation.
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/16384)
(2)
(3)
IOUT = IOUTFS • (16383 - Code/16384)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the refer-
ence current IREF, which is determined by the reference
The segmented architecture results in a significant reduction
of the glitch energy, improves the dynamic performance
(SFDR), and DNL. The current outputs maintain a very high
output impedance of greater than 200ký.
voltage and the external setting resistor, RSET
.
The full-scale output current is determined by the ratio of the
internal reference voltage (1.25V) and an external resistor,
RSET. The resulting IREF is internally multiplied by a factor
of 32 to produce an effective DAC output current that can
IOUTFS = 32 • IREF = 32 • VREF/RSET
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
range from 2mA to 20mA, depending on the value of RSET
.
The DAC2904 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the cur-
rent source array with its associated switches, and the
reference circuitry.
VOUT = IOUT • RLOAD
VOUT = IOUT • RLOAD
(5)
(6)
+VD
+VD
+VA
l
OUT1
Data Input
Port 1
D[13:0]_1
DAC1
Segmented Switches
Current Sources
Input
Latch 1
DAC
Latch 1
lOUT1
REFIN
WRT1
CLK1
CLK2
WRT2
FSA1
FSA2
GSET
PD
Reference
Control Amplifier
DAC2904
lOUT
2
Data Input
Port 2
D[13:0]_2
DAC2
Segmented Switches
Current Sources
Input
Latch 2
DAC
Latch 2
lOUT2
DGND
DGND
AGND
FIGURE 1. Block Diagram of the DAC2904.
DAC2904
SBAS198B
9
The value of the load resistance is limited by the output
compliance specification of the DAC2904. To maintain
specified linearity performance, the voltage for IOUT and
IOUT should not exceed the maximum allowable compliance
range.
be adapted to the output of the DAC2904 by selecting a
suitable transformer while maintaining optimum voltage
levels at IOUT and IOUT. Furthermore, using the differential
output configuration in combination with a transformer will
be instrumental for achieving excellent distortion perfor-
mance. Common-mode errors, such as even-order harmon-
ics or noise, can be substantially reduced. This is particularly
the case with high output frequencies.
The two single-ended output voltages can be combined to
find the total differential output swing:
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a slightly reduced perfor-
mance level.
(2• Code–16383)
VOUTDIFF=VOUT– V
=
• IOUTFS• R
LOAD(7)
OUT
16384
ANALOG OUTPUTS
The DAC2904 provides two complementary current out-
puts, IOUT and IOUT. The simplified circuit of the analog
output stage representing the differential topology is shown
in Figure 2. The output impedance of IOUT and IOUT results
from the parallel combination of the differential switches,
along with the current sources and associated parasitic
capacitances.
OUTPUT CONFIGURATIONS
The current outputs of the DAC2904 allow for a variety of
configurations, some of which are illustrated in Table I. As
mentioned previously, utilizing the converter’s differential
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
or a differential amplifier configuration. The transformer
configuration is ideal for most applications with ac coupling,
while op amps will be suitable for a DC-coupled configura-
tion.
+VA
DAC2904
INPUT CODE (D13 - D0)
IOUT
IOUT
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0000
20mA
10mA
0mA
0mA
10mA
20mA
TABLE I. Input Coding versus Analog Output Current.
IOUT
RL
IOUT
RL
The single-ended configuration may be considered for appli-
cations requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground will convert
the output current into a ground-referenced voltage signal.
To improve on the DC linearity by maintaining a virtual
ground, an I-to-V or op-amp configuration may be consid-
ered.
FIGURE 2. Equivalent Analog Output.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC2904, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
an analog supply of +VA = 5V. Note that the compliance
range decreases to about 1V for a selected output current of
IOUTFS = 2mA. Care should be taken that the configuration
of DAC2904 does not exceed the compliance range to avoid
degradation of the distortion performance and integral lin-
earity.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of convert-
ing the differential output signal into a single-ended signal
while achieving excellent dynamic performance (see Figure 3).
The appropriate transformer should be carefully selected based
on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of
significantly reducing common-mode signals, thus improving
the dynamic performance over a wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio (winding
ratio), the transformer can be used to provide optimum imped-
ance matching while controlling the compliance voltage for the
converter outputs. The model shown, ADTT1-1 (by Mini-
Circuits), has a 1:1 ratio and may be used to interface the
DAC2904 to a 50Ω load. This results in a 25Ω load for each of
the outputs, IOUT and IOUT. The output signals are AC coupled
and inherently isolated because of its magnetic coupling.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5Vp-p. This is the case for a 50Ω doubly terminated load
and a 20mA full-scale output current. A variety of loads can
DAC2904
SBAS198B
10
As shown in Figure 3, the transformer’s center tap is con-
nected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RL,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at RL • IOUTFS/2. However, in
this case, the two resistors, RL, must be used to enable the
necessary DC-current flow for both outputs.
The OPA680 is configured for a gain of two. Therefore,
operating the DAC2904 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate off of a dual power supply (±5V). The tolerance
of the resistors typically sets the limit for the achievable
common-mode rejection. An improvement can be obtained
by fine tuning resistor R4.
This configuration typically delivers a lower level of AC
performance than the previously discussed transformer solu-
tion because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capa-
bilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The AC performance of this circuit may
be improved by adding a small capacitor, CDIFF, between the
outputs IOUT and IOUT (see Figure 4). This will introduce a
real pole to create a low-pass filter in order to slew-limit the
DAC’s fast output signal steps, which otherwise could drive
the amplifier into slew-limitations or into an overload con-
dition; both would cause excessive distortion. The differ-
ence amplifier can easily be modified to add a level shift for
applications requiring the single-ended output voltage to be
unipolar, i.e., swing between 0V and +2V.
ADTT1-1
(Mini-Circuits)
1:1
IOUT
RL
50Ω
RS
RDIFF
DAC2904
50Ω
100Ω
IOUT
RL
50Ω
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
The circuit example of Figure 5 shows the signal output
currents connected into the summing junctions of the dual
voltage-feedback op amp OPA2680 that is set up as a
transimpedance stage, or ‘I-to-V converter’. With this cir-
cuit, the DAC’s output will be kept at a virtual ground,
minimizing the effects of output impedance variations, which
results in the best DC linearity (INL). As mentioned previ-
ously, care should be taken not to drive the amplifier into
slew-rate limitations, and produce unwanted distortion.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC2904 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor
values shown were selected to result in a symmetric 25Ω
loading for each of the current outputs since the input
impedance of the difference amplifier is in parallel to resis-
tors RL, and should be considered.
+5V
50Ω
1/2
OPA2680
–VOUT = IOUT • RF1
RF1
CF1
DAC2904
R2
402Ω
IOUT
CD1
R1
200Ω
IOUT
RF2
CF2
VOUT
DAC2904
OPA680
IOUT
CD2
IOUT
R3
200Ω
COPT
–5V +5V
1/2
OPA2680
RL
28.7Ω
R4
402Ω
RL
26.1Ω
–VOUT = IOUT • RF2
50Ω
–5V
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
DAC2904
SBAS198B
11
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
IOUTFS = 20mA
VOUT = 0V to +0.5V
IOUT
DAC2904
IOUT
50Ω
50Ω
25Ω
(8)
FIGURE 6. Driving a Doubly Terminated 50Ω Cable Directly.
with GBP = Gain Bandwidth Product of OPA
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor, may be mutu-
ally adjusted to provide the desired output signal swing and
performance.
which will give a corner frequency f-3dB of approximately:
(9)
INTERFACING ANALOG
QUADRATURE MODULATORS
The full-scale output voltage is simply defined by the prod-
uct of IOUTFS • RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital commu-
nications. In this application, the DAC is followed by an
analog quadrature modulator, modulating an IF carrier with
the baseband data, as shown in Figure 7. Often, the input
stages of these quadrate modulators consist of npn-type
transistors that require a DC bias (base) voltage of > 0.8V.
The wide output compliance range (–10V to +1.25V) allows
for a direct DC–coupling between the DAC2902 and the
quadrature modulator.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
Figure 8 shows an example of a DC-coupled interface with
DC level-shifting, using a precision resistor network. An ac-
coupled interface, see Figure 9, has the advantage that the
common-mode levels at the input of the modulator can be set
independently of those at the output of the DAC. Further-
more, no voltage loss is obtained in this setup.
VOUT ~ 0Vp to 1.20Vp
VIN ~ 0.6Vp to 1.8Vp
IIN
IREF
IIN
DAC2904
IOUT
1
IREF
I
OUT1
Signal
Conditioning
∑
RF
QIN
IOUT
2
QREF
I
OUT2
Quadrature Modulator
FIGURE 7. Generic Interface to a Quadrature Modulator. Signal Conditioning (Level-Shifting) May Be Required to Ensure
Correct DC Common-Mode Levels At the Input of the Quadrature Modulator.
DAC2904
SBAS198B
12
ence current, IREF, which is determined by the ratio of VREF
and RSET (see Equation 10). The full-scale output current,
IOUTFS, results from multiplying IREF by a fixed factor of 32.
VDC
Using the internal reference, a 2kΩ resistor value results in
a full-scale output of approximately 20mA. Resistors with a
tolerance of 1% or better should be considered. Selecting
higher values, the output current can be adjusted from 20mA
down to 2mA. Operating the DAC2904 at lower than 20mA
output currents may be desirable for reasons of reducing the
total power consumption, improving the distortion perfor-
mance, or observing the output compliance voltage limita-
tions for a given load condition.
R3
VOUT
VOUT
1
1
R4
IOUT
1
DAC2904
IOUT
1
1
It is recommended to bypass the REFIN pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
0.3MHz.
IOUT
1
IOUT
R5
+5V
FIGURE 8. DC-Coupled Interface to Quadrature Modulator
Applying Level Shifting.
+VA
DAC2904
VREF
IREF
=
INTERNAL REFERENCE OPERATION
RSET
FSA
The DAC2904 has an on-chip reference circuit which com-
prises a 1.25V bandgap reference and two control amplifi-
Ref
Current
Sources
Control
Amp
REFIN
RSET
2kΩ
ers, one for each DAC. The full-scale output current, IOUTFS
,
of the DAC2904 is determined by the reference voltage,
VREF, and the value of resistor RSET. IOUTFS can be calcu-
lated by:
0.1µF
+1.25V Ref.
IOUTFS = 32 • IREF = 32 • VREF / RSET
(10)
As shown in Figure 10, the external resistor RSET connects
to the FSA pin (Full-Scale Adjust). The reference control
amplifier operates as a V-to-I converter producing a refer-
FIGURE 10. Internal Reference Configuration.
VDC
R1
IOUT
1
DAC2904
0.01µF
IOUT
1
VOUT
VOUT
1
1
IOUT
1
0.01µF
I
OUT1
50Ω
50Ω
RLOAD
R2
FIGURE 9. AC-Coupled Interface to Quadrature Modulator Applying Level Shifting.
DAC2904
SBAS198B
13
GAIN SETTING OPTIONS
EXTERNAL REFERENCE OPERATION
The full-scale output current on the DAC2904 can be set two
ways: either for each of the two DAC channels independently
or for both channels simultaneously. For the independent gain
set mode, the GSET pin (pin 42) must be LOW (i.e. connected
to AGND). In this mode, two external resistors are required—
one RSET connected to the FSA1 pin (pin 44) and the other to
the FSA2 pin (pin 41). In this configuration, the user has the
flexibility to set and adjust the full-scale output current for each
DAC independently, allowing for the compensation of possible
gain mismatches elsewhere within the transmit signal path.
The internal reference can be disabled by simply applying an
external reference voltage into the REFIN pin, which in this
case functions as an input, as shown in Figure 8. The use of
an external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input.
Alternatively, bringing the GSET pin HIGH (i.e. connected to
+VA), the DAC2904 will switch into the simultaneous gain set
mode. Now the full-scale output current of both DAC chan-
nels is determined by only one external RSET resistor con-
nected to the FSA1 pin. The resistor at the FSA2 pin may be
removed, however this is not required since this pin is not
functional in this mode and the resistor has no effect to the
gain equation. The formula for deriving the correct RSET
remains unchanged, e.g. RSET = 2ký will result in a 20mA
output for both DACs.
POWER-DOWN MODE
The DAC2904 features a power-down function which can
be used to reduce the total supply current to less than 6mA
over the specified supply range of 3.0V to 5.5V. Applying
a logic HIGH to the PD pin will initiate the power-down
mode, while a logic LOW enables normal operation. When
left unconnected, an internal active pull-down circuit will
enable the normal operation of the converter.
+5V
+VA
DAC2904
VREF
IREF
=
RSET
FSA
Ref
Control
Amp
Current
Sources
REFIN
External
Reference
RSET
+1.25V Ref.
FIGURE 11. External Reference Configuration.
DAC2904
SBAS198B
14
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Low noise is required for all supply and ground connections
to the DAC2904. It is recommended to use a multilayer PCB
utilizing separate power and ground planes. Mixed signal
designs require particular attention to the routing of the
different supply currents and signal traces. Generally, analog
supply and ground planes should only extend into analog
signal areas, such as the DAC output signal and the refer-
ence signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can
be realized with a short track of approximately 1/8 inch
(3mm).
Proper grounding and bypassing, short lead length, and the use
of ground planes are particularly important for high-frequency
designs. Multilayer PCBs are recommended for best perfor-
mance since they offer distinct advantages such as minimiza-
tion of ground impedance, separation of signal layers by
ground layers, etc.
The DAC2904 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1µF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. There-
fore they should be located as close as physically possible to
those device leads. Whenever possible, the capacitors should
be located immediately under each pair of supply/ground
pins on the reverse side of the pc board. This layout ap-
proach will minimize the parasitic inductance of component
leads and PCB runs.
The power to the DAC2904 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decou-
pling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage, which can then
be connected to the +VA supply pin of the DAC2904.
Further supply decoupling with surface-mount tantalum ca-
pacitors (1µF to 4.7µF) may be added as needed in proxim-
ity of the converter.
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC2904
SBAS198B
15
PACKAGE DRAWINGS
DAC2904
SBAS198B
16
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
Drawing
DAC2904Y/1K
DAC2904Y/250
ACTIVE
ACTIVE
PFB
48
48
1000
250
None
None
Call TI
Call TI
Call TI
Call TI
PFB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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DAC2904Y/2K
IC PARALLEL, WORD INPUT LOADING, 0.03 us SETTLING TIME, 14-BIT DAC, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48, Digital to Analog Converter
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