DAC8801IDRBT [BB]
14-Bit, Serial Input Multiplying Digital-to-Analog Converter; 14位串行输入乘法数位类比转换器
| 型号： | DAC8801IDRBT |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 14-Bit, Serial Input Multiplying Digital-to-Analog Converter |
| 文件： | 总16页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
14-Bit, Serial Input Multiplying Digital-to-Analog Converter
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
14-Bit Monotonic
The DAC8801 multiplying digital-to-analog converter
is designed to operate from a single 2.7-V to 5.5-V
supply.
±1 LSB INL
±0.5 LSB DNL
The applied external reference input voltage VREF
determines the full-scale output current. An internal
feedback resistor (RFB) provides temperature tracking
for the full-scale output when combined with an
external I-to-V precision amplifier.
Low Noise: 12 nV/√Hz
Low Power: IDD = 2 µA
+2.7 V to +5.5 V Analog Power Supply
2 mA Full-Scale Current ±20%
with VREF = 10 V
A serial-data interface offers high-speed, three-wire
microcontroller compatible inputs using data-in (SDI),
clock (CLK), and chip select (CS).
•
•
•
•
•
•
•
0.5 µs Settling Time
4-Quadrant Multiplying Reference-Input
Reference Bandwidth: 10 MHz
±10 V Reference Input
The DAC8801 is packaged in space-saving 8-lead
SON and MSOP packages.
Reference Dynamics: -105 THD
3-Wire 50-MHz Serial Interface
DAC8801
R
FB
V
DD
Tiny 8-Lead 3 x 3 mm SON and 3 x 5 mm
MSOP Packages
D/A
Converter
I
V
REF
OUT
•
Industry-Standard Pin Configuration
14
DAC
Register
APPLICATIONS
CS
•
•
•
•
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
14
Shift
Register
CLK
SDI
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
(1)
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY NONLINEARITY
DIFFERENTIAL
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
(LSB)
(LSB)
Tape and Reel,
250
DAC8801
±1
±0.5
MSOP-8
MSOP-8
SON-8
DGK
DGK
DRB
DRB
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
F01
F01
E01
E01
DAC8801IDGKT
DAC8801IDGKR
DAC8801IDRBT
DAC8801IDRBR
Tape and Reel,
2500
DAC8801
DAC8801
DAC8801
±1
±1
±1
±0.5
±0.5
±0.5
Tape and Reel,
250
Tape and Reel,
2500
SON-8
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
DAC8801
-0.3 to +7
-0.3 to +VDD + 0.3
-0.3 to +VDD + 0.3
-40 to +105
-65 to +150
+125
UNITS
V
VDD to GND
Digital Input voltage to GND
VOUT to GND
V
V
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation
°C
°C
°C
W
(TJ max - TA) / RΘJA
+55
Thermal impedance, RΘJA
Lead temperature, soldering
Lead temperature, soldering
ESD rating, HBM
°C/W
°C
°C
V
Vapor phase (60s)
Infrared (15s)
+215
+220
1500
ESD rating, CDM
1000
V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications
-40°C to +85°C unless otherwise noted.
DAC8801
PARAMETER
STATIC PERFORMANCE
Resolution
CONDITIONS
MIN
TYP
MAX
UNITS
14
Bits
Relative accuracy
±1
±0.5
10
LSB
Differential nonlinearity
Output leakage current
Output leakage current
Full-scale gain error
Full-scale tempco
LSB
Data = 0000h, TA = 25°C
nA
Data = 0000h, TA = TMAX
10
nA
mV
All ones loaded to DAC register
±1
±3
±4
ppm of FSR/°C
OUTPUT CHARACTERISTICS(1)
Output current
2
mA
pF
Output capacitance
REFERENCE INPUT
VREF Range
Code dependent
50
-15
15
V
Input resistance
5
5
kΩ
pF
Input capacitance
LOGIC INPUTS AND OUTPUT(1)
Input low voltage
VIL VDD = +2.7V
0.6
0.8
V
V
Input low voltage
VIL VDD = +5V
VIH VDD = +2.7V
VIH VDD = +5V
IIL
Input high voltage
2.1
2.4
V
Input high voltage
V
Input leakage current
Input capacitance
10
10
µA
pF
CIL
INTERFACE TIMING
Clock input frequency
Clock pulse width high
Clock pulse width low
CS to Clock setup time
Clock to CS hold time
Data setup time
fCLK
50
MHz
ns
10
10
0
ns
ns
10
5
ns
ns
Data hold time
10
ns
POWER REQUIREMENTS
VDD
2.7
5.5
5
V
IDD (normal operation)
VDD = +4.5V to +5.5V
VDD = +2.7V to +3.6V
AC CHARACTERISTICS
Output voltage settling time
Reference multiplying BW
DAC glitch impulse
Feedthrough error
Logic inputs = 0 V
µA
µA
µA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
3
1
5
2.5
0.5
10
2
µs
MHz
nV/s
dB
VREF = 5 VPP, Data = 3FFFh
VREF = 0 V, Data = 3FFFh to 2000h
VREF = 100 mVRMS, 100kHz, Data = 0000h
-70
2
Digital feedthrough
Total harmonic distortion
Output spot noise voltage
nV/s
dB
100Hz to 20kHz
-105
12
f = 1 kHz, BW = 1 Hz
nV/√Hz
(1) Specified by design and characterization, not production tested.
3
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
PIN ASSIGNMENTS
DGK PACKAGE
(TOP VIEW)
DRB PACKAGE
(TOP VIEW)
8
7
6
5
CS
CLK
SDI
1
8
7
CLK
SDI
1
2
CS
V
DD
2
V
DD
3
4
R
FB
GND
R
FB
3
4
6
5
GND
I
V
REF
OUT
V
REF
I
OUT
TERMINAL FUNCTIONS
PIN
NAME
DESCRIPTION
1
CLK
Clock input, positive edge triggered clocks data into shift register
Serial register input, data loads directly into the shift register MSB first. Extra leading
bits are ignored.
2
3
4
SDI
RFB
Internal matching feedback resistor. Connect to external op amp output.
DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance
versus code.
VREF
5
6
7
IOUT
GND
VDD
DAC current output. Connects to inverting terminal of external precision I to V op amp.
Analog and digital ground
Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V.
Chip select, active low digital input. Transfers shift register data to DAC register on
rising edge. See Table 1 for operation.
8
CS
4
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
0.6
0.4
0.2
0
_
_
0.8
0.6
0.4
0.2
0
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 5.
Figure 6.
5
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE BANDWIDTH
1.6
1.4
6
0
6
−
−
12
18
24
30
36
42
48
54
60
66
72
78
84
90
96
VDD = +5.0V
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1.2
1.0
0.8
0.6
0.4
0.2
0
−
−
−
102
108
114
VDD = +2.7V
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Logic Input Voltage (V)
10
100
1k
10k
100k
1M
10M
100M
Bandwidth (Hz)
Figure 7.
Figure 8.
DAC SETTLING TIME
DAC GLITCH
Voltage Output Settling
Code: 3FFFh to 2000h
Trigger Pulse
Trigger Pulse
µ
Time (0.1 s/div)
µ
Time (0.2 s/div)
Figure 9.
Figure 10.
6
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: VDD = +2.7V
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
0.6
0.4
0.2
0
_
_
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 11.
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 15.
Figure 16.
7
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
THEORY OF OPERATION
The DAC8801 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 17, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to GND or the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 5 kΩ± 25%. The external reference voltage can vary in a range of -10 V
to 10 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC8801 RFB
resistor, output voltage ranges of -VREF to VREF can be generated.
When using an external I/V converter and the DAC8801 RFB resistor, the DAC output voltage is given by
Equation 1:
CODE
16384
VOUT + −VREF
(1)
R
R
R
V
REF
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
R
FB
I
OUT
GND
Figure 17. Equivalent R-2R DAC Circuit
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT terminal changes versus code, the external I/V converter noise gain will
also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC8801 due to offset modulation
versus DAC code. For best linearity performance of the DAC8801, an op amp (OPA277) as shown in Figure 18
is recommended. This circuit allows VREF to swing from -10V to +10V.
V
DD
U1
V
DD
R
FB
15 V
U2
V+
_
DAC8801
I
V
REF
OUT
OPA277
V
O
+
GND
V−
−15 V
Figure 18. Voltage Output Configuration
8
DAC8801
www.ti.com
SDI
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
D13 D12 D11 D10 D9
D8 D7
D6
D1 D0
CLK
t
(DS)
t
(CH)
t
t
(CL)
(DH)
t
t
(CSH)
(CSS)
CS
Figure 19. DAC8801 Timing Diagram
Table 1. Control Logic Truth Table(1)
CLK
X
CS
H
Serial Shift Register
DAC Register
No effect
Latched
↑+
X
L
Shift register data advanced one bit
No effect
Latched
H
Latched
X
↑+
Shift register data transferred to DAC register
New data loaded from serial register
(1) ↑+ Positive logic transition; X = Don't care
Table 2. Serial Input Register Data Format, Data Loaded MSB First
B13
B0
Bit
Data(1)
(MSB)
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
(LSB)
D13
D0
(1) A full 16-bit data word can be loaded into the serial register, but only the last 14 bits are transferred to the DAC register when CS goes
high.
9
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design as shown in Figure 20, the DAC8801 current output (IOUT) and the connection
with the inverting node of the op amp should be as short as possible and according to correct PCB layout design.
For each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is
excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation
capacitor C1 (4 pF to 20 pF typ) can be added to the design as shown in Figure 20.
V
DD
V
DD
R
FB
C1
_
+
I
U1
V
REF
V
REF
OUT
V
OUT
U2
GND
Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor
Positive Voltage Output Circuit
As shown in Figure 21, in order to generate a positive voltage output, a negative reference is input to the
DAC8801. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors
of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground and
a -2.5 V input to the DAC8801 with an op amp.
V
DD
+2.5V Reference
V
IN
V
OUT
GND
R
FB
V
DD
C1
OPA277
V
−
+
REF
DAC8801
GND
−
+
−2.5 V
I
OUT
V
OUT
OPA277
0 3 V
3 +2.5 V
OUT
Figure 21. Positive Voltage Output Circuit
10
DAC8801
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SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
Bipolar Output Circuit
The DAC8801, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces
OUT = -2.5 V to VOUT = +2.5 V.
outpu+t vǒoltages of V
Ǔ
D
VOUT
* 1 VREF
16, 384
(2)
10 kW
10 kW
V
DD
5 kW
C2
−
RFB
V
V
OUT
DD
+
C1
U4
OPA277
V
REF
DAC8801
GND
+2.5 V
−
(+10 V)
I
−2.5 V 3 V
(−10 V 3 V
3 +2.5 V
3 +10 V)
OUT
OUT
+
U2
OPA277
OUT
Figure 22. Bipolar Output Circuit
Programmable Current Source Circuit
A DAC8801 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. A application of this circuit includes a 4-mA to 20-mA current transmitter with up to a 500-Ω load. With
a matched resistor network, the load current of the circuit is shown in Equation 3:
(
)
R2 ) R3 ń R1
IL +
VREF D
R3
(3)
R2
15 kW
C1
10 pF
R14
R34
U2
OPA277
V
DD
150 kW
50 W
−
+
V
R
V
OUT
DD
FB
U2
R2
15 kW
R1
150 kW
OPA277
R3
V
U1
DAC8801
REF
V
REF
50 W
−
I
OUT
+
I
L
GND
LOAD
Figure 23. Programmable Bidirectional Current Source Circuit
11
DAC8801
www.ti.com
SLAS403A–NOVEMBER 2004–REVISED DECEMBER 2004
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive
±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the
circuit compensation capacitor C1 in the circuit is not suggested because of the change in the output impedance
ZO, according to Equation 4:
R1ȀR3(R1 ) R2)
R1(R2Ȁ ) R3Ȁ) * R1Ȁ(R2 ) R3)
ZO +
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; however, for most applications a
value of several pF is suggested.
Cross-Reference
The DAC8801 has an industry-standard pinout. Table 3 provides the cross-reference information.
Table 3. Cross Reference
SPECIFIED
INL
(LSB)
DNL
(LSB)
TEMPERATURE
RANGE
PACKAGE
DESCIPTION
PACKAGE
OPTION
CROSS
REFERENCE
PRODUCT
DAC8801IDGK
DAC8801IDRB
±1
±1
±1
±1
-40°C to +85°C
-40°C to +85°C
8-Lead MicroSOIC
MSOP-8
SON-8
ADS5553CRM
N/A
8-Lead Small Outline
12
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
MSOP
MSOP
SON
Drawing
DAC8801IDGKR
DAC8801IDGKT
DAC8801IDRBR
DAC8801IDRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
8
8
8
8
2000
250
TBD
TBD
TBD
TBD
CU SNPB
CU SNPB
CU
Level-1-220C-UNLIM
Level-1-220C-UNLIM
Level-1-240C-UNLIM
Level-1-240C-UNLIM
DGK
DRB
2500
250
SON
DRB
CU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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Addendum-Page 1
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相关型号：
DAC8803IDBTG4
14-Bit, Quad Channel, Serial Interface, Multiplying Digital-to-Analog Converter 28-SSOP -40 to 85
TI
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