OPA2690I-14DR [BB]
Dual, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable; 双路,宽带电压反馈运算放大器具有禁用型号: | OPA2690I-14DR |
厂家: | BURR-BROWN CORPORATION |
描述: | Dual, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable |
文件: | 总30页 (文件大小:484K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OPA2690
SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
Dual, Wideband, Voltage-Feedback
OPERATIONAL AMPLIFIER with Disable
FD EATURES
DESCRIPTION
FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
2.5V to 6V Dual Supply
The OPA2690 represents a major step forward in
unity-gain stable, voltage-feedback op amps. A new
internal architecture provides slew rate and full-power
bandwidth previously found only in wideband,
D
D
D
D
D
D
WIDEBAND +5V OPERATION: 220MHz (G = 2)
HIGH OUTPUT CURRENT: 190mA
OUTPUT VOLTAGE SWING: 4.0V
HIGH SLEW RATE: 1800V/µs
LOW SUPPLY CURRENT: 5.5mA/ch
LOW DISABLED CURRENT: 100µA/ch
current-feedback op amps.
A new output stage
architecture delivers high currents with a minimal
headroom requirement. These give exceptional
single-supply operation. Using a single +5V supply, the
OPA2690 can deliver a 1V to 4V output swing with over
120mA drive current and 150MHz bandwidth. This
combination of features makes the OPA2690 an ideal
RGB line driver or single-supply Analog-to-Digital
Converter (ADC) input driver.
AD PPLICATIONS
The low 5.5mA/ch supply current of the OPA2690 is
precisely trimmed at +25°C. This trim, along with low
temperature drift, ensures lower maximum supply current
than competing products. System power may be reduced
further using the optional disable control pin. Leaving this
disable pin open, or holding it HIGH, will operate the
OPA2690I-14D normally. If pulled LOW, the
OPA2690I-14D supply current drops to less than
200µA/ch while the output goes to a high-impedance
state.
VIDEO LINE DRIVING
D
D
D
D
D
D
xDSL LINE DRIVER/RECEIVER
HIGH-SPEED IMAGING CHANNELS
ADC BUFFERS
PORTABLE INSTRUMENTS
TRANSIMPEDANCE AMPLIFIERS
ACTIVE FILTERS
OPA2690 RELATED PRODUCTS
+5V
100Ω
2kΩ
+2.5V
SINGLES
DUALS
TRIPLES
+2.5V
+5V
F
100pF
0.1
µ
Voltage-Feedback
Current-Feedback
Fixed Gain
OPA2690
OPA691
OPA692
OPA2680
OPA2691
—
OPA3690
OPA3691
OPA3692
1/2
2k
Ω
O P A 2690
REFB
REFT
499Ω
0.1µF
1k
Ω
35Ω
499Ω
499Ω
HARMONIC DISTORTION vs FREQUENCY
FOR THE SINGLE−SUPPLY ADC DRIVER
IN
IN
10pF
ADS825
−
−
−
−
−
−
−
−
−
−
2.5VCM
2VPP
50
55
60
65
70
75
80
85
90
95
VIN
2VPP Differential Output
10−Bit
40MSPS
35Ω
1k
Ω
10pF
1/2
O P A 2690
Clock
499
Ω
+2.5V
3rd−Harmonic
2nd−Harmonic
Single-Supply Differential ADC Driver
−
100
1
10
20
Frequency (MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2002−2004, Texas Instruments Incorporated
www.ti.com
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
(1)
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
handledwith appropriate precautions. Failure to observe
DC
Internal Power Dissipation . . . . . . . See Thermal Analysis Section
proper handling and installation procedures can cause damage.
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Storage Temperature Range: D, 14D . . . . . . . . . . −40°C to +125°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
J
ESD Resistance:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V
Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1500V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
(1)
PRODUCT
PACKAGE-LEAD
OPA2690ID
OPA2690IDR
Rails, 100
Tape and Reel, 2500
Rails, 58
OPA2690
SO-8
D
D
−40°C to +85°C
−40°C to +85°C
OPA2690
OPA2690
OPA2690I-14D
OPA2690I-14DR
OPA2690
SO-14
Tape and Reel, 2500
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
PIN ASSIGNMENTS
Top View
SO Top View
SO
−
1
2
3
4
5
6
7
14
Out A
In A
+In A
13 NC
Out A
1
2
3
4
8
7
6
5
+VS
A
−
In A
+In A
Out B
12
NC
DIS A
B
−
In B
+In B
−
VS
11 +VS
−
VS
10
9
DIS B
+In B
NC
NC
−
8
In B
Out B
NC = No Connection
2
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS: V = 5V
S
Boldface limits are tested at +25°C.
At R = 402Ω, R = 100Ω, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.
F
L
OPA2690ID, I-14D
TYP
MIN/MAX OVER TEMPERATURE
0°C to
70°C
−40°C to
+85°C
MIN/
MAX
TEST
LEVEL
(2)
(2)
(3)
(1)
PARAMETER
CONDITIONS
+25°C
+25°C
UNITS
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
G = +1, V = 0.5V , R = 25Ω
500
220
30
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
typ
C
B
B
B
C
C
C
C
C
C
C
C
O
PP
F
G = +2, V = 0.5V
165
20
160
19
150
18
O
PP
G = +10, V = 0.5V
O
PP
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G ≥ 10
300
30
200
190
180
G = +2, V < 0.5V
O
PP
V
O
< 0.5V
4
PP
G = +2, V = 5V
200
1800
1.4
2.8
12
MHz
V/µs
ns
O
PP
G = +2, 4V Step
G = +2, V = 0.5V Step
1400
1200
900
Rise-and-Fall Time
O
G = +2, V = 5V Step
ns
O
Settling Time to 0.02%
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
G = +2, V = 5V Step
ns
O
G = +2, V = 5V Step
8
ns
O
G = +2, f = 5MHz, V = 2V
O
PP
R
= 100Ω
≥ 500Ω
= 100Ω
≥ 500Ω
−68
−77
−70
−81
5.5
−64
−70
−68
−78
−62
−68
−66
−76
−60
−66
−64
−75
dBc
dBc
max
max
max
max
typ
L
R
R
B
B
B
C
C
C
C
L
3rd-Harmonic
dBc
L
R
dBc
L
Input Voltage Noise
Input Current Noise
Differential Gain
f > 1MHz
nV/√Hz
pA/√Hz
%
f > 1MHz
3.1
typ
G = +2, NTSC, V = 1.4V , R = 150Ω
0.06
0.03
−85
typ
O
P
L
Differential Phase
G = +2, NTSC, V = 1.4V , R = 150Ω
deg
typ
O
P
L
Channel-to-Channel Crosstalk
f = 5MHz, Input-Referred
dBc
(4)
DC PERFORMANCE
Open-Loop Voltage Gain (A
Input Offset Voltage
)
V
O
= 0V, R = 100Ω
69
58
56
54
dB
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
OL
L
V
CM
V
CM
V
CM
V
CM
V
CM
V
CM
= 0V
= 0V
= 0V
= 0V
= 0V
= 0V
1.0
4.5
5.0
12
5.2
12
Average Offset Voltage Drift
Input Bias Current
µV/°C
µA
nA/°C
µA
+5
11
12
13
Average Bias Current Drift (magnitude)
Input Offset Current
20
40
0.1
1.0
1.4
1.0
1.6
1.5
Average offset Current Drift
nA/°C
INPUT
(5)
Common-Mode Input Range (CMIR)
3.5
65
3.4
60
3.3
57
3.2
56
V
min
min
A
A
Common-Mode Rejection Ratio (CMRR)
Input Impedance
V
CM
=
1V
dB
Differential Mode
V
= 0V
= 0V
190 0.6
3.2 0.9
kΩ pF
MΩ pF
typ
typ
C
C
CM
Common-Mode
V
CM
OUTPUT
Voltage Output Swing
No Load
4.0
3.9
3.8
3.7
3.7
3.6
3.6
3.3
V
V
min
min
min
min
typ
A
A
A
A
C
C
100Ω Load
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current
V
O
V
O
V
O
= 0V
= 0V
= 0V
+190
−190
250
+160
−160
+140
−140
+100
−100
mA
mA
mA
Ω
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.04
typ
(1)
Junction temperature = ambient for +25°C specifications.
(2)
(3)
Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4)
(5)
Current is considered positive out-of-node. V
is the input common-mode voltage.
CM
Tested < 3dB below minimum specified CMRR at CMIR limits.
3
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS: V = 5V (continued)
S
Boldface limits are tested at +25°C.
At R = 402Ω, R = 100Ω, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.
F
L
OPA2690ID, I-14D
TYP
MIN/MAX OVER TEMPERATURE
0°C to
70°C
−40°C to
+85°C
MIN/
MAX
TEST
LEVEL
(2)
(2)
(3)
(1)
PARAMETER
CONDITIONS
+25°C
+25°C
UNITS
DISABLE (SO-14 Only)
Disabled LOW
Power-Down Supply Current (+V )
S
V
= 0, Both Channels
−200
200
25
−400
−480
−520
µA
ns
ns
dB
pF
mV
mV
V
max
typ
A
C
C
C
C
C
C
A
A
A
DIS
Disable Time
V
IN
V
IN
= 1V
= 1V
DC
DC
Enable Time
typ
Off Isolation
G = +2, R = 150Ω, V = 0
G = +2, R = 150Ω, V = 0
70
typ
L
IN
Output Capacitance in Disable
Turn-On Glitch
4
typ
L
IN
50
typ
Turn-Off Glitch
20
typ
Enable Voltage
3.3
1.8
75
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
min
max
max
Disable Voltage
V
Control Pin Input Bias Current (V
)
V
= 0, Each Channel
µA
DIS
DIS
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
5
V
typ
max
max
min
min
C
A
A
A
A
6.0
11.6
10.6
68
6.0
12.4
9.2
6.0
13.2
8.6
V
Maximum Quiescent Current (2 Channels)
Minimum Quiescent Current (2 Channels)
Power-Supply Rejection Ratio (+PSRR)
V
V
=
=
5V
5V
11
11
75
mA
mA
dB
S
S
Input-Referred
66
64
THERMAL CHARACTERISTICS
Specified Operating Range: D, 14D
−40 to +85
°C
typ
C
Thermal Resistance, q
Junction-to-Ambient
JA
D
SO-8
125
100
°C/W
°C/W
typ
typ
C
C
14D
SO-14
(1)
(2)
(3)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
Current is considered positive out-of-node. V
Tested < 3dB below minimum specified CMRR at CMIR limits.
(4)
(5)
is the input common-mode voltage.
CM
4
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS: V = +5V
S
Boldface limits are tested at +25°C.
At R = 402Ω, R = 100Ω to V /2, and G = +2 (see Figure 2 for AC performance only), unless otherwise noted.
F
L
S
OPA2690ID, I-14D
MIN/MAX OVER TEMPERATURE
TEST
TYP
0°C to
70°C
−40°C to
+85°C
MIN/
MAX
LEVEL
(3)
(2)
(2)
(1)
PARAMETER
CONDITIONS
+25°C
+25°C
UNITS
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth
G = +1, V < 0.5V , R
F
=
25Ω
400
190
25
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
C
O
PP
G = +2, V < 0.5V
150
18
145
17
140
16
O
PP
G = +10, V < 0.5V
O
PP
PP
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G ≥ 10
250
20
180
170
160
G = +2, V < 0.5V
O
V
O
< 0.5V
5
PP
G = +2, V = 2V
220
1000
1.6
2.0
12
MHz
V/µs
ns
O
PP
G = +2, 2V Step
G = +2, V = 0.5V Step
700
670
550
Rise-and-Fall Time
O
G = +2, V = 2V Step
ns
O
Settling Time to 0.02%
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
G = +2, V = 2V Step
ns
O
G = +2, V = 2V Step
8
ns
O
G = +2, f = 5MHz, V = 2V
O
PP
R
L
= 100Ω to V /2
−65
−75
−68
−77
5.6
−60
−70
−64
−73
−59
−68
−62
−71
−56
−66
−60
−70
dBc
dBc
max
max
max
max
typ
B
B
B
B
C
C
C
C
S
R
R
≥ 500Ω to V /2
L
S
3rd-Harmonic
= 100Ω to V /2
dBc
L
S
R
L
≥ 500Ω to V /2
dBc
S
Input Voltage Noise
Input Current Noise
Differential Gain
f > 1MHz
nV/√Hz
pA/√Hz
%
f > 1MHz
3.2
typ
G = +2, NTSC, V = 1.4V , R = 150 to V /2
0.06
0.02
typ
O
P
L
S
Differential Phase
G = +2, NTSC, V = 1.4V , R = 150 to V /2
deg
typ
O
P
L
S
(4)
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
V
O
= 2.5V, R = 100Ω to V /2
63
56
54
4.8
10
12
20
1.4
7
52
5.2
10
13
40
1.6
9
dB
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
L
S
V
V
V
V
V
V
= 2.5V
= 2.5V
= 2.5V
= 2.5V
= 2.5V
= 2.5V
1.0
4.5
CM
Average Offset Voltage Drift
Input Bias Current
µV/°C
µA
nA/°C
µA
CM
CM
CM
CM
CM
+5
11
Average Bias Current Drift (magnitude)
Input Offset Current
0.3
1.0
Average Offset Current Drift
nA/°C
INPUT
(5)
Least Positive Input Voltage
1.5
3.5
63
1.6
3.4
58
1.7
3.3
56
1.8
3.2
54
V
V
max
min
min
A
A
A
(5)
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
V
CM
= 2.5V 0.5V
dB
Differential Mode
V
= 2.5V
= 2.5V
92 1.4
2.2 1.5
kΩ pF
MΩ pF
typ
typ
C
C
CM
Common-Mode
V
CM
OUTPUT
Most Positive Output Voltage
No Load
4
3.8
3.7
3.6
3.5
3.5
3.4
1.5
1.7
+80
−80
V
V
min
min
max
max
min
min
typ
A
A
A
A
A
A
C
C
R
R
= 100Ω to 2.5V
No Load
3.9
L
Least Positive Output Voltage
1
1.2
1.4
V
= 100Ω to 2.5V
1.1
1.3
1.5
V
L
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current
+160
−160
250
0.04
+120
−120
+100
−100
mA
mA
mA
Ω
Closed-Loop Output Impedance
G = +2, f = 100kHz
typ
(1)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
(2)
(3)
for information.
Current is considered positive out-of-node. V
Tested < 3dB below minimum specified CMRR at CMIR limits.
(4)
(5)
is the input common-mode voltage.
CM
5
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS: V = +5V (continued)
S
Boldface limits are tested at +25°C.
At R = 402Ω, R = 100Ω to V /2, and G = +2 (see Figure 2 for AC performance only), unless otherwise noted.
F
L
S
OPA2690ID, I-14D
TYP
MIN/MAX OVER TEMPERATURE
TEST
0°C to
70°C
−40°C to
+85°C
MIN/
MAX
LEVEL
(3)
(2)
(2)
(1)
PARAMETER
CONDITIONS
+25°C
+25°C
UNITS
DISABLE (SO-14 Only)
Disabled LOW
Power-Down Supply Current (+V )
S
V
= 0, Both Channels
G = +2, 5MHz
−200
65
−400
−480
−520
µA
dB
pF
mV
mV
V
max
typ
A
C
C
C
C
A
A
C
DIS
Off Isolation
Output Capacitance in Disable
Turn-On Glitch
4
typ
G = +2, R = 150Ω, V = V /2
G = +2, R = 150Ω, V = V /2
50
typ
L
IN
S
Turn-Off Glitch
20
typ
L
IN
S
Enable Voltage
3.3
1.8
75
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
min
max
typ
Disable Voltage
V
Control Pin Input Bias Current (V
)
V
= 0, Each Channel
µA
DIS
DIS
POWER SUPPLY
Specified Single-Supply Operating Voltage
Maximum Single-Supply Operating Voltage
Maximum Quiescent Current (2 Channels)
Minimum Quiescent Current (2 Channels)
Power-Supply Rejection Ratio (+PSRR)
5
V
typ
max
max
min
typ
C
B
A
A
C
12
12
11.44
8.0
12
V
V
V
= +5V
= +5V
9.8
9.8
72
10.88
8.96
12.1
7.72
mA
mA
dB
S
S
Input-Referred
TEMPERATURE RANGE
Specification: D, 14D
−40 to +85
°C
typ
C
Thermal Resistance, q
Junction-to-Ambient
JA
D
SO-8
125
150
°C/W
°C/W
typ
typ
C
C
14D
SO-14
(1)
(2)
(3)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
Current is considered positive out-of-node. V
Tested < 3dB below minimum specified CMRR at CMIR limits.
(4)
(5)
is the input common-mode voltage.
CM
6
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V
S
At T = +25°C, G = +2, R = 402Ω, and R = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
A
F
L
SMALL−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
LARGE−SIGNAL FREQUENCY RESPONSE
6
3
0
3
6
9
9
6
3
0
3
6
G = +1
Ω
RF = 25
VO = 2VPP
G = 2
G = 5
−
−
−
VO = 1VPP
VO = 4VPP
VO = 7VPP
G = 10
−
−
−
−
12
15
0.7
10
Frequency (MHz)
100
700
0.5
1
10
100
500
Frequency (MHz)
SMALL−SIGNAL PULSE RESPONSE
LARGE−SIGNAL PULSE RESPONSE
400
300
200
100
0
4
3
2
1
0
1
2
3
4
G = +2
VO = 0.5VPP
G = +2
VO = 5VPP
−
−
−
−
−
−
−
−
100
200
300
400
Time (5ns/div)
Time (5ns/div)
CHANNEL−TO−CHANNEL CROSSTALK
COMPOSITE VIDEO dG/dP
−
−
−
−
−
−
−
−
−
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
55
60
65
70
75
80
85
90
95
+5V
No Pull−Down
Video In
75Ω
Ω
With 1.3k Pull−Down
1/2
O PA2690
Optional
1.3kΩ
402Ω
Pull−Down
dG
402Ω
dG
−5V
dP
dP
Input Referred
100
−
100
1
2
3
4
1
10
Ω
Number of 150 Loads
Frequency (MHz)
7
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TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At T = +25°C, G = +2, R = 402Ω, and R = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
A
F
L
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
VO = 2VPP
HARMONIC DISTORTION vs LOAD RESISTANCE
−
−
−
−
−
−
−
−
−
−
−
−
60
65
70
75
80
60
65
70
75
80
85
90
VO = 2VPP
f = 5MHz
Ω
RL = 100
f = 5MHz
2nd−Harmonic
2nd−Harmonic
rmonic
3rd−Ha
3rd−Harmonic
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
100
1000
Supply Voltage ( VS)
Ω
Resistance (
)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs FREQUENCY
VO = 2VPP
−
60
65
70
75
80
−
−
−
−
−
−
40
50
60
70
80
90
Ω
RL = 100
Ω
RL = 100
f = 5MHz
2nd−Harmonic
3rd−Harmonic
−
2nd−Harmonic
3rd−Harmonic
−
−
−
−
100
0.1
1
5
0.1
1
10
20
Output Voltage Swing (VPP
)
Frequency (MHz)
HARMONIC DISTORTION vs NONINVERTING GAIN
VO = 2VPP
HARMONIC DISTORTION vs INVERTING GAIN
VO = 2VPP
Ω
RL = 100
f = 5MHz
−
−
−
−
−
−
40
40
50
60
70
80
Ω
RL = 100
−
50 f = 5MHz
−
−
−
−
60
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
70
80
90
3rd−Harmonic
1
10
20
1
10
20
Noninverting Gain (V/V)
Inverting Gain (V/V)
8
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At T = +25°C, G = +2, R = 402Ω, and R = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
A
F
L
2−TONE, 3RD−ORDER
INTERMODULATION SPURIOUS
INPUT VOLTAGE AND CURRENT NOISE DENSITY
100
10
1
−
−
−
−
−
−
−
−
−
−
30
35
40
45
50
55
60
65
70
75
50MHz
20MHz
√
Voltage Noise 5.5nV/ Hz
√
Current Noise 3.1pA/ Hz
z
10MH
Ω
Load Power at Matched 50 Load,
see Figure 1
100
1k
10k
100k
1M
10M
−
−
−
−
2
8
6
4
0
2
4
6
8
10
Frequency (Hz)
Single−Tone Load Power (dBm)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
G = +2
80
70
60
50
40
30
20
10
0
9
6
3
0
CL = 10pF
F
CL = 100p
= 22pF
CL
CL = 47pF
VIN
−
−
−
3
6
9
RS
1
/2
VO U
T
O
P A
2
6
90
Ω
1k
CL
Ω
402
Ω
402
Ω
1k is optional.
10
100
1000
0
20
40
60
80 100 120 140 160 180 200
Capacitive Load (pF)
Frequency (20MHz/div)
DISABLE FEEDTHROUGH vs FREQUENCY
LARGE−SIGNAL DISABLE/ENABLE RESPONSE
VDIS
−
−
−
−
−
−
−
−
−
−
−
45
50
55
60
65
70
75
80
85
90
95
6
4
2
0
VDIS = 0
2.0
1.6
1.2
0.8
0.4
0
Output Voltage
Each Channel
SO−14
Package
Only
Reverse
G = +2
VIN = +1V
Forward
1M
−
100
100k
10M
100M
Time (50ns/div)
Frequency (Hz)
9
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At T = +25°C, G = +2, R = 402Ω, and R = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
A
F
L
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
TYPICAL DC DRIFT OVER TEMPERATURE
5
4
3
2
1
0
1
2
3
4
5
2.0
1.5
20
10
0
Output Current Limited
1W Internal
Power Limit
ut Bias Current (I )
Inp
B
One Channel
Only
1.0
0.5
Input Offset Current (IOS
)
0
Ω
25
Load Line
−
−
−
−
−
−0.5
−1.0
−1.5
−2.0
Ω
50 Load Line
−
10
Ω
100 Load Line
age (V
Input Offset Volt
)
OS
1W Internal
Power Limit
Output Current Limit
−20
−50
−25
0
25
50
75
100
125
−
−
−
100
300
200
0
100
200
300
Ambient Temperature (_C)
IO (mA)
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE
utput Current
14
12
10
8
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
Sourcing O
−
PSRR
CMRR
ing Output Current
Sink
+PSRR
nt
Quiescent Supply Curre
6
4
0
125
−50
−25
0
25
50
75
100
10k
100k
1M
Frequency (MHz)
10M
100M
_
Ambient Temperature ( C)
CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
OPEN−LOOP GAIN AND PHASE
Open−Loop Gain
10
1
70
60
50
40
30
20
10
0
0
+5V
−
30
1/2
OPA2690
200Ω
−60
Open−Loop Phase
ZO
−
90
−5V
Ω
402
−120
Ω
402
−
−
−
150
180
210
0.1
−
−240
10
−
1G
−20
270
0.01
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (MHz)
Frequency (Hz)
10
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: V = +5V
S
At T = +25°C, G = +2, R = 402Ω, and R = 100Ω (see Figure 2 for AC performance only), unless otherwise noted.
A
F
L
SMALL−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
LARGE−SIGNAL FREQUENCY RESPONSE
VO = 2VPP
6
3
0
3
6
9
9
6
3
0
3
6
G = +1
Ω
RF = 25
VO = 3VPP
VO = 1VPP
G = +2
G = +5
−
−
−
G = +10
−
−
0.7 1
10
Frequency (Hz)
100
700
0.5
1
10
Frequency (MHz)
100
500
SMALL−SIGNAL PULSE RESPONSE
LARGE−SIGNAL PULSE RESPONSE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
G = +2
VO = 0.5VPP
G = +2
VO = 2VPP
Time (5ns/div)
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 10pF
50
45
40
35
30
25
20
15
10
5
9
6
3
0
CL = 100pF
+5V
CL = 22pF
Ω
Ω
µ
714
0.1
F
VIN
−
−
−
3
6
9
RS
VOUT
CL
1/2
Ω
714
Ω
58
O PA 2690
714
pF
CL = 47
+5V
Ω
402
Ω
402
0
1
10
100
1000
0
20
40
60
80 100 120 140 160 180 200
Capacitive Load (pF)
Frequency (20MHz/div)
11
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: V = +5V (continued)
S
At T = +25°C, G = +2, R = 402Ω, and R = 100Ω (see Figure 2 for AC performance only), unless otherwise noted.
A
F
L
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2VPP
HARMONIC DISTORTION vs FREQUENCY
VO = 2VPP
−
−
−
−
−
−
−
−
−
−
−
60
65
70
75
80
40
50
60
70
80
90
Ω
RL = 100 to 2.5V
f = 5MHz
2nd−Harmonic
3rd−Harmonic
2nd−Harmonic
3rd−Harmonic
−
100
100
1000
0.1
1
10
20
Ω
Resistance (
)
Frequency (MHz)
2−TONE, 3RD−ORDER
INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−
−
−
−
−
60
65
70
75
80
−
−
−
−
−
−
−
−
−
−
30
35
40
45
50
55
60
65
70
75
Ω
RL = 100 to 2.5V
f = 5MHz
50MHz
3rd−Harmonic
20MHz
2nd−Harmonic
z
10MH
Ω
Load Power at Matched 50 Load, see Figure 2
0.1
1
3
−
−
−
−
−
−
−
2
14
12
10
8
6
4
0
2
Output Voltage Swing (VPP
)
Single−Tone Load Power (dBm)
12
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
within the useable voltage ranges at both the input and the
output. The circuit of Figure 2 establishes an input
midpoint bias using a simple resistive divider from the +5V
supply (two 698Ω resistors). Separate bias networks
would be required at each input. The input signal is then
AC-coupled into the midpoint voltage bias. The input
voltage can swing to within 1.5V of either supply pin, giving
a 2VPP input signal range centered between the supply
pins. The input impedance matching resistor (59Ω) used
for testing is adjusted to give a 50Ω input load when the
parallel combination of the biasing divider network is
included.
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION
The OPA2690 provides an exceptional combination of
high output power capability in a dual, wideband,
unity-gain stable, voltage-feedback op amp using a new
high slew rate input stage. Typical differential input stages
used for voltage-feedback op amps are designed to steer
a fixed-bias current to the compensation capacitor, setting
a limit to the achievable slew rate. The OPA2690 uses a
new input stage which places the transconductance
element between two input buffers, using their output
currents as the forward signal. As the error voltage
increases across the two inputs, an increasing current is
delivered to the compensation capacitor. This provides
very high slew rate (1800V/µs) while consuming relatively
low quiescent current (5.5mA/ch). This exceptional
full-power performance comes at the price of a slightly
higher input noise voltage than alternative architectures.
The 5.5nV/√Hz input voltage noise for the OPA2690 is
exceptionally low for this type of input stage.
+5V
+VS
µ
µ
0.1 F
6.8 F
+
Ω
50 Source
Ω
175
DIS
VO
Ω
50 Load
VD
VI
Ω
50
Ω
50
1/2
OPA2690
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the 5V
Electrical Characteristics and Typical Characteristics.
This is for one channel; the other channel is connected
similarly. For test purposes, the input impedance is set to
50Ω with a resistor to ground and the output impedance is
set to 50Ω with a series output resistor. Voltage swings
reported in the electrical characteristics are taken directly
at the input and output pins, while output powers (dBm)
are at the matched 50Ω load. For the circuit of Figure 1, the
total effective load will be 100Ω 804Ω. The disable
control line (SO-14 package only) is typically left open for
normal amplifier operation. Two optional components are
included in Figure 1. An additional resistor (175Ω) is
included in series with the noninverting input. Combined
with the 25Ω DC source resistance looking back towards
the signal generator, this gives an input bias current
cancelling resistance that matches the 200Ω source
resistance seen at the inverting input (see the DC
Accuracy and Offset Control section). In addition to the
usual power-supply decoupling capacitors to ground, a
0.1µF capacitor is included between the two power-supply
pins. In practical PC board layouts, this optional-added
capacitor will typically improve the 2nd-harmonic
distortion performance by 3dB to 6dB.
µ
0.1 F
RF
Ω
402
RG
402
Ω
µ
µ
0.1 F
6.8 F
+
−
VS
−
5V
Figure 1. DC-Coupled, G = +2, Bipolar Supply,
Specification and Test Circuit
+5V
+VS
+
µ
µ
6.8 F
0.1 F
Ω
698
µ
0.1 F
Ω
50
DIS
VO 100
VD
VI
Ω
Ω
698
1/2
OPA2690
VS/2
Ω
59
RF
Ω
402
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Electrical
and Typical Characteristics. Though not a rail-to-rail
design, the OPA2690 requires minimal input and output
voltage headroom compared to other very wideband
voltage-feedback op amps. It will deliver a 3VPP output
swing on a single +5V supply with > 150MHz bandwidth.
The key requirement of broadband single-supply
operation is to maintain input and output signal swings
RG
402
Ω
µ
0.1 F
Figure 2. DC-Coupled, G = +2, Single-Supply,
Specification and Test Circuit
13
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
Again, an additional resistor (50Ω in this case) is included
directly in series with the noninverting input. This minimum
recommended value provides part of the DC source
resistance matching for the noninverting input bias
current. It is also used to form a simple parasitic pole to roll
off the frequency response at very high frequencies
( > 500MHz) using the input parasitic capacitance. The
gain resistor (RG) is AC-coupled, giving the circuit a DC
gain of +1, which puts the input DC bias voltage (2.5V) on
the output as well. The output voltage can swing to within
1V of either supply pin while delivering > 100mA output
current. A demanding 100Ω load to a midpoint bias is used
in this characterization circuit. The new output stage circuit
used in the OPA2690 can deliver large bipolar output
currents into this midpoint load with minimal crossover
distortion, as shown in the +5V supply harmonic distortion
plots.
The OPA2690 in the circuit of Figure 4 provides > 200MHz
bandwidth for a 2VPP output swing. Minimal 3rd-harmonic
distortion or 2-tone, 3rd-order intermodulation distortion
will be observed due to the very low crossover distortion
in the OPA2690 output stage. The limit of output
Spurious-Free Dynamic Range (SFDR) will be set by the
2nd-harmonic distortion. Without RB, the circuit of Figure 4
measured at 10MHz shows an SFDR of 57dBc. This can
be improved by pulling additional DC bias current (IB) out
of the output stage through the optional RB resistor to
ground (the output midpoint is at 2.5V for Figure 4).
Adjusting IB gives the improvement in SFDR shown in
Figure 3. SFDR improvement is achieved for IB values up
to 5mA, with worse performance for higher values. Using
the dual OPA2690 in an I/Q receiver channel will give
matched AC performance through high frequencies.
70
SINGLE-SUPPLY ADC INTERFACE
V
= 2VPP, 10MHz
O
68
66
64
62
60
58
56
54
52
50
Most modern, high-performance ADCs (such as the TI
ADS8xx and ADS9xx series) operate on a single +5V (or
lower) power supply. It has been a considerable challenge
for single-supply op amps to deliver a low distortion input
signal at the ADC input for signal frequencies exceeding
5MHz. The high slew rate, exceptional output swing, and
high linearity of the OPA2690 make it an ideal
single-supply ADC driver. The circuit on the front page
shows one possible interface paricularly suited to
differential I/O, AC-coupled requirements. Figure 4 shows
the test circuit of Figure 2 modified for a capacitive (ADC)
load and with an optional output pull-down resistor (RB).
This circuit would be suitable to dual-channel ADC driving
with a single-ended I/O.
0
1
2
3
4
5
6
7
8
9
10
Output Pull−Down Current (mA)
Figure 3. SFDR versus I
B
+5V
Power−supply decoupling not shown.
RS
Ω
Ω
698
698
µ
0.1 F
Ω
50
VI
Ω
30
1/2
2.5V DC
1V AC
1VPP
O PA 2690
Ω
59
50pF
ADC Input
Ω
402
Ω
402
RB
IB
µ
0.1 F
Figure 4. SFDR versus I
B
14
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
HIGH-PERFORMANCE DAC
TRANSIMPEDANCE AMPLIFIER
Ω
50
1/2
VO = IO RF
High-frequency DDS Digital-to-Analog Converters
(DACs) require a low distortion output amplifier to retain
their SFDR performance into real-world loads. Figure 5
shows a single-ended output drive implementation. The
diagram shows the signal output current(s) connected into
the virtual ground summing junction(s) of the OPA2690,
which is set up as a transimpedance stage or I-V converter.
If the DAC requires that its outputs terminate to a
compliance voltage other than ground for operation, the
appropriate voltage level may be applied to the
noninverting input of the OPA2690. The DC gain for this
circuit is equal to RF. At high frequencies, the DAC output
capacitance (CD in Figure 5) will produce a zero in the
noise gain for the OPA2690 that may cause peaking in the
closed-loop frequency response. CF is added across RF to
compensate for this noise gain peaking. To achieve a flat
transimpedance frequency response, the pole in each
feedback network should be set to:
OPA2690
High−Speed
DAC
RF1
CF1
IO
CD1
RF2
CF2
CD2
−
IO
1/2
−
−
IO RF
VO
=
OPA2690
→
Ω
GBP Gain Bandwidth
Product (Hz) for the OPA2690
50
Figure 5. DAC Transimpedance Amplifier
WIDEBAND VIDEO MULTIPLEXING
GBP
4pRFCD
1
+
Ǹ
2pRFCF
(1)
One common application for video speed amplifiers that
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple wired-OR
video multiplexer can be easily implemented using the
OP2690I-14D (SO-14 package only), as shown in
Figure 6.
which will give a cutoff frequency f−3dB of approximately:
GBP
2pRFCD
f*3dB
+
Ǹ
(2)
+5V
Ω
2k
VDIS
+5V
Ω
146
DISA
1/2
Video 1
O PA 2690
Ω
75
Ω
82.5
82.5
Ω
340
Ω
340
Ω
Ω
402
402
−
5V
Ω
75 Cable
RG−59
Ω
75 Load
+5V
Ω
1/2
Ω
146
O PA 2690
DISB
Video 2
Ω
75
−
5V
Ω
2k
Figure 6. 2-Channel Video Multiplexer (SO-14 package only)
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are
approximately equal at this time. The make-before-break
disable characteristic of the OPA2690 ensures that there
is always one amplifier controlling the line when using a
wired-OR circuit like that shown in Figure 6. As both inputs
may be on for a short period during the transition between
channels, the outputs are combined through the output
impedance matching resistors (82.5Ω in this case). When
one channel is disabled, its feedback network forms part
of the output impedance and slightly attenuates the signal
in getting out onto the cable. The gain and output matching
resistor have been slightly increased to get a signal gain
of +1 at the matched load and provide a 75Ω output
impedance to the cable. The video multiplexer connection
(see Figure 6) also ensures that the maximum differential
voltage across the inputs of the unselected channel does
not exceed the rated 1.2V maximum for standard video
signal levels.
For a more accurate analysis of the circuit, consider the
group delay for the amplifiers. For example, in the case of
the OPA2690, the group delay in the bandwidth from 1MHz
to 100MHz is approximately 1.0ns. To account for this,
modify the transfer function, which now comes out to be:
(
)
tGR + 2 2RC ) TD
(4)
with TD = (1/360) × (dφ/df) = delay of the op amp itself. The
values of resistors RF and RG should be equal and low to
avoid parasitic effects. If the all-pass filter is designed for
very low delay times, include parasitic board capacitances
to calculate the correct delay time. Simulating this
application using the PSPICE model of the OPA2690 will
allow this design to be tuned to the desired performance.
DIFFERENTIAL RECEIVER/DRIVER
A very versatile application for a dual operational amplifier
is the differential amplifier configuration detailed in
Figure 8. With both amplifiers of the OPA2690 connected
for noninverting operation, the circuit provides a high input
impedance whereas the gain can easily be set by just one
resistor, RG. When operated in low gains, the output swing
may be limited as a result of the common-mode input
swing limits of the amplifier itself. An interesting
modification of this circuit is to place a capacitor in series
with the RG. Now the DC gain for each side is reduced to
+1, whereas the AC gain still follows the standard transfer
function of G = 1 + 2RF/RG. This might be advantageous
for applications processing only a frequency band that
excludes DC or very low frequencies. An input DC voltage
resulting from input bias currents is not amplified by the AC
gain and can be kept low. This circuit can be used as a
differential line receiver, driver, or as an interface to a
differential input ADC.
See the Disable Operation section for the turn-on and
turn-off switching glitches using a 0V input for a single
channel is typically less than 50mV. Where two outputs
are switched (see Figure 6), the output line is always under
the control of one amplifier or the other due to the
make-before-break disable timing. In this case, the
switching glitches for two 0V inputs drops to < 20mV.
HIGH-SPEED DELAY CIRCUIT
The OPA2690 makes an ideal amplifier for a variety of
active filter designs. Shown in Figure 7 is a circuit that uses
the two amplifiers within the dual OPA2690 to design a
2-stage analog delay circuit. For simplicity, the circuit uses
a dual-supply ( 5V) operation, but it can also be modified
to operate on a signal supply. The input to the first filter
stage is driven by the OPA692 wideband buffer amplifier
to isolate the signal input from the filter network.
Each of the two filter stages is a 1st-order filter with a
voltage gain of +1. The delay time through one filter is
given by Equation 3.
t
GR0 + 2RC
(3)
C
VIN
OPA692
C
1/2
OPA2690
1/2
R
VOUT
OPA2690
R
RG
RF
Ω
402
RG
RF
Ω
402
Ω
402
Ω
402
Figure 7. 2-Stage, All-Pass Network
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
SINGLE-SUPPLY MFB DIFFERENTIAL
ACTIVE FILTER: 10MHz BUTTERWORTH
CONFIGURATION
Ω
50
VI
RO
1/2
O PA2690
The active filter circuit shown in Figure 9 can be easily
implemented using the OPA2690. In this configuration,
each amplifier of the OPA2690 operates as an integrator.
For this reason, this type of application is also called
infinite gain filter implementation. A Butterworth filter can
be implemented using the following component ratios:
RF
Ω
402
2RF
RG
VDIFF = 1 +
VI − (−VI)
RF
RG
Ω
402
1
(
)
cutoff frequency
fO +
2 p R C
RO
1/2
R1 + R2 + 0.65 R
R3 + 0.375 R
C1 + C
Ω
50
O PA2690
−
VI
C2 + 2 C
Figure 8. High-Speed Differential Receiver
+12V
Ω
6k
Ω
50
VCM
1/2
OPA2690
1000pF
Ω
6k
C1A
R3A
R1A
100pF
Ω
60
Ω
102
R2A
Ω
102
C2
200pF
R2B
VIN
VOUT
Ω
102
C1B
R1B
R3B
100pF
Ω
102
Ω
60
1/2
OPA2690
Ω
50
VCM
Figure 9. Single-Supply, MFB Active Filter, 10MHz LP Butterworth
17
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ꢢ
ꢣ
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
The frequency response for a 10MHz Butterworth filter is
shown in Figure 10. One advantage for using this type of
filter is the independent setting of WO and Q. Q can be
easily adjusted by changing the R3A, B resistors without
affecting WO.
9
6
3
0
3
6
9
CF = 8.6pF
1
0
−
−
−
−
−
−
−
−
−
−
−
−
1
2
3
4
5
6
7
8
9
−
12
0.1
1
10
Frequency (MHz)
100
500
Figure 11. Single-Supply Differential ADC Driver
For example, CF = 8.6pF in parallel with RF = 402Ω will
control the −3dB frequency to 18MHz.
0.1
1
10
20
Frequency (MHz)
Figure 10. Multiple Feedback Filter Frequency
Response
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
SINGLE-SUPPLY DIFFERENTIAL ADC
DRIVER
Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA2690 in its
two package styles. Both of these are available, free, as
unpopulated PC boards delivered with descriptive
documentation. The summary information for each board
is shown below:
The single-supply differential ADC driver shown on the
front page is ideal for driving high-frequency ADCs. As
shown in the plot on the front page, Harmonic Distortion vs
Frequency for the Single-Supply Differential ADC Driver,
the 2nd-harmonic reacts as expected and drops to a
−95dBc at 1MHz and −87dBc at 5MHz—a significant
improvement in going to differential from single-ended.
LITERATURE
REQUEST
NUMBER
BOARD PART
NUMBER
PRODUCT
PACKAGE
The circuit shown on the front page has a 195MHz, −3dB
bandwidth that can be easily bandlimited by using a
capacitor in parallel with the feedback resistors. Refer to
Figure 11 for more details. The −3dB frequency is given by
Equation 5.
OPA2690ID
OPA2690IDBV
SO-8
SO-14
DEM-OPA268xU
DEM-OPA268xN
SBOU003
SBOU002
Consult the Texas Instruments web site (www.ti.com) to
request either of these boards.
1
f*3dB
+
2pRFCF
(5)
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
the Noise Gain, or NG) will predict the closed-loop
bandwidth. In practice, this only holds true when the phase
margin approaches 90°, as it does in high gain
configurations. At low gains (increased feedback factors),
most amplifiers will exhibit a more complex response with
lower phase margin. The OPA2690 is compensated to
give a slightly peaked response in a noninverting gain of
2 (see Figure 1). This results in a typical gain of +2
bandwidth of 220MHz, far exceeding that predicted by
dividing the 300MHz GBP by 2. Increasing the gain will
cause the phase margin to approach 90° and the
bandwidth to more closely approach the predicted value of
(GBP/NG). At a gain of +10, the 30MHz bandwidth shown
in the Electrical Characteristics agrees with that predicted
using the simple formula and the typical GBP of 300MHz.
MACROMODELS
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the OPA2690 (use two OPA690 SPICE
models) is available through the Texas Instruments web
page (http://www.ti.com). These models do a good job of
predicting small-signal AC and transient performance
under a wide variety of operating conditions. They do not
do as well in predicting the harmonic distortion or dG/dP
characteristics. These models do not attempt to
distinguish between the package types in their
small-signal AC performance.
The frequency response in a gain of +2 may be modified
to achieve exceptional flatness simply by increasing the
noise gain to 2.5. One way to do this, without affecting the
+2 signal gain, is to add an 804Ω resistor across the two
inputs in the circuit of Figure 1. A similar technique may be
used to reduce peaking in unity-gain (voltage follower)
applications. For example, by using a 402Ω feedback
resistor along with a 402Ω resistor across the two op amp
inputs, the voltage follower response will be similar to the
gain of +2 response of Figure 2. Reducing the value of the
resistor across the op amp inputs will further limit the
frequency response due to increased noise gain.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
As the OPA2690 is a unity-gain stable, voltage-feedback
op amp, a wide range of resistor values may be used for
the feedback and gain setting resistors. The primary limits
on these values are set by dynamic range (noise and
distortion) and parasitic capacitance considerations. For a
noninverting unity-gain follower application, the feedback
connection should be made with a 25Ω resistor, not a
direct short. This will isolate the inverting input
capacitance from the output pin and improve the
frequency response flatness. Usually, the feedback
resistor value should be between 200Ω and 1.5kΩ. Below
200Ω, the feedback network will present additional output
loading which can degrade the harmonic distortion
performance of the OPA2690. Above 1.5kΩ, the typical
parasitic capacitance (approximately 0.2pF) across the
feedback resistor can cause unintentional band-limiting in
the amplifier response.
The OPA2690 exhibits minimal bandwidth reduction going
to single-supply (+5V) operation as compared with 5V.
This is because the internal bias control circuitry retains
nearly constant quiescent current as the total supply
voltage between the supply pins is changed.
INVERTING AMPLIFIER OPERATION
Since the OPA2690 is a general-purpose, wideband
voltage-feedback op amp, all of the familiar op amp
application circuits are available to the designer. Inverting
operation is one of the more common requirements and
offers several performance benefits. See Figure 12 for a
typical inverting configuration where the I/O impedances
and signal gain from Figure 1 are retained in an inverting
circuit configuration.
A good rule of thumb is to target the parallel combination
of RF and RG (see Figure 1) to be less than approximately
300Ω. The combined impedance RF RG interacts with
the inverting input capacitance, placing an additional pole
in the feedback network and thus, a zero in the forward
response. Assuming a 2pF total parasitic on the inverting
node, holding RF RG < 300Ω will keep this pole above
250MHz. By itself, this constraint implies that the feedback
resistor RF can increase to several kΩ at high gains. This
is acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out of
the frequency range of interest.
In the inverting configuration, three key design
considerations must be noted. The first is that the gain
resistor (RG) becomes part of the signal channel input
impedance. If input impedance matching is desired (which
is beneficial whenever the signal is coupled through a
cable, twisted-pair, long PC board trace, or other
transmission line conductor), RG may be set equal to the
required termination value and RF adjusted to give the
desired gain. This is the simplest approach and results in
optimum bandwidth and noise performance. However, at
low inverting gains, the resultant feedback resistor value
can present a significant load to the amplifier output. For
an inverting gain of −2, setting RG to 50Ω for input
matching eliminates the need for RM but requires a 100Ω
BANDWIDTH vs GAIN: NONINVERTING
OPERATION
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the Electrical Characteristics. Ideally,
dividing GBP by the noninverting signal gain (also called
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
feedback resistor. This has the interesting advantage that
the noise gain becomes equal to 2 for a 50Ω source
impedance—the same as the noninverting circuits
considered in the previous section. The amplifier output,
however, will now see the 100Ω feedback resistor in
parallel with the external load. In general, the feedback
resistor should be limited to the 200Ω to 1.5kΩ range. In
this case, it is preferable to increase both the RF and RG
values (see Figure 8), and then achieve the input matching
impedance with a third resistor (RM) to ground. The total
input impedance becomes the parallel combination of RG
and RM.
Combining this in parallel with the feedback resistor gives
the RB = 146Ω used in this example. To reduce the
additional high-frequency noise introduced by this resistor,
it is sometimes bypassed with a capacitor. As long as
RB < 350Ω, the capacitor is not required because the total
noise contribution of all other terms will be less than that
of the op amp input noise voltage. As a minimum, the
OPA2690 requires an RB value of 50Ω to damp out
parasitic-induced peaking—a direct short to ground on the
noninverting input runs the risk of a very high-frequency
instability in the input stage.
OUTPUT CURRENT AND VOLTAGE
The OPA2690 provides exceptional output voltage and
current capabilities in a low-cost monolithic op amp. Under
no-load conditions at +25°C, the output voltage typically
swings closer than 1V to either supply rail; the specified
swing limit is within 1.2V of either rail. Into a 15Ω load (the
minimum tested load), it will deliver more than 160mA.
+5V
+
µ
µ
6.8 F
0.1 F
µ
0.1 F
The specifications described previously, though familiar in
the industry, consider voltage and current limits separately.
In many applications, it is the voltage × current, or V-I
product, which is more relevant to circuit operation. Refer
to the Output Voltage and Current Limitations plot in the
Typical Characteristics. The X- and Y-axes of this graph
show the zero-voltage output current limit and the
zero-current output voltage limit, respectively. The four
quadrants give a more detailed view of the OPA2690
output drive capabilities, noting that the graph is bounded
by a Safe Operating Area of 1W maximum internal power
dissipation for each channel separately. Superimposing
resistor load lines onto the plot shows that the OPA2690
can drive 2.5V into 25Ω or 3.5V into 50Ω without
exceeding the output capabilities or the 1W dissipation
limit. A 100Ω load line (the standard test circuit load)
shows the full 3.9V output swing capability (see the
Electrical Characteristics).
RO
Ω
50
VO
1/2
O PA 2690
RB
146
Ω
50 Load
Ω
VO
−
=
2
Ω
50
VI
RG
200
RF
Ω
402
Ω
Source
VI
RM
Ω
67
µ
µ
6.8 F
0.1 F
+
−
5V
Figure 12. Gain of −2 Example Circuit
The second major consideration, touched on in the
previous paragraph, is that the signal source impedance
becomes part of the noise gain equation and influences
the bandwidth. For the example in Figure 12, the RM value
combines in parallel with the external 50Ω source
impedance, yielding an effective driving impedance of
50Ω 67Ω = 28.6Ω. This impedance is added in series
with RG for calculating the noise gain (NG). The resultant
NG is 2.8 for Figure 12, as opposed to only 2 if RM could
be eliminated as discussed above. The bandwidth will
therefore be slightly lower for the gain of −2 circuit of
Figure 12 than for the gain of +2 circuit of Figure 1.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at cold
startup will the output current and voltage decrease to the
numbers shown in the Electrical Characteristic tables. As
the output transistors deliver power, their junction
temperatures increase, decreasing their VBEs (increasing
the available output voltage swing) and increasing their
current gains (increasing the available output current). In
steady-state operation, the available output voltage and
current is always greater than that shown in the
over-temperature specifications because the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistor on
the noninverting input (RB). If this resistor is set equal to the
total DC resistance looking out of the inverting node, the
output DC error, due to the input bias currents, will be
reduced to (Input Offset Current) × RF. If the 50Ω source
impedance is DC-coupled in Figure 10, the total
resistance to ground on the inverting input will be 228Ω.
To protect the output stage from accidental shorts to
ground and the power supplies, output short-circuit
protection is included in the OPA2690. The circuit acts to
limit the maximum source or sink current to approximately
250mA.
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DRIVING CAPACITIVE LOADS
+5V
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including
additional external capacitance which may be
recommended to improve ADC linearity. A high-speed,
high open-loop gain amplifier like the OPA2690 can be
very susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the open-loop output resistance
of the amplifier is considered, this capacitive load
introduces an additional pole in the signal path that can
decrease the phase margin. Several external solutions to
this problem have been suggested. When the primary
considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series-isolation resistor
between the amplifier output and the capacitive load. This
does not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase margin and
improving stability.
Ω
50
Ω
175
RNG
Power−supply decoupling
not shown.
R
Ω
50
1/2
VO
OPA2690
CLOAD
Ω
402
Ω
402
−
5V
Figure 13. Capacitive Load Driving with Noise
Gain Tuning
This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain,
increasing the unloaded phase margin for the op amp.
Although this technique will reduce the required RS
resistor for a given capacitive load, it does increase the
noise at the output. It also will decrease the loop gain,
slightly decreasing the distortion performance. If, however,
the dominant distortion mechanism arises from a high RS
value, significant dynamic range improvement can be
achieved using this technique. Figure 14 shows the
required RS versus CLOAD parametric on noise gain using
this technique. This is the circuit of Figure 13 with RNG
adjusted to increase the noise gain (increasing the phase
margin) then sweeping CLOAD and finding the required RS
to get a flat frequency response. This plot also gives the
required RS versus CLOAD for the OPA2690 operated at
The Typical Characteristics show the recommended RS
versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads greater
than 2pF can begin to degrade the performance of the
OPA2690. Long PC board traces, unmatched cables, and
connections to multiple devices can easily exceed this
value. Always consider this effect carefully, and add the
recommended series resistor as close as possible to the
OPA2690 output pin (see the Board Layout Guidelines
section).
higher signal gains without RNG
.
100
90
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA2690 operating in a gain of +2, the frequency
response at the output pin is already slightly peaked
without the capacitive load requiring relatively high values
of RS to flatten the response at the load. Increasing the
noise gain will reduce the peaking as described previously.
The circuit of Figure 13 demonstrates this technique,
allowing lower values of RS to be used for a given
capacitive load.
80
70
NG = 2
60
50
40
30
20
10
0
NG = 3
NG = 4
1
10
100
1000
Capacitive Load (pF)
Figure 14. Required R vs Noise Gain
S
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
DISTORTION PERFORMANCE
ENI
The OPA2690 provides good distortion performance into
a 100Ω load on 5V supplies. Relative to alternative
solutions, it provides exceptional performance into lighter
loads and/or operating on a single +5V supply. Generally,
until the fundamental signal reaches very high frequency
or power levels, the 2nd-harmonic dominates the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that
the total load includes the feedback network; in the
noninverting configuration (see Figure 1), this is sum of
RF + RG, while in the inverting configuration it is just RF.
Also, providing an additional supply-decoupling capacitor
(0.1µF) between the supply pins (for bipolar operation)
improves the 2nd-order distortion slightly (3dB to 6dB).
Operating differentially also lowers 2nd-harmonic
distortion terms (see the plot on the front page).
1/2
OPA2690
EO
RS
IBN
ERS
RF
√
4kTRS
√
4kTRF
IBI
RG
4kT
RG
−
4kT = 1.6E 20J
_
at 290 K
Figure 15. Op Amp Noise Analysis Model
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 6 shows the general form for the
output noise voltage using the terms shown in Figure 15.
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The new output
stage used in the OPA2690 actually holds the difference
between fundamental power and the 2nd- and
3rd-harmonic powers relatively constant with increasing
output power until very large output swings are required
( > 4VPP). This also shows up in the 2-tone, 3rd-order
intermodulation spurious (IM3) response curves. The
3rd-order spurious levels are extremely low at low output
power levels. The output stage continues to hold them low
even as the fundamental power reaches very high levels.
As the Typical Characteristics show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power
level increases, the dynamic range does not decrease
significantly. For 2 tones centered at 20MHz, with
10dBm/tone into a matched 50Ω load (i.e., 2VPP for each
tone at the load, which requires 8VPP for the overall 2-tone
envelope at the output pin), the Typical Characteristics
show 46dBc difference between the test tone powers and
the 3rd-order intermodulation spurious powers. This
exceptional performance improves further when operating
at lower frequencies or powers.
) ǒI SǓ2
) ǒI FǓ2
2
2
ǒE
) 4kTR ǓNG
E
+
Ǹ
R
R
) 4kTR NG
NI
BN
BI
F
O
S
(6)
Dividing this expression by the noise gain
(NG = (1 + RF/RG)) will give the equivalent input-referred
spot noise voltage at the noninverting input, as shown in
Equation 7.
2
IBIRF
) ǒ Ǔ )
NG
4kTRF
NG
2
ǒ
SǓ2
) 4kTRS
+ Ǹ
EN
ENI ) IBN
R
(7)
Evaluating these two equations for the OPA2690 circuit
and component values (see Figure 1) gives a total output
spot noise voltage of 12.3nV/√Hz and a total equivalent
input spot noise voltage of 6.1nV/√Hz. This is including the
noise added by the bias current cancellation resistor
(175Ω) on the noninverting input. This total input-referred
spot noise voltage is only slightly higher than the
5.5nV/√Hz specification for the op amp voltage noise
alone. This will be the case as long as the impedances
appearing at each op amp input are limited to the
previously recommend maximum value of 300Ω. Keeping
both (RF RG) and the noninverting input source
impedance less than 300Ω will satisfy both noise and
frequency response flatness considerations. As the
resistor-induced noise is relatively negligible, additional
capacitive decoupling across the bias current cancellation
resistor (RB) for the inverting op amp configuration of
Figure 12 is not required.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense of a
higher input noise voltage. The 5.5nV/√Hz input voltage
noise for the OPA2690 is, however, much lower than
comparable amplifiers. The input-referred voltage noise,
and the two input-referred current noise terms, combine to
give low output noise under a wide variety of operating
conditions. Figure 15 shows the op amp noise analysis
model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/√Hz or pA/√Hz.
22
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
+5V
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feedback
op amp allows good output DC accuracy in a wide variety
of applications. The power-supply current trim for the
OPA2690 gives even tighter control than comparable
amplifiers. Although the high-speed input stage does
require relatively high input bias current (typically 5µA out
of each input terminal), the close matching between them
may be used to reduce the output DC error caused by this
current. The total output offset voltage may be
considerably reduced by matching the DC source
resistances appearing at the two inputs. This reduces the
output DC error due to the input bias currents to the offset
current times the feedback resistor. Evaluating the
configuration of Figure 1, and using worst-case +25°C
input offset voltage and current specifications, gives a
worst-case output offset voltage equal to:
Power−supply
decoupling not shown.
1/2
VO
OPA2690
µ
Ω
328
0.1 F
−
5V
RF
RG
500
+5V
Ω
Ω
1k
VI
Ω
Ω
5k
5k
200mV Output Adjustment
Ω
20k
Ω
10k
µ
0.1 F
VO
VI
RF
−
−
2
=
=
RG
(NG × VOS(MAX)
)
(RF × IOS(MAX))
−
5V
= (2 × 4.5mV) (402Ω × 1µA)
= 9.4mV − (NG = noninverting signal gain)
Figure 16. DC-Coupled, Inverting Gain of −2, with
Offset Adjustment
A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques eventually reduce to
adding a DC current through the feedback resistor. In
selecting an offset trim method, one key consideration is
the impact on the desired signal path frequency response.
If the signal path is intended to be noninverting, the offset
control is best applied as an inverting summing signal to
avoid interaction with the signal source. If the signal path
is intended to be inverting, applying the offset control to the
noninverting input may be considered. However, the DC
offset voltage on the summing junction will set up a DC
current back into the source that must be considered.
Applying an offset adjustment to the inverting op amp input
can change the noise gain and frequency response
flatness. For a DC-coupled inverting amplifier, Figure 16
shows one example of an offset adjustment technique that
has minimal impact on the signal frequency response. In
this case, the DC offsetting current is brought into the
inverting input node through resistor values that are much
larger than the signal path resistors. This ensures that the
adjustment circuit has minimal effect on the loop gain and
hence, the frequency response.
DISABLE OPERATION (SO-14 Package Only)
The OPA2690I-14D provides an optional disable feature
that can be used either to reduce system power or to
implement a simple channel multiplexing operation. If the
DIS control pin is left unconnected, the OPA2690I-14D will
operate normally. To disable, the control pin must be
asserted LOW. Figure 17 shows a simplified internal
circuit for the disable control feature.
+VS
Ω
15k
Q1
Ω
Ω
110k
25k
IS
Control
VDIS
−
VS
Figure 17. Simplified Disable Control Circuit
23
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
In normal operation, base current to Q1 is provided
through the 110kΩ resistor, while the emitter current
through the 15kΩ resistor sets up a voltage drop that is
inadequate to turn on the two diodes in Q1’s emitter. As
THERMAL ANALYSIS
Due to the high output power capability of the OPA2690,
heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired junction
temperature will set the maximum allowed internal power
dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed
150°C.
V
DIS is pulled LOW, additional current is pulled through the
15kΩ resistor, eventually turning on those two diodes
(≈100µA). At this point, any further current pulled out of
V
DIS goes through those diodes holding the emitter-base
voltage of Q1 at approximately 0V. This shuts off the
collector current out of Q1, turning the amplifier off. The
supply current in the disable mode are only those required
to operate the circuit of Figure 17. Additional circuitry
ensures that turn-on time occurs faster than turn-off time
(make-before-break).
Operating junction temperature (TJ) is given by
TA + PD × qJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional power
dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. PDL
depends on the required output signal and load but, for a
grounded resistive load, be at a maximum when the output
is fixed at a voltage equal to 1/2 of either supply voltage (for
equal bipolar supplies). Under this condition,
PDL = VS2/(4 × RL), where RL includes feedback
network loading.
When disabled, the output and input nodes go to a
high-impedance state. If the OPA2690 is operating at a
gain of +1, this will show a very high impedance at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(RF + RG) will appear as the impedance looking back into
the output, but the circuit will still show very high forward
and reverse isolation. If configured as an inverting
amplifier, the input and output will be connected through
the feedback network resistance (RF + RG) and the
isolation will be very poor as a result.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using
an OPA2690ID (SO-8 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature
of +85°C and with both outputs driving a grounded 20Ω
load to +2.5V.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 18
shows these glitches for the circuit of Figure 1 with the
input signal at 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
2
P
= 10V × 12.6mA + 2 [5 /(4 × (20Ω || 804Ω))] = 766mW
D
Maximum TJ = +85°C + (0.766W × 125°C/W) = 180°C.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 18, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the DIS input pin provides adequate
bandlimiting using just the parasitic input capacitance on
the DIS pin while still ensuring adequate logic level swing.
This absolute worst-case condition exceeds the specified
maximum junction temperature. Actual PDL is normally
less than that considered here. Carefully consider
maximum TJ in your application.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA2690 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
6
4
VDIS
2
0
30
Output Voltage
20
VO = 0
10
0
−
−
−
10
20
30
b) Minimize the distance (< 0.25”) from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
Time (20ns/div)
Figure 18. Disable/Enable Glitch
24
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these
capacitors. An optional supply decoupling capacitor
(0.1µF) across the two power supplies (for bipolar
operation) will improve 2nd-harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set RS from the plot of Recommended RS vs
Capacitive Load. Low parasitic capacitive loads (< 3pF)
may not need an RS because the OPA2690 is nominally
compensated to operate with a 2pF parasitic load. Higher
parasitic capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin, see Figure 14). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmis-
sion line is acceptable, implement a matched impedance
transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is
normally not necessary on board, and in fact, a higher
impedance environment will improve distortion as shown
in the distortion versus load plots. With a characteristic
board trace impedance defined (based on board material
and trace dimensions), a matching series resistor into the
trace from the output of the OPA2690 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance
will be the parallel combination of the shunt resistor and
the input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. The high output voltage and current capability
of the OPA2690 allows multiple destination devices to be
handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation
of a doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source end
only. Treat the trace as a capacitive load in this case and
set the series resistor value as shown in the plot of
Recommended RS vs Capacitive Load. This will not
preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low,
there will be some signal attenuation due to the voltage
divider formed by the series output into the terminating
impedance.
c) Careful selection and placement of external
components will preserve the high-frequency perfor-
mance of the OPA2690. Resistors should be a very low
reactance type. Surface-mount resistors work best and
allow a tighter overall layout. Metal film or carbon
composition axially-leaded resistors can also provide
good high-frequency performance. Again, keep their leads
and PC board traces as short as possible. Never use
wirewound type resistors in a high-frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Even with a low
parasitic capacitance shunting the external resistors,
excessively high resistor values can create significant time
constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values >
1.5kΩ, this parasitic capacitance can add a pole and/or
zero below 500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with load
driving considerations. The 402Ω feedback used in the
Electrical Characteristics is a good starting point for
design. Note that a 25Ω feedback resistor, rather than a
direct short, is suggested for the unity-gain follower
application. This effectively isolates the inverting input
capacitance from the output pin that would otherwise
cause an additional peaking in the gain of +1 frequency
response.
e) Socketing a high-speed part like the OPA2690 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA2690 onto the board.
d) Connections to other wideband devices on the board
may be made with short, direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
25
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SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (e.g., in
systems with 15V supply parts driving into the OPA2690),
current-limiting series resistors should be added into the
two inputs. Keep these resistor values as low as possible
since high values degrade both noise performance and
frequency response.
INPUT AND ESD PROTECTION
The OPA2690 is built using
a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are
protected with internal ESD protection diodes to the power
supplies, as shown in Figure 19.
+VCC
External
Pin
Internal
Circuitry
−
VCC
Figure 19. Internal ESD Protection
26
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
Drawing
OPA2690I-14D
OPA2690I-14DR
OPA2690ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
14
14
8
58
None
None
None
None
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
2500
100
OPA2690IDR
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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相关型号:
OPA2691I-14DG4
Dual Wideband Current Feedback Operational Amplifier,with Disable 14-SOIC -40 to 85
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