OPA2690IDG4_技术文档

OPA2674

SBOS270A − AUGUST 2003 − REVISED MAY 2006

Dual Wideband, High Output Current

Operational Amplifier with Current Limit

F_DEATURES

DESCRIPTION

WIDEBAND +12V OPERATION: 220MHz (G = +4)

UNITY-GAIN STABLE: 250MHz (G = +1)

HIGH OUTPUT CURRENT: 500mA

The OPA2674 provides the high output current and low

distortion required in emerging xDSL and Power Line

Modem driver applications. Operating on a single +12V

supply, the OPA2674 consumes a low 9mA/ch quiescent

current to deliver a very high 500mA output current. This

output current supports even the most demanding ADSL

CPE requirements with > 380mA minimum output current

(+25°C minimum value) with low harmonic distortion.

Differential driver applications deliver < −85dBc distortion

at the peak upstream power levels of full rate ADSL. The

high 200MHz bandwidth also supports the most

demanding VDSL line driver requirements.

D

OUTPUT VOLTAGE SWING: 10V

HIGH SLEW RATE: 2000V/µs

LOW SUPPLY CURRENT: 18mA

FLEXIBLE POWER CONTROL: SO-14 Only

OUTPUT CURRENT LIMIT ( 800mA)

PP

A_DPPLICATIONS

POWER LINE MODEM

Power control features are included in the SO-14 package

version to allow system power to be minimized. Two logic

control lines allow four quiescent power settings. These

include full power, power cutback for short loops, idle state

for no signal transmission but line match maintenance,

and shutdown for power off with a high impedance output.

D

xDSL LINE DRIVERS

CABLE MODEM DRIVERS

MATCHED I/Q CHANNEL AMPLIFIERS

BROADBAND VIDEO LINE DRIVERS

ARB LINE DRIVERS

Specified on 6V supplies (to support +12V operation), the

OPA2674 will also support a single +5V or dual 5V

supply. Video applications will benefit from a very high

output current to drive up to 10 parallel video loads (15Ω)

with < 0.1%/0.1° dG/dP nonlinearity.

HIGH CAP LOAD DRIVER

OPA2674 RELATED PRODUCTS

SINGLES

OPA691



DUALS

OPA2691

THS6042

OPA2677

TRIPLES

OPA3691



NOTES

Single +12V Capable

15V Capable



Single +12V Capable

+12V

Ω

20

1/2

O PA2674

Ω

17.4

Ω

324

1:1.7

µ

1 F

Ω

2k

+6.0V

Ω

100

AFE

Output

2V_PP

17.7V_PP

17.4

15V_PP

Twisted Pair

Ω

82.5

Ω

324

1/2

O PA2674

Ω

20

Single−Supply CPE Upstream Driver

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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Copyright  2003−2006, Texas Instruments Incorporated

www.ti.com

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

(1)

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE−LEAD

OPA2674

SO-8

D

″

−40°C to +85°C

OPA2674ID

OPA2674IDR

OPA2674I-14D

OPA2674I-14DR

Rails, 100

Tape and Reel, 2500

Rails, 58

″

OPA2674

″

SO-14

″

D

″

−40°C to +85°C

OPA2674I-14D

″

Tape and Reel, 2500

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site

at www.ti.com.

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handledwith appropriate precautions. Failure to observe

(1)

ABSOLUTE MAXIMUM RATINGS

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

DC

Internal Power Dissipation . . . . . . . . . . . . . . See Thermal Analysis

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V

proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

Input Common-Mode Voltage Range . . . . . . . . . . . . . . . . . . . .

V

S

Storage Temperature Range: D, -14D . . . . . . . . . . . −40°C to +125°C

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C

Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

J

ESD Rating

(2)

Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . 2000V

Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . 1000V

Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V

(1)

Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

(2)

Pins 2 and 6 on SO-8 package, and pins 1 and 7 on SO-14

package > 500V HBM.

PIN CONFIGURATIONS

Top View

SO-8

Top View

SO-14

OPA2674I−14D

−

1

2

3

4

5

6

7

14

Out A

In A

OPA2674ID

+In A

A0

13 NC

Out A

1

2

3

4

8

7

6

5

+V_S

12

11

10

9

NC

−

In A

+In A

Out B

Power

Control

−

V_S

+V_S

NC

−

In B

+In B

A1

−

V_S

+In B

NC

−

In B

8

Out B

NC = No Connection

2

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ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

ELECTRICAL CHARACTERISTICS: V = 6V

S

Boldface limits are tested at +25°C.

At T = +25°C, A = A = 1 (full power: for SO-14 only), G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted. See Figure 1 for AC performance only.

A

1

0

F

L

OPA2674ID, OPA2674I-14D

TYP

MIN/MAX OVER TEMPERATURE

TEST

0°C to

−40°C to

MIN/

MAX

LEVEL

(1)

+25°C

(2)

(3)

PARAMETER

AC Performance (see Figure 1)

TEST CONDITIONS

+25°C

+70°C

+85°C

UNITS

Small-Signal Bandwidth (V = 0.5V

O

)

G = +1, R = 511Ω

250

225

220

260

0.2

MHz

dB

typ

min

typ

C

B

C

B

C

B

C

PP

F

G = +2, R = 475Ω

170

200

165

195

160

190

F

G = +4, R = 402Ω

F

G = +8, R = 250Ω

F

Peaking at a Gain of +1

Bandwidth for 0.1dB Gain Flatness

Large-Signal Bandwidth

Slew Rate

G = +1, R = 511Ω

F

G = +4, V = 0.5V

PP

100

220

2000

1.6

40

35

30

MHz

V/µs

ns

min

typ

O

G = +4, V = 5V

160

155

150

O

PP

G = +4, 5V step

1500

1450

1400

min

typ

Rise Time and Fall Time

Harmonic Distortion

2nd-Harmonic

G = +4, V = 2V step

O

G = +4, f = 5MHz, V = 2V

O

PP

R

= 100Ω

≥ 500Ω

= 100Ω

≥ 500Ω

−72

−82

−81

−93

2

−68

−80

−79

−91

2.6

20

−67

−79

−78

−90

2.9

21

−66

−78

−77

−89

3.1

22

dBc

max

typ

B

C

L

R

L

3rd-Harmonic

R

dBc

L

R

dBc

L

Input Voltage Noise

f > 1MHz

nV/√Hz

pA/√Hz

%

Noninverting Input Current Noise

Inverting Input Current Noise

NTSC Differential Gain

16

24

29

30

31

NTSC, G = +2, R = 150Ω

0.03

0.05

0.01

0.04

−92

L

NTSC, G = +2, R = 37.5Ω

%

typ

L

NTCS Differential Phase

NTSC, G = +2, R = 150Ω

deg

typ

L

NTSC, G = +2, R = 37.5Ω

deg

typ

L

Channel-to-Channel Crosstalk

f = 5MHz, Input-Referred

dB

typ

(4)

DC Performance

Open-Loop Transimpedance Gain

Input Offset Voltage

V

= 0V, R = 100Ω

135

1

80

76

5

75

kΩ

mV

min

max

A

B

A

B

A

B

O

L

V

= 0V

4.5

10

5.3

12

CM

Offset Voltage Drift

4

10

32

50

40

100

µV/°C

µA

nA/°C

µA

Noninverting Input Bias Current

10

5

30

35

Noninverting Input Bias Current Drift

Inverting Input Bias Current

50

75

10

35

45

Inverting Input Bias Current Drift

100

150

nA/°C

(4)

Input

(5)

Common-Mode Input Range (CMIR)

4.5

55

4.1

51

4.0

50

4.0

50

V

dB

min

typ

A

C

B

Common-Mode Rejection Ratio (CMRR)

Noninverting Input Impedance

V

= 0V, Input-Referred

CM

250 2

22

kΩ pF

Ω

Minimum Inverting Input Resistance

Maximum Inverting Input Resistance

Open-Loop

12

35

min

max

22

(4)

Output

Output Voltage Swing

No Load

5.1

5.0

4.9

4.8

4.7

4.5

V

min

typ

A

C

A

C

R

= 100Ω

= 25Ω

L

R

4.8

V

L

Current Output

V

= 0

500

800

0.01

380

350

320

mA

Ω

min

typ

O

Short-Circuit Current

Closed-Loop Output Impedance

V

= 0

G = +4, f ≤ 100kHz

typ

(4)

Output

(SO-14 Only)

Current Output at Full Power

Current Output at Power Cutback

Current Output at Idle Power

A1 = 1, A0 = 1, V = 0

500

450

100

380

350

60

350

320

55

320

300

50

mA

min

A

O

A1 = 1, A0 = 0, V = 0

O

A1 = 0, A0 = 1, V = 0

O

(1)

(2)

Junction temperature = ambient for +25°C specifications.

Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature

specifications.

Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation.(C) Typical value only for information.

(3)

(4)

(5)

Current is considered positive out of node. V

is the input common-mode voltage.

CM

Tested < 3dB below minimum CMRR specification at CMIR limits.

3

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

ELECTRICAL CHARACTERISTICS: V = 6V (continued)

S

Boldface limits are tested at +25°C.

At T = +25°C, A = A = 1 (full power: for SO-14 only), G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted. See Figure 1 for AC performance only.

A

1

0

F

L

OPA2674ID, OPA2674I-14D

TYP

MIN/MAX OVER TEMPERATURE

TEST

0°C to

−40°C to

MIN/

MAX

LEVEL

(2)

(1)

+25°C

(3)

+70°C

+85°C

PARAMETER

TEST CONDITIONS

+25°C

UNITS

Power Supply

Specified Operating Voltage

Maximum Operating Voltage

Maximum Quiescent Current

Minimum Quiescent Current

Power-Supply Rejection Ratio (PSRR)

6

V

typ

max

min

C

A

6.3

18.6

17.4

51

6.3

18.8

16.5

49

6.3

19.2

16.0

48

V

=

6V

18

56

mA

dB

S

f = 100kHz, Input-Referred

Power Supply (SO-14 Only)

Maximum Logic 0

A1, A0, +V = +6V

2.5

3.3

2.0

3.6

1.8

4.0

1.5

4.2

V

max

min

max

typ

A

C

S

Minimum Logic 1

A1, A0, +V = +6V

S

Logic Input Current

A1 = 0V, A0 = 0V, Each Line

A1 = 1, A0 = 1 (logic levels)

A1 = 1, A0 = 0 (logic levels)

A1 = 0, A0 = 1 (logic levels)

A1 = 0, A0 = 0 (logic levels)

G = +4, f < 1MHz

60

90

100

18.8

14.4

5.1

105

19.2

14.8

5.3

µA

Supply Current at Full Power

Supply Current at Power Cutback

Supply Current at Idle Power

Supply Current at Shutdown

Output Impedance in Idle Power

Output Impedance in Shutdown

Supply Current Step Time

Output Switching Glitch

Shutdown Isolation

18.0

13.3

4.0

18.6

14.2

4.8

mA

Ω

1.0

1.3

1.4

1.5

0.1

100 4

200

20

kΩ pF

ns

typ

10% to 90% Change

Inputs at GND

typ

mV

dB

typ

G = +4, 1MHz, A1 = 0, A0 = 0

85

typ

Thermal Characteristics

−40 to

+85

Specification: ID, I-14D

°C

Thermal Resistance, q

JA

ID

SO-8

Junction-to-Ambient

125

100

°C/W

typ

C

I-14D SO-14

(1)

(2)

Junction temperature = ambient for +25°C specifications.

Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature

specifications.

Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation.(C) Typical value only for information.

(3)

(4)

(5)

Current is considered positive out of node. V

is the input common-mode voltage.

CM

Tested < 3dB below minimum CMRR specification at CMIR limits.

4

www.ti.com

ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

ELECTRICAL CHARACTERISTICS: V = +5V

S

Boldface limits are tested at +25°C.

At T = +25°C, A = 1, A = 1 (Full Power: for SO-14 only), G = +4, R = 453Ω, and R = 100Ω, unless otherwise noted. See Figure 3 for AC

A

1

0

F

L

performance only.

OPA2674ID, OPA2674I-14D

TYP

MIN/MAX OVER TEMPERATURE

TEST

0°C to

−40°C to

MIN/

MAX

LEVEL

(1)

+25°C

UNITS

(2)

(3)

PARAMETER

TEST CONDITIONS

+70°C

+85°C

AC Performance (see Figure 3)

Small-Signal Bandwidth (V = 0.5V

O

)

G = +1, R = 536Ω

220

175

168

175

0.6

34

MHz

dB

typ

min

typ

C

B

C

B

C

B

C

PP

F

G = +2, R = 511Ω

140

130

140

130

126

130

120

125

F

G = +4, R = 453Ω

F

G = +8, R = 332Ω

F

Peaking at a Gain of +1

Bandwidth for 0.1dB Gain Flatness

Large-Signal Bandwidth

Slew Rate

G = +1, R = 511Ω

F

G = +4, V = 0.5V

O

24

22

20

MHz

V/µs

ns

min

typ

PP

G = +4, V = 5V

190

900

2

140

650

135

625

130

600

O

PP

G = +4, 2V Step

min

typ

Rise Time and Fall Time

Harmonic Distortion

2nd-Harmonic

G = +4, V = 2V Step

O

G = +4, f = 5MHz, V = 2V

O

PP

R

= 100Ω

≥ 500Ω

= 100Ω

≥ 500Ω

−65

−72

−74

2

−63

−70

−71

2.6

20

−62

−69

−70

2.9

21

−61

−68

−69

3.1

22

dBc

max

typ

B

C

L

R

L

3rd-Harmonic

R

dBc

R

dBc

L

Input Voltage Noise

f > 1MHz

nV/√Hz

pA/√Hz

dB

Noninverting Input Current Noise

Inverting Input Current Noise

Channel-to-Channel Crosstalk

16

24

29

30

31

f = 5MHz, Input-Referred

−92

(4)

DC Performance

Open-Loop Transimpedance Gain

Input Offset Voltage

V

= 0V, R = 100Ω

110

0.8

4

72

70

68

kΩ

mV

min

max

A

B

A

B

A

B

O

L

V

= 0V

3.5

10

4.0

10

4.3

12

CM

Offset Voltage Drift

µV/°C

µA

nA/°C

µA

Noninverting Input Bias Current

10

5

30

32

35

Noninverting Input Bias Current Drift

Inverting Input Bias Current

50

75

10

35

40

45

Inverting Input Bias Current Drift

100

150

nA/°C

Input

(5)

Most Positive Input Voltage

3.7

1.3

53

3.3

1.7

49

3.2

1.8

48

3.1

1.9

47

V

min

A

(5)

Most Negative Input Voltage

Common-Mode Rejection Ratio (CMRR)

Noninverting Input Impedance

V

= 2.5V, Input-Referred

dB

CM

250 2

25

kΩ pF

typ

min

max

C

B

Minimum Inverting Input Resistance

Maximum Inverting Input Resistance

Open-Loop

15

40

Ω

25

Output

Most Positive Output Voltage

No Load

4.1

3.9

3.8

1.0

1.1

200

3.8

3.7

1.1

1.2

180

3.6

3.5

1.3

1.5

160

V

min

max

min

typ

A

C

R

= 100Ω

L

Most Negative Output Voltage

No Load

0.8

V

R

= 100Ω

1.0

V

L

Current Output

V

= 0

260

0.02

mA

Ω

O

Closed-Loop Output Impedance

G = +4, f ≤ 100kHz

Output (SO-14 Only)

Current Output at Full Power

Current Output at Power Cutback

Current Output at Idle Power

A1 = 1, A0 = 1, V = 0

260

200

80

200

160

50

180

140

45

160

120

40

mA

min

A

O

A1 = 1, A0 = 0, V = 0

O

A1 = 0, A0 = 1, V = 0

O

(1)

(2)

Junction temperature = ambient for +25°C specifications.

Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature

specifications.

Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation.(C) Typical value only for information.

(3)

(4)

(5)

Current considered positive out of node. V

is the input common-mode voltage.

Tested < 3dB below minimum CMRR at min/max input ranges.

CM

5

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

ELECTRICAL CHARACTERISTICS: V = +5V(continued)

S

Boldface limits are tested at +25°C.

At T = +25°C, A = 1, A = 1 (Full Power: for SO-14 only), G = +4, R = 453Ω, and R = 100Ω, unless otherwise noted. See Figure 3 for AC

A

1

0

F

L

performance only.

OPA2674ID, OPA2674I-14D

TYP

MIN/MAX OVER TEMPERATURE

TEST

0°C to

−40°C to

MIN/

MAX

LEVEL

(1)

+25°C

UNITS

(2)

(3)

+70°C

+85°C

PARAMETER

TEST CONDITIONS

Power Supply (Single−Supply Mode)

Specified Operating Voltage

+5

V

typ

max

min

typ

C

A

C

Maximum Operating Voltage

12.6

14.8

12

12.6

15.2

11.7

12.6

15.6

11.4

V

Maximum Quiescent Current

V

= +5V

13.6

52

mA

dB

S

Minimum Quiescent Current

Power-Supply Rejection Ratio (PSRR)

f = 100kHz, Input-Referred

Power Control (SO-14 Only)

Maximum Logic 0

A1, A0, +V = +5V

1.5

2.4

1.0

2.7

0.9

3.1

0.8

3.3

V

max

min

max

typ

A

C

S

Minimum Logic 1

A1, A0, +V = +5V

S

Logic Input Current

A1 = 0V, A0 = 0V, Each Line

A1 = 1, A0 = 1 (logic levels)

A1 = 1, A0 = 0 (logic levels)

A1 = 1, A0 = 1 (logic levels)

A1 = 0, A0 = 0 (logic levels)

G = +4, f = 1MHz

50

80

90

95

µA

Supply Current at Full Power

Supply Current at Power Cutback

Supply Current at Idle Power

Supply Current at Shutdown

Output Impedance in Idle Power

Output Impedance in Shutdown

Supply Current Step Time

Output Switching Glitch

13.8

10.2

3.0

14.8

10.8

3.2

15.2

11.1

3.5

15.6

11.4

3.8

mA

Ω

0.6

0.9

1.0

1.1

100 4

200

20

kΩ pF

ns

typ

10% to 90% Change

Inputs at GND

typ

mV

dB

typ

Shutdown Isolation

G = +4, 1MHz, A1 = 0, A0 = 0

85

typ

Thermal Characteristics

−40 to

+85

Specification: ID, I-14D

°C

Thermal Resistance, q

JA

ID

SO-8

Junction-to-Ambient

125

100

°C/W

typ

C

I-14D SO-14

(1)

(2)

Junction temperature = ambient for +25°C specifications.

Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature

specifications.

Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation.(C) Typical value only for information.

(3)

(4)

(5)

Current considered positive out of node. V

is the input common-mode voltage.

Tested < 3dB below minimum CMRR at min/max input ranges.

CM

6

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ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

TYPICAL CHARACTERISTICS: V = 6V

S

At T = +25°C, G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted.

A

F

L

INVERTING SMALL−SIGNAL

NONINVERTING SMALL−SIGNAL

FREQUENCY RESPONSE OVER GAIN

3

0

3

6

9

3

0

3

6

9

V_O= 0.5V_PP

Ω

G = +8, R_F= 250

Ω

G = +1, R_F= 511

−

G = +2,

−

Ω

G = 1, R_F= 475

Ω

R_F= 475

−

Ω

G = 2, R_F= 422

−

Ω

G = 4, R_F= 402

−

12

15

12

15

−

Ω

G = 8, R_F= 402

See Figure 2

100

See Figure 1

100

Ω

G = +4, R_F= 402

0

200

300

400

500

0

200

300

400

500

Frequency (MHz)

NONINVERTING SMALL−SIGNAL

FREQUENCY RESPONSE OVER POWER SETTINGS

INVERTING SMALL−SIGNAL

FREQUENCY RESPONSE OVER POWER SETTINGS

15

12

9

15

G = +4

V_O= 0.5V_PP

−

G =

4

12

9

V_O= 0.5V_PP

6

Full Power

3

0

Power Cutback

Idle Power

Power Cutback

−

3

6

−

3

6

See Figure 2 Idle Power

100 200

See Figure 1

100

0

200

300

400

500

0

300

400

500

Frequency (MHz)

NONINVERTING LARGE−SIGNAL

FREQUENCY RESPONSE

INVERTING LARGE−SIGNAL

FREQUENCY RESPONSE

15

12

9

15

12

9

≤

V_O1V_PP

−

G = 4

G = +4

V_O= 2V_PP

V_O= 5V_PP

≤

V_O1V_PP

6

V_O= 10V_PP

3

V_O= 10V_PP

V_O= 8V_PP

0

−

3

6

3

6

See Figure 1

100

See Figure 2

100

0

200

300

400

500

0

200

300

400

500

Frequency (MHz)

7

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

TYPICAL CHARACTERISTICS: V = 6V (continued)

S

At T = +25°C, G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted.

A

F

L

NONINVERTING PULSE RESPONSE

G = +4

Ω

R_L= 100

Left Scale

4V_PP

Large Signal

Right Scale

200mV_PP

Small Signal

See Figure 1

Time (5ns/div)

HARMONIC DISTORTION vs OUTPUT VOLTAGE

f = 5MHz

HARMONIC DISTORTION vs FREQUENCY

−

50

60

70

80

90

−

60

65

70

75

80

85

90

95

G = +4

V_O= 2V_PP

Ω

R_L= 100

2nd−Harmonic

Ω

R_L= 100

2nd−Harmonic

3rd−Harmonic

−

100

105

Single Channel, See Figure 1

0.1

Single Channel, See Figure 1

0.1

−

100

1

10

1

10

20

Output Voltage (V_PP

)

Frequency (MHz)

HARMONIC DISTORTION vs NONINVERTING GAIN

HARMONIC DISTORTION vs INVERTING GAIN

V_O= 2V_PP

−

60

65

70

75

80

85

90

−

60

V_O= 2V_PP

f = 5MHz

−

65

70

75

80

85

90

Ω

R_L= 100

Ω

R_L= 100

2nd−Harmonic

3rd−Harmonic

2nd−Harmonic

3rd−Harmonic

−

Single Channel, See Figure 1

Single Channel, See Figure 2

1

10

1

10

Gain Magnitude (V/V)

−

Gain Magnitude ( V/V)

8

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ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

TYPICAL CHARACTERISTICS: V = 6V (continued)

S

At T = +25°C, G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted.

A

F

L

HARMONIC DISTORTION vs LOAD RESISTANCE

2−TONE, 3rd−ORDER SPURIOUS LEVEL

−

50

55

60

65

70

75

80

85

90

95

−

60

65

70

75

80

85

90

95

V_O= 2V_PP

f = 5MHz

dBc = dB Below Carriers

20MHz

10MHz

2nd−Harmonic

3rd−Harmonic

5MHz

1MHz

Ω

Power at Matched 50 Load, See Figure 1

Single Channel, See Figure 1

−

100

−

100

10

100

Load Resistance ( )

1k

−

5

10

0

5

10

Ω

Single−Tone Load Power (dBm)

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

MAXIMUM OUTPUT SWING vs LOAD RESISTANCE

6

5

4

3

2

1

0

1

2

3

4

5

6

5

4

3

2

1

0

Ω

R_L= 100

Ω

R_L= 50

Ω

R_L= 10

Ω

R_L= 25

1W Internal Power

Single Channel

−

1

2

3

4

5

6

1W Internal Power

Single Channel

−

200

600

400

0

200

400

600

10

100

1k

Ω

I_O(mA)

Load Resistance ( )

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Inverting Current Noise

CHANNEL−TO−CHANNEL CROSSTALK

Input Referred

100

10

1

−

60

65

70

75

80

85

90

95

√

24pA/ Hz

Noninverting Current Noise

√

16pA/ Hz

−

100

105

110

Voltage Noise

√

2.0nV/ Hz

100

1k

10k

100k

1M

10M

1M

10M

100M

Frequency (Hz)

9

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

TYPICAL CHARACTERISTICS: V = 6V (continued)

S

At T = +25°C, G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted.

A

F

L

RECOMMENDED R_Svs CAPACITIVE LOAD

FREQUENCY RESPONSE vs CAPACITIVE LOAD

2

0

90

80

70

60

50

40

30

20

10

0

C_L= 10pF

C_L= 100pF

C_L= 22pF

−

2

4

6

8

−

R

S

1/2

OPA2674

C_L= 47pF

(1)

C

1kΩ

L

402Ω

133Ω

NOTE: (1) 1k is optional.

Ω

−

10

1M

10M

100M

1G

1

10

100

1k

Capacitive Load (pF)

Frequency (Hz)

OPEN−LOOP TRANSIMPEDANCE GAIN AND PHASE

Phase

CMRR AND PSRR vs FREQUENCY

CMRR

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

−

Gain

45

90

−

PSRR

135

180

225

270

+PSRR

1k

10k

100k

1M

10M

100M

10k

100k

1M

10M

100M

1G

Frequency (Hz)

CLOSED−LOOP OUTPUT IMPEDANCE

vs FREQUENCY

COMPOSITE VIDEO dG/dP

100

10

1

0.10

0.09

dP, Positive Video

dP, Negative Video

G = +2

R_F= 475

Ω

0.08 V_S

= 5V

0.07

0.06

0.05

dG, Negative Video

Idle Power

0.1

0.04

0.03

Full Power

0.01

0.02

dG, Positive Video

Power Cutback

1M

0.01

0.001

0

1

100k

10M

Frequency (Hz)

100M

2

3

4

5

6

7

8

9

10

Ω

Number of 150 Loads

10

www.ti.com

ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

TYPICAL CHARACTERISTICS: V = 6V (continued)

S

At T = +25°C, G = +4, R = 402Ω, and R = 100Ω, unless otherwise noted.

A

F

L

NONINVERTING OVERDRIVE RECOVERY

Input

INVERTING OVERDRIVE RECOVERY

4

16

12

8

4

3

2

1

0

−

16

12

8

−

G =

4

Input

Ω

R

_L= 100

3

2

1

0

−

4

Output

0

−

4

8

1

2

3

4

8

1

2

3

4

Output

See Figure 2

G = +4

−

12

16

12

16

Ω

R_L= 100

See Figure 1

−

Time (25ns/div)

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Supply Current, Full Power

TYPICAL DC DRIFT OVER TEMPERATURE

Inverting Bias Current

750

700

650

600

550

500

450

400

350

300

250

20

18

16

14

12

10

8

14

12

10

8

6

4

Noninverting Bias Current

Supply Current, Power Cutback

2

0

Input Offset Voltage

Sinking Output Current

Sourcing Output Current

−

2

4

6

8

6

4

Supply Current, Idle Power

−

10

12

14

2

−

0

−

25

50

0

25

50

75

100

125

−

25

50

0

25

50

75

100

125

_

Temperature ( C)

_

Ambient Temperature ( C)

COMMON−MODE INPUT VOLTAGE RANGE

AND OUTPUT SWING vs SUPPLY VOLTAGE

6

5

4

3

2

1

Positive Output Swing

Negative Output Swing

Negative Common−Mode Input Voltage

Positive Common−Mode Input Voltage

0

2

3

4

5

6

Supply Voltage ( V)

11

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

TYPICAL CHARACTERISTICS: V = 6V

S

At T = +25°C, Differential Gain = +9, R = 300Ω, and R = 70Ω, unless otherwise noted. See Figure 5 for AC performance only.

A

F

L

DIFFERENTIAL LARGE−SIGNAL

FREQUENCY RESPONSE

DIFFERENTIAL SMALL−SIGNAL

FREQUENCY RESPONSE

3

0

3

6

9

22

19

16

13

10

7

1V_PP

Ω

_D= +9

R_L= 70

G

Ω

R_L= 70

G_D= +2,

V_O= 1V_PP

Ω

R_F= 442

4V_PP

−

8V_PP

G_D= +5,

Ω

R_F= 383

16V_PP

G_D= +9,

Ω

R_F= 300

−

12

15

4

See Figure 5

50

See Figure 5

50

1

0

100

150

200

250

300

0

100

150

200

250

300

Frequency (MHz)

DIFFERENTIAL DISTORTION vs FREQUENCY

G = +9

DIFFERENTIAL DISTORTION vs LOAD RESISTANCE

−

50

65

70

80

90

−

60

65

70

75

80

85

90

95

f = 500kHz

G = +9

−

Ω

R_L= 70

−

Ω

R_L= 70

_O= 4V_PP

V

2nd−Harmonic

3rd−Harmonic

See Figure 5

3rd−Harmonic

−

100

105

110

−

100

110

See Figure 5

0.1

1

10

100

10

100

Load Resistance ( )

1k

Frequency (MHz)

Ω

ADSL MULTITONE POWER RATIO

(Upstream)

DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE

−

60

70

80

90

0

V_S

= 6V

f = 500kHz

G = +9

−

10

20

30

40

50

60

70

80

90

Ω

R_L= 70

2nd−Harmonic

3rd−Harmonic

−

100

See Figure 5

0.1

See Figure 5

20

−

110

−

100

1

10

20

0

40

60

80

100

120

140

160

Differential Output Voltage (V_PP

)

Frequency (kHz)

12

www.ti.com

ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

TYPICAL CHARACTERISTICS: V = +5V

S

At T = +25°C, G = +4, R = 453Ω, and R = 100Ω, unless otherwise noted.

A

F

L

NONINVERTING SMALL−SIGNAL

FREQUENCY RESPONSE

INVERTING SMALL−SIGNAL

FREQUENCY RESPONSE

3

0

3

6

9

3

0

3

6

9

−

G = +1

_F= 549

Ω

R

−

G = 8

R_F= 402

−

G = +2

_F= 511

G =

_F= 511

2

Ω

R

Ω

R

−

12

15

18

12

15

18

−

G = 4

_F= 453

−

G =

R_F= 549

1

G = +8

_F= 332

Ω

R

Ω

R

G = +4

_F= 453

See Figure 3

100

See Figure 4

100

Ω

R

0

200

300

400

500

0

200

300

400

500

Frequency (MHz)

INVERTING LARGE−SIGNAL

FREQUENCY RESPONSE

NONINVERTING LARGE−SIGNAL

FREQUENCY RESPONSE

15

12

9

15

12

9

−

G =

4

G = +4

R_L= 100 to V_S/2

Ω

R_L= 100 to V_S/2

Ω

V_O= 2V_PP

6

V_O= 3V_PP

3

V_O= 2V_PP

V_O= 1V_PP

0

V_O= 1V_PP

−

3

6

−

3

6

See Figure 4

100

See Figure 3

100

0

200

300

400

500

0

200

300

400

500

Frequency (MHz)

NONINVERTING PULSE RESPONSE

INVERTING PULSE RESPONSE

Left Scale

2V_PPLarge Signal

Right Scale

200mV_PPSmall Signal

G = +4

R_L= 100 to V_S/2

−

4

G =

R_L= 100 to V_S/2

Ω

See Figure 3

See Figure 4

Time (5ns/div)

13

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

TYPICAL CHARACTERISTICS: V = +5V (continued)

S

At T = +25°C, G = +4, R = 453Ω, and R = 100Ω, unless otherwise noted.

A

F

L

HARMONIC DISTORTION vs OUTPUT VOLTAGE

f = 5MHz

HARMONIC DISTORTION vs FREQUENCY

V_O= 2V_PP

−

60

65

70

75

80

85

90

−

50

55

60

65

70

75

80

85

90

G = +4

Ω

R_L= 100 to V_S/2

Ω

R_L= 100 to V_S/2

2nd−Harmonic

3rd−Harmonic

Single Channel, See Figure 3

1

Single Channel, See Figure 3

0.1

5

0.1

1

10

20

Output Voltage (V_PP

)

Frequency (MHz)

HARMONIC DISTORTION vs INVERTING GAIN

V_O= 2V_PP

HARMONIC DISTORTION vs NONINVERTING GAIN

−

55

60

65

70

75

80

85

−

55

60

65

70

75

80

85

V_O= 2V_PP

f = 5MHz

−

Ω

R_L= 100 to V_S/2

2nd−Harmonic

3rd−Harmonic

−

2nd−Harmonic

3rd−Harmonic

Single Channel, See Figure 4

Single Channel, See Figure 3

1

10

1

10

−

Gain Magnitude ( V/V)

Gain Magnitude (V/V)

2−TONE, 3rd−ORDER SPURIOUS LEVEL

HARMONIC DISTORTION vs LOAD RESISTANCE

V_O= 2V_PP

−

40

45

50

55

60

65

70

75

80

85

90

55

60

65

70

75

80

85

90

95

20MHz

f = 5MHz

−

Ω

R_L= 100 to V_S/2

2nd−Harmonic

10MHz

3rd−Harmonic

5MHz

1MHz

Single Channel. See Figure 3.

Ω

Power at matched 50 load.

Single Channel, See Figure 3

10

100

Load Resistance ( )

1k

−

2

14

12

10

8

6

4

0

2

Ω

Single−Tone Load Power (dBm)

14

www.ti.com

ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

TYPICAL CHARACTERISTICS: V = +5V

S

At T = +25°C, Differential Gain = +9, R = 316Ω, and R = 70Ω, unless otherwise noted.

A

F

L

DIFFERENTIAL SMALL−SIGNAL

FREQUENCY RESPONSE

DIFFERENTIAL PERFORMANCE

TEST CIRCUIT

3

0

3

6

9

+5V

Ω

R_L= 70

−

R

F

316Ω

G_D= +9

R

V

R

C

Ω

R_F= 316

L

O

I

G

R

316Ω

F

G_D= +2

Ω

R_F= 511

−

12

G_D= +5

R_F= 422

Ω

15

×

2

R

V

O

=

0

50

100

150

200

250

300

F

G

= 1 +

D

R

V

G

I

Frequency (MHz)

DIFFERENTIAL LARGE−SIGNAL

FREQUENCY RESPONSE

HARMONIC DISTORTION vs LOAD RESISTANCE

G_D= +9

−

60

65

70

75

80

85

90

95

22

19

16

13

10

7

−

Ω

R_L= 70

f = 500kHz

_O= 4V_PP

2nd−Harmonic

−

V

1V_PP

4V_PP

5V_PP

2V_PP

3rd−Harmonic

Ω

_D= +9

R_L= 70

G

4

1

−

100

0

50

100

150

200

250

300

10

100

Load Resistance ( )

1k

Ω

Frequency (MHz)

HARMONIC DISTORTION vs OUTPUT VOLTAGE

G_D= +9

DIFFERENTIAL DISTORTION vs FREQUENCY

G_D= +9

−

60

70

80

90

−

50

60

70

80

90

Ω

R_L= 70

Ω

R_L= 70

f = 500kHz

−

2nd−Harmonic

3rd−Harmonic

−

100

−

100

1

10

0.1

1

10

100

Output Voltage (V_PP

)

Frequency (MHz)

15

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

Figure 2 shows the DC-coupled, bipolar supply circuit

inverting gain configuration used as the basis for the 6V

Electrical and Typical Characteristics. Key design

considerations of the inverting configuration are

developed in the Inverting Amplifier Operation discussion.

APPLICATION INFORMATION

WIDEBAND CURRENT-FEEDBACK OPERATION

The OPA2674 gives the exceptional AC performance of a

wideband current-feedback op amp with a highly linear,

high-power output stage. Requiring only 9mA/ch

quiescent current, the OPA2674 swings to within 1V of

either supply rail and delivers in excess of 380mA at room

temperature. This low output headroom requirement,

along with supply voltage independent biasing, gives

remarkable single (+5V) supply operation. The OPA2674

delivers greater than 150MHz bandwidth driving a 2V_PP

output into 100Ω on a single +5V supply. Previous boosted

output stage amplifiers typically suffer from very poor

crossover distortion as the output current goes through

zero. The OPA2674 achieves a comparable power gain

with much better linearity. The primary advantage of a

current-feedback op amp over a voltage-feedback op amp

is that AC performance (bandwidth and distortion) is

relatively independent of signal gain. Figure 1 shows the

DC-coupled, gain of +4, dual power-supply circuit

configuration used as the basis of the 6V Electrical and

Typical Characteristics. For test purposes, the input

impedance is set to 50Ω with a resistor to ground and the

output impedance is set to 50Ω with a series output

resistor. Voltage swings reported in the electrical

characteristics are taken directly at the input and output

pins whereas load powers (dBm) are defined at a matched

50Ω load. For the circuit of Figure 1, the total effective load

is 100Ω || 535Ω = 84Ω.

+6V

Power−supply

decoupling

not shown.

Ω

50 Load

Ω

V_O50

1/2

OPA2674

Ω

50

−

6V

R_G

R_F

Ω

402

Source

Ω

100

V_I

R_M

Ω

100

Figure 2. DC-Coupled, G = −4, Bipolar Supply,

Specification and Test Circuit

Figure 3 shows the AC-coupled, gain of +4, single-supply

circuit configuration used as the basis of the +5V Electrical

and Typical Characteristics. Though not a rail-to-rail

design, the OPA2674 requires minimal input and output

voltage headroom compared to other wideband

current-feedback op amps. It will deliver a 3V_PPoutput

swing on a single +5V supply with greater than 100MHz

bandwidth. The key requirement of broadband single-

supply operation is to maintain input and output signal

swings within the usable voltage ranges at both the input

and the output. The circuit of Figure 3 establishes an input

midpoint bias using a simple resistive divider from the +5V

supply (two 806Ω resistors). The input signal is then

AC-coupled into this midpoint voltage bias. The input

voltage can swing to within 1.3V of either supply pin, giving

a 2.4V_PPinput signal range centered between the supply

pins. The input impedance matching resistor (57.6Ω) used

for testing is adjusted to give a 50Ω input match when the

parallel combination of the biasing divider network is

included. The gain resistor (R_G) is AC-coupled, giving the

circuit a DC gain of +1which puts the input DC bias

voltage (2.5V) on the output as well. The feedback resistor

value is adjusted from the bipolar supply condition to

re-optimize for a flat frequency response in +5V, gain of +4,

operation. Again, on a single +5V supply, the output

voltage can swing to within 1V of either supply pin while

delivering more than 200mA output current. A demanding

+6V

+V_S

µ

0.1 F

6.8 F

+

Ω

50 Source

Ω

50 Load

V_I

Ω

V_O50

Ω

50

1/2

OPA2674

R_F

Ω

402

R_G

Ω

133

µ

0.1 F

6.8 F

+

−

V_S

−

6V

100Ω load to

a midpoint bias is used in this

characterization circuit. The new output stage used in the

OPA2674 can deliver large bipolar output currents into this

midpoint load with minimal crossover distortion, as shown

by the +5V supply, harmonic distortion plots in the Typical

Characteristics charts.

Figure 1. DC-Coupled, G = +4, Bipolar Supply,

Specification and Test Circuit

16

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reduction of even-order harmonic distortion products.

Another important advantage for ADSL is that each

amplifier needs only half of the total output swing required

to drive the load.

+5V

+V_S

+

µ

6.8 F

0.1 F

+12V

Ω

806

20Ω

µ

0.1 F

1/2

OPA2674

V_I

Ω

V_O100

I_P= 128mA

Ω

57.6

Ω

806

1/2

OPA2674

V_S/2

17.4Ω

R_F

324Ω

R_M

0.1µF

1:1.7

R_F

Ω

453

AFE

2V_PP

Max

R_G

82.5Ω

2kΩ

Z_Line

+6V

17.7V_PP

100Ω

17.4Ω

R_F

324Ω

R_G

1µF

Assumed

0.1µF

R_M

Ω

150

µ

0.1 F

I_P= 128mA

1/2

OPA2674

20Ω

Figure 3. AC-Coupled, G = +4, Single-Supply,

Specification and Test Circuit

Figure 5. Single-Supply ADSL Upstream Driver

The analog front-end (AFE) signal is AC-coupled to the

driver and the noninverting input of each amplifier is biased

to the mid-supply voltage (in this case, +6V). Furthermore,

by providing the proper biasing to the amplifier, this

scheme also provides high-pass filtering with a corner

frequency set here at 5kHz. As the upstream signal

bandwidth starts at 26kHz, this high-pass filter does not

generate any problems and has the advantage of filtering

out unwanted lower frequencies.

The last configuration used as the basis of the +5V

Electrical and Typical Characteristics is shown in Figure 4.

Design considerations for this inverting, bipolar supply

configuration are covered either in single-supply

configuration (as shown in Figure 3) or in the Inverting

Amplifier Operation discussion.

+5V

The input signal is amplified with a gain set by the following

equation:

+

µ

6.8 F

0.1 F

Ω

806

2 R_F

R_G

G_D+ 1 )

Ω

V_O100

1/2

OPA2674

806

(1)

V_S/2

With R_F= 324Ω and R_G= 82.5Ω, the gain for this

differential amplifier is 8.85. This gain boosts the AFE

signal, assumed to be a maximum of 2V_PP, to a maximum

R_G

R_F

Ω

453

µ

0.1 F

Ω

113

V_I

of 17.7V_PP

.

R_M

Ω

88.7

Refer to the Setting Resistor Values to Optimize

Bandwidth section for a discussion on which feedback

resistor value to choose.

Figure 4. AC-Coupled, G = −4, Single-Supply,

Specification and Test Circuit

The two back-termination resistors (17.4Ω each) added at

each input of the transformer make the impedance of the

modem match the impedance of the phone line, and also

provide a means of detecting the received signal for the

receiver. The value of these resistors (R_M) is a function of

the line impedance and the transformer turns ratio (n),

given by the following equation:

SINGLE-SUPPLY ADSL UPSTREAM DRIVER

Figure 5 shows a single-supply ADSL upstream driver.

The dual OPA2674 is configured as a differential gain

stage to provide signal drive to the primary of the

transformer (here, a step-up transformer with a turns ratio

of 1:1.7). The main advantage of this configuration is the

Z_LINE

2n²

R_M+

(2)

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Consolidating Equations 3 through 6 allows the required

peak-to-peak voltage at the load function of the crest

factor, the load impedance, and the power in the load to be

expressed. Thus:

OPA2674 HDSL2 UPSTREAM DRIVER

Figure 6 shows an HDSL2 implementation of a single-

supply driver.

P

L

Ǹ

+12V

V

_LPP+ 2 CF (1mW) R_L 10₁₀

(7)

20

Ω

This V_LPPis usually computed for a nominal line

impedance and may be taken as a fixed design target.

1/2

OPA2674

I_P= 185mA

11.5

The next step for the driver is to compute the individual

amplifier output voltage and currents as a function of V_PP

on the line and transformer turns ratio. As the turns ratio

changes, the minimum allowed supply voltage also

changes. The peak current in the amplifier is given by:

0.1µF

Ω

324Ω

1:2.4

AFE

2V_PP

Max

2kΩ

+6V

Z_Line

135

82.5Ω

17.7V_PP

11.5Ω

Ω

1µF

324

0.1 F

µ

Assumed

Ω

2 V_LPP

1

2

1

4R_M

" I_P+

n

(8)

I_P= 185mA

With V_LPPdefined in Equation 7 and R_Mdefined in

Equation 2. The peak current is computed in Figure 7 by

noting that the total load is 4R_Mand that the peak current

1/2

OPA2674

20

Ω

is half of the peak-to-peak calculated using V_LPP

.

Figure 6. HDSL2 Upstream Driver

R_M

I_P

The two designs differ by the values of the matching

impedance, the load impedance, and the ratio turns of the

transformers. All of these differences are reflected in the

higher peak current and thus, the higher maximum power

dissipation in the output of the driver.

1:n

2V_LPP

n

V_LPP

n

R_L

V_LPP

R_M

LINE DRIVER HEADROOM MODEL

I_P

The first step in a driver design is to compute the

peak-to-peak output voltage from the target specifications.

This is done using the following equations:

Figure 7. Driver Peak Output Model

2

V_RMS

With the required output voltage and current versus turns

ratio set, an output stage headroom model will allow the

required supply voltage versus turns ratio to be developed.

P_L+ 10 log

(1mW) R_L

(3)

With P_Lpower and V_RMSvoltage at the load, and R_Lload

impedance, this gives:

The headroom model (see Figure 8) can be described with

the following set of equations:

P

L

First, as available output voltage for each amplifier:

Ǹ

V_RMS

+

(1mW) R_L 10₁₀

(4)

(5)

V

_OPP+ V_CC* (V₁) V₂) * I_P (R₁) R₂)

(9)

V_P+ CrestFactor V_RMS+ CF V_RMS

Or, second, as required single-supply voltage:

_CC+ V_OPP) (V₁) V₂) ) I_P (R₁) R₂)

with V_Ppeak voltage at the load and CF Crest Factor;

_LPP+ 2 CF V_RMS

V

(10)

V

(6)

The minimum supply voltage for a power and load

requirement is given by Equation 10.

with V_LPP: peak-to-peak voltage at the load.

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The two output stages used to drive the load of Figure 7

can be seen as an H-Bridge in Figure 9. The average

current drawn from the supply into this H-Bridge and load

will be the peak current in the load given by Equation 8

divided by the crest factor (CF) for the xDSL modulation.

This total power from the supply is then reduced by the

power in R_Tto leave the power dissipated internal to the

drivers in the four output stage transistors. That power is

simply the target line power used in Equation 2 plus the

power lost in the matching elements (R_M). In the examples

here, a perfect match is targeted giving the same power in

the matching elements as in the load. The output stage

power is then set by Equation 11.

+V_CC

R₁

V₁

V_O

I_P

V₂

R₂

I_P

C_F

P_OUT

+

V_CC* 2P_L

(11)

The total amplifier power is then:

I_P

Figure 8. Line Driver Headroom Model

P_TOT+ I_q V_CC

)

V_CC* 2P_L

C_F

(12)

Table 1 gives V₁, V₂, R₁, and R₂for both +12V and +5V

operation of the OPA2674.

For the ADSL CPE upstream driver design of Figure 5, the

peak current is 128mA for a signal that requires a crest

factor of 5.33 with a target line power of 13dBm into 100Ω

(20mW). With a typical quiescent current of 18mA and a

nominal supply voltage of +12V, the total internal power

Table 1. Line Driver Headroom Model Values

V

R

V

R

2

1

2

dissipation for the solution of Figure 5 will be:

+5V

0.9V

5Ω

2Ω

0.8V

0.9V

5Ω

2Ω

(13)

+12V

128mA

(

)

( ) ( )

12V * 2 20mW + 464mW

P

_TOT+ 18mA 12V )

5.33

TOTAL DRIVER POWER FOR xDSL

APPLICATIONS

DESIGN-IN TOOLS

DEMONSTRATION FIXTURES

The total internal power dissipation for the OPA2674 in an

xDSL line driver application will be the sum of the

quiescent power and the output stage power. The

OPA2674 holds a relatively constant quiescent current

versus supply voltage—giving a power contribution that is

simply the quiescent current times the supply voltage used

(the supply voltage will be greater than the solution given

in Equation 10). The total output stage power may be

computed with reference to Figure 9.

Two printed circuit boards (PCBs) are available to assist

in the initial evaluation of circuit performance using the

OPA2674 in its two package options. Both of these are

offered free of charge as unpopulated PCBs, delivered

with a user’s guide. The summary information for these

fixtures is shown in Table 2.

Table 2. Demonstration Fixtures by Package

LITERATURE

NUMBER

ORDERING

NUMBER

PRODUCT

PACKAGE

+V_CC

OPA2674ID

SO-8

SBOU003

DEM-OPA-SO-2A

DEM-OPA-SO-2D

I_P

I_AVG

=

OPA2674I-14D

SO-14

SBOU002

C_F

The demonstration fixtures can be requested at the Texas

Instruments web site (www.ti.com) through the OPA2674

product folder.

R_T

MACROMODELS AND APPLICATIONS

SUPPORT

Computer simulation of circuit performance using SPICE

is often useful when analyzing the performance of analog

circuits and systems. This is particularly true for video and

RF amplifier circuits where parasitic capacitance and

Figure 9. Output Stage Power Model

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inductance can have a major effect on circuit performance.

A SPICE model for the OPA2674 is available through the

TI web site (www.ti.com). This model does a good job of

predicting small-signal AC and transient performance

under a wide variety of operating conditions, but does not

do as well in predicting the harmonic distortion or dG/dP

characteristics. This model does not attempt to distinguish

between the package types in small-signal AC

performance, nor does it attempt to simulate channel-to-

channel coupling.

I

= feedback error current signal

ERR

Z(s) = frequency dependent open-loop transimpe-

dance gain from I to V

ERR

O

R_F

R_G

NG + NoiseGain + 1 )

The buffer gain is typically very close to 1.00 and is normal-

ly neglected from signal gain considerations. This gain,

however, sets the CMRR for a single op amp differential

amplifier configuration. For a buffer gain of α < 1.0, the

CMRR = −20 • log(1 − α)dB.

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO OPTIMIZE

BANDWIDTH

R_I, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA2674 inverting

output impedance is typically 22Ω.

A current-feedback op amp such as the OPA2674 can hold

an almost constant bandwidth over signal gain settings

with the proper adjustment of the external resistor values,

which are shown in the Typical Characteristics; the

small-signal bandwidth decreases only slightly with

increasing gain. These characteristic curves also show

that the feedback resistor is changed for each gain setting.

The resistor values on the inverting side of the circuit for a

current-feedback op amp can be treated as frequency

response compensation elements, whereas the ratios set

the signal gain. Figure 10 shows the small-signal

frequency response analysis circuit for the OPA2674.

A current-feedback op amp senses an error current in the

inverting node (as opposed to a differential input error

voltage for a voltage-feedback op amp) and passes this on

to the output through an internal frequency dependent

transimpedance gain. The Typical Characteristics show

this open-loop transimpedance response, which is

analogous to the open-loop voltage gain curve for a

voltage-feedback op amp. Developing the transfer

function for the circuit of Figure 10 gives Equation 14:

R

_aǒ_{1 )}^FǓ

R

V_O

V_I

G

a NG

+

R

)R NG

R

F

I

1 )

R

)R_Iǒ1)_R^FǓ

Z(s)

F

G

1 )

Z(s)

(14)

This is written in a loop-gain analysis format, where the

errors arising from a non-infinite open-loop gain are shown

in the denominator. If Z(s) were infinite over all frequen-

cies, the denominator of Equation 14 reduces to 1 and the

ideal desired signal gain shown in the numerator is

achieved. The fraction in the denominator of Equation 14

determines the frequency response. Equation 15 shows

this as the loop-gain equation:

V_I

α

V_O

R_I

Z_(S)I_ERR

I_ERR

Z(s)

R_F) R_I NG

+ LoopGain

R_F

(15)

If 20 log(R_F+ NG × R_I) is drawn on top of the open-loop

transimpedance plot, the difference between the two

would be the loop gain at a given frequency. Eventually,

Z(s) rolls off to equal the denominator of Equation 15, at

which point the loop gain has reduced to 1 (and the curves

have intersected). This point of equality is where the

amplifier closed-loop frequency response given by

Equation 14 starts to roll off, and is exactly analogous to

the frequency at which the noise gain equals the open-loop

voltage gain for a voltage-feedback op amp. The

difference here is that the total impedance in the

denominator of Equation 15 may be controlled somewhat

separately from the desired signal gain (or NG). The

OPA2674 is internally compensated to give a maximally

flat frequency response for R_F= 402Ω at NG = 4 on 6V

R_G

Figure 10. Current-Feedback Transfer Function

Analysis Circuit

The key elements of this current-feedback op amp model

are:

α = buffer gain from the noninverting input to the

inverting input

R = buffer output impedance

I

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supplies. Evaluating the denominator of Equation 15

(which is the feedback transimpedance) gives an optimal

target of 490Ω. As the signal gain changes, the

contribution of the NG × R_Iterm in the feedback

transimpedance changes, but the total can be held

constant by adjusting R_F. Equation 16 gives an

approximate equation for optimum R_Fover signal gain:

INVERTING AMPLIFIER OPERATION

As the OPA2674 is a general-purpose, wideband

current-feedback op amp, most of the familiar op amp

application circuits are available to the designer. Those

dual op amp applications that require considerable

flexibility in the feedback element (for example,

integrators, transimpedance, and some filters) should

consider a unity-gain stable, voltage-feedback amplifier

such as the OPA2822, because the feedback resistor is

the compensation element for a current-feedback op amp.

Wideband inverting operation (and especially summing) is

particularly suited to the OPA2674. Figure 12 shows a

typical inverting configuration where the I/O impedances

and signal gain from Figure 1 are retained in an inverting

circuit configuration.

R_F+ 490 * NG R_I

(16)

As the desired signal gain increases, this equation

eventually suggests a negative R_F. A somewhat subjective

limit to this adjustment can also be set by holding R_Gto a

minimum value of 20Ω. Lower values load both the buffer

stage at the input and the output stage if R_Fgets too

lowactually decreasing the bandwidth. Figure 11 shows

the recommended R_Fversus NG for both 6V and a single

+5V operation. The values for R_Fversus gain shown here

are approximately equal to the values used to generate the

Typical Characteristics. They differ in that the optimized

values used in the Typical Characteristics are also

correcting for board parasitic not considered in the

simplified analysis leading to Equation 16. The values

shown in Figure 11 give a good starting point for designs

where bandwidth optimization is desired.

+6V

Power−supply

decoupling not

shown.

Ω

50 Load

Ω

50

V_O

1/2

O PA 2674

Ω

50

Source

R_G

R_F

Ω

392

97.6

600

500

V_I

R_M

Ω

102

−

6V

+5V

400

Figure 12. Inverting Gain of −4 with Impedance

Matching

In the inverting configuration, two key design

considerations must be noted. First, the gain resistor (R_G)

becomes part of the signal source input impedance. If

input impedance matching is desired (which is beneficial

whenever the signal is coupled through a cable, twisted

pair, long PCB trace, or other transmission line conductor),

it is normally necessary to add an additional matching

resistor to ground. R_G, by itself, normally is not set to the

required input impedance since its value, along with the

desired gain, will determine an R_F, which may be

nonoptimal from a frequency response standpoint. The

total input impedance for the source becomes the parallel

combination of R_Gand R_M.

6V

5

300

200

Ω

R_G= 20

0

10

15

20

25

Noise Gain

Figure 11. Feedback Resistor vs Noise Gain

The total impedance going into the inverting input may be

used to adjust the closed-loop signal bandwidth. Inserting

a series resistor between the inverting input and the

summing junction increases the feedback impedance (the

denominator of Equation 15), decreasing the bandwidth.

The internal buffer output impedance for the OPA2674 is

slightly influenced by the source impedance coming from

of the noninverting input terminal. High-source resistors

also have the effect of increasing R_I, decreasing the

bandwidth. For those single-supply applications that

develop a midpoint bias at the noninverting input through

high valued resistors, the decoupling capacitor is essential

for power-supply ripple rejection, noninverting input noise

current shunting, and to minimize the high-frequency

value for R_Iin Figure 10.

The second major consideration is that the signal source

impedance becomes part of the noise gain equation and

has a slight effect on the bandwidth through Equation 15.

The values shown in Figure 12 have accounted for this by

slightly decreasing R_F(from the optimum values) to

reoptimize the bandwidth for the noise gain of Figure 12

(NG = 3.98). In the example of Figure 12, the R_Mvalue

combines in parallel with the external 50Ω source

impedance, yielding an effective driving impedance of

50Ω || 102Ω = 33.5Ω. This impedance is added in series

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with R_Gfor calculating the noise gainwhich gives

NG = 3.98. This value, and the inverting input impedance

of 22Ω, are inserted into Equation 16 to get the R_Fthat

appears in Figure 12. Note that the noninverting input in

this bipolar supply inverting application is connected

directly to ground.

specifications since the output stage junction

temperatures will be higher than the minimum specified

operating ambient.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an analog-to-digital (A/D)

converterincluding additional external capacitance that

may be recommended to improve the A/D converter

linearity. A high-speed, high open-loop gain amplifier like

the OPA2674 can be very susceptible to decreased

stability and closed-loop response peaking when a

capacitive load is placed directly on the output pin. When

the amplifier open-loop output resistance is considered,

this capacitive load introduces an additional pole in the

signal path that can decrease the phase margin. Several

external solutions to this problem have been suggested.

It is often suggested that an additional resistor be

connected to ground on the noninverting input to achieve

bias current error cancellation at the output. The input bias

currents for a current-feedback op amp are not generally

matched in either magnitude or polarity. Connecting a

resistor to ground on the noninverting input of the

OPA2674 in the circuit of Figure 12 actually provides

additional gain for that input bias and noise currents, but

does not decrease the output DC error because the input

bias currents are not matched.

OUTPUT CURRENT AND VOLTAGE

When the primary considerations are frequency response

flatness, pulse response fidelity, and/or distortion, the

simplest and most effective solution is to isolate the

capacitive load from the feedback loop by inserting a

series isolation resistor between the amplifier output and

the capacitive load. This does not eliminate the pole from

the loop response, but rather shifts it and adds a zero at a

higher frequency. The additional zero acts to cancel the

phase lag from the capacitive load pole, thus increasing

the phase margin and improving stability. The Typical

Characteristics show the Recommended R_Svs Capacitive

Load and the resulting frequency response at the load.

Parasitic capacitive loads greater than 2pF can begin to

degrade the performance of the OPA2674. Long PC board

traces, unmatched cables, and connections to multiple

devices can easily cause this value to be exceeded.

Always consider this effect carefully, and add the

recommended series resistor as close as possible to the

OPA2674 output pin (see the Board Layout Guidelines

section).

The OPA2674 provides output voltage and current

capabilities that are unsurpassed in a low-cost dual

monolithic op amp. Under no-load conditions at 25°C, the

output voltage typically swings closer than 1V to either

supply rail; the tested (+25°C) swing limit is within 1.1V of

either rail. Into a 6Ω load (the minimum tested load), it

delivers more than 380mA.

The specifications described previously, though familiar in

the industry, consider voltage and current limits separately.

In many applications, it is the voltage times current (or V−I

product) that is more relevant to circuit operation. Refer to

the Output Voltage and Current Limitations plot in the

Typical Characteristics (see page 9). The X and Y axes of

this graph show the zero-voltage output current limit and

the zero-current output voltage limit, respectively. The four

quadrants give a more detailed view of the OPA2674

output drive capabilities, noting that the graph is bounded

by a safe operating area of 1W maximum internal power

dissipation (in this case, for one channel only).

Superimposing resistor load lines onto the plot shows that

the OPA2674 can drive 4V into 10Ω or 4.5V into 25Ω

without exceeding the output capabilities or the 1W

dissipation limit. A 100Ω load line (the standard test circuit

load) shows the full 5.0V output swing capability, as

stated in the Electrical Characteristics tables. The

minimum specified output voltage and current over

temperature are set by worst-case simulations at the cold

temperature extreme. Only at cold startup will the output

current and voltage decrease to the numbers shown in the

Electrical Characteristics tables. As the output transistors

deliver power, the junction temperatures increase,

decreasing the V_BEs (increasing the available output

voltage swing), and increasing the current gains

(increasing the available output current). In steady-state

operation, the available output voltage and current will

always be greater than that shown in the over-temperature

DISTORTION PERFORMANCE

The OPA2674 provides good distortion performance into

a 100Ω load on 6V supplies. It also provides exceptional

performance into lighter loads and/or operating on a single

+5V supply. Generally, until the fundamental signal

reaches very high frequency or power levels, the

2nd-harmonic dominates the distortion with a negligible

3rd-harmonic component. Focusing then on the

2nd-harmonic, increasing the load impedance improves

distortion directly. Remember that the total load includes

the feedback networkin the noninverting configuration

(see Figure 1), this is the sum of R_F+ R_G; in the inverting

configuration, it is R_F. Also, providing an additional supply

decoupling capacitor (0.01µF) between the supply pins

(for bipolar operation) improves the 2nd-order distortion

slightly (3dB to 6dB).

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In most op amps, increasing the output voltage swing

directly increases harmonic distortion. The Typical

Characteristics show the 2nd-harmonic increasing at a

little less than the expected 2x rate, whereas the

3rd-harmonic increases at a little less than the expected 3x

rate. Where the test power doubles, the difference

between it and the 2nd-harmonic decreases less than the

expected 6dB, whereas the difference between it and the

3rd-harmonic decreases by less than the expected 12dB.

This factor also shows up in the 2-tone, 3rd-order

intermodulation spurious (IM3) response curves. The

3rd-order spurious levels are extremely low at low-output

power levels. The output stage continues to hold them low

even as the fundamental power reaches very high levels.

As the Typical Characteristics show, the spurious

intermodulation powers do not increase as predicted by a

traditional intercept model. As the fundamental power

level increases, the dynamic range does not decrease

significantly. For two tones centered at 20MHz, with

10dBm/tone into a matched 50Ω load (that is, 2V_PPfor

each tone at the load, which requires 8V_PPfor the overall

2-tone envelope at the output pin), the Typical

Characteristics show 67dBc difference between the

test-tone power and the 3rd-order intermodulation

spurious levels. This exceptional performance improves

further when operating at lower frequencies.

The total output spot noise voltage can be computed as the

square root of the sum of all squared output noise voltage

contributors. Equation 17 shows the general form for the

output noise voltage using the terms given in Figure 13.

2

₎ǒ

_SǓ

₎ǒ_I

S

_FǓ

_{) 4kTR NG}Ǔ

R

ǒ_E

Ǹ

E

+

I

R

) 4kTR

NI

BN

BI

F

O

(17)

E_NI

1/2

OPA2674

E_O

R_S

I_BN

E_RS

R_F

√4

kTR_S

√

4kTR_F

I_BI

R_G

4kT

R_G

−

4kT = 1.6E 20J

_

at 290 K

Figure 13. Op Amp Noise Analysis Model

Dividing this expression by the noise gain (NG = (1 + R_F/R_G))

gives the equivalent input-referred spot noise voltage at the

noninverting input, as shown in Equation 18.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a

higher output noise than comparable voltage-feedback op

amps. The OPA2674 offers an excellent balance between

voltage and current noise terms to achieve low output

noise. The inverting current noise (24pA/√Hz) is lower than

earlier solutions whereas the input voltage noise

(2.0nV/√Hz) is lower than most unity-gain stable,

wideband voltage-feedback op amps. This low input

voltage noise is achieved at the price of higher

noninverting input current noise (16pA/√Hz). As long as

the AC source impedance from the noninverting node is

less than 100Ω, this current noise does not contribute

significantly to the total output noise. The op amp input

voltage noise and the two input current noise terms

combine to give low output noise under a wide variety of

operating conditions. Figure 13 shows the op amp noise

analysis model with all noise terms included. In this model,

all noise terms are taken to be noise voltage or current

density terms in either nV/√Hz or pA/√Hz.

2

I

R

ǒ^BIǓ

4kTR

F

)

F

2

₎ǒ

_SǓ

E

+

E

I R

) 4kTR

)

ǒ

Ǹ

_NGǓ

N

NI

BN

S

NG

(18)

Evaluating these two equations for the OPA2674 circuit

and component values of Figure 1 gives a total output spot

noise voltage of 14.3nV/√Hz and a total equivalent input

spot noise voltage of 3.6nV/√Hz. This total input-referred

spot noise voltage is higher than the 2.0nV/√Hz

specification for the op amp voltage noise alone. This

reflects the noise added to the output by the inverting

current noise times the feedback resistor. If the feedback

resistor is reduced in high-gain configurations (as

suggested previously), the total input-referred voltage

noise given by Equation 18 approaches just the 2.0nV/√Hz

of the op amp. For example, going to a gain of +10 using

R_F= 298Ω gives a total input-referred noise of 2.3nV/√Hz.

DIFFERENTIAL NOISE PERFORMANCE

As the OPA2674 is used as a differential driver in xDSL

applications, it is important to analyze the noise in such a

configuration. See Figure 14 for the op amp noise model

for the differential configuration.

23

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

In order to minimize the noise contributed by I_N, it is

recommended to keep the noninverting source impedance

as low as possible.

I_N

Driver

DC ACCURACY AND OFFSET CONTROL

E_N

A current-feedback op amp such as the OPA2674

provides exceptional bandwidth in high gains, giving fast

pulse settling but only moderate DC accuracy. The

Electrical Characteristics show an input offset voltage

comparable to high-speed, voltage-feedback amplifiers;

however, the two input bias currents are somewhat higher

and are unmatched. While bias current cancellation

techniques are very effective with most voltage-feedback

op amps, they do not generally reduce the output DC offset

for wideband current-feedback op amps. Because the two

input bias currents are unrelated in both magnitude and

polarity, matching the input source impedance to reduce

error contribution to the output is ineffective. Evaluating

the configuration of Figure 1, using worst-case +25°C

input offset voltage and the two input bias currents, gives

a worst-case output offset range equal to:

R_S

√

4kTR_F

I_I

E_RS

R_F

√4

kTR_S

R_G

2

E_O

√

4kTR_G

R_F

√

4kTR_F

I_N

V

=

(NG × V

) (I × R /2 × NG) (I × R )

OS

where NG = noninverting signal gain

(4 × 4.5mV) (30µA × 25Ω × 4) (402Ω × 35µA)

= 18mV 3mV 14mV

= 35.0mV (max at 25°C)

IO(MAX) BN S BI F

E_N

I_I

R_S

E_RS

=

√4

kTR_S

V

OS

Figure 14. Differential Op Amp Noise Analysis

Model

POWER CONTROL OPERATION (SO-14 ONLY)

The OPA2674I-14D provides a power control feature that

may be used to reduce system power. The four modes of

operation for this power control feature are full-power,

power cutback, idle state, and power shutdown. These

four operating modes are set through two logic lines A0

and A1. Table 3 shows the different modes of operation.

As a reminder, the differential gain is expressed as:

2 R_F

G_D+ 1 )

R_G

(19)

The output noise voltage can be expressed as shown below:

(20)

Table 3. Power Control Mode of Operation

MODE OF

2

OPERATION

A1

1

A0

1

2

₎ǒ

_SǓ

ǒ

_FǓ

ǒ

_DǓ

F

e

+

2 G

Ǹ

ǒe_N

i

R

) 4kTR_SǓ) 2 i R

) 2 4kTR G

D

N

I

O

Full-Power

Power Cutback

Idle State

1

0

Dividing this expression by the differential noise gain

G_D= (1 + 2R_F/R_G) gives the equivalent input-referred

spot noise voltage at the noninverting input, as shown in

Equation 21.

0

1

Shutdown

0

(21)

The full-power mode is used for normal operating

condition. The power cutback mode brings the quiescent

power to 13.5mA. The idle state mode keeps a low output

impedance but reduces output power and bandwidth. The

shutdown mode has a high output impedance as well as

the lowest quiescent power (1.0mA).

2

R

I

G

4kTR

F

2

₎ǒ_i

R

N

_SǓ

_) 4kTRǓ_) 2ǒ_iǓ _) 2ǒ Ǔ

₊Ǹ

ǒ_e

e

2

N

S

G

D

Evaluating this equation for the OPA2674 circuit and

component values of Figure 5 gives a total output spot

noise voltage of 31.0nV/√Hz and a total equivalent input

spot noise voltage of 3.5nV/√Hz.

If the A0 and A1 pins are left unconnected, the

OPA2674I-14D operates normally (full-power).

24

www.ti.com

ꢂ ꢀꢉ ꢠꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

To change the power mode, the control pins (either A0 or

A1) must be asserted low. This logic control is referenced

to the positive supply, as shown in the simplified circuit of

Figure 15.

T

_{J MAX}= 70°C + ((12V × 18.8mA) + 12V × 128mA/(5.33)

− 40mW) × 125°C/W = 129°C

This maximum junction temperature is well below the

maximum of 150°C but may exceed system design

targets. Lower junction temperature would be possible

using the SO-14 package and the power cutback feature.

Repeating this calculation for that solution gives:

+V_S

T

_{J MAX}= 70°C + ((12V × 14.2mA) + 12V × 128mA/(5.33)

− 40mW) × 100°C/W = 112°C

Ω

120k

1.2V

For extremely high internal power applications, where

improved thermal performance is required, consider the

PSO-8 package of the OPA2677—a similar part with no

output stage current limit and a thermal impedance of less

than 50°C/W.

Q2

Q1

Ω

60k

BOARD LAYOUT GUIDELINES

Ω

46k

Achieving optimum performance with a high-frequency

amplifier like the OPA2674 requires careful attention to

board layout parasitic and external component types.

Recommendations that optimize performance include:

A0 or A1

−

V_S

V_SControl

Figure 15. Supply Power Control Circuit

The shutdown feature for the OPA2674 is a positive-sup-

ply referenced, current-controlled interface. Open-collec-

tor (or drain) interfaces are most effective, as long as the

controlling logic can sustain the resulting voltage (in open

mode) that appears at the A0 or A1 pins. The A0/A1 pin

voltage is one diode below the positive supply voltage

applied to the OPA2674 if the logic interface is open. For

voltage output logic interfaces, the on/off voltage levels

described in the Electrical Characteristics apply only for

either the +6V used for the 6V specifications or the +5V

for the single-supply specifications. An open-drain

interface is recommended to operate the A1 and A0 pins

using a higher positive supply and/or logic families with

inadequate high-level voltage swings.

a) Minimize parasitic capacitance to any AC ground for

all of the signal I/O pins. Parasitic capacitance on the

output and inverting input pins can cause instability; on the

noninverting input, it can react with the source impedance

to cause unintentional band limiting. To reduce unwanted

capacitance, a window around the signal I/O pins should

be opened in all of the ground and power planes around

those pins. Otherwise, ground and power planes should

be unbroken elsewhere on the board.

b) Minimize the distance (< 0.25″) from the power-supply

pins to high-frequency 0.1µF decoupling capacitors. At the

device pins, the ground and power plane layout should not

be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. The power-supply

connections (on pins 4 and 8 for an SO-8 package) should

always be decoupled with these capacitors. An optional

supply decoupling capacitor across the two power supplies

(for bipolar operation) improves 2nd-harmonic distortion

performance. Larger (2.2µF to 6.8µF) decoupling

capacitors, effective at a lower frequency, should also be

used on the main supply pins. These can be placed

somewhat farther from the device and may be shared

among several devices in the same area of the PC board.

THERMAL ANALYSIS

Due to the high output power capability of the OPA2674,

heat-sinking or forced airflow may be required under extreme

operating conditions. Maximum desired junction temperature

sets the maximum allowed internal power dissipation,

described below. In no case should the maximum junction

temperature be allowed to exceed 150°C.

Operating junction temperature (T_J) is given by T_A+ P_D×

q_JA. The total internal power dissipation (P_D) is the sum of

quiescent power (P_DQ) and additional power dissipation in

the output stage (P_DL) to deliver load power. Quiescent

power is the specified no-load supply current times the

total supply voltage across the part. P_DLdepends on the

required output signal and load. Using the example power

calculation for the ADSL CPE line driver concluded in

Equation 13, and a worst-case analysis at +70°C ambient,

the maximum internal junction temperature for the SO-8

package will be:

c) Careful selection and placement of external

components preserve the high-frequency performance

of the OPA2674. Resistors should be of a very low

reactance type. Surface-mount resistors work best and

allow a tighter overall layout. Metal film and carbon

composition axially leaded resistors can also provide good

high-frequency performance. Again, keep the leads and

PCB trace length as short as possible. Never use

wire-wound type resistors in a high-frequency application.

Although the output pin and inverting input pin are the most

T_{J MAX}= T_AMBIENT+ P_MAX× 125°C/W

25

ꢂꢀꢉꢠ ꢡꢢ ꢣ

SBOS270A − AUGUST 2003 − REVISED MAY 2006

www.ti.com

sensitive to parasitic capacitance, always position the

feedback and series output resistor, if any, as close as

possible to the output pin. Other network components,

such as noninverting input termination resistors, should

also be placed close to the package. Where double-side

component mounting is allowed, place the feedback

resistor directly under the package on the other side of the

board between the output and inverting input pins. The

frequency response is primarily determined by the

feedback resistor value as described previously.

Increasing the value reduces the bandwidth, whereas

decreasing it gives a more peaked frequency response.

The 402Ω feedback resistor used in the Typical

Characteristics at a gain of +4 on 6V supplies is a good

starting point for design. Note that a 511Ω feedback

resistor, rather than a direct short, is recommended for the

unity-gain follower application. A current-feedback op amp

requires a feedback resistor even in the unity-gain follower

configuration to control stability.

devices to be handled as separate transmission lines,

each with their own series and shunt terminations. If the

6dB attenuation of a doubly-terminated transmission line

is unacceptable, a long trace can be series-terminated at

the source end only. Treat the trace as a capacitive load in

this case, and set the series resistor value as shown in the

plot of R_Svs Capacitive Load. However, this does not

preserve signal integrity as well as a doubly-terminated

line. If the input impedance of the destination device is low,

there is some signal attenuation due to the voltage divider

formed by the series output into the terminating

impedance.

e) Socketing a high-speed part like the OPA2674 is not

recommended. The additional lead length and pin-to-pin

capacitance introduced by the socket can create an

extremely troublesome parasitic network, which can make

it almost impossible to achieve a smooth, stable frequency

response. Best results are obtained by soldering the

OPA2674 onto the board.

d) Connections to other wideband devices on the board

may be made with short direct traces or through onboard

transmission lines. For short connections, consider the

trace and the input to the next device as a lumped

capacitive load. Relatively wide traces (50mils to 100mils)

should be used, preferably with ground and power planes

opened up around them. Estimate the total capacitive load

and set R_Sfrom the plot of Recommended R_Svs

Capacitive Load (see page 10). Low parasitic capacitive

loads (< 5pF) may not need an R_Sbecause the OPA2674

is nominally compensated to operate with a 2pF parasitic

load. If a long trace is required, and the 6dB signal loss

intrinsic to a doubly-terminated transmission line is

acceptable, implement a matched impedance transmis-

sion line using microstrip or stripline techniques (consult

an ECL design handbook for microstrip and stripline layout

techniques). A 50Ω environment is normally not necessary

onboard. In fact, a higher impedance environment

improves distortion; see the distortion versus load plots.

With a characteristic board trace impedance defined

based on board material and trace dimensions, a matching

series resistor into the trace from the output of the

OPA2674 is used, as well as a terminating shunt resistor

at the input of the destination device. Remember also that

the terminating impedance is the parallel combination of

the shunt resistor and the input impedance of the

destination device.

INPUT AND ESD PROTECTION

The OPA2674 is built using a high-speed complementary

bipolar process. The internal junction breakdown voltages

are relatively low for these very small geometry devices

and are reflected in the absolute maximum ratings table.

All device pins have limited ESD protection using internal

diodes to the power supplies, as shown in Figure 16.

These diodes provide moderate protection to input

overdrive voltages above the supplies as well. The

protection diodes can typically support 30mA continuous

current. Where higher currents are possible (for example,

in systems with 15V supply parts driving into the

OPA2674), current-limiting series resistors should be

added into the two inputs. Keep these resistor values as

low as possible, because high values degrade both noise

performance and frequency response.

+V_CC

External

Internal

Circuitry

−

V_CC

This total effective impedance should be set to match the

trace impedance. The high output voltage and current

capability of the OPA2674 allows multiple destination

Figure 16. ESD Steering Diodes

26

Revision History

DATE

REV

PAGE

SECTION

Design-In-Tools

DESCRIPTION

Demonstrationfixture numbers changed.

5/06

A

19

:

NOTE Page numbers for previous revisions may differ from page numbers in the current version.

PACKAGE OPTION ADDENDUM

www.ti.com

25-Apr-2006

PACKAGING INFORMATION

Orderable Device

OPA2674I-14D

OPA2674I-14DG4

OPA2674I-14DR

OPA2674I-14DRG4

OPA2674ID

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

14

8

58 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SOIC

D

58 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

OPA2674IDG4

OPA2674IDR

8

100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

OPA2674IDRG4

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

16

OPA2674I-14DR

OPA2674IDR

D

14

8

SITE 41

6.5

6.9

9.5

5.4

2.1

2.0

8

16

12

Q1

330

12

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

OPA2674I-14DR

OPA2674IDR

D

14

8

SITE 41

346.0

33.0

29.0

Pack Materials-Page 2

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型号：	OPA2690IDG4
厂家：	TEXAS INSTRUMENTS
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