VSP5000PM_技术文档

VSP5000

SLES057 – DECEMBER 2002

12-BIT 30 MSPS DUAL CHANNEL

CCD SIGNAL FRONT END FOR DIGITAL COPIER

FEATURES

APPLICATIONS

D

Copiers

D

Dual Channel CCD Signal Processing:

– Correlated Double Sampler (CDS)

– Sample Hold Mode

– Digital Programmable Amplifier

– CCD Offset Correction (OB loop)

Scanners

Facsimiles

DESCRIPTION

The VSP5000 device is a complete application specific

standard product (ASSP) for charge-coupled device

(CCD) line sensor applications such as copiers, scanners,

and facsimiles. The VSP5000 device provides two

independent channels of processing lines and performs

analog front-end processing and analog-to-digital (A/D)

conversion. Each channel has a correlated double

sampler (CDS)/sample hold (SH) circuit, a 14-bit

analog-to-digital converter (ADC), a digital programmable

gain amplifier (DPGA), and an optical black (OB)

correction loop. Data output is 12 bits in length and the

2-channel A/D data is multiplexed and output.

High Performance A/D:

– 12-Bit Resolution

– INL: ±2 LSB

– DNL: ±0.5 LSB

– No Missing Codes

High-Speed Operation

– Sample Rate: 30 MHz (Minimum)

D

78-dB Signal-To-Noise Ratio (at 0-dB Gain)

Low Power Consumption:

– Low Voltage: 3 V to 3.6 V

– Low Power: 290 mW (Typ) at 3.3 V

– Standby Mode: 20 mW (Typ)

The VSP5000 is available in a 64-lead LQFP package and

operates from a single 3.3-V supply.

Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

VSP5000

www.ti.com

SLES057 – DECEMBER 2002

Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring

storageor handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE

OUTLINE

DESIGNATOR

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

(1)

VSP5000PM

Tray

VSP5000

64-LeadLQFP

PM

–25°C to 85°C

VSP5000PM

VSP5000PMR

Tape and reel

(1)

A detailed drawing and a dimension table are located at the end of the data sheet.

ABSOLUTE MAXIMUM RATINGS

overoperating free-air temperature range unless otherwise noted

(1)

UNITS

4 V

Supply voltage, V , V

CC DD

Supply voltage differences, among V

CC

terminals

±0.1 V

Ground voltage differences, AGND, DGND

Digitalinputvoltage

–0.3 V to V

+ 0.3 V

DD

Analoginputvoltage

–0.3 V to V

CC

Input current (any leads except supplies)

Ambient temperature under bias

Storage temperature

±10 mA

–40°C to 125°C

–55°C to 150°C

150°C

Junction temperature

Lead temperature (soldering, 5 sec)

Package temperature (IR reflow, peak)

260°C

250°C

(1)

Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and

functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

all specifications at T = 25°C, all power supply voltages = 3.3 V, and conversion rate (f

) = 30 MHz (unless otherwise noted)

ADCCK

A

VSP5000

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

12

2

MAX

Resolution

Signal pass

Bits

ch

Maximumconversionrate

30

MHz

DIGITAL INPUTS

V

Inputlow-to-highthresholdvoltage

Inputhigh-to-lowthresholdvoltage

Input logic high current

Input logic low current

Inputlimit

1.8

1.1

V

T+

T–

I

V = 3 V

±20

µA

IH

I

V = 0 V

I

IL

–0.3

V

CC

+0.3

SYSCLK clock duty cycle

Inputcapacitance

50%

5

pF

DIGITAL OUTPUTS (even and odd channels)

Logiccoding

Straightbinary

60

2.5

Multiplexfrequency

MHz

V

Output logic high voltage

Output logic low voltage

I

= –2 mA

OH

= 2 mA

0.4

V

OL

2

VSP5000

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SLES057– DECEMBER 2002

ELECTRICAL CHARACTERISTICS (CONTINUED)

all specifications at T = 25°C, all power supply voltages = 3.3 V, and conversion rate (f

) = 30 MHz (unless otherwise noted)

ADCCK

A

VSP5000

TYP

PARAMETER

ANALOG INPUT (CCDIN)

TEST CONDITIONS

UNIT

MIN

MAX

Input signal level for full-scale output

Allowablefeed-throughlevel

Inputcapacitance

DPGA gain = 0 dB

1400

mV

V

1

15

pF

V

Input limit

–0.3

3.3

TRANSFERCHARACTERISTICS

CDS mode, DPGA gain = 0 dB

SH mode, DPGA gain = 0 dB

CDS mode, DPGA gain = 0 dB

SH mode, DPGA gain = 0 dB

DPGA gain = 0 dB

±0.5

±1

±4

LSB

DNL

INL

Differential nonlinearity

Integral nonlinearity

±0.5

±2

±4

No missing codes

Assured

Step input settling time

Overload recovery time

Full-scale step input

1

2

pixel

Step input from 2 V to 0 V

pixels

Clock

Cycles

Data latency

9 (fixed)

DPGA gain = 0 dB

DPGA gain = 24 dB

78

54

(1)

Signal-to-noise ratio

dB

Channel mismatch

±3%

CORRELATED DOUBLE SAMPLER (CDS)

Reference level sample settling time

Data level sample settling time

INPUT CLAMP

Within 1 LSB, driver impedance = 50 Ω

8.3

ns

Clamp-on resistance

400

1.5

Ω

Clamp level

V

OPTICAL BLACK CLAMP LOOP

CCD offset correction range

DAC resolution

–300

300

mV

Bits

µA

µs

10

±0.15

±153

40.7

Minimum DAC output current

Maximum DAC output current

Loop time constant

COB pin

C

= 0.1 µF

COB

C

= 0.1 µF, at current DAC full scale

Slew rate

1530

V/s

output

Programrange

0

510

Optical black clamp level

LSB

OB clamp code = 0101 0000

160

REFERENCE

Positivereferencevoltage

Negativereferencevoltage

1.85

1.1

V

DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA)

Gain program resolution

10

16

8

Bits

Gain code = 11 1111 1111

24 dB

18 dB

0 dB

–

Gain code = 10 0000 0000

Gain code = 00 0100 0000

Gain code = 00 0000 0000

Gain

V/V

dB

1

0

Gain error

±0.5

(1)

SNR = 20 log (16384 / output rms noise in LSB), input connected to ground through a capacitor.

3

VSP5000

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SLES057– DECEMBER 2002

ELECTRICAL CHARACTERISTICS (CONTINUED)

all specifications at T = 25°C, all power supply voltages = 3.3 V, and conversion rate (f

) = 30 MHz (unless otherwise noted)

ADCCK

A

VSP5000

TYP

PARAMETER

SERIAL INTERFACE

Datalength

TEST CONDITIONS

UNIT

MIN

MAX

Chip address: 2 bits

Register address: 4 bits

Data: 10 bits

2

byte

MHz

Serial clock frequency

POWER SUPPLY

10

V , V

CC DD

Supplyvoltage

3

3.3

290

20

3.6

V

= V

= 3.3 V, f

DD SYSCLK

= 30 MHz,

CC

Load = 10 pF

Powerdissipation

mW

Stand-bymode

TEMPERATURE RANGE

Operating temperature

–25

–55

85

°C

Storage temperature

Thermal resistance

125

θ

64-leadLQFP

83

°C/W

JA

PIN ASSIGNMENTS

PM PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

1

B0 (LSB)

BYP_EV

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

B1

B2

B3

B4

B5

CCDIN_EV

AGND

3

4

V

CC

5

REFN_EV

CM_EV

REFP_EV

AGND

6

7

CLPOB

SYSCLK

SHD

SHP

B6

8

9

V

CC

10

11

12

13

14

15

16

REFP_OD

CM_OD

REFN_OD

B7

B8

V

CC

B9

B10

B11 (MSB)

AGND

CCDIN_OD

BYP_OD

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

4

VSP5000

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SLES057– DECEMBER 2002

FUNCTIONAL BLOCK DIAGRAM

SCLK SDI

RDO WRT

BYPP_EV

COB_EV

BYPM_EV BYP_EV REFP_EV CM_EV

REFN_EV

CA0

CA1

Serial

Interface

Even Channel

Internal Reference

RESET

Current

D-to-A

Buf

Decoder

Converter

CCD

Out Signal

Clamp

14-Bit

A-to-D

Converter

Digital

PGA

Output

Register

CDS/SH

CCDIN_EV

OUTENB

CDS/SH SEL

CLPOB

INPUTCLP

SHP

Output

Control

Timing / Control

12-Bit

Digital

Output

SHD

SYSCLK

14-Bit

A-to-D

Converter

CCDIN_OD

Digital

PGA

Output

Register

CDS/SH

CCD

Out Signal

Clamp

Current

D-to-A

Converter

Buf

Decoder

Odd Channel

Internal Reference

BYPP_OD

COB_OD BYPM_OD BYP_OD REFP_OD CM_OD

REFN_OD

5

VSP5000

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SLES057 – DECEMBER 2002

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

(1)

NO.

1

NAME

B0 (LSB)

B1

DO

DI

A/D converter output, bit 0 (LSB)

2

A/D converter output, bit 1

A/D converter output, bit 2

A/D converter output, bit 3

A/D converter output, bit 4

A/D converter output, bit 5

Optical black clamp pulse

System clock input

3

B2

4

B3

5

B4

6

B5

7

CLPOB

SYSCLK

SHD

SHP

B6

8

DI

9

DI

CCD data sampling pulse

CCD reference sampling pulse

A/D converter output, bit 6

A/D converter output, bit 7

A/D converter output, bit 8

A/D converter output, bit 9

A/D converter output, bit 10

A/D converter output, bit 11 (MSB)

Digital ground for digital outputs (B0–B11)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

DI

DO

P

B7

B8

B9

B10

B11 (MSB)

DGND

V

P

Digital power supply for digital outputs (B0–B11)

Analogground

DD

AGND

P

V

CC

P

Analog power supply

AGND

SDI

P

Analogground

DI

Serial interface data input

SCLK

WRT

DI

Serial interface data shift clock (triggered at the rising edge)

Serial interface data write pulse (triggered at the rising edge)

Serial interface register read output

Analogground

DI

RDO

DO

P

AGND

P

Analogground

V

CC

P

Analog power supply

COB_OD

BYPR_OD

BYPP_OD

BYPM_OD

BYP_OD

CCDIN_OD

AGND

AO

AI

Optical black loop output voltage (odd), connect a 0.1-µF capacitor from terminal to ground

Inputbuffer reference bypass (odd)

CDS positive reference bypass (odd), leave open or bypass to ground through a 0.1-µF capacitor

CDS negative reference bypass (odd), leave open or bypass to ground through a 0.1-µF capacitor

CDS common reference bypass (odd), bypass to ground through a 0.1-µF capacitor

CCD signal input (odd)

P

Analogground

V

CC

P

Analog power supply

REFN_OD

CM_OD

AO

P

A/D converter negative reference bypass (odd), bypass to ground through a 0.1-µF capacitor

A/D converter common reference bypass (odd), bypass to ground through a 0.1-µF capacitor

A/D converter positive reference bypass (odd), bypass to ground through a 0.1-µF capacitor

Analog power supply

REFP_OD

V

CC

AGND

P

Analogground

(1)

Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output

6

VSP5000

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TERMINAL

SLES057– DECEMBER 2002

Terminal Functions (Continued)

(1)

TYPE

DESCRIPTION

NO.

NAME

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

REFP_EV

CM_EV

AO

P

A/D converter positive reference bypass (even), bypass to ground through a 0.1-µF capacitor

A/D converter common reference bypass (even), bypass to ground through a 0.1-µF capacitor

A/D converter negative reference bypass (even), bypass to ground through a 0.1-µF capacitor

Analog power supply

REFN_EV

V

CC

AGND

P

Analogground

CCDIN_EV

BYP_EV

BYPM_EV

BYPP_EV

BYPR_EV

COB_EV

AI

CCD signal input (even)

AO

P

CDS common reference bypass (even), bypass to ground through a 0.1-µF capacitor

CDS negative reference bypass (even), bypass to ground through a 0.1-µF capacitor

CDS positive reference bypass (even), bypass to ground through a 0.1-µF capacitor

Inputbuffer reference bypass (even), bypass to ground through a 0.1-µF capacitor

Optical black loop output voltage (even), connect a 0.1-µF capacitor from terminal to ground

Analog power supply

V

CC

AGND

P

Analogground

AGND

P

Analogground

CDS_SEL

DI

CDS/SH mode select: High = CDS mode

Low = SH mode

57

58

59

60

61

CA1

DI

Chip address 1

CA0

Chip address 0

INPUTCLP

RESET

OUTENB

Input clamp control (active low)

Asynchronous register reset (active low)

Outputenable/disable:

High = High impedance

Low = Output enable

62

63

64

AGND

P

Analogground

V

Analog power supply

CC

DGND

Digital ground for digital outputs (B0–B11)

(2)

Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output

7

VSP5000

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SLES057– DECEMBER 2002

TIMING SPECIFICATION

VSP5000 CDS Mode Timing Specification (Even and Odd Channels)

CCD

Output

Signal

N

N+1

N+2

N+3

t

(CKP)

w(P)

SHP

t

d(S)

(PD)

t

(DP)

t

(CKP)

w(D)

SHD

t

d(S)

t

(CKP)

(INHIBIT)

(ADC)

SYSCLK

t

h(O)

d(O)

N*10

N*9

N*8

N*7

B[11:0]

(EV)

(OD)

(EV)

(OD)

(EV)

(OD)

(EV)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t

Clock period

33

ns

(CKP)

(ADC)

w(P)

SYSCLK pulse width

SHP pulse width

SHD pulse width

16.7

8.3

6

8

8.3

w(D)

SHP trailing edge to SHD leading edge

SHD trailing edge to SHP leading edge

Samplingdelay

(PD)

(DP)

3.5

d(S)

Inhibited clock period

10

6

(INHIBIT)

h(O)

Output hold time

(1)

Output delay at data output delay = 0 ns

9

(1)

(2)

t

d(O)

Output delay at data output delay = 3 ns

13

Clock

Cycles

DL

Data latency

9

(1)

(2)

Load = 25 pF, data output delay = 0 ns, meaning the delay time setting by configuration register of the serial interface.

Load = 25 pF, data output delay = 3 ns, meaning the delay time setting by configuration register of the serial interface.

8

VSP5000

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SLES057– DECEMBER 2002

VSP5000 SH Mode Timing Specification (Even and Odd Channels)

CCD

Output

N

N+1

N+2

N+3

Signal

(Even/

Odd)

t

(CKP)

w(D)

SHD

t

(DS)

d(S)

t

(CKP)

(ADC)

SYSCLK

t

d(O)

h(O)

N*10

N*9

N*8

N*7

B[11:0]

(EV)

(OD)

(EV)

(OD)

(EV)

(OD)

(EV)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

ns

t

Clock period

33

(CKP)

(ADC)

w(D)

d(S)

SYSCLK pulse width

SHD pulse width

Samplingdelay

16.7

8.3

ns

6

ns

3.5

ns

SHD trailing edge to SYSCLK leading edge

(1)

–8

6

ns

(DS)

h(O)

Output hold time

6

ns

(1)

(2)

Output delay at data output delay = 0 ns

9

ns

t

d(O)

Output delay at data output delay = 3 ns

13

ns

Clock

Cycles

DL

Data latency

9

(1)

(2)

Load = 25 pF, data output delay = 0 ns, meaning the delay time setting by configuration register of the serial interface.

Load = 25 pF, data output delay = 3 ns, meaning the delay time setting by configuration register of the serial interface.

9

VSP5000

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SLES057– DECEMBER 2002

VSP5000 Serial Interface Timing Specification 1 (Write)

t

h(X)

su(X)

WRT

t

su(W)

w(CKL)

t

(CKP)

w(CKH)

SCLK

t

h(D)

t

su(D)

MSB

(CA1)

LSB

(D0)

SD

2 Bytes

SYMBOL

PARAMETER

MIN

100

40

TYP

MAX

UNIT

ns

t

Clock period

(CKP)

w(CKH)

w(CKL)

su(D)

h(D)

Clock high pulse width

Clock low pulse width

Data setup time

ns

40

ns

30

ns

Data hold time

30

ns

WRT to SCLK setup time

SCLK to WRT hold time

WRT setup time

15

ns

su(X)

h(X)

15

ns

15

ns

su(W)

10

VSP5000

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SLES057– DECEMBER 2002

VSP5000 Serial Interface Timing Specification 2 (Read)

t

su(X)

WRT

t

su(XW)

t

w(CKH)

w(WR)

t

h(X)

t

w(CKL)

w(CKH)

SCLK

1

2

15

16

1

2

9

10

t

w(CKH)

su(D)

h(D)

t

(CKP)

MSB

(CA1)

LSB

(D0)

SD

t

(CKP)

2 Bytes

t

su(R)

MSB

(D9)

LSB

(D0)

RD

10 Bits

SYMBOL

PARAMETER

MIN

100

40

TYP

MAX

UNIT

ns

t

Clock period

(CKP)

w(CKH)

w(CKL)

su(D)

Clock high pulse width

Clock low pulse width

Data setup time (write)

Data hold time (write)

WRT to SCLK setup time

SCLK to WRT hold time

WRT setup time

ns

40

ns

30

ns

30

ns

h(D)

15

ns

su(X)

15

ns

h(X)

15

ns

su(XW)

w(WR)

su(R)

MinimumWRT width

Data setup time (read)

10

ns

30

ns

11

VSP5000

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SLES057– DECEMBER 2002

PRINCIPLES OF OPERATION

INTRODUCTION

The VSP5000 device was developed for an analog front-end of CCD line image sensor applications such as copiers,

facsimiles, and scanners. The VSP5000 device provides two independent even/odd channels of processing line, each

operating at 30 MHz.

The output signals from each even/odd channel of the CCD image sensor are sampled by a correlated double sampling

(CDS)circuitandthentransmittedtoa14-bithigh-precisionanalog-to-digitalconverter(ADC). TheADCoutputisamplified

totherequiredgaininthedigitalprogrammablegainamplifier(DPGA), thenroundedto12-bitdata, andoutputsequentially

as even/odd data, which synchronizes with SYSCLK. The CDS can be used as a sample/hold (SH) circuit by setting

terminal 56 (CDS_SEL) low.

Each channel has an optical black level clamp circuit (OB loop) and automatically compensates for offsets of the CCD and

CDS/SH during the OB pixel period (CLPOB). The OB level output value can be set at the required value by the serial

interface. DC bias lost in ac-coupling is reproduced as an input clamp voltage, which is at a necessary level for internal

operation. The input clamp voltage charges a capacitor connected to CCDIN during the dummy pixel period (INPUTCLP)

by SHP.

Gain setting, operation polarity of each clock, and selection of operation mode are accomplished through a serial interface

by accessing an internal register.

All register bits are reset to their default values by setting terminal 60 (RESET) to low.

CORRELATED DOUBLE SAMPLER (CDS) AND SAMPLE HOLD (SH) CIRCUIT

The CDS circuit removes low frequency and common-mode noise from the CCD image sensor output as it fluctuates per

pixel. Noise longer than one pixel in duration among the input signals is rejected by the subtraction operation at the CDS

circuit. Figure 1 shows a simplified CDS block graphic.

VSP5000

SHP

C

= 10 pF

1

2

+

CCDIN

OPA

CCD Output

–

C

IN

C

INPUTCLP

SHD

SHP

VCLAMP

Figure 1. Simplified Block Diagram of CDS and Input Clamp

The CDS can be configured as a sample hold (SH) circuit by setting terminal 56 (CDS_SEL) low. Figure 2 shows a

simplified SH circuit block graphic.

In the SH mode, the input clamp voltage (V

) is charged by the INPUTCLP signal and the sampling signal (SHD) to

CLAMP

the C capacitor. INPUTCLP is activated at the dummy pixel (or OB pixel) of the CCD. By these operations, the dummy

IN

pixel (or OB pixel) level voltage is fixed to V

at the CCDIN terminal.

CLAMP

12

VSP5000

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SLES057– DECEMBER 2002

At the sampling for the OB pixel and effective pixel, V

voltage is charged to capacitor C . The voltage lower than

1

CLAMP

V

according to the signal voltage from the CCD, is charged to capacitor C . As the voltage difference in C and C

CLAMP,

2 1 2

is acquired at the hold period, the signals from the CCD are acquired as the voltage based on V

.

CLAMP

In the CDS mode, signal voltage takes as voltage difference between sampled voltage by SHP (reference level) and SHD

(data level), the signal level is not affected, even when V changes or fluctuates in some degree due to leakage, etc.

CLAMP

However, when operated as SH, V

fluctuation causes an offset error, because the signal is acquired based on

CLAMP

V

. In order to prevent V

CLAMP

leakage, a buffer is inserted to input in the SH mode.

CLAMP

VSP5000

V

CLAMP

SHD

C

= 10 pF

1

+

OPA

–

CCDIN

2

CCD Output

C

IN

SHD

INPUTCLP

SHD

VCLAMP

Figure 2. Simplified Sample Hold (SH) Circuit

INPUT CLAMP (DUMMY PIXEL CLAMP)

Output from the CCD image sensor is ac-coupled with the VSP5000 device through a capacitor. The input clamp

reproduces the dc bias lost by ac-coupling and supplies optimum dc bias for proper operation of the CDS/SH circuit.

Simplified block diagrams of the input clamp circuit are shown in Figure 1 and Figure 2.

TheinputsignallevelisclampedtotheinternalreferencevoltagebyactivatingbothSHP(whenatCDSmodeorSHDwhen

at SH mode) and INPUTCLP during the CCD dummy pixel output period.

HIGH PERFORMANCE ANALOG-TO-DIGITAL CONVERTER (ADC)

The analog-to-digital converter of the VSP5000 device is composed of pipeline architecture. The ADC converter has

complete differential circuit configuration, error correction circuit, and 14-bit resolution is assured.

Circuits which generate the necessary reference voltage at the ADC are built inside the device and are shown as REFP

(high-potentialreference), REFN(low-potentialreference), andCM(common-modevoltage)terminalsoutsidethedevice.

In order to assure ADC accuracy, these reference voltage terminals need to be sufficiently decoupled by capacitors.

DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA)

The digital programmable gain amplifier (DPGA) circuit controls the gain value in the range of 0 fold to 16 fold (24 dB) by

inputting the digital code through the serial interface. See the serial interface section for details. Gain changes linearly in

proportion to the setting code.

13

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SLES057– DECEMBER 2002

GAIN

vs

INPUT GAIN CODE

18

16

14

12

10

8

6

4

2

0

64 128 192 256 320 384 448 512 576 640 704 768 832 896 960

Input Gain Code ( Decimal, 0 to 1023)

Figure 3. Setting Code vs Gain

OPTICAL BLACK (OB) LEVEL LOOP AND OB CLAMP LEVEL

The VSP5000 device has a built-in self calibration circuit (OB loop), which compensates the OB level by using the optical

black(OB)pixelsthatareoutputfromtheCCDimagesensor. Figure 4 shows a block diagram of the OB loopandOBclamp

circuit.

The CCD offset is compensated by converging the calibration circuit, while activating CLPOB during a period when the

OB pixels are output from the CCD.

Inthe CDS mode, the CCD offsetiscompensatedasadifferencebetweenthereferencelevelanddatalevelofanOBpixel.

In the SH mode, V

is compensated by INPUTCLP as a difference between the fixed dummy pixel and the OB pixel.

CLAMP

These compensated signal levels are recognized as actual OB levels and the outputs are clamped to the OB levels set

by the serial interface. These OB levels are the black base for the effective pixel period thereafter.

Since the DPGA is a gain stage outside the OB loop, the OB levels are not affected even when the gain is changed.

The converging time of the OB loop is determined based on the capacitor value connected to the COB terminal and the

output from the current output DAC of the loop. The time constant can be obtained from the following equation:

C

T +

ǒ

Ǔ

16384 I

MIN

where, C is the capacitor value connected to COB, I

is the minimum current (0.15 µA) of the current DAC, and 0.15 µA

MIN

is equivalent to 1 LSB of the DAC output. When C = 0.1 µF, T is 40.7 µs. Slew rate (SR) can be obtained from following

equation:

I

MAX

C

SR +

where, C is the capacitor value connected to COB, I

is equivalent to 1023 LSB of the DAC output.

is the maximum current (153 µA) of the current DAC, and 153 µA

MAX

14

VSP5000

www.ti.com

SLES057– DECEMBER 2002

OB Clamp

Level

ADC

DPGA

CDS/SH

Data Out

CCDIN

BYPP

Current

DAC

Decoder

CLPOB

COB

Figure 4. OB Loop and OB Level Clamp

The OB clamp level (digital output value) can be set through the serial interface by inputting a digital code to the OB clamp

level register. Table 1 shows the digital code and the corresponding OB clamp level.

Table 1. Input Code and OB Clamp Level To Be Set

INPUT CODE

00000000

00000001

L

OB CLAMP LEVEL (12-BIT)

0 LSB

2 LSB

L

0100 1111

01010000(default)

01010001

L

158 LSB

160 LSB

162 LSB

L

1011 1111

1111 1111

508 LSB

510 LSB

SETTLING OF OB LOOP AND INPUT CLAMP

As the input clamp voltage of the capacitor connected to CCDIN and the voltage of the OB loop COB capacitor are

completely discharged at start-up and after a long standby state, these two capacitors need to be charged to the proper

operational voltage.

The charging time for the input clamp voltage is logical AND of SHP (SHD when in SH mode) and INPUTCLP. Actual

chargingtime per line is only the width of the numbers of the SHP in the dummy pixel period. Equally, COB is only charged

during the OB pixel period. Therefore, some time is necessary to bring the VSP5000 device to normal operation status at

start-up.

Though start-up time depends on the number of dummy and pixels per line, 500 ms to 1 s must be kept to be on the safe

side.

15

VSP5000

www.ti.com

SLES057– DECEMBER 2002

STANDBY MODE

Normal operation mode and standby mode can be switched by the serial interface.

In standby mode, power consumption can be reduced as operation is suspended, except for the interface circuit and

referencevoltage supply. During standby mode, further power reduction may be obtained by suspending SYSCLK. When

restoringSYSCLK, which was suspendedduringstandbymode,morethantwoclocksofSYSCLKmustbeacquiredbefore

inputting the first command.

OUTPUT DATA DELAY

At the timing when the output data changes, large transient noise occurs due to many logic lines changing at one time.

Whenthistransientnoisetimingoverlapstheanalogsignalsamplingtiming,itmayaffecttheA/Dconvertingvalue.Toavoid

this, changing the timing of the VSP5000 output data can be delayed in approximately 3-ns steps by the serial control.

Delayedvalue, in this case, means the time addition for the default time between SYSCLK and the data output of the timing

specification.

TEST MODE AND TEST PATTERN

TheVSP5000devicecanbesettothetestmodebysettingtheconfigurationregister. Duringthetestmode, thetestpattern

generated inside the device is output with or without input.

There are two test patterns. One is a pattern which outputs code that is OB level +128 LSB per specific number of pixels

(stripe pattern) and the other is a pattern which increments code from 1 to 4095 in specified LSB per pixel (gradation

pattern). These can be selected by the serial interface setting the configuration register.

CHIP ADDRESS

The VSP5000 device has two chip address terminals, CA0 and CA1. The setting of these terminals gives a particular

addressfor the device and the data-writing device can be selected by the address in the serial interface data. By using this

function, the serial interface can be used as a common line for up to four devices.

REGISTER READING

Each register data can be read from the RDO terminal by setting the A3 bit of the serial interface data to 1 and setting the

reading register address to A[2:0].

After writing data which specifies the register, pulldown WRT and pullup SCLK and the output reading register value will

be output sequentially on RDO. See the serial interface section for details.

While reading the register, the writing function is disabled.

SERIAL INTERFACE

The serial interface of the VSP5000 device is composed of three signals: SDI, SCLK, and WRT. SDI data is sequentially

stored in the shift register at the SCLK rising edge and shift register data is stored to parallel latch at the WRT rising edge.

Serial data is 2-bytes fixed length and is composed of a 2-bit chip address, a 4-bit register address, and 10-bit data. The

chip address can only write to a register in a device that matches its value to the address set by CA0 and CA1. By using

this 2-bit chip address, the serial interface can be shared by other devices.

Both address and data store from MSB data first and LSB data last. When data with more than 2 bytes is applied, the final

2 bytes immediately before the WRT rising edge are effective and data stored first is lost.

Table 2 shows the register configuration and serial data format.

Each register value is defined at the time of power on. Resetting to the default value by the RESET signal or setting to the

desired value by the serial interface is necessary.

16

VSP5000

www.ti.com

SLES057– DECEMBER 2002

Table 2. Serial Interface Data Format

MSB

LSB

REGISTERS

CA1 CA0

A3

0

A2

0

A1

0

A0

0

D9

0

D8

0

D7

C7

0

D6

C6

0

D5

0

D4

C4

0

D3

0

D2

C2

0

D1

C1

0

D0

C0

S0

G0

O0

T0

0

Configuration

X

Standbymode

DPGA gain even

DPGA gain odd

OB clamp level even

OB clamp level odd

Test mode

0

1

0

1

0

G9

0

G8

0

G7

O7

0

G6

O6

0

G5

O5

T5

0

G4

O4

T4

0

G3

O3

0

G2

O2

T2

0

G1

O1

0

1

0

1

0

1

0

1

0

1

0

Reserved

0

1

0

Read out

1

R2

R1

R0

X

REGISTER DEFINITION

Configuration Register (address = 00h)

C[2:0]: Clock polarity select (default = 000)

C0: INPUTCLP polarity

C1: CLPOB polarity

C2: SHP/SHD polarity

0 = active low, 1 = active high

C4: Data output order (default = 0)

0 = Even/Odd, 1 = Odd/Even

C[7:6]: Data output delay (default = 00)

C7 = 0, C6 = 0

C7 = 0, C6 = 1

C7 = 1, C6 = 0

C7 = 1, C6 = 1

Delay time = 0 ns (typ)

Delay time = 3 ns (typ)

Delay time = 6 ns (typ)

Delay time = 9 ns (typ)

Standby Mode (address = 01h)

S0: Standby/normal operation select (default = 0)

0 = Normal operation mode, 1 = standby mode

Even Channel gain Register (address = 02h)

G[9:0]: Gain value = GAIN[9:0] /64 (default = 00 0100 0000)

Odd Channel Gain Register (address = 03h)

G[9:0]: Gain value = GAIN[9:0] /64 (default = 00 0100 0000)

Even Channel OB Clamp Register (address = 04h)

O[7:0]: OB clamp level = 2LSB x O[7:0] (default = 0101 0000)

Odd Channel OB Clamp Register (address = 05h)

O[7:0]: OB clamp level = 2LSB x O[7:0] (default = 0101 0000)

Test Mode Register (address = 06h)

T0: Test mode enable/disable (default = 0)

0 = Disable, 1 = Enable

T2: Test pattern select (default = 0)

0 = Gradation Pattern, 1 = Stripe Pattern

T[5:4]: Test pattern data interval (default = 00)

T5 = 0, T4 = 0

T5 = 0, T4 = 1

T5 = 1, T4 = 0

T5 = 1, T4 = 1

Stripe pattern = 8 pixels, gradation pattern = 2 pixels

Stripe pattern = 16 pixels, gradation pattern = 4 pixels

Stripe pattern = 32 pixels, gradation pattern = 8 pixels

Stripe pattern = 64 pixels, gradation pattern = 16 pixels

17

VSP5000

www.ti.com

SLES057– DECEMBER 2002

Register Read Out

R[2:0]: sets reading register address (A[2:0])

POWER SUPPLY, GROUNDING, AND DEVICE DECOUPLING RECOMMENDATIONS

The VSP5000 device incorporates high-precision, high-speed, ADC and analog circuitry, which are vulnerable to any

extraneousnoise from the voltage rails or elsewhere. For this reason, although the VSP5000 device has analog and digital

supply terminals, it must be treated as an analog component and all supply terminals except for V must be powered by

DD

the analog supply only. This ensures the most consistent results, since digital power lines often carry high levels of

wide-band noise that would otherwise be coupled into the device and degrade the achievable performance.

Propergrounding,shortleadlength,andtheuseofgroundplanesarealsoimportantforhigh-frequencydesigns.Multilayer

PC boards are recommended for the best performance, since they offer distinct advantages, for example, minimized

ground impedance and separation of signal layers by ground layers. It is highly recommended that the analog and digital

ground terminals of the VSP5000 device be joined together at the IC and be connected only to the analog ground of the

system.

The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply V (terminal 18). V must be

DD

separated from the other supply terminals completely or at least with a ferrite bead.

Because of the high operational speed, the ADC also generates high-frequency current transients and noises that are fed

back into the supply and reference lines. This requires the supply and reference terminals to be sufficiently bypassed. In

most cases, 0.1-µF ceramic chip capacitors are adequate to decouple the reference terminals. Supply terminals should

be decoupled to the ground plane with a parallel combination of tantalum (1 µF to 22 µF) and ceramic (0.1 µF)capacitors.

The effectiveness of the decoupling largely depends on the proximity to the individual terminal. V must be decoupled

DD

to the proximity of DGND (terminal 17 and terminal 64).

18

VSP5000

www.ti.com

SLES057– DECEMBER 2002

MECHANICAL DATA

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–ā7°

11,80

1,45

1,35

0,75

0,45

SeatingPlane

1,60 MAX

0,08

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

19

PACKAGE OPTION ADDENDUM

www.ti.com

22-Mar-2005

PACKAGING INFORMATION

Orderable Device

VSP5000PM

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

ACTIVE

LQFP

PM

64

160

Pb-Free

(RoHS)

A42 SNBI

Call TI

Level-1-260C-UNLIM

Call TI

VSP5000PMR

VSP5000Y

ACTIVE

LQFP

SOIC

PM

D

1000

Pb-Free

(RoHS)

PREVIEW

TBD

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

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型号：	VSP5000PM
厂家：	BURR-BROWN CORPORATION
描述：	12-BIT 30 MSPS DUAL CHANNEL CCD SIGNAL FRONT END FOR DIGITAL COPIER 12位30 MSPS双通道CCD信号前端数字复印机 CD
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