CS4365 [CIRRUS]
114 dB, 192 kHz 6-Channel D/A Converter; 114分贝192千赫6声道D / A转换器型号: | CS4365 |
厂家: | CIRRUS LOGIC |
描述: | 114 dB, 192 kHz 6-Channel D/A Converter |
文件: | 总51页 (文件大小:735K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CS4365
114 dB, 192 kHz 6-Channel D/A Converter
Features
Description
! Advanced Multi-bit Delta Sigma Architecture
! 24-bit Conversion
The CS4365 is a complete 6-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
half-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Follow-
ing this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.
! Automatic Detection of Sample Rates up to 192
kHz
! 114 dB Dynamic Range
! -100 dB THD+N
! Direct Stream Digital Mode
– Non-Decimating Volume Control
– On-Chip 50 kHz Filter
The CS4365 also has a proprietary DSD processor
which allows for volume control and 50 kHz on-chip fil-
tering without an intermediate decimation stage. It also
offers an optional path for direct DSD conversion by di-
rectly using the multi-element switched capacitor array.
– Matched PCM and DSD Analog Output
Levels
! Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
The CS4365 accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.
! Selectable Digital Filters
! Volume Control with 1/2-dB Step Size and Soft
Ramp
! Low Clock Jitter Sensitivity
! +5 V Analog Supply, +2.5 V Digital Supply
ORDERING INFORMATION
! Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
See page 45.
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Hardware Mode or
I2C/SPI Software Mode
Control Data
Internal Voltage
Reference
Register/Hardware
Configuration
Reset
Serial Audio Port
Supply = 1.8 V to 5 V
Six Channels of
Differential
Outputs
Switch-Cap
DAC and
Analog Filters
6
6
Volume
Controls
Digital
Filters
Multi-bit ∆Σ
Modulators
PCM Serial
Audio Input
6
TDM Serial
Audio Input
External Mute
Control
DSD Processor
-Volume control
-50 kHz filter
Mute Signals
6
DSD Audio
Input
Copyright © Cirrus Logic, Inc. 2005
MAY '05
DS670PP1
(All Rights Reserved)
http://www.cirrus.com
CS4365
TABLE OF CONTENTS
1. PIN DESCRIPTION..................................................................................................................... 6
2. CHARACTERISTICS AND SPECIFICATIONS.......................................................................... 8
3. APPLICATIONS ....................................................................................................................... 20
3.1 Master Clock..................................................................................................................... 20
3.2 Mode Select...................................................................................................................... 21
3.3 Digital Interface Formats .................................................................................................. 22
3.3.1 OLM #1 ................................................................................................................ 23
3.3.2 OLM #2 ................................................................................................................ 24
3.3.3 TDM ..................................................................................................................... 24
3.4 Oversampling Modes........................................................................................................ 24
3.5 Interpolation Filter............................................................................................................. 25
3.6 De-Emphasis .................................................................................................................... 25
3.7 ATAPI Specification.......................................................................................................... 26
3.8 Direct Stream Digital (DSD) Mode.................................................................................... 26
3.9 Grounding and Power Supply Arrangements ................................................................... 27
3.9.1 Capacitor Placement............................................................................................ 27
3.10 Analog Output and Filtering............................................................................................ 27
3.11 The MUTEC Outputs...................................................................................................... 29
3.12 Recommended Power-Up Sequence............................................................................. 29
3.12.1 Hardware Mode ................................................................................................. 29
3.12.2 Software Mode................................................................................................... 29
3.13 Recommended Procedure for Switching Operational Modes......................................... 30
3.14 Control Port Interface ..................................................................................................... 31
3.14.1 MAP Auto Increment.......................................................................................... 31
2
3.14.2 I C Mode............................................................................................................ 31
2
3.14.2.1 I C Write ............................................................................................ 31
2
3.14.2.2 I C Read ............................................................................................ 32
3.14.3 SPI™ Mode........................................................................................................ 33
3.14.3.1 SPI Write............................................................................................ 33
3.15 Memory Address Pointer (MAP)
............................................................................... 33
4. REGISTER QUICK REFERENCE ........................................................................................... 34
5. REGISTER DESCRIPTION ...................................................................................................... 35
5.1 Chip Revision (address 01h) ........................................................................................... 35
5.1.1 Part Number ID (part) [Read Only] ...................................................................... 35
5.2 Mode Control 1 (address 02h).......................................................................................... 35
5.2.1 Control Port Enable (CPEN) ................................................................................ 35
5.2.2 Freeze Controls (Freeze)..................................................................................... 35
5.2.3 PCM/DSD Selection (DSD/PCM)......................................................................... 36
5.2.4 DAC Pair Disable (DACx_DIS) ............................................................................ 36
5.2.5 Power Down (PDN).............................................................................................. 36
5.3 PCM Control (address 03h)............................................................................................. 36
5.3.1 Digital Interface Format (dif) ................................................................................ 36
5.3.2 Functional Mode (FM).......................................................................................... 37
5.4 DSD Control (address 04h) ............................................................................................. 37
5.4.1 DSD Mode Digital Interface Format (DSD_dif) .................................................... 37
5.4.2 Direct DSD Conversion (DIR_DSD)..................................................................... 38
5.4.3 Static DSD Detect (static_DSD)........................................................................... 38
5.4.4 Invalid DSD Detect (invalid_DSD) ....................................................................... 38
5.4.5 DSD Phase Modulation Mode Select (DSD_PM_mode) ..................................... 38
5.4.6 DSD Phase Modulation Mode Enable (DSD_pm_EN) ........................................ 38
5.5 Filter Control (address 05h)............................................................................................. 39
5.5.1 Interpolation Filter Select (FILT_SEL).................................................................. 39
2
DS670PP1
CS4365
5.6 Invert Control (address 06h)............................................................................................ 39
5.6.1 Invert Signal Polarity (Inv_xx) .............................................................................. 39
5.7 Group Control (address 07h)........................................................................................... 39
5.7.1 Mute Pin Control (MUTEC1, MUTEC0) ............................................................... 39
5.7.2 Channel A Volume = Channel B Volume (Px_A=B) ............................................ 40
5.7.3 Single Volume Control (Snglvol).......................................................................... 40
5.8 Ramp and Mute (address 08h)........................................................................................ 40
5.8.1 Soft Ramp AND Zero Cross CONTROL (SZC) ................................................... 40
5.8.2 Soft Volume Ramp-Up after Error (RMP_UP) ..................................................... 41
5.8.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ................................... 41
5.8.4 PCM Auto-Mute (PAMUTE)................................................................................. 41
5.8.5 DSD Auto-Mute (DAMUTE) ................................................................................. 41
5.8.6 MUTE Polarity and DETECT (MUTEP1:0) .......................................................... 42
5.9 Mute Control (address 09h)............................................................................................. 42
5.9.1 Mute (MUTE_xx).................................................................................................. 42
5.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h)................................................................ 43
5.10.1 De-Emphasis Control (PX_DEM1:0).................................................................. 43
5.11 ATAPI Channel Mixing and Muting (ATAPI)................................................................... 43
5.12 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h) ............................................. 44
5.12.1 Digital Volume Control (xx_VOL7:0).................................................................. 44
5.13 PCM Clock Mode (address 16h).................................................................................... 45
5.13.1 Master Clock DIVIDE by 2 ENABLE (mclkdiv)................................................... 45
6. PARAMETER DEFINITIONS.................................................................................................... 46
7. REFERENCES.......................................................................................................................... 46
8. ORDERING INFORMATION .................................................................................................... 46
9. PACKAGE DIMENSIONS ........................................................................................................ 47
10. APPENDIX ............................................................................................................................. 48
DS670PP1
3
CS4365
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing..................................................................................................... 14
Figure 2. TDM Serial Audio Interface Timing............................................................................................ 14
Figure 3. Direct Stream Digital - Serial Audio Input Timing....................................................................... 15
Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation mode.......................... 15
2
Figure 5. Control Port Timing - I C Format ............................................................................................... 16
Figure 6. Control Port Timing - SPI Format............................................................................................... 17
Figure 7. Typical Connection Diagram, Software Mode............................................................................ 18
Figure 8. Typical Connection Diagram, Hardware Mode .......................................................................... 19
Figure 9. Format 0 - Left-Justified up to 24-bit Data ................................................................................. 22
2
Figure 10. Format 1 - I S up to 24-bit Data............................................................................................... 22
Figure 11. Format 2 - Right-Justified 16-bit Data...................................................................................... 22
Figure 12. Format 3 - Right-Justified 24-bit Data...................................................................................... 22
Figure 13. Format 4 - Right-Justified 20-bit Data...................................................................................... 23
Figure 14. Format 5 - Right-Justified 18-bit Data...................................................................................... 23
Figure 15. Format 8 - One Line Mode 1.................................................................................................... 23
Figure 16. Format 9 - One Line Mode 2.................................................................................................... 24
Figure 17. Format 12 - TDM Mode............................................................................................................ 24
Figure 18. De-Emphasis Curve................................................................................................................. 25
Figure 19. ATAPI Block Diagram (x = channel pair 1, 2, or 3) .................................................................. 26
Figure 20. DSD phase modulation mode diagram.................................................................................... 27
Figure 21. Full-Scale Output ..................................................................................................................... 28
Figure 22. Recommended Output Filter.................................................................................................... 28
Figure 23. Recommended Mute Circuitry ................................................................................................. 29
2
Figure 24. Control Port Timing, I C Mode................................................................................................. 32
Figure 25. Control Port Timing, SPI mode ................................................................................................ 33
Figure 26. Single-Speed (fast) Stopband Rejection.................................................................................. 48
Figure 27. Single-Speed (fast) Transition Band........................................................................................ 48
Figure 28. Single-Speed (fast) Transition Band (detail)............................................................................ 48
Figure 29. Single-Speed (fast) Passband Ripple...................................................................................... 48
Figure 30. Single-Speed (slow) Stopband Rejection ................................................................................ 48
Figure 31. Single-Speed (slow) Transition Band....................................................................................... 48
Figure 32. Single-Speed (slow) Transition Band (detail)........................................................................... 49
Figure 33. Single-Speed (slow) Passband Ripple..................................................................................... 49
Figure 34. Double-Speed (fast) Stopband Rejection ................................................................................ 49
Figure 35. Double-Speed (fast) Transition Band....................................................................................... 49
Figure 36. Double-Speed (fast) Transition Band (detail)........................................................................... 49
Figure 37. Double-Speed (fast) Passband Ripple..................................................................................... 49
Figure 38. Double-Speed (slow) Stopband Rejection............................................................................... 50
Figure 39. Double-Speed (slow) Transition Band ..................................................................................... 50
Figure 40. Double-Speed (slow) Transition Band (detail) ......................................................................... 50
Figure 41. Double-Speed (slow) Passband Ripple ................................................................................... 50
Figure 42. Quad-Speed (fast) Stopband Rejection................................................................................... 50
Figure 43. Quad-Speed (fast) Transition Band ......................................................................................... 50
Figure 44. Quad-Speed (fast) Transition Band (detail) ............................................................................. 51
Figure 45. Quad-Speed (fast) Passband Ripple ....................................................................................... 51
Figure 46. Quad-Speed (slow) Stopband Rejection.................................................................................. 51
Figure 47. Quad-Speed (slow) Transition Band........................................................................................ 51
Figure 48. Quad-Speed (slow) Transition Band (detail)............................................................................ 51
Figure 49. Quad-Speed (slow) Passband Ripple...................................................................................... 51
4
DS670PP1
CS4365
LIST OF TABLES
Table 1. Single-Speed Mode Standard Frequencies .................................................................... 20
Table 2. Double-Speed Mode Standard Frequencies................................................................... 20
Table 3. Quad-Speed Mode Standard Frequencies ..................................................................... 20
Table 4. PCM Digital Interface Format, Hardware Mode Options................................................. 21
Table 5. Mode Selection, Hardware Mode Options ...................................................................... 21
Table 6. Direct Stream Digital (DSD), Hardware Mode Options ................................................... 21
Table 7. Digital Interface Formats - PCM Mode............................................................................ 37
Table 8. Digital Interface Formats - DSD Mode ............................................................................ 37
Table 9. ATAPI Decode ................................................................................................................ 43
Table 10. Example Digital Volume Settings.................................................................................. 44
Table 11. Revision History ........................................................................................................... 52
DS670PP1
5
CS4365
1. PIN DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
AOUTA2-
AOUTA2+
AOUTB2+
AOUTB2-
DSDA2
DSDB1
DSDA1
VD
1
2
3
4
GND
5
32
31
30
29
28
27
26
25
VA
6
GND
MCLK
LRCK
SDIN1
SCLK
CS4365
7
AOUTA3-
AOUTA3+
AOUTB3+
AOUTB3-
MUTEC2
MUTEC3
8
9
10
M4(TST)
SDIN2 11
M3(TST)
2
1
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
#
Pin Description
VD
4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Rec-
ommended Operating Conditions for appropriate voltages.
GND
5
Ground (Input) - Ground reference. Should be connected to analog ground.
31
MCLK
LRCK
6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Table 5 illustrates several standard audio sample rates and the required master clock
frequencies.
7
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active
on the serial audio data line. The frequency of the left/right clock must be at the audio
sample rate, Fs.
SDIN1
SDIN2
SDIN3
8
11
13
Serial Data Input (Input) - Input for two’s complement serial audio data.
SCLK
TST
9
Serial Clock (Input) - Serial clocks for the serial audio interface.
Test - These pins need to be tied to analog ground.
14
44
45
RST
VA
19 Reset (Input) - The device enters a low power mode and all internal registers are
reset to their default settings when low.
32 Analog Power (Input) - Positive power supply for the analog section. Refer to the
Recommended Operating Conditions for appropriate voltages.
VLS
43 Serial Audio Interface Power (Input) - Determines the required signal level for the
serial audio interface. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
VLC
18 Control Port Power (Input) - Determines the required signal level for the control port
and hardware mode configuration pins. Refer to the Recommended Operating Condi-
tions for appropriate voltages.
6
DS670PP1
CS4365
Pin Name
#
Pin Description
VQ
21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ
must be capacitively coupled to analog ground, as shown in the Typical Connection
Diagram. The nominal voltage level is specified in the Analog Characteristics and
Specifications section. VQ presents an appreciable source impedance and any cur-
rent drawn from this pin will alter device performance. However, VQ can be used to
bias the analog circuitry assuming there is no AC signal component and the DC cur-
rent is less then the maximum specified in the Analog Characteristics and Specifica-
tions section.
FILT+
20 Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits. Requires the capacitive decoupling to analog ground as shown in
the Typical Connection Diagram.
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
39,40 Differential Analog Output (Output) - The full scale differential analog output level is
37,38 specified in the Analog Characteristics specification table.
35,36
33,34
29,30
27,28
MUTEC1
MUTEC2
MUTEC3
MUTEC4
MUTEC5
MUTEC6
41 Mute Control (Output) - The Mute Control pins go high during power-up initialization,
26 reset, muting, power-down or if the master clock to left/right clock frequency ratio is
25 incorrect. These pins are intended to be used as a control for external mute circuits on
24 the line outputs to prevent the clicks and pops that can occur in any single supply sys-
23 tem. Use of Mute Control is not mandatory but recommended for designs requiring
22 the absolute minimum in extraneous clicks and pops.
Hardware Mode Definitions
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables
6 and 7.
M0
M1
M2
M3
M4
17
16
15
12
10
Software Mode Definitions
SCL/CCLK
15 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
2
external pull-up resistor to the logic interface voltage in I C mode as shown in the
Typical Connection Diagram.
2
SDA/CDIN
16
Serial Control Port Data (Input/Output) - SDA is a data I/O line in I C mode and is
open drain, requiring an external pull-up resistor to the logic interface voltage, as
shown in the Typical Connection Diagram; CDIN is the input data line for the control
port interface in SPI mode.
2
AD0/CS
17
Address Bit 0 (I C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address
2
pin in I C mode; CS is the chip select signal for SPI mode.
TST
10, 12 Test - These pins need to be tied to analog ground.
DSD Definitions
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
3
2
1
48
47
46
DSD_SCLK
42
DS670PP1
7
CS4365
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and T = 25°C.
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
VA
VD
VLS
VLC
4.75
2.37
1.71
1.71
5.0
2.5
5.0
5.0
5.25
2.63
5.25
5.25
V
V
V
V
Specified Temperature Range
Absolute Maximum Ratings
-CQZ
-EQZ
T
-10
-40
-
-
+70
+105
°C
°C
A
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
DC Power Supply
Analog power
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
6.0
3.2
6.0
6.0
V
V
V
V
Digital internal power
Serial data port interface power
Control port interface power
Input Current
Any Pin Except Supplies
I
-
±10
mA
in
Digital Input Voltage
Serial data port interface
Control port interface
V
V
-0.3
-0.3
VLS+ 0.4
VLC+ 0.4
V
V
IND-S
IND-C
Ambient Operating Temperature (power applied)
Storage Temperature
T
-55
-65
125
150
°C
°C
op
T
stg
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
8
DS670PP1
CS4365
DAC ANALOG CHARACTERISTICS
Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load R = 3 kΩ, C = 100 pF; Measure-
L
L
ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
Parameters
Symbol
Min
Typ
Max
Unit
CS4365-CQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range
T
-10
-
70
°C
A
24-bit A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
108
105
-
-
114
111
97
-
-
-
-
dB
dB
dB
dB
94
Total Harmonic Distortion + Noise
THD+N
24-bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-94
-
-45
-
-
-
dB
dB
dB
dB
dB
dB
(Note 2) 16-bit
Idle Channel Noise / Signal-to-noise ratio
-
114
-
dB
CS4365-EQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range (Note 1)
T
-40
-
105
°C
A
24-bit A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
105
102
-
-
114
111
97
-
-
-
-
dB
dB
dB
dB
94
Total Harmonic Distortion + Noise
(Note 1) THD+N
0 dB
24-bit
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-91
-
-42
-
-
-
dB
dB
dB
dB
dB
dB
-20 dB
-60 dB
0 dB
-20 dB
(Note 2) 16-bit
-60 dB
Idle Channel Noise / Signal-to-noise ratio
-
114
-
dB
Notes:
1. One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
DS670PP1
9
CS4365
DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED)
Parameters
Symbol
Min
Typ
Max
Units
Interchannel Isolation
(1 kHz)
-
110
-
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
-
-
0.1
-
-
dB
100
ppm/°C
Analog Output
Full Scale Differential-
Output Voltage
PCM, DSD processor
Direct DSD mode
V
132%•V
134%•V
136%•V
A
Vpp
Vpp
FS
A
A
94%•V
96%•V
98%•V
A
A
A
Output Impedance
(Note 3)
Z
-
-
-
-
-
-
130
1.0
3
-
-
-
-
-
-
Ω
mA
kΩ
OUT
Max DC Current draw from an AOUT pin
Min AC-Load Resistance
Max Load Capacitance
I
OUTmax
R
L
C
100
pF
L
Quiescent Voltage
V
50% V
VDC
µA
Q
A
Max Current draw from V
I
10
Q
QMAX
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
(Note 4)
normal operation, VA= 5 V
I
I
-
-
-
-
-
56
20
2
84
200
61
26
-
-
-
mA
mA
µA
µA
µA
A
D
VD= 2.5 V
(Note 5) Interface current, VLC=5 V
VLS=5 V
I
LC
I
LS
(Note 6) power-down state (all supplies)
I
pd
Power Dissipation (Note 4)
VA = 5 V, VD = 2.5 V
normal operation
-
-
332
1
372
-
mW
mW
(Note 6) power-down
Package Thermal Resistance
θ
θ
-
-
48
15
-
-
°C/Watt
°C/Watt
JA
JC
Power Supply Rejection Ratio (Note 7)
(1 kHz) PSRR
(60 Hz)
-
-
60
40
-
-
dB
dB
Notes:
3.
V
is tested under load R and includes attenuation due to Z
FS L OUT
4. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
5.
I
measured with no external loading on the SDA pin.
LC
6. Power down mode is defined as RST pin = Low with all clock and data lines held static.
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 7 and 8.
10
DS670PP1
CS4365
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs.
(See note 12.)
Fast Roll-Off
Parameter
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
.454
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
Frequency Response
StopBand
StopBand Attenuation
Group Delay
De-emphasis Error (Note 11)
(Relative to 1 kHz)
-0.01
0.547
102
(Note 10)
-
-
-
-
-
-
-
10.4/Fs
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
±0.23
±0.14
±0.09
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
.430
.499
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.583
80
-
-
-
(Note 10)
-
-
6.15/Fs
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.105
.490
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.635
90
-
-
-
(Note 10)
-
7.1/Fs
Notes:
8. Slow Roll-off interpolation filter is only available in software mode.
9. Response is clock dependent and will scale with Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in hard-
ware mode.
12. Amplitude vs. Frequency plots of this data are available starting on page 47.
DS670PP1
11
CS4365
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(CONTINED)
Slow Roll-Off (Note 8)
Parameter
Min
Typ
Max
Unit
Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
0.417
0.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.583
64
-
(Note 10)
-
-
-
7.8/Fs
De-emphasis Error (Note 11)
(Relative to 1 kHz)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.36
±0.21
±0.14
dB
dB
dB
Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.296
.499
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.792
70
-
-
-
(Note 10)
-
5.4/Fs
Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.104
.481
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.868
75
-
-
-
(Note 10)
-
6.6/Fs
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter
Min
Typ
Max
Unit
DSD Processor mode
Passband (Note 9)
Frequency Response
Roll-off
to -3 dB corner
10 Hz to 20 kHz
0
-
-
-
50
+0.05
-
kHz
dB
dB/Oct
-0.05
27
Direct DSD mode
Passband (Note 9)
to -0.1 dB corner
to -3 dB corner
0
0
-0.1
-
-
-
26.9
176.4
0
kHz
kHz
dB
Frequency Response 10 Hz to 20 kHz
12
DS670PP1
CS4365
DIGITAL CHARACTERISTICS
Parameters
Input Leakage Current
Symbol
Min
Typ
Max
±10
-
Units
µA
pF
(Note 13)
I
-
-
-
in
Input Capacitance
8
High-Level Input Voltage
Serial I/O
Control I/O
V
V
70%
70%
-
-
-
-
V
V
IH
IH
LS
LC
Low-Level Input Voltage
Serial I/O
Control I/O
V
V
-
-
-
-
30%
30%
V
V
IL
IL
LS
LC
High-Level Output Voltage (I = -1.2 mA)
Control I/O
Control I/O
V
80%
-
-
-
-
V
V
OH
OH
LC
LC
Low-Level Output Voltage (I = 1.2 mA)
V
20%
OL
OL
MUTEC auto detect input high voltage
MUTEC auto detect input low voltage
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
V
70%
-
-
-
VA
VA
mA
V
IH
V
-
-
-
-
30%
IL
I
3
-
-
-
max
V
VA
0
OH
V
V
OL
13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-
up
DS670PP1
13
CS4365
SWITCHING CHARACTERISTICS - PCM
(Inputs: Logic 0 = GND, Logic 1 = VLS, C = 30 pF)
L
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
(Note 14)
1
-
ms
MCLK Frequency
1.024
45
55.2
55
MHz
%
MCLK Duty Cycle
(Note 15)
Input Sample Rate - LRCK (Manual selection)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
F
F
F
4
50
100
54
108
216
kHz
kHz
kHz
s
s
s
Input Sample Rate - LRCK (Auto detect)
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
4
84
170
54
108
216
kHz
kHz
kHz
Quad-Speed Mode
LRCK Duty Cycle
45
45
8
55
55
-
%
%
SCLK Duty Cycle
SCLK High Time
t
ns
ns
ns
ns
ns
ns
sckh
SCLK Low Time
t
8
-
sckl
lcks
lckd
LRCK Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Falling Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
t
5
-
t
5
-
t
3
-
ds
t
5
-
dh
Notes:
14. After powering up, RST should be held low until after the power supplies and clocks are settled.
15. See Tables 1 - 3 on page 20 for suggested MCLK frequencies.
LRCK
LRCK
SCLK
SDIN1
tlcks
tsckh
tsckl
t
t
lckd
t
t
sckh
t
lcks
lcks
sckl
SCLK
tds
t
t
tdh
MSB
ds
dh
SDINx
MSB
MSB-1
MSB-1
Figure 1. Serial Audio Interface Timing
Figure 2. TDM Serial Audio Interface Timing
14
DS670PP1
CS4365
SWITCHING CHARACTERISTICS - DSD
(Logic 0 = AGND = DGND; Logic 1 = VLS; C = 20 pF)
L
Parameter
MCLK Duty Cycle
Symbol
Min
40
Typ
Max
Unit
%
-
-
-
60
-
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
t
160
160
ns
sclkl
t
-
ns
sclkh
DSD_SCLK Frequency
(64x Oversampled)
(128x Oversampled)
1.024
2.048
-
-
3.2
6.4
MHz
MHz
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
DSD clock to data transition (Phase Modulation mode)
t
20
20
-
-
-
-
-
ns
ns
ns
sdlrs
t
sdh
t
-20
20
dpm
t
sclkh
t
sclkl
DSD_SCLK
DSDxx
t
t
sdlrs
sdh
Figure 3. Direct Stream Digital - Serial Audio Input Timing
t
t
dpm
dpm
DSD_SCLK
(128Fs)
DSD_SCLK
(64Fs)
DSDxx
Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase
Modulation mode
DS670PP1
15
CS4365
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
L
Parameter
SCL Clock Frequency
Symbol
Min
-
Max
Unit
kHz
ns
f
100
scl
RST Rising Edge to Start
t
500
4.7
4.0
4.7
4.0
4.7
0
-
-
-
-
-
-
-
irs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
t
µs
buf
t
µs
hdst
t
µs
low
Clock High Time
t
µs
high
Setup Time for Repeated Start Condition
t
µs
sust
SDA Hold Time from SCL Falling
(Note 16)
t
µs
hdd
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
t
250
-
-
1
ns
µs
ns
µs
ns
sud
t , t
rc rc
t , t
-
300
-
fc fc
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
t
4.7
300
susp
t
1000
ack
Notes:
16. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
RST
t
irs
Repeated
Start
Stop
Start
Stop
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
low
hdd
Figure 5. Control Port Timing - I2C Format
16
DS670PP1
CS4365
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
L
Parameter
CCLK Clock Frequency
Symbol
Min
-
Max
Unit
MHz
ns
f
6
-
sclk
RST Rising Edge to CS Falling
t
500
500
srs
CCLK Edge to CS Falling
(Note 17)
t
-
ns
spi
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t
1.0
20
66
66
40
15
-
-
-
-
-
-
µs
ns
ns
ns
ns
ns
csh
t
css
t
scl
CCLK High Time
t
sch
dsu
CDIN to CCLK Rising Setup Time
t
CCLK Rising to DATA Hold Time
(Note 18)
t
dh
Rise Time of CCLK and CDIN
(Note 19)
t
-
-
100
100
ns
ns
r2
Fall Time of CCLK and CDIN
(Note 19)
t
f2
Notes:
17.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For F < 1 MHz.
t
only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi spi
SCK
RST
t
t
srs
CS
t
t
t
spi css
scl
sch
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Figure 6. Control Port Timing - SPI Format
DS670PP1
17
CS4365
+2.5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
32
VA
VD
220 Ω
6
7
9
MCLK
39
40
AOUTA1+
AOUTA1-
Analog Conditioning
and Muting
LRCK
SCLK
PCM
Digital
Audio
8
11
13
Source
SDIN1
SDIN2
SDIN3
38
37
AOUTB1+
AOUTB1-
Analog Conditioning
and Muting
470 Ω
470 Ω
35
36
AOUTA2+
AOUTA2-
Analog Conditioning
and Muting
43
+1.8 V to +5 V
VLS
CS4365
0.1 µF
34
33
AOUTB2+
AOUTB2-
Analog Conditioning
and Muting
3
29
30
DSDA1
DSDB1
DSDA2
AOUTA3+
AOUTA3-
Analog Conditioning
and Muting
2
1
DSD
Audio
Source
48
28
27
DSDB2
DSDA3
DSDB3
AOUTB3+
AOUTB3-
Analog Conditioning
and Muting
47
46
42
41
DSD_SCLK
MUTEC1
MUTEC2
26
25
MUTEC3
MUTEC4
Mute
Drive
24
23
22
19
RST
MUTEC5
MUTEC6
15
16
Micro-
Controller
SCL/CCLK
SDA/CDIN
17
ADO/CS
Note*
20
21
FILT+
18
+1.8 V to +5 V
VLC
+
CMOUT
0.1 µF
F
47 µF
0.1 µ
F
1 µF
0.1 µ
+
GND
5
TST
GND
31
10, 12,
14, 44, 45
Note*: Necessary for I2C
control port operation
Figure 7. Typical Connection Diagram, Software Mode
18
DS670PP1
CS4365
+2.5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
VD
32
VA
220 Ω
6
MCLK
39
40
41
7
9
8
AOUTA1+
AOUTA1-
MUTEC1
LRCK
SCLK
SDIN1
SDIN2
Analog Conditioning
and Muting
PCM
Digital
Audio
Source
11
13
38
37
26
SDIN3
AOUTB1+
AOUTB1-
MUTEC2
Analog Conditioning
and Muting
470 Ω
470 Ω
43
+1.8 V to +5 V
VLS
CS4365
0.1 µF
35
36
25
AOUTA2+
AOUTA2-
MUTEC3
Analog Conditioning
and Muting
3
2
DSDA1
DSDB1
DSDA2
1
34
DSD
Audio
Source
AOUTB2+
AOUTB2-
MUTEC4
48
Analog Conditioning
and Muting
33
24
DSDB2
47
46
42
DSDA3
DSDB3
DSD_SCLK
29
30
23
AOUTA3+
AOUTA3-
MUTEC5
Analog Conditioning
and Muting
Optional
47 KΩ
10
12
M4
M3
28
27
22
AOUTB3+
AOUTB3-
MUTEC6
15
16
Analog Conditioning
and Muting
M2
M1
Stand-Alone
Mode
Configuration
17
19
M0
RST
20
21
FILT+
+
CMOUT
F
47 µF
18
0.1 µ
F
0.1 µ
1 µF
+1.8 V to +5 V
VLC
+
0.1 µF
GND
5
TST
14, 44, 45
GND
31
Figure 8. Typical Connection Diagram, Hardware Mode
DS670PP1
19
CS4365
3. APPLICATIONS
The CS4365 serially accepts twos complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4365 can be configured in hardware mode by the M0, M1, M2 , M3 and M4 pins and in software mode
2
through I C or SPI.
3.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3. The LRCK frequency is equal to Fs, the
frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are
then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates
and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
Sample Rate
(kHz)
MCLK (MHz)
256x
8.1920
11.2896
12.2880
384x
512x
768x
1024x
32.7680
45.1584
49.1520
1152x
36.8640
32
44.1
48
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Table 1. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x
8.1920
11.2896
12.2880
192x
256x
384x
512x
64
88.2
96
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
Table 2. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Table 3. Quad-Speed Mode Standard Frequencies
= Denotes clock ratio and sample rate combinations which are NOT supported under auto
speed-mode detection. Please see “Switching Characteristics - PCM” on page 14.
20
DS670PP1
CS4365
3.2
Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually
scanned for any changes. These pins require connection to supply or ground as outlined in figure 8. For
M0, M1, M2 supply is VLC and for M3 and M4 supply is VLS. Tables 4 - 6 show the decode of these pins.
In software mode the operational mode and data format are set in the FM and DIF registers. “Parameter
Definitions” on page 45.
M1
M0
DESCRIPTION
FORMAT
FIGURE
(DIF1)
(DIF0)
Left Justified, up to 24-bit data
0
0
0
1
0
1
9
10
2
I S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
1
1
0
1
2
3
11
12
Table 4. PCM Digital Interface Format, Hardware Mode Options
M4
M3
M2
DESCRIPTION
(DEM)
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 18
Double-Speed (50 to 100 kHz sample rates)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
Quad-Speed (100 to 200 kHz sample rates)
Auto Speed-Mode Detect (32 kHz to 200 kHz sample rates)
Auto Speed-Mode Detect with 44.1 kHz De-Emphasis; see Figure 18
DSD Processor Mode (see Table 6 for details)
Table 5. Mode Selection, Hardware Mode Options
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
0
1
0
1
0
1
0
1
Table 6. Direct Stream Digital (DSD), Hardware Mode Options
DS670PP1
21
CS4365
3.3
Digital Interface Formats
The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, One-Line Mode
(OLM) and TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 9-17.
Data is clocked into the DAC on the rising edge. OLM and TDM configurations are only supported in soft-
ware mode.
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
LSB
MSB
LSB
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 9. Format 0 - Left-Justified up to 24-bit Data
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
LSB
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
Figure 10. Format 1 - I2S up to 24-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
9 8 7
6
5 4
3
2 1
0
9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
Figure 11. Format 2 - Right-Justified 16-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
7
6
5 4
3
2 1
0
7 6 5 4 3 2 1 0
0
23 22 21 20 19 18
32 clocks
23 22 21 20 19 18
Figure 12. Format 3 - Right-Justified 24-bit Data
22
DS670PP1
CS4365
Right Channel
LRCK
SCLK
Left Channel
SDINx
1 0
19 18 17 16
19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 13. Format 4 - Right-Justified 20-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
1 0
17 16
17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 14. Format 5 - Right-Justified 18-bit Data
3.3.1 OLM #1
OLM #1 serial audio interface format operates in single, double, or quad-speed mode and
will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on
SDIN1.
64 clks
64 clks
LRCK
Left Channel
Right Channel
SCLK
MSB
LSB MSB
LSB MSB
DAC_A3
20 clks
LSB
MSB
DAC_B1
20 clks
LSB MSB
LSB MSB
LSB
DAC_B3
20 clks
MSB
SDIN1
DAC_A2
20 clks
DAC_B2
20 clks
DAC_A1
20 clks
Figure 15. Format 8 - One Line Mode 1
DS670PP1
23
CS4365
3.3.2 OLM #2
OLM #2 serial audio interface format operates in single, double, or quad-speed mode and will slave to
SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on SDIN1.
128 clks
128 clks
LRCK
Left Channel
Right Channel
SCLK
MSB
DAC_A1
24 clks
LSB MSB
LSB MSB
DAC_A3
24 clks
LSB
MSB
DAC_B1
24 clks
LSB MSB
LSB MSB
DAC_B3
24 clks
LSB
MSB
SDIN1
DAC_A2
24 clks
DAC_B2
24 clks
Figure 16. Format 9 - One Line Mode 2
3.3.3 TDM
The TDM serial audio interface format operates in single, double, or quad-speed mode and will slave to
SCLK at 256 Fs. Data is received most significant bit first on the first SCLK after an LRCK transition and is
valid on the rising edge of SCLK. LRCK identifies the start of a new frame and is equal to the sample rate,
Fs. LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data
sample and must be held valid for one SCLK period. Each time slot is 32 bits wide, with the valid data sam-
ple left justified within the time slot with the remaining bits being zero padded.
256 clks
LRCK
SCLK
SDIN1
MSB
LSB MSB
LSB MSB
DAC_A3
32 clks
LSB
MSB
DAC_B1
32 clks
LSB MSB
DAC_B2
32 clks
LSB MSB
DAC_B3
32 clks
LSB
DAC_A1
DAC_A2
32 clks
Data
32 clks
zero
32 clks
32 clks
MSB
LSB
Figure 17. Format 12 - TDM Mode
3.4
Oversampling Modes
The CS4365 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the M4, M3 and M2 pins in hardware mode or the FM bits in software mode. Single-Speed
mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed mode sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
The auto-speed mode detect feature allows for the automatic selection of speed mode based off of the in-
coming sample rate. This allows the CS4365 to accept a wide range of sample rates with no external inter-
vention necessary. The auto-speed mode detect feature is available in both hardware and software mode.
3.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4365 incorporates
selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in
24
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CS4365
each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a va-
riety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Parameter
Definitions” on page 45 for more details).
When in hardware mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 26 to 49.
3.6
De-Emphasis
The CS4365 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommo-
date older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure 18
shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally
with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been se-
lected.
In software mode the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected
via the de-emphasis control bits.
In hardware mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sam-
ple rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis
filter will be scaled by a factor of the actual Fs over 44,100.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 18. De-Emphasis Curve
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CS4365
3.7
ATAPI Specification
The CS4365 implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 9 on page 42 and Figure 19 for additional informa-
tion.
A Channel
Volume
Control
Left Channel
Audio Data
MUTE
AoutAx
Σ
Σ
SDINx
B Channel
Volume
Control
Right Channel
Audio Data
MUTE
AoutBx
Figure 19. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
3.8
Direct Stream Digital (DSD) Mode
In software mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The DSD_DIF bits
(Reg 04h) then control the expected DSD rate and MCLK ratio.
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The first
method uses a decimation free DSD processing technique which allows for features such as matched PCM level
output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data directly to the on-
chip switched-capacitor filter for conversion (without the above mentioned features).
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data input. In
this mode the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see
Figure 20). Use of phase modulation mode may not directly effect the performance of the CS4365, but may lower
the sensitivity to board level routing of the DSD data signals.
The CS4365 can detect errors in the DSD data which does not comply with the SACD specification. The
STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4365 to alter the incoming invalid DSD data.
Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins
would be set according to the DAMUTE bit (Reg. 08h)).
More information for any of these register bits can be found in the “Parameter Definitions” on page 45.
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index)
at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at
these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be
26
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CS4365
set to -3.0 dB. This same volume control register affects PCM output levels. There is no need to change the vol-
ume control setting between PCM and DSD in order to have the 0dB output levels match (both 0 dBFS and 0 dB-
SACD will output at -3 dB in this case).
DSD Phase
DSD Normal Mode
Modulation Mode
BCKA
(128Fs)
Not Used
DSD_SCLK
DSD_SCLK
BCKA
(64Fs)
BCKD
(64Fs)
DSD_SCLK
Not Used
DSDAx,
DSDBx
D0
D0
D1
D2
D2
D1
DSDAx,
DSDBx
Not Used
D1
Figure 20. DSD phase modulation mode diagram
3.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4365 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the rec-
ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4365 should be connect-
ed to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
3.9.1 Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same sup-
ply, but a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4365 evaluation board demonstrates the optimum layout and power supply arrangements.
3.10 Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4365 evalua-
tion board, CDB4365, as seen in Figure 22. The CS4365 does not include phase or amplitude compensa-
tion for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on
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CS4365
the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale output
level to below 2 Vrms.
Figure 21 shows how the full-scale differential analog output level specification is derived.
3.85 V
2.5 V
AOUT+
AOUT-
1.15 V
3.85 V
2.5 V
1.15 V
Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp
Figure 21. Full-Scale Output
Figure 22. Recommended Output Filter
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CS4365
3.11 The MUTEC Outputs
The MUTEC1-6 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time
of reset. The external mute circuitry needs to be self biased into an active state in order to be muted during reset.
Upon release of reset, the CS4365 will detect the status of the MUTEC pins (high or low) and will then select that
state as the polarity to drive when the mutes become active. The external-bias voltage level that the MUTEC pins
see at the time of release of reset must meet the “MUTEC auto detect input high/low voltage” specs as outlined in
the Digital Characteristics section.
Figure 23 shows a single example of both an active high and an active low mute drive circuit. In these designs, the
pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold when used with
the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in
extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Figure 23. Recommended Mute Circuitry
3.12 Recommended Power-Up Sequence
3.12.1 Hardware Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in section 3.1. In this state, the registers
are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
3.12.2 Software Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 3.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
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CS4365
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format
and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit can
not be set in time then the SDINx pins should remain static low (this way no audio data can be
converted incorrectly by the hardware mode settings).
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
3.13 Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met
during clock source changes.
3.14 Control Port Interface
The control port is used to load all the internal register settings in order to operate in software mode (see
the “Parameter Definitions” on page 45). The operation of the control port may be completely asynchronous
with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
2
The control port operates in one of two modes: I C or SPI.
3.14.1 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the
2
MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I C writes or reads and SPI
writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes
of successive registers.
2
3.14.2 I C Mode
2
In the I C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 24 for the clock to data relationship). There is no CS pin. Pin AD0 en-
ables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND as required,
before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after
power-up, SPI mode will be selected.
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2
3.14.2.1 I C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifi-
cations in section 2.
2
1. Initiate a START condition to the I C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
2
5. If the INCR bit is set to 0 and further I C writes to other registers are desired, it is necessary to ini-
tiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to
other registers are desired, initiate a STOP condition to the bus.
2
3.14.2.2 I C Read
To read from the device, follow the procedure below while adhering to the control port Switching Spec-
ifications.
2
1. Initiate a START condition to the I C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP,
2
or the default address (see section 3.14.1) if an I C read is the first operation performed on the device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then
initiate a STOP condition to the bus.
2
5. If the INCR bit is set to 0 and further I C reads from other registers are desired, it is necessary to
2
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I C
2
Write instructions followed by step 1 of the I C Read section. If no further reads from other registers are
desired, initiate a STOP condition to the bus.
Note 1
ADDR
AD0
DATA
1-8
DATA
1-8
001100
R/W
ACK
ACK
ACK
SDA
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 24. Control Port Timing, I2C Mode
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CS4365
3.14.3 SPI™ Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 25 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
3.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifi-
cations in Section 2.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired,
bring CS high.
CS
CCLK
CHIP
ADDRESS
MAP
DATA
0011000
LSB
CDIN
MSB
R/W
byte 1
byte n
MAP = Memory Address Pointer
Figure 25. Control Port Timing, SPI mode
3.15 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
3.15.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
3.15.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
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CS4365
4. REGISTER QUICK REFERENCE
Addr
01h Chip Revision
default
02h Mode Control
default
03h PCM Control
default
04h DSD Control
Function
7
PART4
0
6
PART3
1
5
PART2
1
4
PART1
0
3
PART0
1
2
REV
x
1
REV
x
0
REV
x
CPEN
0
FREEZE DSD/PCM Reserved DAC3_DIS DAC2_DIS DAC1_DIS
PDN
1
0
DIF2
0
0
DIF0
0
0
0
0
FM1
1
0
DIF1
0
DIF3
0
Reserved Reserved
FM0
1
0
0
DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_D INVALID_D DSD_PM_ DSD_PM_
SD
SD
MD
EN
0
0
0
0
1
0
0
0
default
05h Filter Control
default
06h Invert Control
default
07h Group Control
default
Reserved Reserved Reserved Reserved Reserved Reserved Reserved FILT_SEL
0
0
0
INV_B3
0
0
INV_A3
0
0
0
INV_A2
0
0
INV_B1
0
0
INV_A1
0
Reserved Reserved
INV_B2
0
0
0
P2_A=B
0
MUTEC1 MUTEC0 Reserved
P1_A=B
0
P3_A=B
0
Reserved SNGLVOL
0
SZC1
1
0
SZC0
0
0
0
0
08h Ramp and Mute
default
RMP_UP RMP_DN PAMUTE DAMUTE MUTE_P1 MUTE_P0
1
1
1
1
0
0
09h Mute Control
default
Reserved Reserved MUTE_B3 MUTE_A3 MUTE_B2 MUTE_A2 MUTE_B1 MUTE_A1
0
0
0
0
0
0
0
0
0Ah Mixing Control
Pair 1 (AOUTx1)
Reserved P1_DEM1 P1_DEM0 P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0
0
0
0
0
1
0
0
1
default
0Bh Vol. Control A1
default
A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0
0
0
0
0
0
0
0
0
0Ch Vol. Control B1
default
B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0
0
0
0
0
0
0
0
0
0Dh Mixing Control
Pair 2 (AOUTx1)
Reserved P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0
0
0
0
0
1
0
0
1
default
0Eh Vol. Control A2
default
A2_VOL7 A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0
0
0
0
0
0
0
0
0
0Fh Vol. Control B2
default
B2_VOL7 B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0
0
0
0
0
0
0
0
0
10h Mixing Control
Pair 3 (AOUTx1)
Reserved P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0
0
0
0
0
1
0
0
1
default
11h Vol. Control A3
default
A3_VOL7 A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0
0
0
0
0
0
0
0
0
12h Vol. Control B3
default
B3_VOL7 B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0
0
0
0
0
0
0
0
0
16h PCM clock mode Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved
0
0
0
0
0
0
0
0
default
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CS4365
5. REGISTER DESCRIPTION
2
Note: All registers are read/write in I C mode and write only in SPI, unless otherwise noted.
5.1
Chip Revision (address 01h)
7
PART4
0
6
PART3
1
5
PART2
1
4
PART1
0
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
5.1.1 Part Number ID (part) [Read Only]
01101 - CS4365
Revision ID (REV) [Read Only]
000 - Revision A
Function:
This read-only register can be used to identify the model and revision number of the device.
5.2
Mode Control 1 (address 02h)
7
CPEN
0
6
FREEZE
0
5
DSD/PCM
0
4
Reserved
0
3
2
1
0
PDN
1
DAC3_DIS DAC2_DIS DAC1_DIS
0
0
0
5.2.1 Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be
accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers
and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should
write this bit within 10 ms following the release of Reset.
5.2.2 Freeze Controls (Freeze)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, en-
able the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
34
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5.2.3 PCM/DSD Selection (DSD/PCM)
Default = 0
0 - PCM
1 - DSD
Function:
This function selects DSD or PCM Mode. The appropriate data and clocks should be present before chang-
ing modes, or else MUTE should be selected.
5.2.4 DAC Pair Disable (DACx_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is
advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility
of audible artifacts.
5.2.5 Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be dis-
abled before normal operation in Control Port mode can occur.
5.3
PCM Control (address 03h)
7
DIF3
0
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
Reserved
0
2
Reserved
0
1
FM1
1
0
FM0
1
5.3.1 Digital Interface Format (dif)
Default = 0000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether PCM
or DSD mode is selected.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 9-17.
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CS4365
DIF3
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
0
0
0
0
1
X
0
0
1
1
0
0
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
1
0
X
0
1
2
3
4
5
8
9
9
Left Justified, up to 24-bit data
I S, up to 24-bit data
2
10
11
12
13
14
15
16
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
One-line Mode 1, 24-bit Data
One-line Mode 2, 20-bit Data
Reserved
Reserved
TDM
All other combinations are Reserved
12
17
Table 7. Digital Interface Formats - PCM Mode
5.3.2 Functional Mode (FM)
Default = 11
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or Auto Speed Mode.
5.4
DSD Control (address 04h)
7
6
5
4
3
2
1
0
DSD_DIF2 DSD_DIF1 DSD_DIF0
DIR_DSD STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN
0
0
0
0
1
1
0
0
5.4.1 DSD Mode Digital Interface Format (DSD_dif)
Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)
Function:
The relationship between the oversampling ratio of the DSD audio data and the required Master clock to
DSD data rate is defined by the Digital Interface Format pins.
The DSD/PCM bit determines whether PCM or DSD mode is selected.
DIF2
DIF1
DIFO
DESCRIPTION
0
0
0
0
0
0
1
1
0
1
0
1
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
Table 8. Digital Interface Formats - DSD Mode
36
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CS4365
DIF2
DIF1
DIFO
DESCRIPTION
1
1
1
1
0
0
1
1
0
1
0
1
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 8. Digital Interface Formats - DSD Mode
5.4.2 Direct DSD Conversion (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode the full scale DSD and PCM levels will not be matched (see Section 2), the dynamic range
performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available
(see section 2 for filter specifications).
5.4.3 Static DSD Detect (static_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE reg-
ister.
When set to 0, this function is disabled.
5.4.4 Invalid DSD Detect (invalid_DSD)
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
5.4.5 DSD Phase Modulation Mode Select (DSD_PM_mode)
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation mode.
(See Figure 20 on page 27)
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.
5.4.6 DSD Phase Modulation Mode Enable (DSD_pm_EN)
Function:
When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
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5.5
Filter Control (address 05h)
7
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
FILT_SEL
0
Reserved
0
5.5.1 Interpolation Filter Select (FILT_SEL)
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in figures 26 to 49 found on the page 27.
5.6
Invert Control (address 06h)
7
6
Reserved
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
Reserved
0
5.6.1 Invert Signal Polarity (Inv_xx)
Function:
When set to 1, this bit inverts the signal polarity of channel xx.
When set to 0 (default), this function is disabled.
5.7
Group Control (address 07h)
7
6
MUTEC0
0
5
Reserved
0
4
P1_A=B
0
3
P2_A=B
0
2
P3_A=B
0
1
Reserved
0
0
SNGLVOL
0
MUTEC1
0
5.7.1 Mute Pin Control (MUTEC1, MUTEC0)
Default = 00
00 - Six mute control signals
01, 10 - One mute control signal
11 - Three mute control signals
Function:
Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When set
to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on MUTEC2,
etc. When set to ‘01’ or ‘10’, there is a single mute control signal on the MUTEC1 pin. When set to ‘11’,
there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on MUTEC1,
AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3.
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5.7.2 Channel A Volume = Channel B Volume (Px_A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined
by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ig-
nored when this function is enabled.
5.7.3 Single Volume Control (Snglvol)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control Bytes
when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Con-
trol Byte, and the other Volume Control Bytes are ignored when this function is enabled.
5.8
Ramp and Mute (address 08h)
7
SZC1
1
6
SZC0
0
5
RMP_UP
1
4
RMP_DN
1
3
PAMUTE
1
2
DAMUTE
1
1
MUTE_P1
0
0
MUTE_P0
0
5.8.1 Soft Ramp AND Zero Cross CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout
period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping,
in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
DS670PP1
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CS4365
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
5.8.2 Soft Volume Ramp-Up after Error (RMP_UP)
Function:
An un-mute will be performed after executing an LRCK/MCLK ratio change or error, and after changing the
Functional Mode.
When set to 1 (default), this un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross
bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
5.8.3 Soft Ramp-Down before Filter Mode Change (RMP_DN)
Function:
If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to change
its filter values. This bit selects how the data is effected prior to and after the change of the filter values.
When set to 1 (default), a mute will be performed prior to executing a filter mode change and an un-mute
will be performed after executing the filter mode change. This mute and un-mute are effected, similar to
attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
5.8.4 PCM Auto-Mute (PAMUTE)
Function:
When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. De-
tection and muting is done independently for each channel. The quiescent voltage on the output will be
retained and the Mute Control pin will go active during the mute period.
When set to 0 this function is disabled.
5.8.5 DSD Auto-Mute (DAMUTE)
Function:
When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 256 re-
peated 8-bit DSD mute patterns (as defined in the SACD specification).
A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained and
the Mute Control pin will go active during the mute period.
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5.8.6 MUTE Polarity and DETECT (MUTEP1:0)
Default = 00
00 - Auto polarity detect, selected from MUTEC1 pin
01 - Reserved
10 - Active low mute polarity
11 - Active high mute polarity
Function:
Auto mute polarity detect (00)
See section 3.11 on page 29 for description.
Active low mute polarity (10)
When RST is low the outputs are high impedance and will need to be biased active. Once reset has been
released and after this bit is set, the MUTEC output pins will be active low polarity.
Active high mute polarity (11)
At reset time the outputs are high impedance and will need to be biased active. Once reset has been re-
leased and after this bit is set, the MUTEC output pins will be active high polarity.
5.9
Mute Control (address 09h)
7
6
Reserved
0
5
MUTE_B3
0
4
MUTE_A3
0
3
MUTE_B2
0
2
MUTE_A2
0
1
MUTE_B1
0
0
MUTE_A1
0
Reserved
0
5.9.1 Mute (MUTE_xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be
retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits.
The MUTE pins will go active during the mute period according to the MUTEC bits.
DS670PP1
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CS4365
5.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h)
7
Reserved
0
6
Px_DEM1
0
5
Px_DEM0
0
4
PxATAPI4
0
3
PxATAPI3
1
2
PxATAPI2
0
1
PxATAPI1
0
0
PxATAPI0
1
5.10.1 De-Emphasis Control (PX_DEM1:0)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response
at 32, 44.1 or 48 kHz sample rates. (see Figure 18)
De-emphasis is only available in Single-Speed Mode.
5.11 ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are
applied per A-B pair. Refer to Table 9 and Figure 19 for additional information.
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
AOUTBx
MUTE
bR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
bL
b[(L+R)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
bL
b[(L+R)/2]
Table 9. ATAPI Decode
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DS670PP1
CS4365
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
AOUTBx
MUTE
bR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
bL
[(bL+aR)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
bL
[(aL+bR)/2]
Table 9. ATAPI Decode (Continued)
5.12 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)
7
xx_VOL7
0
6
xx_VOL6
0
5
xx_VOL5
0
4
xx_VOL4
0
3
xx_VOL3
0
2
xx_VOL2
0
1
0
xx_VOL0
0
xx_VOL1
0
These six registers provide individual volume and mute control for each of the six channels.
The values for “xx” in the bit fields above are as follows:
Register address 0Bh - xx = A1
Register address 0Ch - xx = B1
Register address 0Eh - xx = A2
Register address 0Fh - xx = B2
Register address 11h - xx = A3
Register address 12h - xx = B3
5.12.1 Digital Volume Control (xx_VOL7:0)
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in Table 10. The volume changes are imple-
mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that the
values in the volume setting column in Table 10 are approximate. The actual attenuation is determined by
taking the decimal value of the volume register and multiplying by 6.02/12.
Table 10. Example Digital Volume Settings
Binary Code
00000000
00000001
00000110
11111111
Decimal Value
Volume Setting
0 dB
0
1
6
-0.5 dB
-3.0 dB
-127.5 dB
255
DS670PP1
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CS4365
5.13 PCM Clock Mode (address 16h)
7
Reserved
0
6
Reserved
0
5
MCLKDIV
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
5.13.1 Master Clock DIVIDE by 2 ENABLE (mclkdiv)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
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6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure-
ment to full scale. This technique ensures that the distortion components are below the noise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Engineer-
ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
Note: "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
Note: CDB4365 Datasheet
Note: “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note AN48
2
Note: “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
8. ORDERING INFORMATION
Product
CS4365
CDB4365
Description
Package Pb-Free
Grade
Temp Range
Container Order #
Tray
CS4365-CQZ
Commercial -10° to +70° C
Automotive -40° to +105° C
Tape & Reel CS4365-CQZR
114 dB, 192 kHz 6-
channel D/A Converter
48-pin
YES
LQFP
Tray
Tape & Reel CS4365-EQZR
CDB4365
CS4365-EQZ
CS4365 Evaluation Board
-
-
-
-
DS670PP1
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CS4365
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D1
D
1
e
B
∝
A
A1
L
INCHES
NOM
MILLIMETERS
NOM
DIM
MIN
MAX
MIN
MAX
A
A1
B
D
D1
E
E1
e*
L
∝
---
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
---
1.40
0.10
0.22
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
4°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm.
JEDEC Designation: MS022
46
DS670PP1
CS4365
10.APPENDIX
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−100
−120
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 26. Single-Speed (fast) Stopband Rejection
Figure 27. Single-Speed (fast) Transition Band
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.02
0.015
0.01
0.005
0
−0.005
−0.01
−0.015
−0.02
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 28. Single-Speed (fast) Transition Band (detail)
Figure 29. Single-Speed (fast) Passband Ripple
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 30. Single-Speed (slow) Stopband Rejection
Figure 31. Single-Speed (slow) Transition Band
DS670PP1
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CS4365
0.02
0.015
0.01
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.005
0
−0.005
−0.01
−0.015
−0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 32. Single-Speed (slow) Transition Band (detail)
Figure 33. Single-Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 34. Double-Speed (fast) Stopband Rejection
Figure 35. Double-Speed (fast) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 36. Double-Speed (fast) Transition Band (detail)
Figure 37. Double-Speed (fast) Passband Ripple
48
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0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 38. Double-Speed (slow) Stopband Rejection
Figure 39. Double-Speed (slow) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 40. Double-Speed (slow) Transition Band (detail)
Figure 41. Double-Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 42. Quad-Speed (fast) Stopband Rejection
Figure 43. Quad-Speed (fast) Transition Band
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0
0.2
0.15
0.1
1
2
3
0.05
0
4
5
6
0.05
7
0.1
0.15
0.2
8
9
10
0
0.05
0.1
0.15
0.2
0.25
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 44. Quad-Speed (fast) Transition Band (detail)
Figure 45. Quad-Speed (fast) Passband Ripple
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 46. Quad-Speed (slow) Stopband Rejection
Figure 47. Quad-Speed (slow) Transition Band
0
1
0.02
0.015
0.01
0.005
0
2
3
4
5
6
0.005
0.01
0.015
0.02
7
8
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 48. Quad-Speed (slow) Transition Band (detail)
Figure 49. Quad-Speed (slow) Passband Ripple
50
DS670PP1
CS4365
Table 11. Revision History
Changes
Release
A1
PP1
Date
OCT 2004
APR 2005
Initial Release
Updated package ordering information
Updated description for 3) in section 3.12.2
Added section 3.13
Updated descritpion for function mode bit
Updated description for RMP_UP and RMP_DN bits
Corrected group delay specifications
Corrected de-emphasis error specifications
Updated output impedance spec on page 10
Improved interchannel isolation spec on page 10
Updated Legal text
Re-formatted ordering information
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this infor-
mation, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks,
trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be
made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to
other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY
DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-
STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUD-
ING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT
IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
DS670PP1
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