CS5322-BLZ [CIRRUS]
24-bit, Variable-bandwidth A/D Converter Chipset; 24位可变带宽A / D转换器芯片组
| 型号： | CS5322-BLZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 24-bit, Variable-bandwidth A/D Converter Chipset |
| 文件： | 总36页 (文件大小：654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS5321/22
24-bit, Variable-bandwidth A/D Converter Chipset
Features
Description
The CS5321/CS5322 chipset functions as a unique
A/D converter intended for very high-resolution
measurement of signals below 1600 Hz. It is specif-
ically designed for applications that require both a
high dynamic range and a low total harmonic distor-
tion. The chipset performs sampling, A/D
conversion, and anti-alias filtering.
z CMOS A/D Converter Chipset
z Dynamic Range
- 130 dB @ 25 Hz Bandwidth
- 121 dB @ 411 Hz Bandwidth
z Delta-sigma Architecture
- Fourth-order Modulator
- Variable Oversampling: 64X to 4096X
- Internal Track-and-hold Amplifier
The CS5321 uses Delta-Sigma modulation to pro-
duce highly accurate conversions. The ∆Σ
modulator oversamples, virtually eliminating the
need for external analog anti-alias filters. The
CS5322 linear-phase FIR digital filter decimates the
output to any one of seven selectable update peri-
ods: 16, 8, 4, 2, 1, 0.5, and 0.25 milliseconds. Data
is output from the digital filter in a 24-bit serial
format.
z CS5321 Signal-to-distortion: 115 dB
z Clock-jitter-tolerant Architecture
z Input Voltage Range: +4.5 V
z Flexible Filter Chip
- Hardware- or Software-selectable Options
- Seven Selectable Filter Corners (-3 dB)
Frequencies: 25, 51, 102, 205, 411, 824 and
1650 Hz
ORDERING INFORMATION
z Low Power Dissipation: <100 mW
See page 36.
CS5321
CS5322
V
V
V
V
ss2
VD+
SYNC CLKIN CS R/W
dd1
ss1
dd2
LPWR
OFST
RESET
RSEL
SCLK
SID
MSYNC
SOD
MFLG
MCLK
AINR
AIN+
Digital
Filter
ERROR
DRDY
ORCAL
DECA
DECB
DECC
Analog
Modulator
MDATA
AIN-
MDATA
HBR
VD+
DGND
CSEL
VREF+
VREF-
AGND
DGND
H/S TDATA PWDN USEOR DGND
SEP ‘05
DS454F2
Copyright © Cirrus Logic, Inc. 2005
http://www.cirrus.com
(All Rights Reserved)
CS5321/22
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS............................................... 4
CS5321 ANALOG CHARACTERISTICS .................................................... 4
CS5321 SWITCHING CHARACTERISTICS .............................................. 6
CS5321 DIGITAL CHARACTERISTICS ..................................................... 7
CS5321 RECOMMENDED OPERATION CONDITIONS ........................... 7
CS5321 ABSOLUTE MAXIMUM RATINGS ............................................... 7
CS5322 FILTER CHARACTERISTICS ...................................................... 8
CS5322 POWER SUPPLY ....................................................................... 10
CS5322 SWITCHING CHARACTERISTICS ............................................ 10
CS5322 DIGITAL CHARACTERISTICS ................................................... 15
CS5322 RECOMMENDED OPERATION CONDITIONS ......................... 15
CS5322 ABSOLUTE MAXIMUM RATINGS ............................................. 15
2. GENERAL DESCRIPTION ............................................................................ 16
2.1. Analog Input ...................................................................................... 18
2.2. The OFST Pin.................................................................................... 18
2.3. Input Range and Overrange Conditions ............................................ 19
2.4. Voltage Reference............................................................................. 20
2.5. Clock Source ..................................................................................... 20
2.6. Low Power Mode............................................................................... 21
2.7. Digital Interface and Data Format...................................................... 21
2.8. Performance ...................................................................................... 22
2.9. Power Supply Considerations............................................................ 23
2.10. Power Supply Rejection Ratio ......................................................... 23
2.11. RESET Operation............................................................................ 23
2.12. Power-down Operation.................................................................... 23
2.13. SYNC Operation.............................................................................. 24
2.14. Serial Read Operation ..................................................................... 24
2.15. Serial Write Operation ..................................................................... 24
2.16. Offset Calibration Operation ............................................................ 25
2.17. Status Bits ....................................................................................... 26
2.18. Board Layout Considerations .......................................................... 28
3. CS5321 PIN DESCRIPTIONS ....................................................................... 29
Power Supplies ......................................................................................... 29
Analog Inputs ............................................................................................ 29
Digital Inputs ............................................................................................. 30
Digital Outputs .......................................................................................... 30
4. CS5322 PIN DESCRIPTIONS ....................................................................... 31
Power Supplies ......................................................................................... 31
Digital Outputs .......................................................................................... 31
Digital Inputs ............................................................................................. 32
5. PARAMETER DEFINITIONS......................................................................... 34
6. PACKAGE DIMENSIONS.............................................................................. 35
7. ORDERING INFORMATION ......................................................................... 36
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ... 36
9. REVISION HISTORY .................................................................................... 36
2
DS454F2
CS5321/22
LIST OF FIGURES
Figure 1. Rise and Fall Times ..................................................................................... 6
Figure 2. CS5321 Interface Timing, HBR=1 ............................................................... 6
Figure 3. CS5322 Filter Response ............................................................................. 8
Figure 4. CS5322 Digital Filter Passband Ripple, f = 62.5 Hz .................................. 8
0
Figure 5. CS5322 Digital Filter Passband Ripple, f = 125 Hz ................................... 8
0
Figure 6. CS5322 Digital Filter Passband Ripple, f = 250 Hz ................................... 8
0
Figure 7. CS5322 Digital Filter Passband Ripple, f = 500 Hz ................................... 9
0
Figure 8. CS5322 Digital Filter Passband Ripple, f = 1000 Hz ................................. 9
0
Figure 9. CS5322 Digital Filter Passband Ripple, f = 2000 Hz ................................. 9
0
Figure 10. CS5322 Digital Filter Passband Ripple, f = 4000 Hz ............................... 9
0
Figure 11. CS5322 Impulse Response, f = 62.5 Hz .................................................. 9
0
Figure 12. CS5322 Impulse Response, f = 1000 Hz ................................................. 9
0
Figure 13. CS5322 Serial Port Timing ...................................................................... 11
Figure 14. TDATA Setup/Hold Timing ...................................................................... 12
Figure 15. DRDY Timing .......................................................................................... 13
Figure 16. RESET Timing ......................................................................................... 13
Figure 17. CS5321/CS5322 Interface Timing ........................................................... 14
Figure 18. CS5321 Block Diagram ........................................................................... 16
Figure 19. CS5322 Block Diagram ........................................................................... 17
Figure 20. System Connection Diagram ................................................................... 19
Figure 21. 4.5 Voltage Reference with two filter options .......................................... 20
Figure 22. 1024 Point FFT Plot with -20 dB Input,
100 Hz Input, ten averages 22
Figure 23. 1024 Point FFT Plot with Full Scale Input,
100 Hz Input, HBR = 1, ten averages ............................................. 22
Figure 24. 1024 Point FFT Plot with Full Scale Input,
100 Hz Input, HBR = 0, ten averages ............................................. 22
LIST OF TABLES
Table 1. Output Coding for the CS5321 and CS5322 Combination ....................... 21
Table 2. Configuration Data Bits ............................................................................ 25
Table 3. Status Data (from the SOD Pin) ............................................................... 26
Table 4. Bandwidth Selection: Truth Table ............................................................ 27
DS454F2
3
CS5321/22
1. CHARACTERISTICS AND SPECIFICATIONS
CS5321 ANALOG CHARACTERISTICS (T = (See Note 1); V , V = -5 V; V , V = +5 V;
A
ss1 ss2
dd1 dd2
VD+ = 5 V; AGND = DGND = 0 V; HBR = V LPWR = 0, MCLK = 1.024 MHz; Device connected as shown in Figure 20,
dd
CS5322 used for filtering; Logic 1 = VD+, Logic 0 = 0V; unless otherwise specified.)
CS5321
Parameter*
Symbol
Min
Typ
Max
Unit
Dynamic Performance
Dynamic Range
HBR = 1
OFST = 1
(Note 2)
DR
f = 4000 Hz
-
-
103
118
121
124
127
129
130
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
O
f = 2000 Hz
O
f = 1000 Hz
116
O
f = 500 Hz
-
-
-
-
O
f = 250 Hz
O
f = 125 Hz
O
f = 62.5 Hz
O
HBR = 0
OFST = 1
f = 4000 Hz
-
-
-
-
-
-
-
99
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
O
f = 2000 Hz
115
118
121
124
126
127
O
f = 1000 Hz
O
f = 500 Hz
O
f = 250 Hz
O
f = 125 Hz
O
f = 62.5 Hz
O
Signal-to-Distortion
(Note 3)
HBR = 1
HBR = 0
SDR
108
110
115
120
-
-
dB
dB
Intermodulation Distortion
DC Accuracy
(Note 4)
IMD
FSE
-
110
-
dB
Full Scale Error
Full Scale Drift
(Note 5)
(Note 5,6)
(Note 5)
(Note 7)
(Note 8)
-
-
-
-
-
-
1
5
-
-
-
-
-
-
%
ppm/°C
mV
TC
FS
Offset
V
10
ZSE
Offset after Calibration
Offset Calibration Range
Offset Drift
±100
100
60
µV
%F.S.
µV/°C
(Note 5,6) TC
ZSE
o
o
o
o
Notes: 1. CS5321-BL is guaranteed from -55 to +85 C, CS5322-BL is guaranteed from -40 to +85 C.
2. f = CS5322 output word rate. Refer to “CS5322 FILTER CHARACTERISTICS” on page 8 for details
O
on the FIR Filter.
3. Characterized with full scale input signal of 50 Hz; fo = 500 Hz.
4. Characterized with input signals of 30 Hz and 50 Hz, each 6 dB down from full scale with fo = 1000 Hz.
5. Specification is for the parameter over the specified temperature range and is for the CS5321 device
only (VREF = +4.5 V). It does not include the effects of external components; OFST = 0.
6. Drift specifications are guaranteed by design and/or characterization.
7. The offset after calibration specification applies to the effective offset voltage for a ± 4.5 volt input to the
CS5321 modulator, but is relative to the output digital codes from the CS5322 after ORCAL and USEOR
have been made active.
8. The CS5322 offset calibration is performed digitally and includes ± ±full scale (± 4.5 volts into CS5321).
Calibration of offsets greater than ± 5% of full scale will begin to subtract from the dynamic range.
4
DS454F2
CS5321/22
CS5321 ANALOG CHARACTERISTICS (Continued)
CS5321
Typ
Parameter*
Symbol
Min
Max
Unit
Input Characteristics
Input Signal Frequencies
Input Voltage Range
(Note 9)
(Note 10)
(Note 10)
BW
DC
-4.5
-
-
-
-
1600
+4.5
5
Hz
V
V
IN
Input Overrange Voltage
Power Supplies
I
%F.S.
OVR
DC Power Supply Currents
(Note 11)
LPWR = 0 Positive Supplies
Negative Supplies
-
-
5.5
5.5
3.0
3.0
7.5
7.5
4.5
4.5
mA
mA
mA
mA
LPWR = 1 Positive Supplies
Negative Supplies
Power Consumption
(Note 11)
Normal Operating Mode (Note12)
Lower Power Mode (Note 13)
P
P
-
-
55
30
75
45
mW
mW
DN
DL
Power Down
P
-
-
2
-
-
mW
dB
D
Power Supply Rejection
(dc to 128 kHz) (Note 14)
PSR
60
Notes: 9. The upper bandwidth limit is determined by the CS5322 digital filter.
10. This input voltage range is for the configuration shown in Figure 20, the System Connection Diagram,
and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3.
11. All outputs unloaded. All logic inputs forced to V or GND respectively.
dd
12. LPWR = 0.
13. The CS5321 power dissipation can be reduced under the following conditions:
a) LPWR=1; MCLK=512 kHz, HBR=1
b) LWPR=1; MCLK=1.024 MHz, HBR=0
14. Characterized with a 100 mVp-p sine wave applied separately to each supply.
* Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
DS454F2
5
CS5321/22
CS5321 SWITCHING CHARACTERISTICS (T = (See Note 1); V , V = 5 V ± ±5%; V
,
ss1
A
dd1
dd2
V
= -5 V ± ±5%; Inputs: Logic 0 = 0 V Logic 1 = V+; C = 50 pF (Note 15))
ss2
L
Parameter
Symbol
Min
0.250
40
Typ
Max
1.2
60
Units
MHz
%
MCLK Frequency
MCLK Duty Cycle
MCLK Jitter (In-band)
Rise Times:
(Note 16)
f
1.024
c
-
-
-
300
ps
Any Digital Input
Any Digital Output
(Note 17)
(Note 17)
t
-
-
-
50
100
200
ns
ns
risein
t
riseout
Fall Times:
Any Digital Input
Any Digital Output
t
-
-
-
50
100
200
ns
ns
fallin
t
fallout
MSYNC Setup Time to MCLK rising
MSYNC Hold Time after MCLK rising
MCLK rising to Valid MFLG
t
t
20
20
-
-
-
ns
ns
ns
ns
mss
msh
-
-
t
140
170
255
300
mfh
MCLK rising to Valid MDATA
t
-
mdv
Notes: 15. Guaranteed by design, characterization, or test.
16. If MCLK is removed, the modulator will enter the power down mode.
17. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.
t
t
fallin
risein
t
t
fallout
riseout
4.0 V
1.0 V
4.6 V
0.4 V
Figure 1. Rise and Fall Times
MCLK
t
mss
t
msh
MSYNC
MDATA
t
t
m dv
mdv
mfh
VALID DATA
VALID DATA
t
MFLG
Figure 2. CS5321 Interface Timing, HBR=1
6
DS454F2
CS5321/22
CS5321 DIGITAL CHARACTERISTICS (T = (See Note 1); V = V
= 5.0 V ± 5%; GND =
dd2
A
dd1
0 V; measurements performed under static conditions)
Parameter
Symbol
Min
Typ
Max
Units
V
High-Level Input Drive Voltage
Low-Level Input Drive Voltage
High-Level Output Voltage IOUT = -40 µA
Low-Level Output Voltage IOUT = +40 µA
Input Leakage Current
(Note 18)
(Note 18)
(Note 19)
(Note 19)
V
(V )-0.6
-
-
-
1.0
-
IH
dd
V
-
V
IL
V
(V )-0.3
-
V
OH
dd
V
-
-
-
-
-
0.3
±10
-
V
OL
I
-
µA
pF
pF
LKG
Digital Input Capacitance
C
9
9
IN
Digital Output Capacitance
C
-
OUT
Notes: 18. Device is intended to be driven with CMOS logic levels.
19. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.
CS5321 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND =
0 V, See Note 20)
Parameter
Symbol
Positive V
Min
Typ
Max
Units
DC Supply:
V
4.75
-4.75
5.0
-5.0
5.25
-5.25
V
V
dd1, dd2
Negative V ,V
ss1 ss2
Ambient Operating Temperature
-BL
T
-55
-
+85
°C
A
Notes: 20. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital
Supply of the CS5322 must be less than 0.25 V.
CS5321 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0 V)
Parameter
Symbol
Min
Max
Units
DC Supply:
Positive
Negative
V
V
V
-0.3
+0.3
6.0
-6.0
V
V
dd1, dd2
,V
ss1 ss2
Input Current, Any Pin Except Supplies
Output Current
(Note 21)
I
-
-
±10
25
1
mA
mA
W
in
I
out
Total Power (all supplies and outputs)
Digital Input Voltage
P
-
t
V
-0.3
-65
(V )+0.3
V
IND
dd
Storage Temperature
T
150
°C
stg
Notes: 21. Transient currents of up to 100 mA will not cause SCR latch up.
*WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
DS454F2
7
CS5321/22
CS5322 FILTER CHARACTERISTICS (T = (See Note 1); VD+ = 5.0 V; GND = 0 V;
A
CLKIN = 1.024 MHz; transfer function shown in Figure 3; unless otherwise specified.)
Output Word Rate
Passband Flatness
(dB)
Passband f1
(Hz)
-3dB Freq. f2 Stopband f3 (Hz)
Group Delay
(ms)
f (Hz)
R
PB
(Hz)
(Note 22)
0
4000
2000
1000
500
250
125
1500
750
375
187.5
93.8
46.9
23.4
0.2
1652.5
824.3
411.9
205.9
102.9
51.5
2000
1000
500
250
125
7.25
14.5
29
0.04
0.08
0.1
0.1
0.1
58
116
232
464
62.5
31.25
62.5
0.1
25.7
Notes: 22. G = -130 dB for all Output Word Rates.
SB
dB
0
-3
G
SB
-130
f1
f2 f3
f
Figure 3. CS5322 Filter Response
f0 = 62.5 Hz
Figure 4. CS5322 Digital Filter Passband Ripple
Figure 5. CS5322 Digital Filter Passband Ripple
f0 = 125 Hz
Figure 6. CS5322 Digital Filter Passband Ripple
f0 = 250 Hz
8
DS454F2
CS5321/22
Figure 7. CS5322 Digital Filter Passband Ripple
f0 = 500 Hz
Figure 8. CS5322 Digital Filter Passband Ripple
f0 = 1000 Hz
Figure 9. CS5322 Digital Filter Passband Ripple
f0 = 2000 Hz
Figure 10. CS5322 Digital Filter Passband Ripple
f0 = 4000 Hz
-5,206,250
-5,212,500
-5,218,750
-5,225,000
-5,231,250
-5,206,250
-5,208,328
-5,212,500
-5,218,750
-5,225,000
-5,231,250
-5,237,500
-5,243,750
-5,250,000
-5,240,723
-5,237,500
-5,243,750
-5,250,000
1
8
15
22
29
36
43
50
57
1
8
15
22
29
36
43
50
57
Tim e (# of O utput W ords)
Tim e (# of O utput W ords)
Figure 11. CS5322 Impulse Response,
f0 = 62.5 Hz
Figure 12. CS5322 Impulse Response,
f0 = 1000 Hz
DS454F2
9
CS5321/22
CS5322 POWER SUPPLY (T = (See Note 1); VD+ = 5 V; CLKIN = 1.024 MHz)
A
CS5322-BL
Parameter
Min
Typ
Max
Unit
Power Supply Current:
Power Dissipation:
ID+
(Note 11)
-
2.2
4
mA
(Note 11)
PWDN Low
PWDN High
-
-
11
0.6
20
2.5
mW
mW
CS5322 SWITCHING CHARACTERISTICS (T = (See Note 1); VD+ = 5 V ± 5%; DGND = 0 V;
A
Inputs: Logic 0 = 0 V Logic 1 = VD+; C = 50 pF (Note 23)
L
Parameter
CLKIN Frequency
Symbol
Min
0.512
40
Typ
1.024
-
Max
1.2
60
Units
MHz
%
f
c
CLKIN Duty Cycle
Rise Times:
Any Digital Input
Any Digital Output
t
-
-
-
50
100
100
ns
ns
rise
Fall Times:
Any Digital Input
Any Digital Output
t
-
-
-
50
100
100
ns
ns
fall
Serial Port Read Timing
DRDY to Data Valid
t
-
50
20
-
-
-
-
-
-
-
-
-
-
-
-
-
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ddv
RSEL Setup Time before Data Valid
Read Setup before CS Active
Read Active to Data Valid
t
rss
rsc
rdv
rdd
rph
t
-
t
50
50
-
SCLK rising to New SOD bit
SCLK Pulse Width High
t
t
-
30
30
100
-
SCLK Pulse Width Low
t
-
rpl
SCLK Period
t
-
rsp
SCLK falling to DRDY falling
CS High to Output Hi-Z
t
50
20
-
rst
rch
rhc
rds
t
t
t
-
Read Hold Time after CS Inactive
Read Select Setup to SCLK falling
Serial Port Write Timing
20
20
-
Write Setup Before CS Active
SCLK Pulse Width Low
t
20
30
30
100
20
20
20
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
wsc
t
wpl
SCLK Pulse Width High
t
wph
SCLK Period
t
wsp
wws
Write Setup Time to First SCLK falling
Data Setup Time to First SCLK falling
Write Select Hold Time after SCLK falling
Write Hold Time after CS Inactive
Data Hold Time after SCLK falling
t
t
wds
t
wwh
t
whc
t
wdh
23. Guaranteed by design, characterization and/or test.
10
DS454F2
CS5321/22
t
rss
RSEL
D RDY
R/W
t
ddv
t
rst
t
rsc
t
rhc
CS
t
rch
t
rdv
Hi-Z
Hi-Z
SO D
M SB-1
LSB
M SB
LSB+1
t
rdd
SCLK
t
rsp
t
t
rpl
rph
t
rds
Serial Port Read Timing
(R/W = 1, CS = 0, RSEL = 1 DRDY Does not toggle if reading status, RSEL = 0)
CS
t
w hc
t
wsc
R/W
t
wph
t
w w s
t
w w h
SCLK
t
w sp
t
w ds
t
wpl
t
w dh
LSB
M SB
M SB-1
LSB+1
SID
Serial Port Write Timing
Figure 13. CS5322 Serial Port Timing
DS454F2
11
CS5321/22
CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter
Test Data (TDATA) Timing
Symbol
Min
Typ
Max
Units
SYNC Setup Time to CLKIN rising
SYNC Hold Time after CLKIN rising
TDATA Setup Time to CLKIN rising after SYNC
TDATA Hold Time after CLKIN rising
ORCAL Setup Time to CLKIN rising
ORCAL Hold Time after CLKIN rising
DRDY Timing
t
20
20
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ss
t
sh
t
20
150
-
tds
tdh
t
-
t
20
20
os
t
-
oh
CLKIN rising to DRDY falling
t
-
-
-
140
150
140
-
-
-
ns
ns
ns
df
dr
ec
CLKIN falling to DRDY rising
t
CLKIN rising to ERROR change
RESET Timing
t
RESET Setup Time to CLKIN rising
RESET Hold Time after CLKIN rising
SYNC Setup Time to CLKIN rising
SYNC Hold Time after CLKIN rising
t
20
20
20
20
-
-
-
-
-
-
-
-
ns
ns
ns
ns
rs
rh
ss
sh
t
t
t
CLKIN
t
sh
t
t
ss
os
SYNC
t
oh
ORCAL
LSYNC*
t
tds
t
t
t
tdh
rdh
tds
TDATA
VALID
VALID
FILTER
SA MPLES
DATA
Figure 14. TDATA Setup/Hold Timing
12
DS454F2
CS5321/22
C LK IN
S YN C
LS YN C *
D R D Y
t
t
df
dr
t
ec
E R R O R
*N ote: For overw rite case, D R D Y w ill rem ain high.
Figure 15. DRDY Timing
CLKIN
t
rh
t
rs
RESET
t
sh
t
ss
SYNC
Figure 16. RESET Timing
DS454F2
13
CS5321/22
CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter
Symbol
Min
0.512
40
Typ
1.024
-
Max
1.1
60
Units
MHz
%
MCLK Frequency
MCLK Duty Cycle
Rise Times:
(Note 24)
f
c
Any Digital Input
Any Digital Output
(Note 25)
(Note 25)
t
-
-
-
50
100
200
ns
ns
rise
Fall Times:
Any Digital Input
Any Digital Output
t
-
-
-
50
100
200
ns
ns
fall
SYNC Setup Time to CLKIN rising
SYNC Hold Time after CLKIN rising
CLKIN edge to MCLK edge
t
20
20
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ss
t
-
sh
t
30
50
90
mss
msh
msd
MCLK rising to Valid MDATA
t
t
-
MSYNC Delay from MCLK rising
(Note 26)
-
Notes: 24. If MCLK is removed, the modulator will enter the power down mode.
25. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.
26. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return
low at any time as long as it remains high for at least one MCLK cycle.
C LKIN
t
sh
t
ss
S Y N C
LSY N C*
M C LK
t
m ss
t
t
m sd
m sd
M S Y N C
M D A TA
t
t
m sh
m sh
VALID D A TA
V A LID D A TA
FILTER
SA M PLES
D A TA
M FL G
* Internal tim ing signal generated in the C S 5322
Figure 17. CS5321/CS5322 Interface Timing
14
DS454F2
CS5321/22
CS5322 DIGITAL CHARACTERISTICS (T = (See Note 1); VD+ = 5.0 V ± 5%; GND = 0 V;
A
measurements performed under static conditions)
Parameter
High-Level Input Drive Voltage
Symbol
Min
Typ
Max
-
Units
V
V
(VD+)-0.3
-
-
IH
Low-Level Input Drive Voltage
V
-
0.3
-
V
IL
High-Level Input Threshold
(Note 27)
(Note 27)
(Note 28)
(Note 28)
(VD+)-1.0
-
V
Low-Level Input Threshold
-
-
1.0
-
V
High-Level Output Voltage IOUT = -40µA
Low-Level Output Voltage IOUT = +1.6 mA
V
(VD+)-0.6
-
V
OH
V
-
-
-
-
-
-
0.4
±10
±10
-
V
OL
Input Leakage Current
All pins except MFLG, SOD
I
-
µA
µA
pF
pF
LKG
Three-State Leakage Current
Digital Input Capacitance
Digital Output Capacitance
I
-
OZ
C
9
9
IN
C
-
OUT
Notes: 27. Device is intended to be driven with CMOS logic levels.
28. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.
CS5322 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND =
0 V)
Parameter
Symbol
Min
Typ
Max
Units
DC Supply:
(Note 29)
Positive
Negative
VD+
VD-
4.75
-4.75
5.0
-5.0
5.25
-5.25
V
V
Ambient Operating Temperature
-BL
T
-40
-
+85
°C
A
Notes: 29. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital
Supply of the CS5322 must be less than 0.25 V.
CS5322 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0 V)
Parameter
Symbol
Min
Typ
Max
Units
DC Supply:
(Note 29)
(Note 30)
Positive
Negative
VD+
VD-
-0.3
0.3
-
-
(VD+)+0.3
-6.0
V
V
Input Current, Any Pin Except Supplies
Digital Input Voltage
I
-
-
-
-
±10
(VD+)+0.3
150
mA
V
in
VIND
-0.3
-65
Storage Temperature
T
°C
stg
Notes: 30. Transient currents of up to 100 mA will not cause SCR latch up.
*WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
DS454F2
15
CS5321/22
2. GENERAL DESCRIPTION
The CS5321 is a fourth-order CMOS monolithic The CS5322 is a monolithic digital Finite Impulse
analog modulator designed specifically for very Response (FIR) filter with programmable decima-
high resolution measurement of signals between dc tion. The CS5322 and CS5321 are intended to be
and 1600 Hz. Configuring the CS5321 with the used together to form a unique high dynamic range
CS5322 FIR filter results in a high resolution A/D ADC chipset. The CS5322 provides the digital
converter system that performs sampling and A/D anti-alias filter for the CS5321 modulator output.
conversion with a dynamic range exceeding 120 The CS5322 consists of: a multi-stage FIR filter,
dB.
four registers (status, data, offset, and configura-
tion), a flexible serial input and output port, and a
2-channel input data multiplexer that selects data
from the CS5321 (MDATA) or user test data
(TDATA). The CS5322 decimates (64x to 4096x)
the output to any of seven selectable up-date peri-
ods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. Data
is output from the digital filter in a 24-bit serial for-
mat. Figure 19 illustrates the CS5322 Block Dia-
gram.
The CS5321 uses a fourth-order oversampling ar-
chitecture to achieve high resolution A/D conver-
sion. The modulator consists of a 1-bit A/D
converter embedded in a negative feedback loop.
The modulator provides an oversampled serial bit
stream at 256 kbits per second (HBR=1) and 128
kbits per second (HBR=0) operating with a clock
rate of 1.024 MHz. Figure 18 illustrates the
CS5321 block diagram.
AGND
DGND
Vdd1
Vss1
Vdd2
Vss2
LPWR
OFST
Digital
Control
Osc.
Detect
MFLG
AINR
AIN+
AIN-
Σ
HBR
Clock
Generation
MCLK
A/D
MSYNC
MDATA
MDATA
D/A
VREF+
VREF-
Figure 18. CS5321 Block Diagram
16
DS454F2
CS5321/22
SID
TDATA
M D ATA
CSEL
PW DN
ORC AL
US EO R
D EC C
DE CB
DE CA
DATA M UX
CO N FIG REG
CO NFIG M UX
FIR 1
H/S
SCLK
CLKIN
RESET
SYNC
C S
FIR 2
R/W
M FLG
CON TROL
D R DY
ERRO R
M SYN C
M C LK
FIR 3
DATA REG
STATUS REG
BIT SELECT
BIT SELECT
M UX
SO D
RSEL
Figure 19. CS5322 Block Diagram
DS454F2
17
CS5321/22
ing may be accomplished in an amplifier stage
ahead of the CS5321 modulator or with the RC in-
put filter at the AIN+ and AINR input pins. The RC
filter at the AIN+ and AINR pins is recommended
to reduce the "charge kick" that the driving ampli-
fier sees as the switched capacitor sampling is per-
formed.
2.1 Analog Input
The CS5321 modulator uses a switched capacitor
architecture for its signal and voltage reference in-
puts. The signal input uses three pins; AINR, AIN+,
and AIN-. The AIN- pin acts as the return pin for
the AINR and AIN+ pins. The AINR pin is a
switched capacitor "rough charge" input for the
AIN+ pin. The input impedance for the rough Figure 20 illustrates the CS5321 and CS5322 sys-
charge pin (AINR) is 1/fC where f is two times the tem connections. The input components on AINR
modulator sampling clock rate and C is the internal
and AIN+ should be identical values for optimum
sampling capacitor (about 40 pF). Using a 1.024 performance. In choosing the components the ca-
MHz master clock (HBR = 1) yields an input im- pacitor should be a minimum of 0.1 µF (C0G di-
pedance of about 1/(512 kHz)X(40 pF) or about 50 electric ceramic preferred). For minimum board
kΩ. Internal to the chip the rough charge input pre-
charges the sampling capacitor used on the AIN+
input, therefore the effective input impedance on
the AIN+ pin is orders of magnitude above the im-
pedance seen on the AINR pin.
space, the RC components on the AINR input can
be removed, but this will force the driving amplifi-
er to source the full dynamic charging current of
the AINR input. This can increase distortion in the
driving amplifier and reduce system performance.
In choosing the RC filter components, increasing C
and minimizing R is preferred. Increasing C reduc-
es the instantaneous voltage change on the pin, but
may require paralleling capacitors to maintain
smaller size (the recommended 0.1 µF C0G ceram-
ic capacitor is larger than other similar-valued ca-
pacitors with different dielectrics). Larger resistor
values will increase the voltage drop across the re-
sistor as the recharging current charges the
switched capacitor input.
The analog input structure inside the VREF+ pin is
very similar to the AINR pin but includes addition-
al circuitry whose operating current can change
over temperature and from device to device. There-
fore, if gain accuracy is important, the VREF+ pin
should be driven from a low source impedance.
The current demand of the VREF+ pin will produce
a voltage drop of approximately 45 mV across the
200 Ω source resistor of Figure 20 and Figure 21
Option A with MCLK = 1.024 MHz, HBR = 1, and
temperature = 25°C.
2.2 The OFST Pin
When the CS5321 modulator is operated with a 4.5
V reference it will accept a 9 V p-p input signal, but
modulator loop stability can be adversely affected
by high frequency out-of-band signals. Therefore,
input signals must be band-limited by an input fil-
ter. The -3 dB corner of the input filter must be
equal to the modulator sampling clock divided by
64. The modulator sampling clock is MCLK/4
when HBR = 1 or MCLK/8 when HBR = 0. With
MCLK = 1.024 MHz, HBR = 1, the modulator
sampling clock is 256 kHz which requires an input
filter with a -3 dB corner of 4 kHz. The bandlimit-
The CS5321 modulator can produce "idle tones"
which occur in the passband when the input signal
is steady state dc signal within about
± 50 mV of bipolar zero. In the CS5321 these tones
are about 135 dB down from full scale. The user
can force these idle tones "out-of-band" by adding
100 mV of dc offset to the signal at the AIN input.
Alternately, if the user circuitry has a low offset
voltage such that the input signal is within ± 50 mV
of bipolar zero when no AC signal is present, the
OFST pin on the CS5321 can be activated. When
OFST = 1, +100 mV of input referred offset will be
18
DS454F2
CS5321/22
added internal to the CS5321 and guarantee that
See the Voltage Reference section of this data sheet
any idle tones present will lie out-of-band. The user for voltage reference requirements.
should be certain that when OFST is active (OFST
The modulator is a fourth order delta-sigma and is
=1) that the offset voltage generated by the user cir-
cuitry does not negate the offset added by the
OFST pin.
therefore conditionally stable. The modulator may
go into an oscillatory condition if the analog input
is overranged. Input signals which exceed either
plus or minus full scale by more than 5 % can intro-
duce instability in the modulator. If an unstable
condition is detected, the modulator will be re-
duced to a first order system until loop stability is
achieved. If this occurs the MFLG pin will transi-
tion from a low to a high and result in an error bit
being set in the CS5322. The input signal must be
reduced to within the full scale range of the con-
verter for at least 32 MCLK cycles for the modula-
tor to recover from this error condition.
2.3 Input Range and Overrange
Conditions
The analog input is applied to the AIN+ and AINR
pins with the AIN- pin connected to GND. The in-
put is fully differential but for proper operation the
AIN- pin must remain at GND potential.
The analog input span is defined by the voltage ap-
plied between the VREF+ and VREF- input pins.
+5V
Analog
Supply
+5 V
Digital
Supply
+
10 µF
0.1 µF
0.01 µF
22
2
0.1 µF
21
VD+
20
V
V
23
dd1
dd2
DGND
1
GND11
GND1
25
24
SID
28
27
26
SOD
OFST
LPWR
HBR
Control
Logic
26
1
SCLK
CS
Ω
200
Serial
Data
5
6
+4.5V
VREF
28
22
VREF+
VREF-
25
5
6
R/W
+
µ
68
F
0.1 µF
MSYNC
MFLG
MSYNC
MFLG
TANT.
DRDY
Interface
24
20
27
23
RSEL
7
402 Ω
MCLK
MCLK
ERROR
10
12
10
18
AINR
0.1 µF
COG
CSEL
MDATA
MDATA
402 Ω
9
8
Signal
Source
CS5321
AIN+
AIN-
CS5322
0.1 µF
COG
13
14
15
19
18
17
16
4
H/S
PWDN
USEOR
ORCAL
DECA
17
11
Test
Data
MDATA
TDATA
14
13
12
GND7
GND6
GND5
Hardware
Control
15
16
3
2
GND8
GND9
CLKIN
SYNC
11
7
Clock
DECB
GND4
GND3
Source
DECC
19
4
RESET
GND10
GND2
V
V
ss1
ss2
21
VD+
8
DGND
9
0.1 µF
3
Unused logic
inputs must be
connected to
DGND or VD+
-5V
Analog
Supply
0.01 µF
+5 V
Digital
Supply
+
10 µF
0.1 µF
Figure 20. System Connection Diagram
DS454F2
19
CS5321/22
for dc-measurement applications. Due to its dy-
namic (switched-capacitor) input the input imped-
ance of the +VREF pin of the CS5321 will change
any time MCLK or HBR is changed. Therefore the
current required from the voltage reference will
change any time MCLK or HBR is changed. This
can affect gain accuracy due to the high source im-
pedance of the filter resistor in Figure 20 and Fig-
ure 21 Option A. If gain error is to be minimized,
especially when MCLK or HBR is changed, the
voltage reference should have lower output imped-
ance. The buffer of Figure 21 Option B offers lower
output impedance and will exhibit better system
gain stability.
2.4 Voltage Reference
The CS5321 is designed to operate with a voltage
reference in the range of 4.0 to 4.5 Volts. The volt-
age reference is applied to the VREF+ pin with the
VREF- pin connected to the GND. A 4.5 V refer-
ence will result in the best S/N performance but
most 4.5 V references require a power supply volt-
age greater than 5.0 V for operation. A 4.0 V refer-
ence can be used for those applications which must
operate from only 5.0 V supplies, but will yield a
S/N slightly lower (1-2 dB) than when using a 4.5
V reference. The voltage reference should be de-
signed to yield less than 2 µVrms of noise in band
at the VREF+ pin of the CS5321. The CS5322 filter
selection will determine the bandwidth over which
the voltage reference noise will affect the
CS5321/22 dynamic range.
2.5 Clock Source
For proper operation, the CS5321 must be provided
with a CMOS-compatible clock on the MCLK pin.
The MCLK for the CS5321 is usually provided by
the CS5322 filter. MCLK is usually 1.024 MHz to
set the seven selectable output word rates from the
CS5322. The MCLK frequency can be as low as
250 kHz and as high as 1.2 MHz. The choice of
clock frequency can affect performance; see the
Performance section of the data sheet. The clock
For a 4.5 V reference, the LT1019-4.5 voltage ref-
erence yields low enough noise if the output is fil-
tered with a low pass RC filter as shown in Figure
21 Option A. The filter in Figure 21 Option A is ac-
ceptable for most spectral measurement applica-
tions, but a buffered version with lower source
impedance (Figure 21 Option B) may be preferred
Ω
10
Option A
+9 to
15V
Ω
200
µ
0.1
F
To V R E F+
µ
µ
F
0.1
F
68
+
LT1019-4.5
+9 to 15 V
Option B
Ω
Ω
1k
49.9
Ω
100
1k
+
-
To V R E F+
+
+
µ
100
AL
F
F
µ
µ
Ω
10k
0.1
F
68
F
+
Tant
Ω
µ
100
AL
LT1007
Figure 21. 4.5 Voltage Reference with two filter options
20
DS454F2
CS5321/22
must have less than 300 ps jitter to maintain data CS5321 must be furnished with an MSYNC signal
sheet performance from the device. The CS5321 is
equipped with loss of clock detection circuitry erated by the CS5322, resets the MCLK counter-di-
which will cause the CS5321 to enter a powered- vider in the CS5321 to the correct phase so that the
prior to data conversion. The MSYNC signal, gen-
down state if the MCLK is removed or reduced to bitstream can be properly sampled by the CS5322
a very low frequency. The HBR pin on the CS5321 digital filter.
modifies the sampling clock rate of the modulator.
When operated with the CS5322 digital filter the
When HBR = 1, the modulator sampling clock will
output codes from the CS5321/22 will range from
be at MCLK/4; with HBR = 0 the modulator sam-
approximately decimal -5,242,880 to +5,242,879
pling clock will be at MCLK/8. The chip set will ex-
for an input to the CS5321 of ± 4.5 V. Table 1 illus-
trates the output coding for various input signal am-
hibit about 3 dB less S/N performance when the
HBR pin is changed from a logic "1" to a logic "0"
plitudes. Note that with a signal input defined as a
for the same output word rate from the CS5322.
full scale signal (4.5 V with VREF+ = 4.5 V) the
CS5321/22 chipset does not output a full scale dig-
2.6 Low Power Mode
ital code of 8,388,607 but is scaled to a lower value
The CS5321 includes a low power operating mode
to allow some overrange capability. Input signals
(LPWR =1). When operated with LPWR = 1, the
can exceed the defined full scale by up to 5% and
CS5321 modulator sampling clock must be restrict-
still be converted properly.
ed to rates of 128 kHz or less. Operating in low
power mode with modulator sample rates greater
CS5322 Filter
than 128 kHz will greatly degrade performance.
Output Code
HEX Decimal
Error Flag Possible
Modulator Input
Signal
2.7 Digital Interface and Data Format
> (+VREF + 5%)
≈ (+VREF + 5%)
+VREF
The MCLK signal (normally 1.024 MHz) is divid-
ed by four, or by eight inside the CS5321 to gener-
ate the modulator oversampling clock. The HBR
pin determines whether the clock divider inside the
CS5321 divides by four (HBR =1) or by eight
(HBR = 0). The modulator outputs a ones density
bit stream from its MDATA and MDATA pins pro-
portional to the analog input signal, but at a bit rate
determined by the modulator over sampling clock.
For proper synchronization of the bitstream, the
53FFFF(H)
+5505023
+5242879
0
4FFFFF(H)
000000(H)
B00000(H)
AC0000(H)
0V
-VREF
-5242880
-5505024
≈ - (+VREF +5%)
> - (+VREF +5%)
Error Flag Possible
Table 1. Output Coding for the CS5321 and
CS5322 Combination
DS454F2
21
CS5321/22
2.8 Performance
0
Dynamic Range = 122.0 dB
HBR = 1
OFST = 0
LPW R = 0
Figure 22, 23 and 24 illustrate the spectral perfor-
mance of the CS5321/22 and chipset when operat-
ing from a 1.024 MHz master clock. Ten 1024
point FFTs were averaged to produce the plots.
-20
-40
-60
-80
-100
-120
-140
-160
-180
Figure 22 illustrates the chip set with a 100 Hz,
-20 dB input signal. The sample rate was set at 1
kHz. Dynamic range is 122 dB.
The dynamic range calculated by the test soft-ware
is reduced somewhat in Figures 23 and 24 because
of jitter in the signal test oscillator. Jitter in the
100 Hz signal source is interpreted by the signal
processing software to be increased noise.
0
500
Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz
Input, ten averages
0
The choice of master clock frequency will affect
performance. The CS5321 will exhibit the best Sig-
nal to Distortion performance with slower modula-
tor sampling clock rates as slower sample rates
allow more time for amplifier settling.
S/D = 116.0 dB
S/N = 118.4 dB
S/N+D = 114.2 dB
HBR = 1
O FST = 0
LPW R = 0
-20
-40
-60
-80
-100
-120
-140
-160
-180
see text
For lowest offset drift, the CS5321 should be oper-
ated with MCLK = 1.024 MHz and HBR = 1. Slow-
er modulator sampling clock rates will exhibit
more offset drift. Changing MCLK to 512 kHz
(HBR = 1) or changing HBR to zero (MCLK =
1.024 MHz) will cause the drift rate to double. Off-
set drift is not linear over temperature so it is diffi-
cult to specify an exact drift rate. Offset drift
characteristics vary from part to part and will vary
as the power supply voltages vary. Therefore, if the
CS5321 is to be used in precision dc measurement
applications where offset drift is to be minimized,
the power supplies should be well regulated. The
CS5321 will exhibit about 6 ppm/°C of offset drift
with MCLK = 1 and HBR = 1. Gain drift of the
CS5321 itself is about 5 ppm/°C and is not affected
by either modulator sample rate or by power supply
variation.
0
500
Figure 23. 1024 Point FFT Plot with Full Scale Input,
100 Hz Input, HBR = 1, ten averages
0
S/D = 122.7 dB
S/N = 117.1 dB
S/N+D = 116.4 dB
HBR = 0
OFST = 0
-20
-40
-60
-80
-100
-120
-140
-160
-180
LPW R = 0
see text
0
500
Figure 24. 1024 Point FFT Plot with Full Scale Input,
100 Hz Input, HBR = 0, ten averages
22
DS454F2
CS5321/22
2.9 Power Supply Considerations
2.11 RESET Operation
The system connection diagram, Figure 20, illus-
trates the recommended power supply arrange-
ments. There are two positive power supply pins
The RESET pin puts the CS5322 into a known ini-
tialized state. RESET is recognized on the next
CLKIN rising edge after the RESET pin has been
for the CS5321 and two negative power supply brought high (RESET=1). All internal logic is ini-
pins. Power must be supplied to all four pins and tialized when RESET is active.
each of the supply pins should be de-coupled with
a 0.1 µF capacitor to the nearest ground pin on the
device.
Normal device operation begins on the second
CLKIN rising edge after RESET is brought low.
The CS5322 will remain in an idle state, not per-
When used with the CS5322 digital filter, the max- forming convolutions, until triggered by a SYNC
imum voltage differential between the positive sup- event.
plies of the CS5321 and the positive digital supply
A RESET operation clears memory, sets the data
of the CS5322 must be less than 0.25 V. Operation
output register, offset register, and status flags to all
beyond this constraint may result in loss of analog
zeroes, and sets the configuration register to the
performance in the CS5321/22 system perfor-
state of the corresponding hardware pins (PWDN,
ORCAL, DECC, DECB, DECA, USEOR, and
mance.
Many seismic or portable data acquisition systems CSEL). The reset state is entered on power on, in-
are battery powered and utilize dc-dc converters to dependent of the RESET pin. If RESET is low, the
generate the necessary supply voltages for the sys- first CLKIN will exit the power on reset state.
tem. To minimize the effects of power supply inter-
2.12 Power-down Operation
ference, it is desirable to operate the dc-dc
The PWDN pin puts the CS5322 into the power-
down state. The power-down state is entered on the
first CLKIN rising edge after the PWDN pin is
brought high. While in the power-down state, the
MCLK and MSYNC signals to the CS5321 analog
modulator are held low. The loss of the MCLK sig-
nal to the modulator causes it to power-down. The
signals on the MDATA and MFLG pins are ig-
nored. The serial interface of the CS5322 remains
active allowing read and write operations. Informa-
tion in the data register, offset register, configura-
tion register, and convolution data memory are
maintained during power-down. The internal con-
troller requires 64 clock cycles after PWDN is as-
serted before CLKIN stops.
converter at a frequency which is rejected by the
digital filter, or locked to the modulator sample
clock rate.
A synchronous dc-dc converter, whose operating
frequency is derived from the 1.024 MHz clock
used to drive the CS5322, will minimize the poten-
tial for "beat frequencies" appearing in the pass-
band between dc and the corner frequency of the
digital filter.
2.10 Power Supply Rejection Ratio
The PSRR of the CS5321 is frequency dependent.
The CS5322 digital filter attenuation will aid in re-
jection of power supply noise for frequencies
above the corner frequency setting of the CS5322.
For frequencies between dc and the corner frequen- The CS5322 exits the power-down state on the first
cy of the digital filter, the PSRR is nearly constant CLKIN rising edge after the PWDN pin is brought
at about 60 dB.
low. The CS5322 then enters an idle state until trig-
gered by a SYNC event.
DS454F2
23
CS5321/22
To avoid possible high current states while in the SCLK falling edge, each SCLK rising edge shifts
power down state, the following conditions apply:
out a new bit. Status reads are 16 bits, and data
reads are 24 bits. Both streams are supplied as MSB
first, LSB last.
1) CLKIN must be active for at least 64 clock cy-
cles after PWDN entry.
In the event more SCLK pulses are supplied than
necessary to clock out the requested information,
trailing zeroes will be output for data reads and
trailing LSB’s for status reads. If the read operation
is terminated before all the bits are read, the inter-
nal bit pointer is reset to the MSB so that a re-read
will give the same data as the first read, with one
exception. The status error flags are cleared on read
and will not be available on a re-read.
2) CSEL and TDATA must not both be asserted
high.
2.13 SYNC Operation
The SYNC pin is used to start convolutions and
synchronize the CS5322 and CS5321 to an external
sampling source or timing reference. The SYNC
event is recognized on the first CLKIN rising edge
after the SYNC pin goes high. SYNC may remain
high indefinitely. Only the sequence of SYNC ris-
ing followed by CLKIN rising generates a SYNC
event.
The status error flags must be read before entering
the power-down state. If an error has occurred be-
fore entering powerdown and the status bit (ER-
ROR) has not been read, the status bits (ERROR,
OVERWRITE, MFLG, ACC1 and ACC2) may not
be cleared on status reads. Upon exiting the power-
down state and entering normal operation, the user
may be flagged that an error is still present.
The SYNC event aligns the output sample and
causes the filter to begin convolutions. The first
SYNC event causes an immediate DRDY provided
DRDY is low. Subsequent data ready events will
occur at a rate determined by the decimation rate
inputs DECC, DECB, and DECA. Multiple SYNC
events can be applied with no effect on operation if
they are perfectly timed according to the decima-
tion rate. Any SYNC event not in step with the dec-
imation rate will cause a realignment and loss of
data.
The SOD pin floats when read operation is deacti-
vated (R/W=1, CS=1). This enables the SID and
SOD pins to be tied together to form a bi-direction-
al serial data bus. There is an internal nominal
100 kΩ±pull-up resistor on the SOD pin.
2.15 Serial Write Operation
2.14 Serial Read Operation
Serial write is used to write data to the configura-
tion register. The CS, R/W, SCLK and SID pins
control the serial write operation. The serial write
operation is activated when CS goes low (CS=0)
with R/W pin low (R/W=0).
Serial read is used to obtain status or conversion
data. The CS, R/W, SCLK, RSEL, and SOD pins
control the read operation. The serial read opera-
tion is activated when CS goes low (CS=0) with the
R/W pin high (R/W=1). The RSEL pin selects be-
tween conversion data (data register) or status in-
formation (status register). The selected serial bit
stream is output on the SOD (Serial Output Data)
pin.
Serial input data on the SID pin is sampled on the
falling edge of SCLK. The input bits are stored in a
temporary buffer until either the write operation is
terminated or 8 bits have been received. The data is
then parallel loaded into the configuration register.
If fewer than 8 bits are input before the write termi-
nation, the other bits may be indeterminate.
On read select, SCLK can either be high or low, the
first bit appears on the SOD pin and should be
latched on the falling edge of SCLK. After the first
24
DS454F2
CS5321/22
Note that a write will occur when CS = 0 and R/W
cept when ORCAL = 1 and the CS5322 is RESET
= 0 even if SCLK is not toggled. Failure to clock in as this toggles the ORCAL internally). After OR-
data with the appropriate number of SCLKs can CAL has been toggled, the SYNC signal must be
leave the configuration register in an indeterminate applied to the CS5322. The filter settles on the in-
condition.
put value in 56 output words. The output word rate
is determined by the state of the decimation rate
control pins, DECC, DECB, and DECA. On the
57th output word, the CS5322 issues the OR-
CALD status flag, outputs the offset data sample,
and internally loads the offset register. During cal-
ibration, the offset register value is not used.
The serial bit stream is received MSB first, LSB
last. The order of the input control data is PWDN
first, followed by ORCAL, USEOR, CSEL, Re-
served, DECC, DECB, and DECA. The configura-
tion data bits are defined in Table 2. The
configuration data controls device operation only
when in the software mode, i.e., the H/S pin is low If USEOR is high (USEOR=1), subsequent sam-
(H/S = 0). The Reserved configuration data bit
must always be written low.
ples will have the offset subtracted from the output.
The state of USEOR must remain high for the com-
plete duration of the convolution cycle. If USEOR
is low (USEOR=0), the output word is not correct-
ed, but the offset register retains its value for later
use. The results of the last calibration will be held
in the offset register until the end of a new calibra-
tion, or until the CS5322 is reset using the RESET
pin. USEOR does not alter the offset register value,
only its usage.
2.16 Offset Calibration Operation
The offset calibration routine computes the offset
produced by the CS5321 modulator and stores this
value in the offset register. The USEOR pin or bit
determines if the offset register data is to be used to
correct output words.
After power is applied to the chip set the CS5322
must be RESET. To begin an offset calibration, the
CS5321 analog input must represent the offset val-
ue. Then in software mode (H/S = 0) the ORCAL
bit must be toggled from a low to a high. In hard-
ware mode the ORCAL pin must be toggled low
for at least one CLKIN cycle, then taken high (ex-
To restart a calibration, ORCAL and SYNC must
be taken low for at least one CLKIN cycle. OR-
CAL must then be taken high. The calibration will
restart on the next SYNC event. If the ORCAL pin
remains in a high state, only a single calibration
will start on the first SYNC signal.
Equivalent Hardware
Input Bit #
Function
PWDN
ORCAL
USEOR
CSEL
Description
Standby mode
1 (MSB)
2
Self-offset calibration
Use Offset Register
Channel Select
3
4
5
Reserved
DECC
Factory use only
Filter BW selection
Filter BW selection
Filter BW selection
6
7
DECB
8 (LSB)
DECA
Table 2. Configuration Data Bits
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25
CS5321/22
tempted, the CS5322 assumes that data is not want-
ed and does not assert OVERWRITE, and the old
data is over-written by the new data. On an OVER-
WRITE condition, the old partially read data is pre-
served, and the new data word is lost.
2.17 Status Bits
The Status Register is a 16-bit register which al-
lows the user to read the flags and configuration
settings of the CS5322. Table 3 documents the data
bits of the Status Register.
Status reads have no effect on OVERWRITE assert
operations. The OVERWRITE bit is cleared on a
status register read or RESET.
The ERROR bit and ERROR pin value are the
OR’ed result of OVERWRITE, MFLG, ACC1, and
ACC2. The ERROR bit is active high whenever
any of the four error bits are set due to a fault con- The MFLG error bit reflects the CS5321 MFLG
dition. The ERROR pin output is active low and signal. Any high level on the CS5322 MFLG pin
has a nominal 100 kΩ±internal pull-up resistor.
will set the MFLG status bit. The bit is cleared on a
status register read or RESET operation, only if the
MFLG pin on the CS5322 has returned low. A in-
ternal nominal 100 kΩ±pulldown resistor is on the
MFLG pin.
The OVERWRITE bit is set when new conversion
data is ready to be loaded into the data register, but
the previous data was not completely read out. This
can occur on either of two conditions: a read oper-
ation is in progress or a read operation was started,
The accumulator error bits, ACC1 and ACC2, indi-
then aborted, and not completed. These two condi- cate that an underflow or overflow has occurred in
tions are data read attempts. The attempt is identi- the FIR1 filter for ACC1, or the FIR2 and FIR3 fil-
fied by the first SCLK low edge (MSB read) of a
ters for ACC2. Both errors are cleared on a status
data register read. If a data register read is not at- read, provided the error conditions are no longer
Output Bit #
Function
Error
Description
Detects one of the errors below
Overwrite Error
1 (MSB)
2
3
OVERWRITE Error
MFLG Error
ACC1 Error
ACC2 Error
DRDY
Modulator Flag Error
Accumulator 1 Error
Accumulator Error
4
5
6
Data Ready
7
1SYNC
First sample after SYNC
Offset calibration done
Standby mode
8
ORCALD
PWDN
9
10
11
12
13
14
15
16
ORCAL
Self-offset Calibration
Use Offset Register
Channel Select
USEOR
CSEL
Reserved
DECC
Factory use only
Bandwidth Selection Status
Bandwidth Selection Status
Bandwidth Selection Status
DECB
DECA
Table 3. Status Data (from the SOD Pin)
26
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CS5321/22
present. In normal operation the ACC1 error will
only occur when the input data stream to FIR1 is all
1’s for more than 32 bits. The ACC2 error cannot
occur in normal operation.
able in the output register. This flag is high only
during that sample and is otherwise low.
The remaining five status bits (PWDN, ORCAL,
USEOR, CSEL, Reserved, DECC, DECB, and DE-
The DRDY bit reflects the state of the DRDY pin. CA) provide configuration readback for the user.
DRDY rising edge indicates that a new data word These bits echo the control source for the CS5322
has been loaded into the data register and is avail- such that in the hardware mode (H/S=1), they fol-
able for reading. DRDY will fall after the SCLK low the corresponding input pins. In host mode
falling edge that reads the data register LSB. If no-
(H/S=0) they follow the corresponding configura-
data read attempt is made, DRDY will pulse low tion bits.
for 1/2 CLKIN cycle, providing a positive edge on
A brief explanation of the eight bits are as follows:
the new data availability. In the OVERWRITE
case, DRDY remains high because new data is not
loaded at the normal end of conversion time.
PWDN - When high, indicates that the CS5322 is in
the power-down state.
ORCAL - When high, indicates a potential calibra-
tion start.
The 1SYNC status bit provides an indication of the
filter group delay. It goes high on the second output
sample after SYNC and is valid for only that sam-
ple. For repetitive SYNC operations, SYNC must
run at one fourth the output word rate or slower to
avoid interfering with the 1SYNC operation. With
these slower repetitive SYNC’s or non-periodic
SYNC’s separated by at least three output words,
1SYNC will occur on the second output sample af-
ter SYNC.
USEOR - When high, indicates the Offset Register is
used. During calibration, this bit will read zero indi-
cating the offset register is not being used during cal-
ibration.
CSEL- When high, TDATA is selected as the filter
source. When low, the MDATA output signal from
the CS5321 is selected as the input source to the fil-
ter.
ORCALD indicates that calibration of the offset
register is complete and the offset sample is avail-
Reserved - Always read low.
DECC, DECB, and DECA - Indicate the decimation
rate of the filter and are defined in Table 4.
DECC
DECB
DECA
Output Word Rate (Hz)
Clocks Filter Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
62.5
125
16384
8192
4096
2048
1024
512
250
500
1000
2000
4000
Reserved
256
-
Table 4. Bandwidth Selection: Truth Table
DS454F2
27
CS5321/22
AINR pins should be placed with their leads on the
same axis, not side-by-side. If these capacitors are
placed side-by-side their electric fields can interact
and cause increased distortion. The chip should be
surrounded with a ground plane. Trace fill should
be used around the analog input components.
2.18 Board Layout Considerations
All of the 0.1 µF filter capacitors on the power sup-
plies, AIN+, and AINR, should be placed very
close to the chip and connect to the nearest ground
pin on the device. The capacitors between VREF+
and VREF- should be located as close to the chip as
possible. The 0.l µF capacitors on the AIN+ and
28
DS454F2
CS5321/22
3. CS5321 PIN DESCRIPTIONS
Power Supplies
Vdd1 – Positive Power One, PIN 2
Positive supply voltage. Nominally +5 Volts.
Vdd2 – Positive Power Two, PIN 22
Positive supply voltage. Nominally +5 Volts.
Vss1 – Negative Power One, PIN 3
Negative supply voltage. Nominally -5 Volts.
Vss2 – Negative Power Two, PIN 21
Negative supply voltage. Nominally -5 Volts.
GND1 through GND11 – Ground, PINS 1, 4, 7, 11, 12, 13, 14, 15, 16, 19, 23.
Ground reference.
Analog Inputs
AIN+ - Positive Analog Input, PIN 9
Nominally ± ±4.5V
AIN- - Negative Analog Input, PIN 8
This pin is tied to ground.
DS454F2
29
CS5321/22
AINR - Analog Input Rough, PIN 10
Allows a non-linear current to bypass the main external anti-aliasing filter which if allowed to
happen, would cause harmonic distortion in the modulator. Please refer to the System
Connection Diagram and the Analog Input and Voltage Reference section of the data sheet for
recommended use of this pin.
VREF+ – Positive Voltage Reference Input, PIN 5
This pin accepts an external +4.5 V voltage reference.
VREF- – Negative Voltage Reference Input, PIN 6
This pin is tied to ground.
Digital Inputs
MCLK – Clock Input, PIN 20
A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary
clock for operation of the modulator and data output portions of the A/D converter. MCLK is
normally supplied by the CS5322
MSYNC – Modulator Sync, PIN 25
A transition from a low to high level on this input will re-initialize the CS5321. MSYNC resets
a divider-counter to align the MDATA output bit stream from the CS5321 with the timing
inside the CS5322.
OFST - Offset, PIN 28
When high, adds approximately 100 mV of input referred offset to guarantee that any zero
input limit cycles are out of band if present. When low, zero offset is added.
LPWR - Low Power Mode, PIN 27
The CS5321 power dissipation can be reduced from its nominal value of 55 mW to 30 mW
under the following conditions:
LPWR=1; MCLK = 512 kHz, HBR=1; or LPWR=1; MCLK = 1.024 MHz, HBR=0
HBR – High Bit Rate, Pin 26
Selects either 1 ⁄4 MCLK (HBR=1) or 1 ⁄8MCLK (HBR=0) for the modulator sampling clock.
Digital Outputs
MDATA – Modulator Data Output, PIN 18
Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz (HBR=1) or
128 kHz (HBR=0) with MCLK operating at 1.024 MHz.
MDATA – Modulator Data Output, PIN 17
Inverse of the MDATA output.
MFLG – Modulator Flag, PIN 24
A transition from a low to high level signals that the CS5321 modulator is unstable due to an
overrange on the analog input
30
DS454F2
CS5321/22
4. CS5322 PIN DESCRIPTIONS
CHIP SELECT
CS
FRAME SYNC SYNC
CLOCK INPUT CLKIN
R/W
READ/WRITE
RSEL REGISTER SELECT
SCLK SERIAL CLOCK
RESET RESET
MODULATOR SYNC MSYNC
MODULATOR FLAG MFLG
MODULATOR CLOCK MCLK
SID
SERIAL INPUT DATA
SERIAL OUTPUT DATA
4
3
2
1
28 27 2 6
SOD
5
25
24
23
22
21
20
19
6
CS5322
ERROR ERROR FLAG
DRDY DATA READY
7
TOP
POSITIVE DIGITAL POWER
VD+
8
VIEW
9
DIGITAL GROUND DGND
MODULATOR DATA MDATA
TEST DATA TDATA
VD+
POSITIVE DIGITAL POWER
10
11
DGND DIGITAL GROUND
ORCAL OFFSET CALIBRATION
DECA DECIMATION RATE CONTROL
12 13 14 15 16 17 18
CHANNEL SELECT CSEL
HARDWARE/SOFTWARE MODE
H/S
DECIMATION RATE CONTROL
DECIMATION RATE CONTROL
DECB
DECC
POWER DOWN PWDN
USEOR USE OFFSET REGISTER
Power Supplies
VD+ – Positive Digital Power, Pin 8, 21
Positive digital supply voltage. Nominally +5 volts.
DGND – Digital Ground, Pin 9, 20
Digital ground reference.
Digital Outputs
MCLK – Modulator Clock Output, Pin 7
A CMOS-compatible clock output (nominally 1.024 MHz) that provides the necessary clock for
operation of the modulator.
MSYNC – Modulator Sync, Pin 5
The transition from a low to high level on this output will re-initialize the CS5321.
ERROR - Error Flag, Pin 23
This signal is the output of an open pull-up NOR gate with a nominal 100 kΩ±pull-up resistor
to which the error status data (OVERWRITE error, MFLG error, ACC1 error and ACC2 error)
are inputs. When low, it notifies the host processor that an error condition exists. The ERROR
signal can be wire OR’d together with other filters’ outputs. The value of the internal pull-up
resistor is 100 kΩ.
DRDY - Data Ready, Pin 22
When high, data is ready to be shifted out of the serial port data register.
DS454F2
31
CS5321/22
SOD - Serial Output Data, Pin 24
The output coding is 2’s complement with the data bits presented MSB first, LSB last. Data
changes on the rising edge of SCLK. An internal nominal 100 kΩ±pull-up resistor is included.
Digital Inputs
MDATA – Modulator Data, Pin 10
Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz; (CLKIN =
1.024 MHz).
TDATA - Test Data, Pin 11
Input for user test data.
MFLG – Modulator Flag, Pin 6
A transition from a low to high level signals that the CS5321 modulator is unstable due to an
over-range on the analog input. A Status Bit will be set in the digital filter indicating an error
condition. An internal nominal 100 kΩ±pull-down resistor included on the input pin.
RESET - Filter Reset, Pin 4
Performs a hard reset on the chip, all registers and accumulators are cleared. All signals to the
device are locked out except CLKIN. The error flags in the Status Register are set to zero and
the Data Register and Offset Register are set to zero. The configuration register is set to the
values of the corresponding input pins. SYNC must be applied to resume convolutions after
RESET deasserts.
CLKIN - Clock Input, Pin 3
A CMOS-Compatible clock input to this pin (nominally 1.024 MHz) provides the necessary
clock for operation the modulator and filter.
SYNC - Frame Sync, Pin 2
Conversion synchronization input. This signal synchronizes the start of the filter convolution.
More than one SYNC signal can occur with no effect on filter performance, providing the
SYNC signals are perfectly timed at intervals equal to the output sample period.
CSEL - Channel Select, Pin 12
When high, information on the TDATA pin is presented to the digital filter. A low causes data
on the MDATA input to be presented to the digital filter.
PWDN - Powerdown, Pin 14
Powers down the filter when taken high. Convolution cycles in the digital filter and the MCLK
signal are stopped. The registers maintain their data and the serial port remains active. SYNC
must be applied to resume convolutions after PWDN deasserts.
DECA - Decimation Rate Control, Pin 18
See Table 4.
DECB - Decimation Rate Control, Pin 17
See Table 4.
32
DS454F2
CS5321/22
DECC - Decimation Rate Control, Pin 16
See Table 4.
H/S - Hardware/Software Mode Select, Pin 13
When high, the device pins control device operation; when low, the value entered by a prior
configuration write controls device operation.
CS - Chip Select, Pin 1
When high, all signal activity on the SID, R/W and SCLK pins is ignored. The DRDY and
ERROR signals indicate the status of the chip’s internal operation.
R/W - Read/Write, Pin 28
Used in conjunction with CS such that when both signals are low, the filter inputs data from the
SID pin on the falling edge of SCLK. If CS is low and R/W is high, the filter outputs data on
the SOD pin on the rising edge of SCLK. R/W low floats the SOD pin allowing SID and SOD
to be tied together, forming a bidirectional serial data bus.
SCLK - Serial Clock, Pin 26
Clock signal generated by host processor to either input data on the SID input pin, or output
data on the SOD output pin. For write, data must be valid on the SID pin on the falling edge of
SCLK. Data changes on the SOD pin on the rising edge of SCLK.
SID - Serial Data Input, Pin 25
Data bits are presented MSB first, LSB last. Data is latched on the falling edge of SCLK.
RSEL - Register Select, Pin 27
Selects conversion data when high, or status data when low.
USEOR - Use Offset Register, Pin 15
Use offset register value to correct output words when high. Output words will not be offset
corrected when low.
ORCAL - Offset Register Calibrate, Pin 19
Initiates an offset calibration cycle when SYNC goes high after ORCAL has been toggled from
low to high. The offset value is output on the 57th word following SYNC. Subsequent words
will have their offset correction controlled by USEOR.
DS454F2
33
CS5321/22
5. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full-scale (rms) signal to the broadband (rms) noise signal. Broadband noise is
measured with the input grounded within the bandwidth of 1 Hz to f3 Hz (See “CS5322
FILTER CHARACTERISTICS” on page 8). Units in dB.
Signal-to-Distortion
The ratio of the full-scale (rms) signal to the rms sum of all harmonics up to f3 Hz.
Units in dB.
Intermodulation Distortion
The ratio of the rms sum of the two test frequencies (30 and 50 Hz) which are each 6 dB down
from full-scale to the rms sum of all intermodulation components within the bandwidth of dc to
f3 Hz. Units in dB.
Full Scale Error
The ratio of the difference between the value of the voltage reference and analog input voltage
to the full scale span (two times the voltage reference value). This ratio is calculated after the
effects of offset and the external bias components are removed and the analog input voltage is
adjusted. Measurement of this parameter uses the circuitry illustrated in the System Connection
Diagram. Units in %.
Full Scale Drift
The change in the Full Scale value with temperature. Units in %/°C.
Offset
The difference between the analog ground and the analog voltage necessary to yield an output
code from the CS5321/22 of 000000(H). Measurement of this parameter uses the circuit
configuration illustrated in the System Connection Diagram. Units in mV.
Offset Drift
The change in the Offset value with temperature. Measurement of this parameter uses the
circuit configuration illustrated in the System Connection Diagram. Units in µV/°C.
34
DS454F2
CS5321/22
6. PACKAGE DIMENSIONS
28L PLCC PACKAGE DRAWING
e
D2/E2
E1 E
B
D1
D
A1
A
INCHES
MILLIMETERS
DIM
A
A1
B
MIN
MAX
MIN
4.043
2.205
MAX
4.572
3.048
0.165
0.090
0.013
0.485
0.450
0.390
0.485
0.450
0.390
0.040
0.180
0.120
0.021
0.495
0.456
0.430
0.495
0.456
0.430
0.060
0.319
0.533
D
11.883
11.025
9.555
11.883
11.025
9.555
12.573
11.582
10.922
12.573
11.582
10.922
1.524
D1
D2
E
E1
E2
e
0.980
JEDEC #: MS-018
DS454F2
35
CS5321/22
7. ORDERING INFORMATION
Model
CS5321-BL
Temperature
Package
-55 to +85 °C
CS5321-BLZ (Lead Free)
CS5322-BL
28-pin SSOP
-40 to +85 °C
CS5322-BLZ (Lead Free)
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
CS5321-BL
Peak Reflow Temp
225 °C
MSL Rating*
Max Floor Life
260 °C
CS5321-BLZ (Lead Free)
CS5322-BL
2
365 Days
225 °C
260 °C
CS5322-BLZ (Lead Free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
9. REVISION HISTORY
Revision
Date
Changes
PP3
OCT 2003
Initial Release.
Update ordering information. MSL data added. Change CS5321 T spec to -40 to
A
F1
F2
AUG 2005
SEP 2005
+85 degrees.
Change CS5321 T spec to -55 to +85 degrees.
A
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
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to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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or service marks of their respective owners.
36
DS454F2
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