CS5467-IS_技术文档

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CS5467

Four-channel Power/Energy IC

Features

Description

• Energy Data Linearity: ±±0.1 of Reading over

.±±±:. Dynamic Range

The CS5467 is an integrated power measure-

ment device which combines four ∆Σ

analog-to-digital converters, power calculation

engine, energy-to-frequency converter, and a

serial interface on a single chip. It is designed to

accurately measure instantaneous current and

• On-chip Functions:

- Instantaneous Voltage, Current, and Power

- I

and V

, Active, Reactive, and Apparent

RMS

Power

- Current Fault and Voltage Sag Detect

- System Calibrations / Phase Compensation

- Temperature Sensor

- Energy-to-pulse Conversion

- Positive-only Accumulation Mode

voltage and calculate V

, I

, instantaneous

RMS RMS

power, active power, apparent power, and reac-

tive power for high-performance power

measurement applications.

• Meets Accuracy Spec for IEC, ANSI, & JIS

• Low Power Consumption

The CS5467 is optimized to interface to shunt re-

sistors or current transformers for current

measurement, and to resistive dividers or poten-

tial transformers for voltage measurement.

• GND-referenced Signals with Single Supply

• On-chip, 205 V Reference

The CS5467 also features system-level calibra-

tion, a temperature sensor, voltage sag & current

fault detection, and phase compensation.

• Power Supply Monitor

• Simple Three-wire Digital Serial Interface

• “Auto-boot” Mode from Serial E²PROM0

• Power Supply Configurations

ORDERING INFORMATION:

VA+ = +5 V; AGND = ± V; VD+ = +303 V to +5 V

See Page 45.

VA+

RESET

VD+

IIN1+

IIN1-

4th Order ∆Σ

Digital

Filter

HPF

Option

PGA

x10

Modulator

MODE

CS

SDI

VIN1+

VIIN1-

2nd Order ∆Σ

Modulator

SDO

SCLK

INT

Digital

Filter

HPF

Option

Serial

Interface

Power

Calculation

Engine

E1

E2

E3

IIN2+

IIN2-

4th Order ∆Σ

Modulator

Digital

Filter

HPF

Option

E-to-F

PGA

VIN2+

VIN2-

2nd Order ∆Σ

Modulator

Digital

Filter

HPF

Option

Calibration

x10

x1

VREFIN

Temperature

Sensor

System

Clock

Generator

Power

Monitor

/K

Voltage

VREFOUT

Reference

PFMON

XIN XOUT CPUCLK

DGND

AGND

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Advance Product Information

MAR ‘06

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CS5467

TABLE OF CONTENTS

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended Operating Conditions 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7

Analog Characteristics 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7

Voltage Reference 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9

Digital Characteristics 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9

Switching Characteristics 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ..

Absolute Maximum Ratings 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .3

4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

40. Digital Filters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .4

402 Voltage and Current Measurements 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .5

403 Power Measurements 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .5

404 Linearity Performance 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .6

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

50. Analog Inputs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

50.0. Voltage Channel Input 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

50.02 Current Channel Inputs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

502 IIR Filters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

503 High-pass Filters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

504 Performing Measurements 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

505 Energy Pulse Output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .8

5050. Active Energy 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .8

50502 Apparent Energy Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .9

50503 Reactive Energy Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .9

50504 Voltage Channel Sign Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2±

50505 PFMON Output Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2±

506 Sag and Fault Detect Feature 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2±

507 On-chip Temperature Sensor 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2±

508 Voltage Reference 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

509 System Initialization 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

50.± Power-down States 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

50.. Oscillator Characteristics 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

50.2 Event Handler 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

50.20. Typical Interrupt Handler 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22

50.3 Serial Port Overview 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22

50.30. Serial Port Interface 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22

50.4 Register Paging 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23

50.5 Commands 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24

6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

60. Page ± Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28

602 Page . Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34

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603 Page 2 Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38

7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

70. Channel Offset and Gain Calibration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39

70.0. Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39

70.0.0. Duration of Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39

70.02 Offset Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39

70.020. DC Offset Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39

70.0202 AC Offset Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4±

70.03 Gain Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4±

70.030. AC Gain Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4±

70.0302 DC Gain Calibration Sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.

70.04 Order of Calibration Sequences 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.

702 Phase Compensation 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.

703 Active Power Offset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.

2

8. Auto-boot Mode Using E PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

80. Auto-boot Configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42

2

802 Auto-boot Data for E PROM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42

2

803 Which E PROMs Can Be Used? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42

9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 45

13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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LIST OF FIGURES

Figure 1. CS5464 Read and Write Timing Diagrams ................................................................. 12

Figure 2. Timing Diagram for E1, E2, and E3 ...................................................................................... 13

Figure 3. Data Measurement Flow Diagram............................................................................... 14

Figure 4. Data Measurement Flow Diagram............................................................................... 14

Figure 5. Power Calculation Flow............................................................................................... 15

Figure 6. Active and Reactive energy pulse outputs .................................................................. 19

Figure 7. Apparent energy pulse outputs.................................................................................... 19

Figure 8. Voltage Channel Sign Pulse outputs........................................................................... 20

Figure 9. PFMON output to pin E3........................................................................................................ 20

Figure 10. Sag and Fault Detect................................................................................................. 20

Figure 11. Oscillator Connection ................................................................................................ 21

Figure 12. CS5467 Memory Map................................................................................................ 23

Figure 13. Calibration Data Flow ................................................................................................ 39

Figure 14. System Calibration of Offset...................................................................................... 39

Figure 15. System Calibration of Gain........................................................................................ 40

Figure 16. Example of AC Gain Calibration................................................................................ 40

Figure 17. Example of AC Gain Calibration................................................................................ 40

Figure 18. Typical Interface of E²PROM to CS5467 .................................................................. 42

Figure 19. Typical Connection Diagram ^{(Single-phase, 3-wire – Direct Connect to Power Line)}...................... 43

LIST OF TABLES

Table .0 Current Channel PGA Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .7

Table 20 E2 Pin Configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .8

Table 30 E3 Pin Configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .8

Table 40 Interrupt Configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22

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1. OVERVIEW

The CS5467 is a CMOS monolithic power measurement device with a computation engine and an ener-

gy-to-frequency pulse output. The CS5467 combines four ∆Σ analog-to-digital converters (ADCs), system

calibration, and a computation engine on a single chip.

The CS5467 is designed for power measurement applications and is optimized to interface to a cur-

rent-sense resistor or transformer for current measurement, and to a resistive divider or potential trans-

former for voltage measurement. The current channels provide programmable gains to accommodate

various input levels from a multitude of sensing elements. With a single +5 V supply on VA+/AGND, the

CS5467’s four input channels can accommodate common mode plus signal levels between

(AGND - 0.25 V) and VA+.

The CS5467 also is equipped with a computation engine that calculates instantaneous power, I_RMS

,

V_RMS, apparent power, active (real) power, reactive power, and power factor. Additional features of the

CS5467 include line frequency monitoring, current and voltage sag detection, zero-cross detection, pos-

itive-only accumulation mode, and three programmable pulse output pins. To facilitate communication to

a microprocessor, the CS5467 includes a simple three-wire serial interface which is SPI™ and Microw-

ire™ compatible. The CS5467 provides three outputs for energy registration. Pins E1, E2, and E3 are de-

signed to interface to a microprocessor.

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2. PIN DESCRIPTION

Crystal Out

XOUT

CPUCLK

VD+

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

XIN

SDI

Crystal In

CPU Clock Output

Positive Digital Supply

Digital Ground

Serial Data Input

Energy Output 2

Energy Output 1

Interrupt

E2

E1

INT

RESET

E3

PFMON

IIN1+

IIN1-

VA+

AGND

IIN2+

IIN2-

DGND

SCLK

SDO

Serial Clock

Serial Data Ouput

Chip Select

Reset

CS

High-frequency Energy Output

Power Fail Monitor

Differential Current Input

Positive Analog Supply

Analog Ground

Mode Select

Differential Voltage Input

MODE

VIN1+

VIN1-

9

10

11

12

13

14

Voltage Reference Output VREFOUT

Voltage Reference Input

Differential Voltage Input

VREFIN

VIN2+

VIN2-

Differential Current Input

Clock Generator

XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to

a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to

the XIN pin to provide the system clock for the device.

Crystal Out

Crystal In

1,28

2

CPU Clock Output

CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.

Control Pins and Serial Data I/O

SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of

the transmit buffer onto the SDO pin when CS is low.

Serial Clock Input

5

Serial Data Output

Chip Select

6

7

8

SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.

CS - Low, activates the serial port interface.

Mode Select

MODE - High, enables the “auto-boot” mode. The mode pin is pull-down by an internal resistor.

22, 25,

26

Energy Output

Reset

E3, E1, E2 - Active low pulses with an output frequency proportional to energy.

RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which

drive output pins) are set to their default states.

23

Interrupt

24

27

INT - Low, indicates that an enabled event has occurred.

Serial Data Input

Analog Inputs/Outputs

SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.

9,10

13, 14

Differential Voltage Inputs

Differential Current Inputs

Voltage Reference Output

VIN1+, VIN1-, VIN2+, VIN2- - Differential analog input pins for the voltage channel.

IIN+, IIN-, IIN2+, IIN2- - Differential analog input pins for the current channel.

19,20,

15,16

VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-

tude of 2.5 V and is referenced to the AGND pin on the converter.

11

12

Voltage Reference Input

Power Supply Connections

Positive Digital Supply

Digital Ground

VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.

3

4

VD+ - The positive digital supply.

DGND - Digital Ground.

Positive Analog Supply

Analog Ground

18

17

VA+ - The positive analog supply.

AGND - Analog ground.

PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is

tripped, a Low-Supply Detect (LSD) event is set in the status register.

Power Fail Monitor

21

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3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

Positive Digital Power Supply

Positive Analog Power Supply

Voltage Reference

Symbol

VD+

Min

3.135

4.75

-

Typ

5.0

2.5

-

Max

Unit

V

5.25

-

VA+

V

VREFIN

V

Specified Temperature Range

T

-40

+85

°C

A

ANALOG CHARACTERISTICS

•

Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.

MCLK = 4.096 MHz.

Parameter

Symbol

Min

Typ

Max

Unit

Accuracy

Active Power

(Note 1)

All Gain Ranges

Input Range 0.1% - 100%

P

Active

-

±0.1

±0.2

-

%

Average Reactive Power

(Note 1 and 2)

All Gain Ranges

Input Range 0.1% - 100%

Q

Avg

Power Factor

(Note 1 and 2)

All Gain Ranges

Input Range 1.0% - 100%

PF

-

±0.2

±0.27

-

%

Input Range 0.1% - 1.0%

Current RMS

(Note 1)

All Gain Ranges

Input Range 1.0% - 100%

Input Range 0.1% - 1.0%

%

I

-

±0.1

±0.17

-

RMS

Voltage RMS

(Note 1)

All Gain Ranges

Input Range 5% - 100%

V

RMS

-

±0.1

-

%

Analog Inputs (All Channels)

Common Mode Rejection

(DC, 50, 60 Hz)

CMRR

80

-

dB

V

Common Mode + Signal

-0.25

VA+

Analog Inputs (Current Channels)

Differential Input Range

[(IIN+) - (IIN-)]

(Gain = 10)

(Gain = 50)

-

500

100

-

mV

P-P

IIN

Total Harmonic Distortion

(Gain = 50)

THD

80

-

94

-115

27

-

dB

Crosstalk with Voltage Channel at Full Scale

Input Capacitance

(50, 60 Hz)

dB

pF

kΩ

IC

-

Effective Input Impedance

Noise (Referred to Input)

EII

30

(Gain = 10)

(Gain = 50)

-

22.5

4.5

µV

rms

N

I

µV

Offset Drift (Without the High Pass Filter)

Gain Error

OD

GE

-

4.0

-

µV/°C

%

(Note 3)

±0.4

Notes: 1. Applies when the HPF option is enabled.

2. Applies when the line frequency is equal to the product of the Output Word Rate (OWR) and the value

^{of epsilon (}ε).

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ANALOG CHARACTERISTICS (Continued)

Parameter

Analog Inputs (Voltage Channel)

Differential Input Range

Symbol

Min

Typ

Max

Unit

mV

[(VIN+) - (VIN-)]

VIN

-

500

-

P-P

Total Harmonic Distortion

Crosstalk with Current Channel at Full Scale

Input Capacitance

THD

65

-

75

-70

2.0

-

dB

(50, 60 Hz)

-

All Gain Ranges

IC

-

pF

Effective Input Impedance

Noise (Referred to Input)

EII

2

-

MΩ

N

-

140

µV

V

rms

Offset Drift (Without the High Pass Filter)

Gain Error

OD

GE

-

16.0

±3.0

-

µV/°C

%

(Note 3)

Temperature Channel

Temperature Accuracy

T

-

±5

-

°C

Power Supplies

Power Supply Currents (Active State)

I_A+

PSCA

PSCD

-

1.3

2.9

1.7

-

mA

I_D+(VA+ = VD+ = 5 V)

I

_D+(VA+ = 5 V, VD+ = 3.3 V)

Power Consumption

(Note 4)

Active State (VA+ = VD+ = 5 V)

Active State (VA+ = 5 V, VD+ = 3.3 V)

-

33

20

7

36

23

-

mW

uW

PC

Stand-by State

Sleep State

10

-

Power Supply Rejection Ratio (50, 60 Hz)

(Note 5)

Voltage Channel

48

68

60

55

75

65

-

dB

PSRR

Current Channel (Gain = 50x)

Current Channel (Gain = 10x)

PFMON Low-voltage Trigger Threshold

(Note 6)

(Note 7)

PMLO

PMHI

2.3

-

2.45

2.55

-

V

PFMON High-voltage Power-on Trip Point

2.7

Notes: 3. Applies before system calibration.

4. All outputs unloaded. All inputs CMOS level.

5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV

(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The

“+” and “-” input pins of both input channels are shorted to AGND. The CS5464 is then commanded to

continuous conversion acquisition mode, and digital output data is collected for the channel under test.

The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted

into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied

at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined

as Veq. PSRR is (in dB)^:

150

V_eq

---------

PSRR = 20 ⋅ log

6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1.

7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on

PFMON at which the LSD bit can be permanently reset back to 0.

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VOLTAGE REFERENCE

Parameter

Symbol

Min

Typ

Max

Unit

Reference Output

Output Voltage

VREFOUT

+2.4

-

+2.5

25

+2.6

60

V

Temperature Coefficient

(Note 8) TC

ppm/°C

VREF

R

Load Regulation

(Note 9)

∆V

-

6

10

mV

Reference Input

Input Voltage Range

Input Capacitance

Input CVF Current

VREFIN

+2.4

+2.5

4

+2.6

V

-

pF

nA

100

Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the

following formula is used to calculate the VREFOUT Temperature Coefficient:.

(

1.0 x 10⁶

(VREFOUTMAX - VREFOUTMIN)

VREFOUT^AVG

1

TC_VREF

=

(

T_A^MAX- T_A^MIN

9. Specified at maximum recommended output of 1 µA, source or sink.

DIGITAL CHARACTERISTICS

•

Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

MCLK = 4.096 MHz.

Parameter

Master Clock Characteristics

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

Master Clock Duty Cycle

CPUCLK Duty Cycle

Internal Gate Oscillator (Note 11) MCLK

(Note 12 and 13)

2.5

40

4.096

20

60

MHz

%

-

%

Filter Characteristics

Phase Compensation Range

Input Sampling Rate

(Voltage Channel, 60 Hz)

DCLK = MCLK/K

(Both Channels) OWR

-3 dB

-2.8

-

+2.8

°

Hz

-

DCLK/8

-

Digital Filter Output Word Rate

High-pass Filter Corner Frequency

DCLK/1024

-

Hz

-

0.5

-

Hz

Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR

25

100

%F.S.

µs

Channel-to-channel Time-shift Error

Input/Output Characteristics

High-level Input Voltage

(Note 15)

1.0

All Pins Except XIN and SCLK and RESET

0.6 VD+

(VD+) - 0.5

0.8 VD+

-

V

IH

XIN

SCLK and RESET

Low-level Input Voltage (VD = 5 V)

All Pins Except XIN and SCLK and RESET

-

0.8

1.5

0.2 VD+

V

IL

XIN

SCLK and RESET

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CS5467

Parameter

Symbol

Min

Typ

Max

Unit

Low-level Input Voltage (VD = 3.3 V)

All Pins Except XIN and SCLK and RESET

-

0.48

0.3

0.2 VD+

V

IL

XIN

SCLK and RESET

High-level Output Voltage

Low-level Output Voltage

I_out= +5 mA

V

(VD+) - 1.0

-

V

OH

I_out= -5 mA (VD = +5V)

V

I

-

0.4

V

OL

I_out= -2.5 mA (VD = +3.3V)

Input Leakage Current

(Note 16)

-

±1

-

±10

-

µA

pF

in

3-state Leakage Current

Digital Output Pin Capacitance

I

OZ

C

5

out

Notes: 10. All measurements performed under static conditions.

11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is

used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between

2.5 MHz - 5.0 MHz.

12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.

13. The frequency of CPUCLK is equal to MCLK.

14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is

limited by the full-scale signal applied to the channel input.

15. Configuration Register bits PC[6:0] are set to “0000000”.

16. The MODE pin is pulled low by an internal resistor.

10

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CS5467

SWITCHING CHARACTERISTICS

•

Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Parameter

Symbol

Min

Typ

Max

Unit

Rise Times

(Note 17)

t

-

50

1.0

-

µs

ns

rise

Any Digital Output

Fall Times

(Note 17)

t

-

50

1.0

-

µs

ns

fall

ost

Start-up

Oscillator Start-up Time

XTAL = 4.096 MHz (Note 18)

t

-

60

-

ms

Serial Port Timing

Serial Clock Frequency

Serial Clock

SCLK

-

2

MHz

Pulse Width High

Pulse Width Low

t

200

-

ns

1

2

SDI Timing

CS Falling to SCLK Rising

t

50

-

ns

3

4

5

Data Set-up Time Prior to SCLK Rising

Data Hold Time After SCLK Rising

100

SDO Timing

CS Falling to SDO Driving

t

-

20

50

ns

6

7

8

SCLK Falling to New Data Bit (hold time)

CS Rising to SDO Hi-Z

Auto-Boot Timing

Serial Clock

Pulse Width Low

Pulse Width High

t

8

MCLK

9

t

10

MODE setup time to RESET Rising

RESET rising to CS falling

CS falling to SCLK rising

t

50

48

ns

MCLK

ns

11

12

13

14

15

16

t

100

8

SCLK falling to CS rising

16

CS rising to driving MODE low (to end auto-boot sequence)

SDO guaranteed setup time to SCLK rising

50

100

ns

Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

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CS5467

t₃

C S

t₁

t₂

SC LK

SD I

t₄

t₅

Com m and Tim e 8 S C LK s

High B yte

M id B yte

Low B yte

SDI Write Timing (Not to Scale)

CS

t₈

High Byte

Mid Byte

Low Byte

t₆

SDO

SCLK

SDI

UNKNOW N

t₁

t₇

t₂

Command Time 8 SCLKs

SYNC0 or SYNC1

Command

SYNC0 or SYNC1

Command

SYNC0 or SYNC1

Command

SDO Read Timing (Not to Scale)

t_{1 1}

t_{1 5}

M O D E

(IN P U T )

R E S E T

(IN P U T )

t_{1 4}

t_{1 2}

t₇

t_{1 3}

C S

(O U T P U T )

S C L K

(O U T P U T )

t_{1 0}

t_{1 6}

t₉

t₄

S D O

(O U T P U T )

t₅

L a s t 8

B its

S D I

(IN P U T )

D a ta fro m E E P R O M

Auto-boot Sequence Timing (Not to Scale)

Figure 1. CS5464 Read and Write Timing Diagrams

12

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CS5467

SWITCHING CHARACTERISTICS (Continued)

Parameter

Symbol

Min

Typ

Max

Unit

E1, E2, and E3 Timing

(Note 19 and 20)

Period

t

250

244

6

-

µs

period

Pulse Width

t

pw

Rising Edge to Falling Edge

t

3

E2 Setup to E1 and/or E3 Falling Edge

E1 Falling Edge to E3 Falling Edge

t

1.5

248

4

t

5

Notes: 19. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to

5.5 Energy Pulse Output on page 18 for more information on pulse output pins.

20. Timing is proportional to the frequency of MCLK.

t_period

t₃

t_pw

E1

t₄

E2

E3

t_period

t₃

t₅

t₄

t_pw

t₅

Figure 2. Timing Diagram for E1, E2, and E3

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Parameter

Symbol

Min

Typ

Max

Unit

DC Power Supplies

(Notes 21 and 22)

Positive Digital

Positive Analog

VD+

VA+

-0.3

-

+6.0

V

Input Current, Any Pin Except Supplies

(Notes 23, 24, 25)

I

-

±10

100

mA

IN

Output Current, Any Pin Except VREFOUT

I

OUT

Power Dissipation

(Note 26)

PD

-

500

mW

V

Analog Input Voltage

All Analog Pins

V

- 0.3

(VA+) + 0.3

INA

Digital Input Voltage

All Digital Pins

-0.3

-40

-65

-

(VD+) + 0.3

V

IND

Ambient Operating Temperature

Storage Temperature

T

85

°C

A

T

150

stg

Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)] ≤ + 6.0 V.

22. VD+ and AGND must satisfy [(VD+) - (AGND)] ≤ + 6.0 V.

23. Applies to all pins including continuous over-voltage conditions at the analog input pins.

24. Transient current of up to 100 mA will not cause SCR latch-up.

25. Maximum DC input current for a power supply pin is ±50 mA.

26. Total power dissipation, including all input currents and output currents.

DS714A1

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CS5467

V

V_DCoff

gn

X

APF

+

2nd Order

∆Σ

Modulator

V

+

DELAY

REG

3

VOLTAGE

x10

IIR

HPF

X

Σ

SINC

V_Q

Digital Filter

SYS_Gain

X

IIR

Q

ε

X

Control Register

VHPF IHPF

...

PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]

3 2 1 0

2322

6

5

2π

Operational Modes Register

X

P

7

4th Order

+

DELAY

REG

3

SINC

IIR

∆Σ

X

HPF

APF

X

Σ

CURRENT PGA

REGISTER NAMES INDICATED

IN SHADED AREAS.

I

Modulator

+

SYS_Gain

Digital Filter

I

gn

I_DCoff

Figure 3. Data Measurement Flow Diagram

4. THEORY OF OPERATION

The CS5467 is a four-channel analog-to-digital convert-

er (ADC) followed by a computation engine that per-

forms power calculations and energy-to-pulse

conversion. The data flow for the voltage and current

channel measurement and the power calculation algo-

rithms are depicted in Figures 3, 4, and 5.

gains of the programmable gain amplifier (PGA). The

amplified signals are sampled by a fourth-order

delta-sigma modulator for digitization. The converters

sample at a rate of MCLK/8. The over-sampling pro-

vides a wide dynamic range and simplified anti-alias fil-

ter design.

The CS5467 analog inputs are structured with two Cur-

rent channels and two Voltage channels, and are opti-

mized to simplify interfacing to various sensing

elements. As shown in Figures 3 and 4, the current and

voltage channels are fully independent.

4.1 Digital Filters

The decimating digital filters on the four channels are

3

Sinc filters followed by 3rd-order IIR filters. The sin-

gle-bit data is passed to the low-pass decimation filter

and output at a fixed word rate. The output word is

passed to an IIR filter to compensate for the magnitude

roll off of the low-pass filtering operation.

The voltage-sensing elements introduces a voltage

waveform on the two voltage channel inputs VIN± and

VIN2± , which is subject to a gain of 10x. A second-order

delta-sigma modulator samples the amplified signal for

digitization.

An optional digital high-pass filter (HPF in Figures 3 and

4) removes any DC component from the selected signal

path. By removing the DC component from the voltage

and/or the current channel, any DC content will also be

removed from the calculated active power as well. With

both HPFs enabled the DC component will be removed

Simultaneously, the current-sensing elements introduce

a voltage waveform on the two current channel inputs

IIN± and IIN2± , which is subject to the two selectable

V2

gn

V2_dcoff

APF

HHPPFF

+

2nd Order

∆Σ

Modulator

V2

+

DELAY

REG

3

IIR

X

VOLTAGE 2

X10

X

Σ

SINC

V2_Q

Q2

SYS_Gain

Digital Filter

IIR

X

ε

Control Register

VHPF IHPF

...

PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]

...

3

2 1 0

2322

π

8

7

X

P2

Operational Modes Register

7

4th Order

+

DELAY

REG

3

SINC

IIR

∆Σ

HPF

APF

X

CURRENT 2

PGA

Σ

I2

Modulator

+

REGISTER NAMES INDICATED

IN SHADED AREAS.

SYS_Gain

I2

gn

I2_dcoff

Digital Filter

Figure 4. Data Measurement Flow Diagram

14

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CS5467

V_acoff

(V2_acoff

)

+

N

+

V_RMS

(V2_RMS

X

S (S2)

V (V2)

I (I2)

Σ

÷

N

)

√

Σ

I_acoff

(I2_acoff

+

Q_TRIG

(Q2_TRIG

X

Σ

)

√

-

+

N

+

I_RMS

(I2_RMS

PF

(PF2)

Inverse

X

Σ

N

)

Σ

E1

E2

E3

P_off(P2_off

+

)

PulseRateE

X

Energy-to-pulse

N

P_ACTIVE

(P2_ACTIVE

P (P2)

Q (Q2)

÷

Σ

N

)

+

Σ

X

N

Q_AVG

(Q2_AVG

REGISTER NAMES (CHANNEL 2 REGISTER

NAMES) INDICATED IN SHADED AREAS.

)

Σ

Figure 5. Power Calculation Flow

from the calculated V

parent power.

and I

, as well as the ap-

RMS

4.3 Power Measurements

RMS

The instantaneous voltage and current samples are

multiplied to obtain the instantaneous power (see Fig-

ure 3 and 4). The product is then averaged over N con-

versions to compute active power. The average active

power measured on channels 1 and 2 is used to drive

energy pulse output E1. Energy output E2 is config-

urable and can provide an energy sign or a pulse output

that is proportional to the average apparent power mea-

sured on channels 1 and 2. Energy output E3 provides

a pulse output that is proportional to the average reac-

tive power or the average apparent power measured on

channels 1 and 2. Output E3 can also be set to indicate

the PFMON comparator output or to indicate the sign of

the voltage applied to the voltage channel.

When the optional HPF in either channel is disabled, an

all-pass filter (APF) in the complementary channel is im-

plemented. The APF has an amplitude response that is

flat within the channel bandwidth and is used for match-

ing phase in systems where only one channel’s HPF is

engaged.

4.2 Voltage and Current Measurements

The digital filter output word is subject to a DC-offset ad-

justment and a gain calibration (See Section 7. System

Calibration on page 39). The calibrated measurement is

available by reading the instantaneous voltage and cur-

rent registers.

The Root Mean Square (RMS in Figure 5) calculations

are performed on N instantaneous voltage and current

samples, Vn and In, respectively (where N is the cycle

count), using the formula:

The apparent power (S, S2) is the combination of the

active power and reactive power, without reference to

an impedance phase angle, and is calculated by the

CS5467 using the following formula:

S = V_RMS× I_RMS

Power Factor (PF, PF2) is the active power (P

,

Active

N – 1

P2

) divided by the apparent power (S, S2)

Active

I

∑

n

I

=

P_Active

RMS

n = 0

--------------------

N

------------------

PF =

S

The sign of the power factor is determined by the active

power.

and likewise for V_RMS, using Vn. I_RMSand V_RMSare ac-

cessible by register reads, which are updated once ev-

ery cycle count (referred to as a computational cycle).

DS714A1

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CS5467

The CS5467 calculates the reactive power (Q

,

Trig

Q2 ) utilizing trigonometric identities, using the formu-

Trig

la

N

Q_Trig

=

S²– P_A²_ctive

Q

∑

N

n

=

n = 1

Q_Avg

------------------------

The average reactive power calculation (Q , Q2 ) is

Avg

generated by averaging the voltage and multiplying that

value by the current measurement with a 90° phase dif-

ference between the two. The 90° phase shift is realized

by applying an IIR digital filter in the voltage channel to

obtain quadrature voltage (see Figure 3 and 4). This fil-

ter will give exactly -90° phase shift across all frequen-

^{cies, and utilizes epsilon (}ε) to achieve unity gain at the

line frequency.

The peak current (I

, I2

) and peak voltage (V

,

peak

V2

) are the instantaneous current and voltage, re-

peak

spectively, with the greatest magnitude detected during

the previous computation cycle. Active, apparent, reac-

tive, and fundamental power are updated every compu-

tation cycle.

4.4 Linearity Performance

The instantaneous quadrature voltage (V , V2 ) and

Q

current (I, I2) samples are multiplied to obtain the in-

stantaneous quadrature power (Q, Q2). The product is

then averaged over N conversions, utilizing the formula

The linearity of the V

, I

, active, reactive, and

RMS RMS

power-factor power measurements (before calibration)

will be within ±0.1% of reading over the ranges speci-

fied, with respect to the input voltage levels required to

cause full-scale readings in the I

and V

regis-

RMS

ters. Refer to Accuracy Specifications on page 7.

Until the CS5467 is calibrated, the accuracy of the

CS5467 (with respect to a reference line-voltage and

line-current level on the power mains) is not guaranteed

16

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CS5467

5. FUNCTIONAL DESCRIPTION

5.1 Analog Inputs

The CS5467 is equipped with four fully differential input

channels. The inputs VIN± ± VIN2± ± IIN± , and IIN2± are

designated as the voltage, voltage 2, current, and cur-

rent 2 channel inputs, respectively. The full-scale differ-

ential input voltage for the current and voltage channel

The Current Gain Register also facilitates an additional

programmable gain of up to 4x. If an additional gain is

applied to the voltage and/or current channel, the maxi-

mum input range should be adjusted accordingly.

5.2 IIR Filters

The current and voltage channels are equipped with a

3rd-order IIR filter, that is used to compensate for the

magnitude roll off of the low-pass decimation filter.

is ± 250 mV .

P

5.1.1 Voltage Channel Input

The output of the line voltage resistive divider or trans-

former is connected to the VIN+ (VIN2+) and VIN-

(VIN2-) input pins of the CS5467. The voltage channels

are equipped with a 10x fixed-gain amplifier. The

full-scale signal level that can be applied to the voltage

channel is ± 250 mV. If the input signal is a sine wave,

the maximum RMS voltage at a gain 10x is:

5.3 High-pass Filters

By removing the offset from either channel, no error

component will be generated at DC when computing the

active power. By removing the offset from both chan-

nels, no error component will be generated at DC when

computing V

, I

, and apparent power. Operation-

RMS RMS

al Mode Register bits VHPF, VHPF2, IHPF and IHPF2

activate the HPF in the voltage and current channel, re-

spectively. When a high-pass filter is active in only one

channel, an all-pass filter (APF) is applied to the com-

panion channel. The APF has an amplitude response

that is flat within the channel bandwidth and is used for

matching phase in systems where only one HPF is en-

gaged.

250mV

P

--------------------

≅ 176.78mV

RMS

2

which is approximately 70.7% of maximum peak volt-

age. The voltage channel is also equipped with a Volt-

age Gain Register, allowing for an additional

programmable gain of up to 4x.

5.1.2 Current Channel Inputs

5.4 Performing Measurements

The output of the current-sense resistor or transformer

is connected to the IIN+ (IIN2+) and IIN- (IIN2-) input

pins of the CS5467. To accommodate different cur-

rent-sensing elements, the current channel incorpo-

rates a programmable gain amplifier (PGA) with two

programmable input gains. Configuration Register bit

Igain (I2gain) defines the two gain selections and corre-

sponding maximum input signal level.

The CS5467 performs measurements of instantaneous

voltage (V ) and current (I ), and calculates instanta-

n

neous power (P ) at an output word rate (OWR) of

n

(MCLK ⁄ K)

----------------------------

OWR =

1024

where K is the value of the clock divider selected in the

Configuration Register by bits K[3:0]. Note that a value

of K[3:0] = 0000 results in a clock divider setting of 16,

rather than zero.

Igain, I2gain

Maximum Input

Gain

0

1

±250 mV

±50 mV

10x

50x

The RMS voltage (V

, V2

), RMS current (I

,

RMS

I2

), and active power (P

, P2

) are comput-

RMS

active

Table 1. Current Channel PGA Setting

ed using N instantaneous samples of V , I , and P re-

n n n

spectively, where N is the value in the Cycle Count

Register and is referred to as a “computation cycle”. The

For example, if Igain=0 (I2gain=0), current channel 1(2)

PGA gain is set to 10x. If the input signals are pure si-

nusoids with zero phase shift, the maximum peak differ-

ential signal on the current or voltage channel is

apparent power (S, S2) is the product of V

and I

.

RMS

A computation cycle is derived from the master clock

(MCLK), with frequency: Under default conditions and

± 250 mV . The input signal levels are approximately

P

70.7% of maximum peak voltage and produce a

full-scale energy pulse registration equal to 50% of ab-

solute maximum energy registration. This will be dis-

cussed further in See Section 5.5 Energy Pulse Output

on page 18.

OWR

N

---------------

Computation Cycle =

with K = 1, N = 4000, and MCLK = 4.096 MHz – the

OWR = 4000 and the Computation Cycle = 1 Hz.

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CS5467

All measurements are available as a percentage of full

scale. The format for signed registers is a two’s comple-

ment, normalized value between -1 and +1. The format

for unsigned registers is a normalized value between 0

and 1. A register value of

The E1 pulse output is designed to indicate the average

active energy measured on channels 1 and 2. The E2

pin can be used to register average apparent energy

measured on channels 1 and 2 or to indicate the sign of

energy. Table 2 defines the pulse output mode, which is

controlled by bit E2MODE in the Operational Mode Reg-

ister.

23

(2 – 1)

23

2

-----------------------

= 0.99999988

E2MODE

E2 Output Mode

Sign of Energy

0

1

represents the maximum possible value.

Apparent Energy

At each instantaneous measurement, the CRDY bit will

be set in the Status Register, and the INT pin will be-

come active if the CRDY bit is unmasked in the Mask

Register. At the end of each computation cycle, the

DRDY bit will be set in the Status Register, and the INT

pin will become active if the DRDY bit is unmasked in

the Mask Register. When these bits are asserted, they

must be cleared before they can be asserted again.

Table 2. E2 Pin Configuration

The E3 pin can be set to register average reactive ener-

gy measured on channels 1 and 2 (default), PFMON,

voltage channel sign, or average apparent energy mea-

sured on channels 1 and 2. Table 3 defines the pulse

output format, which is controlled by bits E3MODE[1:0]

in the Operational Mode Register.

If the Cycle Count Register (N) is set to 1, all output cal-

culations are instantaneous, and DRDY, like CRDY, will

indicate when instantaneous measurements are fin-

ished. Some calculations are inhibited when the cycle

count is less than 2.

E3MODE1 E3MODE0

E3 OutPut Mode

Reactive Energy

PFMON

0

1

0

1

0

1

Voltage Channel Sign

Apparent Energy

^{Epsilon (}ε) is the ratio of the input line frequency (f ) to

i

the sample frequency (f ) of the ADC.

s

Table 3. E3 Pin Configuration

ε = f_i⁄ f_s

The pulse output frequencies of E1, E2, and E3 are di-

rectly proportional to the power calculated from the input

signals. The value contained in the PulseRateE Regis-

ter is the ratio of the frequency of energy-output pulses

to the number of samples, at full scale, which defines

the average frequency for the output pulses. The pulse

where f = MCLK / (K x 1024). With MCLK = 4.096 MHz

s

and clock divider K = 1, f = 4000 Hz. For the two

s

most-common line frequencies, 50 Hz and 60 Hz

ε = 50 Hz ⁄ 4000 Hz = 0.0125

width, t in Figure 2, is an integer multiple of MCLK cy-

pw

cles approximately equal to:

and

1

------------------------------------

t

(sec) ≅

pw

( MCLK/K ) / 1024

ε = 60 Hz ⁄ 4000 Hz = 0.015

respectively. Epsilon is used to set the gain of the 90°

phase shift (IIR) filter for the average reactive power cal-

culation.

If MCLK = 4.096 MHz and K = 1 then t_pw≅ 0.25 ms.

5.5.1 Active Energy

The E1 pin produces active-low pulses with an output

frequency proportional to the average active power

measured on channels 1 and 2. The E2 pin is the ener-

gy direction indicator. Positive energy is represented by

E1 pin falling while the E2 is high. Negative energy is

represented by the E1 pin falling while the E2 is low.

The E1 and E2 switching characteristics are specified in

Figure 2. Timing Diagram for E1, E2, and E3 on page

13.

5.5 Energy Pulse Output

The CS5467 provides three output pins for energy reg-

istration. By default, E1 is used to register average ac-

tive energy measured on channels 1 and 2, E3 is used

to register average reactive energy measured on chan-

nels 1 and 2, and E2 indicates the sign of both active

and reactive energy. (See Figure 2. Timing Diagram for

E1, E2, and E3 on page 13.)

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Figure 6 illustrates the pulse output format with positive

active energy and negative reactive energy.

FREQ = [(S + S2) ⁄ 2] × PulseRate

S

where

E1

E2

E3

VIN(2) × V(2)gain × IIN(2) × I(2)gain

-----------------------------------------------------------------------------------------------------------

^S(²) =

2

VREFIN

FREQ = Average frequency of apparent energy E2 and/or E3 pulses [Hz]

S

VIN(2) = rms voltage across VIN(2)+ and VIN(2)- [V]

V(2)gain = Voltage channel gain

Figure 6. Active and Reactive energy pulse outputs

IIN(2) = rms voltage across IIN(2)+ and IIN(2)- [V]

I(2)gain = Current channel gain

PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]

VREFIN = Voltage at VREFIN pin [V]

The pulse output frequency of E1 is directly proportional

to the active power calculated from the input signals. To

calculate the output frequency of E1, the following trans-

fer function can be utilized:

With MCLK = 4.096 MHz and default settings, the puls-

es will have an average frequency equal to the frequen-

cy specified by PulseRateE when the input signals

applied to the voltage and current channels cause

full-scale readings in the instantaneous voltage and cur-

rent registers. The maximum pulse frequency from the

E2 (and/or E3) pin is (MCLK/K)/2048. The E2 (and/or

E3) pin outputs apparent energy, but has no energy di-

rection indicator.

FREQ = [(P

+ P2

) ⁄ 2] × PulseRate

Active

P

where

VIN(2) × V(2)gain × IIN(2) × I(2)gain × PF(2)

-----------------------------------------------------------------------------------------------------------------------------------

^P(²)_Active

=

2

VREFIN

FREQ = Average frequency of active energy E1 pulses [Hz]

P

VIN(2) = rms voltage across VIN(2)+ and VIN(2)- [V]

V(2)gain = Voltage channel gain

IIN(2) = rms voltage across IIN(2)+ and IIN(2)- [V]

I(2)gain = Current channel gain

PF(2) = Power Factor

PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]

VREFIN = Voltage at VREFIN pin [V]

5.5.3 Reactive Energy Mode

Reactive energy pulses are output on pin E3 by setting

bit E3MODE[1:0] = 0 (default) in the Operational Mode

Register. Positive reactive energy is registered by E3

falling when E2 is high. Negative reactive energy is reg-

istered by E3 falling when E2 is low. Figure 6 on

page 19 illustrates the pulse output format with negative

reactive energy output on pin E3 and the sign of the en-

ergy on E2. The E3 and E2 pulse output switching char-

acteristics are specified in Figure 2 on page 13.

With MCLK = 4.096 MHz, PF = 1, and default settings,

the pulses will have an average frequency equal to the

frequency specified by PulseRateE when the input sig-

nals applied to the voltage and current channels cause

full-scale readings in the instantaneous voltage and cur-

rent registers. The maximum pulse frequency from the

E1 pin is (MCLK/K)/2048.

The pulse output frequency of E3 is directly proportional

to the reactive power calculated from the input signals.

To calculate the output frequency on E3, the following

transfer function can be utilized:

5.5.2 Apparent Energy Mode

Pin E2 outputs apparent energy pulses when the Oper-

ational Mode Register bit E2MODE = 1. Pin E3 outputs

apparent energy pulses when the Operational Mode

Register bits E3MODE[1:0] = 3 (11b). Figure 7 illus-

trates the pulse output format with apparent energy on

E2 (E2MODE = 1 and E3MODE[1:0] = 0)

FREQ = [(Q

+ Q2

) ⁄ 2] × PulseRate

Avg

Q

where

VIN(2) × V(2)gain × IIN(2) × I(2)gain × PQ(2)

------------------------------------------------------------------------------------------------------------------------------------

Q(2)

=

Avg

2

VREFIN

E1

E2

E3

FREQ = Average frequency of reactive energy E3 pulses [Hz]

Q

VIN(2) = rms voltage across VIN(2)+ and VIN(2)- [V]

V(2)gain = Voltage channel gain

IIN(2) = rms voltage across IIN(2)+ and IIN(2)- [V]

I(2)gain = Current channel gain

Figure 7. Apparent energy pulse outputs

2

PQ = 1 – PF

PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]

VREFIN = Voltage at VREFIN pin [V]

The pulse output frequency of E2 (and/or E3) is directly

proportional to the apparent power calculated from the

input signals. Since apparent power is without reference

to an impedance phase angle, the following transfer

function can be utilized to calculate the output frequency

on E2 (and/or E3).

With MCLK = 4.096 MHz, PF = 0 and default settings,

the pulses will have an average frequency equal to the

frequency specified by PulseRateE when the input sig-

nals applied to the voltage and current channels cause

full-scale readings in the instantaneous voltage and cur-

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rent registers. The maximum pulse frequency from the

E1 pin is (MCLK/K)/2048.

rent, respectively. Voltage and current sag duration is

specified in terms of ADC cycles.

5.5.4 Voltage Channel Sign Mode

Setting bits E3MODE[1:0] = 2 (10b) in the Operational

Mode Register outputs the sign of the voltage channel

on pin E3. Figure 8 illustrates the output format with volt-

age channel sign on E3

E1

E2

E3

Level

Figure 8. Voltage Channel Sign Pulse outputs

Output pin E3 is high when the line voltage is positive

and pin E3 is low when the line voltage is negative.

Duration

Figure 10. Sag and Fault Detect

5.5.5 PFMON Output Mode

Setting bit E3MODE[1:0] = 1 (01b) in the Operational

Mode Register outputs the state of the PFMON compar-

ator on pin E3. Figure 9 illustrates the output format with

PFMON on E3

5.7 On-chip Temperature Sensor

The on-chip temperature sensor is designed to assist in

characterizing the measurement element over a desired

temperature range. Once a temperature characteriza-

tion is performed, the temperature sensor can be uti-

lized to assist in compensating for temperature drift.

E1

E2

E3

Above PFMON Threshold

Below PFMON Threshold

Temperature measurements are performed when a one

is written to the Temperature Measurement (T

) reg-

Figure 9. PFMON output to pin E3

meas

ister and stored in the Temperature Register. The Tem-

perature Register (T) default is Celsius scale (°C). The

When PFMON is greater than the threshold, pin E3 is

high and when PFMON is less than the threshold pin E3

is low.

Temperature Gain Register (T

) and Temperature

gain

Offset Register (T ) are constant values allowing for

off

temperature scale conversions.

5.6 Sag and Fault Detect Feature

The temperature update rate is a function of the number

of ADC samples. With MCLK = 4.096 MHz and K = 1

the update rate is:

Status bit VSAG (V2SAG) and IFAULT (I2FAULT) in the

Status Register, indicates a sag occurred in the power

line voltage (voltage 2) and current (current 2), respec-

tively. For a sag condition to be identified, the absolute

value of the instantaneous voltage or current must be

less than the sag level for more than half of the sag du-

ration (see Figure 10).

2240 samples

---------------------------------------

= 0.56 sec

(^MCLK⁄ ^K) ⁄ 1024

The Cycle Count Register (N) must be set to a value

greater than one. Status bit TUP in the Status Register,

indicates when the Temperature Register is updated.

To activate voltage sag detection, a voltage sag level

must be specified in the Voltage Sag Level Register

(VSAGlevel, V2SAGlevel), and a voltage sag duration

must be specified in the Voltage Sag Duration Register

(VSAGduration, V2SAGduration). To activate current fault

detection, a current sag level must be specified in the

Current Fault Level Register (ISAGlevel, I2SAGlevel), and

a current sag duration must be specified in the Current

Fault Duration Register (ISAGduration, I2SAGduration).

The voltage and current sag levels are specified as the

average of the absolute instantaneous voltage and cur-

The Temperature Offset Register sets the zero-degree

measurement. To improve temperature measurement

accuracy, the zero-degree offset may need to be adjust-

ed after the CS5467 is initialized. Temperature-offset

calibration is achieved by adjusting the Temperature

Offset Register (T ) by the differential temperature

off

(∆T) measured from a calibrated digital thermometer

and the CS5467 temperature sensor. A one-degree ad-

justment to the Temperature Register (T) is achieved by

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-4

adding 2.737649x10 to the Temperature Offset Regis-

ter (T ). Therefore,

5.10 Power-down States

off

The CS5467 has two power-down states, Stand-by and

Sleep. In the stand-by state all circuitry except the volt-

age reference and crystal oscillator is turned off. To re-

turn the device to the active state, a power-up command

is sent to the device.

–4

T

= T_off+ (∆T × 2.737649 ⋅ 10

)

off

if T = -0.094488 and ∆T = -2.0 (°C), then

off

T

= (– 0.094488 + (–2.0 × 2.737649 ⋅ 10^–4)) = –0.09504

off

In Sleep state, all circuitry except the instruction decod-

er is turned off. When the power-up command is sent to

the device, a system initialization is performed (See

Section 5.9 System Initialization on page 21).

or 0xF3D5BB (2’s compliment notation) is stored in the

Temperature Offset Register (T ).

off

To convert the Temperature Register (T) from a Celsius

5.11 Oscillator Characteristics

scale (°C) to a Fahrenheit scale (°F) utilize the formula

XIN and XOUT are the input and output of an inverting

amplifier configured as an on-chip oscillator, as shown

in Figure 11. The oscillator circuit is designed to work

with a quartz crystal. To reduce circuit cost, two load ca-

pacitors C1 and C2 are integrated in the device, from

XIN to DGND, and XOUT to DGND. PCB trace lengths

should be minimized to reduce stray capacitance. To

drive the device from an external clock source, XOUT

should be left unconnected while XIN is driven by the

external circuitry. There is an amplifier between XIN and

the digital section which provides CMOS level signals.

This amplifier works with sinusoidal inputs so there are

no problems with slow edge times.

9

5

o

(

)

F = -- C+ 17.7778

Applying the above relationship to the CS5461A tem-

perature measurement algorithm

–4

o

9

--

⎛

⎝

⎞

⎛

⎝

⎞

⎠

T 〈 F〉 =

×T

T 〈 C〉 +

T

+ (17.7778 × 2.737649 ⋅ 10

)

⎠

gain

off

5

If T = -0.09504 and T

= 26.443 for a Celsius scale,

gain

the modified values are T = -0.09017 (0xF47550) and

off

T

= 47.6 (0x5F3333) for a Fahrenheit scale.

gain

The CS5467 can be driven by an external oscillator

ranging from 2.5 to 20 MHz, but the K divider value must

be set such that the internal MCLK will run somewhere

between 2.5 MHz and 5 MHz. The K divider value is set

with the K[3:0] bits in the Configuration Register. As an

example, if XIN = MCLK = 15 MHz, and K is set to 5,

DCLK will equal 3 MHz, which is a valid value for DCLK.

5.8 Voltage Reference

The CS5467 is specified for operation with a +2.5 V ref-

erence between the VREFIN and AGND pins. To utilize

the on-chip 2.5 V reference, connect the VREFOUT pin

to the VREFIN pin of the device. The VREFIN can be

used to connect external filtering and/or references.

5.12 Event Handler

The INT pin is used to indicate that an internal error or

event has taken place in the CS5467. Writing a logic 1

5.9 System Initialization

Upon powering up, the digital circuitry is held in reset

until the analog voltage reaches 4.0 V. At that time, an

eight-XIN-clock-period delay is enabled to allow the os-

cillator to stabilize. The CS5467 will then initialize.

XOUT

A hardware reset is initiated when the RESET pin is as-

serted with a minimum pulse width of 50 ns. The RE-

SET signal is asynchronous, with a Schmitt-trigger

input. Once the RESET pin is de-asserted, an

C1

Oscillator

Circuit

eight-XIN-clock-period delay is enabled

.

XIN

A software reset is initiated by writing the command

0x80. After a hardware or software reset, the internal

registers (some of which drive output pins) will be reset

to their default values. Status bit DRDY in the Status

Register, indicates the CS5467 is in its active state and

ready to receive commands.

C2

DGND

C1 = C2 = 22 pF

Figure 11. Oscillator Connection

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to any bit in the Mask Register allows the corresponding

INTERRUPT HANDLER ROUTINE:

4) Read the Status Register.

5) Disable all interrupts.

bit in the Status Register to activate the INT pin. The in-

terrupt condition is cleared by writing a logic 1 to the bit

that has been set in the Status Register.

6) Branch to the proper interrupt service routine.

The behavior of the INT pin is controlled by the IMODE

and IINV bits of the Configuration Register.

7) Clear the Status Register by writing back the read

value in step 4.

IMODE

IINV

INT Pin

8) Re-enable interrupt

0

Active-low Level

9) Return from interrupt service routine.

This handshaking procedure ensures that any new in-

terrupts activated between steps 4 and 7 are not lost

(cleared) by step 7.

0

1

0

1

Active-high Level

Low Pulse

5.13 Serial Port Overview

High Pulse

The CS5467 incorporates a serial port transmit and re-

ceive buffer with a command decoder that interprets

one-byte (8-bit) commands as they are received. There

are four types of commands: instructions, synchroniz-

ing, register writes, and register reads (See Section

5.15 Commands on page 24).

Table 4. Interrupt Configuration

If the interrupt output signal format is set for either falling

or rising edge, the duration of the INT pulse will be at

least one DCLK cycle (DCLK = MCLK/K).

Instructions are one byte in length and will interrupt any

instruction currently executing. Instructions do not affect

register reads currently being transmitted.

5.12.1 Typical Interrupt Handler

The steps below show how interrupts can be handled.

INITIALIZATION:

Synchronizing commands are one byte in length and

only affect the serial interface. Synchronizing com-

mands do not affect operations currently in progress.

1) All Status bits are cleared by writing 0xFFFFFF to

the Status Register.

Register writes must be followed by three bytes of data.

Register reads can return up to four bytes of data.

2) The condition bits which will be used to generate

interrupts are set to logic 1 in the Mask Register.

Commands and data are transferred most-significant bit

(MSB) first. Figure 1 on page 12, defines the serial port

timing and required sequence necessary for writing to

and reading from the serial port receive and transmit

buffer, respectively. While reading data from the serial

port, commands and data can be written simultaneous-

ly. Starting a new register read command while data is

being read will terminate the current read in progress.

This is acceptable if the remainder of the current read

data is not needed. During data reads, the serial port re-

quires input data. If a new command and data is not

sent, SYNC0 or SYNC1 must be sent.

3) Enable interrupts.

5.13.1 Serial Port Interface

The serial port interface is a “4-wire” synchronous serial

communications interface. The interface is enabled to

start excepting SCLKs when CS (Chip Select) is assert-

ed (logic 0). SCLK (Serial bit-clock) is a Schmitt-trigger

input that is used to strobe the data on SDI (Serial Data

In) into the receive buffer and out of the transmit buffer

onto SDO (Serial Data Out).

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If the serial port interface becomes unsynchronized with

respect to the SCLK input, any attempt to clock valid

commands into the serial interface may result in unex-

pected operation. Therefor, the serial port interface

must be re-initialized by one of the following actions:

registers in another page, the Page Register (address

0x1F) must be written with the desired page number.

±xFFF

-

Drive the CS pin high, then low.

ROM

2048 Words

Pages

0x40 - 0x7F

Hardware Reset (drive RESET pin low for at

least 10 µs).

-

Issue the Serial Port Initialization Sequence,

which is 3 (or more) SYNC1 command bytes

(0xFF) followed by one SYNC0 command byte

(0xFE).

±x8±±

±x7FF

Hardware Registers*

Pages

0x20 - 0x3F

32 Pages

If a re-synchronization is necessary, it is best to re-ini-

tialize the part either by hardware or software reset

(command 0x80), as the state of the part may be un-

known.

±x4±±

±x3FF

Software Register*

Pages

0 - 0x1F

32 Pages

±x±±±

5.14 Register Paging

* Accessed using register read/write commands.

Read/write commands access one of the 32 registers

within a specified page. By default, Page = 0. To access

Figure 12. CS5467 Memory Map

Example:

Reading register 6 in page 3.

1. Write 3 to page register with command and data:

0x7E 0x00 0x00 0x03

2. Read register 6 with command:

0x0C 0xFF 0xFF 0xFF

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5.15 Commands

All commands are 8 bits in length. Any command byte value that is not listed in this section is invalid. Commands

that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other com-

mands (e.g., while reading data, a new command can be sent which can execute during the original read). All com-

mands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.

5.15.1 Start Conversions

B7

B6

B5

B4

B3

B2

B1

B0

1

0

C3

0

Initiates acquiring measurements and calculating results. The device has two modes of acquisition.

C3

Modes of acquisition/measurement

0 = Perform a single computation cycle

1 = Perform continuous computation cycles

5.15.2 SYNC0 and SYNC1

B7

B6

B5

B4

B3

B2

B1

B0

1

SYNC

The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands fol-

lowed by a SYNC0 command. The SYNC0 or SYNC1 commands can also be used as a NOP command.

SYNC

Designates calibration

0 = This command is the end of the serial port re-initialization sequence.

1 = This command is part of the serial port re-initialization sequence.

5.15.3 Power-down, Power-up, Halt and Software Reset

B7

B6

B5

B4

B3

B2

B1

B0

1

0

S1

S0

0

To conserve power the CS5467 has two power-down states. In stand-by state all circuitry, except the analog/digital

clock generators, is turned off. In the sleep state all circuitry, except the digital clock generator and the command

decoder, is turned off. Bringing the CS5467 out of sleep state requires more time than bringing it out of stand-by

state, because of the extra time needed to re-start and re-stabilize the analog clock signal. If the device is pow-

ered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all computations will be

halted.

S[1:0]

Power-down state

00 = Software Reset

01 = Halt and enter sleep power saving state. This state requires a slow power-on time

10 = Power-up and Halt

11 = Halt and enter stand-by power saving state. This state allows quick power-on time

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5.15.4 Register Read/Write

B7

B6

B5

B4

B3

B2

B1

B0

0

W/R

RA4

RA3

RA2

RA1

RA0

0

The Read/Write informs the command decoder that a register access is required. During a read operation, the ad-

dressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the

th

data is clocked into the input buffer and transferred to the addressed register upon completion of the 24 SCLK.

W/R

Write/Read control

0 = Read register

1 = Write register

RA[4:0]

Register address bits (bits 5 through 1) of the read/write command.

Page 0

Address

RA[4:0]

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Name

Config

I

V

P

Description

Configuration

0

1

2

3

4

5

6

7

Instantaneous Current

Instantaneous Voltage

Instantaneous Power

Average Active (Real) Power

RMS Current

P

Active

I

RMS

V

RMS Voltage

RMS

I2

Instantaneous Current 2

Instantaneous Voltage 2

Instantaneous Power 2

Average Active (Real) Power 2

RMS Current 2

8

9

V2

P2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Active

RMS

I2

V2

RMS Voltage 2

RMS

Q

Average Reactive Power

Instantaneous Reactive Power

Status (Write of ‘1’ to status bit will clear the bit)

Average Reactive Power 2

Instantaneous Reactive Power 2

Peak Current

Peak Voltage

Apparent Power

Power Factor

Peak Current 2

Peak Voltage 2

Apparent Power 2

Power Factor 2

Mask

Temperature

Control

Avg

Status

Q2

Avg

I

peak

V

S

peak

PF

I2

peak

V2

S2

peak

PF2

Mask

T

Ctrl

P

S

Active Energy Pulse Output Accumulator

Apparent Energy Pulse Output Accumulator

/ Page Reactive Energy Pulse Output Accumulator (read only)

and Page (write only)

pulse

Q

pulse

Note: For proper operation, do not attempt to write to unspecified registers.

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Page1

Address

RA[4:0]

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01111

10000

10001

10011

10100

10101

10110

10111

11010

11100

Name

Description

Current DC offset

Current Gain Calibration

Voltage DC offset

Voltage Gain Calibration

Power Offset

Current AC (RMS) offset

Voltage AC (RMS) offset

Current DC offset 2

Current Gain Calibration 2

Voltage DC offset 2

Voltage Gain Calibration 2

Power Offset 2

Current AC (RMS) offset 2

Voltage AC (RMS) offset 2

Sets the energy-to-frequency output pulse rate

Operational Modes

0

1

2

3

4

5

6

7

I

dcoff

gn

V

P

dcoff

gn

off

I

acoff

V

acoff

I2

dcoff

gn

8

9

V2

P2

dcoff

gn

10

11

12

13

15

16

17

19

20

21

22

23

26

28

off

I2

acoff

V2

acoff

PulseRateE

Mode

Epsilon

Cycle Count

Q_Trig

Epsilon

Number of conversions in one computation cycle (N)

Reactive Power calculated from Power Triangle

Reactive Power calculated from Power Triangle 2

Temperature Sensor Gain

Temperature Sensor Offset

Temperature Measurement

Q2_Trig

T

Gain

off

meas

SYS

System Gain

gain

Page2

Address

RA[4:0]

00000

00001

00100

00101

01000

01001

01100

01101

Name

VSAG

Description

VSAG Duration

VSAG Level

ISAG Duration

ISAG Level

VSAG Duration 2

VSAG Level 2

ISAG Duration 2

ISAG Level 2

0

1

4

5

8

9

12

13

duration

level

ISAG

duration

level

V2SAG

I2SAG

duration

level

duration

level

Note: For proper operation, do not attempt to write to unspecified registers.

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5.15.5 Calibration

B7

B6

B5

B4

B3

B2

B1

B0

1

0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

The CS5467 can perform system calibrations. Proper input signals must be applied to the current and voltage chan-

nel before performing a designated calibration.

CAL[5:4]*

CAL[3:0]*

Designates calibration to be performed

00 = Channel DC offset

01 = Channel DC gain

10 = Channel AC offset

11 = Channel AC gain

Designates channel to calibrate

0001 = Current channel

0010 = Voltage channel

0100 = Current channel 2

1000 = Voltage channel 2

*By utilizing different combinations for CAL[3:0], multiple channels can be calibrated simultaneously, e.g.

CAL[5:0] = 001111 commands the CS5467 to perform a DC offset calibration on all four channels. Values

for CAL[5:0] not specified should not be used.

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6. REGISTER DESCRIPTION

1. “Default” = bit status after power-on or reset

2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.

6.1 Page 0 Registers

6.1.1 Configuration (Config) Register

Address: 0

23

22

21

20

19

18

17

16

PC[7]

PC[6]

PC[5]

PC[4]

PC[3]

PC[2]

PC[1]

PC[0]

15

14

13

12

11

10

9

8

EWA

-

IMODE

IINV

-

7

6

5

4

3

2

1

0

-

iCPU

K[3]

K[2]

K[1]

K[0]

Default = 0x000001

PC[7:0]

Phase compensation. Sets a delay in the voltage channel relative to the current channel 1. De-

fault setting is 00000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).

EWA

Allows the E1 and E2 pins to be configured as open-collector output pins.

0 = Normal outputs (default)

1 = Only the pull-down device of the E1 and E2 pins are active

IMODE, IINV Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.

00 = Active-low level (default)

01 = Active-high level

10 = Low pulse

11 = High pulse

iCPU

Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals

are sampled, the logic driven by CPUCLK should not be active during the sample edge.

0 = Normal operation (default)

1 = Minimize noise when CPUCLK is driving rising edge logic

K[3:0]

Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal

clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-

tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero). K = 1 at reset.

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6.1.2 Instantaneous Current (I, I2), Voltage (V, V2), and Power (P, P2) Registers

Address: 1 (I), 2 (V), 3 (P), 7 (I2), 8 (V2), 9 (P2)

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

I (I2) and V (V2)contain the instantaneous measured values for current and voltage, respectively. The instanta-

neous voltage (voltage 2) and current (current 2) samples are multiplied to obtain Instantaneous Power, P (P2).

The value is represented in two's complement notation and in the range of -1.0 ≤ I, V, P < 1.0

(-1.0 ≤ I2, V2, P2 < 1.0), with the binary point to the right of the MSB.

6.1.3 Active (Real) Power (P_Active, P2_Active) Registers

Address: 4 (P

), 10 (P2

)

Active

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power,

P_Active(P2_Active). The value will be within in the range of -1.0 ≤ P_Active< 1.0 (-1.0 ≤ P2_Active< 1.0). The value is rep-

resented in two's complement notation, with the binary point to the right of the MSB.

6.1.4 RMS Current (I_RMS, I2_RMS) & Voltage (V_RMS, V2_RMS) Registers

Address: 5 (I

), 6 (V

), 11 (I2

), 12 (V2

)

RMS

MSB

LSB

-1

-2

-3

-4

-5

-6

-7

-8

-18

-19

-20

-21

-22

-23

-24

.....

2

I

(I2

) and V

(V2

) contain the Root Mean Square (RMS) values of I (I2) and V (V2), calculated

RMS

each computation cycle. The value is represented in unsigned binary notation and in the range of

0.0 ≤ I , V_RMS< 1.0 (0.0 ≤ I2 , V2_RMS< 1.0), with the binary point to the left of the MSB.

RMS

6.1.5 Instantaneous Reactive Power (Q, Q2) Registers

Address: 14 (Q), 17 (Q2)

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The Instantaneous Reactive Power (Q, Q2) is the product of the voltage (voltage 2) signal, shifted 90 degrees,

and the current (current 2) signal. The value is represented in two's complement notation and in the range of

-1.0 < Q < 1.0 (1.0 < Q2 < 1.0), with the binary point to the right of the MSB.

6.1.6 Average Reactive Power (Q_Avg, Q2_Avg) Registers

Address: 13 (Q ), 16 (Q2

)

Avg

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The Average Reactive Power (Q

, Q2

) is Q (Q2) averaged over N samples. The value is represented in

AVG

two's complement notation and in the range of -1.0 < Q_AVG< 1.0 (-1.0 < Q2_AVG< 1.0), with the binary point to

the right of the MSB.

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6.1.7 Status (Status) and Mask (Mask) Register

Address: 15 (Status); 26 (Mask)

23

22

21

20

19

18

17

16

DRDY

I2OR

V2OR

CRDY

I2ROR

V2ROR

IOR

VOR

15

14

13

12

11

10

9

8

E2OR

IROR

VROR

EOR

IFAULT

VSAG

I2FAULT

V2SAG

7

6

5

4

3

2

1

0

TUP

V2OD

I2OD

VOD

IOD

LSD

FUP

IC

Default = 0x800001 (Status Register), 0x000000 (Mask Register)

The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit

to reset. Writing a '0' to a bit will not change it’s current state.

The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the

corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.

DRDY

Data Ready. During conversions, this bit will indicate the end of computation cycles. For cal-

ibrations, this bit indicates the end of a calibration sequence.

IOR (I2OR)

VOR (V2OR)

CRDY

Current Out of Range. Set when the magnitude of the measured current value causes the I

(I2) register to overflow.

Voltage Out of Range. Set when the magnitude of the measured voltage value causes the

V (V2) register to overflow.

Conversion Ready. Indicates a new conversion is ready. This will occur at the output word

rate.

IROR (I2ROR)

RMS Current Out of Range. Set when the calculated RMS current value causes the I

RMS

(I2

) register to overflow.

RMS

VROR (V2ROR) RMS Voltage Out of Range. Set when the calculated RMS voltage value causes the V

RMS

(V2

) register to overflow.

RMS

EOR (E2OR)

Energy Out of Range. Set when P

(P2

) overflows.

Active

IFAULT (I2FAULT) Indicates a current fault occurred in the power line current. If the absolute value of the in-

stantaneous current is less than ISAG^level(I2SAGlevel) for more than half of the ISAGduration

(I2SAGduration), the IFAULT (I2FAULT) bit will be set.

VSAG (V2SAG)

Indicates a voltage sag occurred in the power line voltage. If the absolute value of the in-

stantaneous voltage is less than VSAG^level(V2SAGlevel) for more than half of the VSAGduration

(V2SAGduration), the VSAG (V2SAG) bit will be set.

TUP

Temperature Updated. Indicates a temperature conversion is ready.

VOD (V2OD)

Modulator Oscillation Detected on the voltage (voltage 2) channel. Set when the modulator

oscillates due to an input above full scale. The level at which the modulator oscillates is sig-

nificantly higher than the voltage (voltage 2) channel’s differential input voltage range.

IOD (I2OD)

Modulator Oscillation Detected on the current (current 2) channel. Set when the modulator

oscillates due to an input above full scale. The level at which the modulator oscillates is sig-

nificantly higher than the current (current 2) channel’s differential input voltage range.

Note: The IOD (I2OD) and VOD (V2OD) bits may be ‘falsely’ triggered by very brief voltage

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spikes from the power line. This event should not be confused with a DC overload

situation at the inputs, when the IOD (I2OD) and VOD (V2OD) bits will re-assert

themselves even after being cleared, multiple times.

LSD

Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-

old (PMLO), with respect to AGND pin. For a given part, PMLO can be as low as 2.3 V. LSD bit

cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage

threshold (PMHI), which is typically 100 mV above the device’s low-voltage threshold. PMHI will

never be greater than 2.7 V.

FUP

IC

Epsilon Updated. Indicates an update to the epsilon value has been placed in the register.

Invalid Command. Normally logic 1. Set to logic 0 if the host interface is strobed with an 8-bit

word that is not recognized as one of the valid commands (see See Section 5.15 Commands

on page 24).

6.1.8 Peak Current (I_peak, I2_peak) and Peak Voltage (V_peak, V2_peak) Register

Address: 18 (I

), 19 (V

), 22 (I2

), 23 (V2

)

peak

MSB

-(2⁰)

LSB

2^-23

2^-1

2^-2

2^-3

2^-4

2^-5

2^-6

2^-7

2^-17

2^-18

2^-19

2^-20

2^-21

2^-22

.....

, V2

The Peak Current (I

, I2

) and Peak Voltage (V

) registers contain the instantaneous current

peak

and voltage with the greatest magnitude detected during the last computation cycle. The value is represented

in two's complement notation and in the range of -1.0 ≤ I

binary point to the right of the MSB.

, V

< 1.0 (-1.0 ≤ I2

, V2 < 1.0), with the

peak

6.1.9 Apparent Power (S, S2) Register

Address: 20 (S), 24 (S2)

MSB

LSB

-(2⁰)

2^-1

2^-2

2^-3

2^-4

2^-5

2^-6

2^-7

2^-17

(V2

2^-18

2^-19

2^-20

2^-21

and I2 ), The value is represented in

RMS

2^-22

2^-23

.....

Apparent power S (S2) is the product of the V

and I

RMS

unsigned notation and in the range of 0 ≤ S < 1.0 (0 ≤ S2 < 1.0), with the binary point to the right of the MSB.

6.1.10 Power Factor (PF, PF2) Register

Address: 21 (PF), 25 (PF2)

MSB

LSB

-(2⁰)

2^-1

2^-2

2^-3

2^-4

2^-5

2^-6

2^-7

2^-17

2^-18

2^-19

2^-20

2^-21

2^-22

2^-23

.....

Power Factor is calculated by dividing the Active (Real) Power by Apparent Power. The value is represented in

two's complement notation and in the range of -1.0 ≤ PF < 1.0 (-1.0 ≤ PF2 < 1.0), with the binary point to the

right of the MSB.

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6.1.11 Temperature (T) Register

Address: 27

MSB

LSB

7

6

5

4

3

2

1

0

-10

-11

-12

-13

-14

-15

-16

.....

-(2 )

2

T contains measurements from the on-chip temperature sensor. Measurements are performed during continu-

ous conversions, with the default the Celsius scale (^oC). The value is represented in two's complement notation

and in the range of -128.0 ≤ T < 128.0, with the binary point to the right of the eighth MSB.

6.1.12 Control (Crtl) Register

Register Address: 28

23

22

21

20

19

18

17

16

PC2[7]

PC2[6]

PC2[5]

PC2[4]

PC2[3]

PC2[2]

PC2[1]

PC2[0]

15

14

13

12

11

10

9

8

-

I2gain

-

STOP

7

6

5

4

3

2

1

0

-

Igain

INTOD

-

NOCPU

NOOSC

-

Default = 0x000000

PC2[7:0]

Phase compensation. Sets a delay in the voltage channel relative to current channel 2. Default

setting is 00000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).

Igain (I2gain) Sets the gain of the current (current 2) PGA.

0 = Gain is 10 (default)

1 = Gain is 50

STOP

Terminates the auto-boot sequence.

0 = Normal (default)

1 = Stop sequence

INTOD

NOCPU

NOOSC

Converts INT output pin to an open drain output.

0 = Normal (default)

1 = Open drain

Saves power by disabling the CPUCLK pin.

0 = Normal (default)

1 = Disables CPUCLK

Saves power by disabling the crystal oscillator.

0 = Normal (default)

1 = Disabling oscillator circuit

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6.1.13 Active Energy Pulse Output Accumulator (P_pulse) Register

Address: 29

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The Active Energy Pulse Output Accumulator (P

) contains the average active energy measured on chan-

pulse

nels 1 & 2 and is used to drive the pulse output. The value is represented in two's complement notation and in

the range of -1.0 ≤ P_pulse< 1.0, with the binary point to the right of the MSB.

6.1.14 Apparent Energy Pulse Output Accumulator (S_pulse) Register

Address: 30

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The Apparent Energy Pulse Output Accumulator (S

) contains the average apparent power measured on

pulse

channels 1 & 2 and is used to drive the pulse output. This result is updated after each computation cycle. The

value is represented in two's complement notation and in the range of -1.0 ≤ S_pulse< 1.0, with the binary point

to the right of the MSB.

6.1.15 Reactive Energy Pulse Output Accumulator (Q_pulse) Register

Address: 31 (read only)

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The Reactive Energy Pulse Output Accumulator (Q

) contains the average reactive power measured chan-

pulse

nels 1 & 2 and is used to drive the pulse output. The value is represented in two's complement notation and in

the range of -1.0 ≤ Q_pulse< 1.0, with the binary point to the right of the MSB.

6.1.16 Page Register

Address: 31 (write only)

MSB

LSB

6

5

4

3

2

1

0

2

Default = 0x00

Determines which register page the serial port will access.

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6.2 Page 1 Registers

6.2.1 Current DC Offset (I_dcoff, I2_dcoff) and Voltage DC Offset (V_dcoff, V2_dcoff) Registers

Address: 0 (I

), 2 (V

), 7 (I2

), 9 (V2

)

dcoff

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

Default = 0x000000

The DC Offset registers (I_dcoff,V_dcoff, I2_dcoff,V2_dcoff) are initialized to 0.0 on reset. When DC Offset calibration is

performed, the register is updated with the DC offset measured over a computation cycle. DRDY will be set at

the end of the calibration. This register may be read and stored for future system offset compensation. The value

is represented in two's complement notation and in the range of -1.0 ≤ I_dcoff, V_dcoff< 1.0

(-1.0 ≤ I2_dcoff, V2_dcoff< 1.0), with the binary point to the right of the MSB. See Section 7.1.2.1 DC Offset Calibra-

tion Sequence on page 39 for more information.

6.2.2 Current Gain (I_gn, I2_gn) and Voltage Gain (V_gn, V2_gn) Registers

Address: 1 (I ), 3 (V ), 8 (I2 ), 10 (V2 )

gn

MSB

LSB

1

0

-1

-2

-3

-4

-5

-6

-16

-17

-18

-19

-20

-21

-22

.....

2

Default = 0x400000 = 1.000

The gain registers (I_gn,V_gn, I2_gn,V2_gn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is

performed, the register is updated with the gain measured over a computation cycle. DRDY will be set at the

end of the calibration. This register may be read and stored for future system gain compensation. The value is

in the range 0.0 ≤ I_gn,V_gn< 3.9999 (0.0 ≤ I2_gn,V2_gn< 3.9999), with the binary point to the right of the second

MSB.

6.2.3 Power Offset (P_off, P2_off) Registers

Address: 4 (P ), 11 (P2 )

off

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

Default = 0x000000

Power Offset (P , P2 ) is added to the instantaneous power being accumulated in the P

(P2 ) regis-

active

off

active

ter, and can be used to offset contributions to the energy result that are caused by undesirable sources of energy

that are inherent in the system. The value is represented in two's complement notation and in the range of

-1.0 ≤ Poff < 1.0 (-1.0 ≤ P2off < 1.0), with the binary point to the right of the MSB.

6.2.4 Current AC Offset (I_acoff, I2_acoff) and Voltage AC Offset (V_acoff, V2_acoff) Registers

Address: 5 (I

), 6 (V

), 12 (I2

), 13 (V2

)

acoff

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

Default = 0x000000

The AC Offset Registers (V^acoff, Iacoff, V2acoff, I2acoff)are initialized to zero on reset, allowing for uncalibrated normal

operation. AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cy-

cles (where N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration.

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These values may be read and stored for future system AC offset compensation. The value is represented in

two's complement notation in the range of -1.0 ≤ Vacoff, Iacoff < 1.0 (-1.0 ≤ V2acoff, I2acoff < 1.0), with the binary point

to the right of the MSB.

6.2.5 PulseRateE Register

Address: 15

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)

PulseRateE sets the frequency of E1, E2, & E3 pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at

full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's comple-

ment notation and in the range is -1.0 ≤ PulseRateE < 1.0, with the binary point to the right of the MSB. Negative

values have the same effect as positive. See Section 5.5 Energy Pulse Output on page 18 for more information.

6.2.6 Operational Mode (Mode) Register

Address: 16

23

22

21

20

19

18

17

16

-

15

14

13

12

11

10

9

8

-

E2MODE

VHPF2

7

6

5

4

3

2

1

0

IHPF2

VHPF

IHPF

-

E3MODE[1]

E3MODE[0]

POS

AFC

Default = 0x000000

E2MODE E2 Output Mode

0 = Sign of Active Power (default)

1 = Apparent Power

VHPF(VHPF2) Enables the High Pass Filter on the voltage channel.

0 = High-pass filter disabled (default)

1 = High-pass filter enabled

IHPF(IHPF2) Enables the High Pass Filter on the current channel.

0 = High-pass filter disabled (default)

1 = High-pass filter enabled

E3MODE1:0

E3 Output Mode

00 = Reactive Power (default)

01 = PFMON

10 = Voltage sign

11 = Apparent Power

POS

AFC

Positive Energy Only. Negative energy pulses on E1 are suppressed. However, negative P reg-

ister results will NOT be suppressed.

Enables automatic line frequency measurement and sets the frequency of the local sine/cosine

generator used in fundamental/harmonic measurements. When AFC is enabled, the Epsilon

register will be updated periodically.

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6.2.7 Epsilon (ε) Register

Address: 17

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

Default = 0x01999A = 0.0125 sec

^{Epsilon (}ε) is the ratio of the input line frequency to the sample frequency of the ADC (See Section 5.4 Perform-

ing Measurements on page 17). Epsilon is either written to the register, or measured during conversions. The

value is represented in two's complement notation and in the range of -1.0 ≤ ε < 1.0, with the binary point to the

right of the MSB. Negative values have no significance.

6.2.8 Cycle Count Register

Address: 19

MSB

LSB

23

22

21

20

19

18

17

16

6

5

4

3

2

1

0

.....

2

Default = 0x000FA0 = 4000

Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,

the computation cycle frequency is (MCLK/K)/(1024∗N). A one second computational cycle period occurs when

MCLK = 4.096 MHz, K = 1, and N = 4000.

6.2.9 Reactive Power (Q_Trig, Q2_Trig) Registers

Address: 20 (Q ), 21 (Q2

)

Trig

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

The Reactive Power (Q , Q2 ) is calculated using trigonometric identities. (See Section 4.3 Power Mea-

Trig

surements on page 15). The value is represented in unsigned notation and in the range of 0 ≤ Q_Trig< 1.0

(0 ≤ Q2_Trig< 1.0), with the binary point to the right of the MSB.

6.2.10 Temperature Gain (T_Gain) Register

Address: 22

MSB

LSB

6

5

4

3

2

1

0

-1

-11

-12

-13

-14

-15

-16

-17

.....

2

Default = 0x34E2E7 = 26.443169117

Temperature gain (T

) is utilized to convert from one temperature scale to another. The Celsius scale (^oC) is

Gain

the default. Values will be within in the range of 0 ≤ T_Gain< 128. The value is represented in unsigned notation,

with the binary point to the right of bit 7th MSB.

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6.2.11 Temperature Offset (T_off) Register

Address: 23

MSB

LSB

0

-1

-2

-3

-4

-5

-6

-7

-17

-18

-19

-20

-21

-22

-23

.....

-(2 )

2

Default = 0xF38701 = -0.0974425

Temperature offset (T ) is used to remove the temperature channel’s offset at the zero-degree reading. Values

off

are represented in two's complement notation and in the range of -1.0 ≤ Toff < 1.0, with the binary point to the

right of the MSB.

6.2.12 Temperature Measurement (T_meas) Register

Address: 26

MSB

LSB

23

22

21

20

19

18

17

16

6

5

4

3

2

1

0

.....

2

Default = 0x000000

The Temperature Measurement register is used to cycle-steal voltage channel 2 for temperature measurement.

Writing a one to the LSB causes the temperature to be measured and the Temperature register (T) to be updat-

ed.

6.2.13 System Gain Register ( SYS_Gain

)

Address: 28

MSB

LSB

1

0

-1

-2

-3

-4

-5

-6

-16

-17

-18

-19

-20

-21

-22

.....

-(2 )

2

Default = 0x500000 = 1.25

System Gain (SYS^Gain) determines the one’s density of the channel measurements. Small changes in the mod-

ulator due to temperature can be fine adjusted by changing the system gain. The value is represented in two's

complement notation and in the range of -2.0 < SYSGain < 2.0, with the binary point to the right of the second

MSB.

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6.3 Page 2 Registers

6.3.1 Voltage Sag Duration (VSAG_duration, V2SAG_duration) Registers

Address: 0 (VSAG

), 8 (V2SAG

)

duration

MSB

LSB

22

21

20

19

18

17

16

6

5

4

3

2

1

0

.....

2

Default = 0x000000

Voltage Sag Duration (VSAG_duration, V2SAG_duration) defines the number of instantaneous measurements utilized

to determine a sag event. Setting these register to zero will disable this feature. The value is represented in un-

signed notation. See Section 5.6 Sag and Fault Detect Feature on page 20

6.3.2 Current Fault Duration (ISAG_duration, I2SAG_duration) Registers

Address: 4 (ISAG

), 12 (I2SAG

)

duration

MSB

LSB

22

21

20

19

18

17

16

6

5

4

3

2

1

0

.....

2

Default = 0x000000

Current Fault Duration (ISAG_duration, I2SAG_duration) defines the number of instantaneous measurements utilized

to determine a sag event. Setting these register to zero will disable this feature. The value is represented in un-

signed notation. See Section 5.6 Sag and Fault Detect Feature on page 20.

6.3.3 Voltage Sag Level (VSAG_level, V2SAG_Level) Registers

Address: 1 (VSAG

), 9 (V2SAG

)

level

MSB

LSB

-1

-2

-3

-4

-5

-6

-7

-8

-18

-19

-20

-21

-22

-23

-24

.....

2

Default = 0x000000

Voltage Sag Level (VSAG_level), V2SAG_level) defines the voltage level that the magnitude of input samples, aver-

aged over the sag duration, must fall below in order to register a sag condition. These value are represented in

unsigned notation and in the range of 0 ≤ VSAG_level< 1.0 (0 ≤ V2SAG_level< 1.0), with the binary point to the left

of the MSB. See Section 5.6 Sag and Fault Detect Feature on page 20.

6.3.4 Current Fault Level (ISAG_level, I2SAG_level) Registers

Address: 5 (ISAG

), 13 (I2SAG

)

level

MSB

LSB

-1

-2

-3

-4

-5

-6

-7

-8

-18

-19

-20

-21

-22

-23

-24

.....

2

Default = 0x000000

Current Fault Level (ISAG_level, I2SAG_level) defines the voltage level that the magnitude of input samples, aver-

aged over the fault duration, must fall below in order to register a fault condition. These value are represented

in unsigned notation and in the range of 0 ≤ ISAG_level< 1.0 (0 ≤ I2SAG_level< 1.0), with the binary point to the left

of the MSB. See Section 5.6 Sag and Fault Detect Feature on page 20.

38

DS714A1

ADVANCE RELEASE

CS5467

7. SYSTEM CALIBRATION

N + 30 conversion cycles to complete. For AC offset cal-

ibrations, the sequence takes at least 6N + 30 ADC cy-

cles to complete, (about 6 computation cycles). As N is

increased, the accuracy of calibration results will in-

crease.

7.1 Channel Offset and Gain Calibration

The CS5467 provides digital DC offset and gain com-

pensation that can be applied to the instantaneous volt-

age and current measurements, and AC offset

compensation to the voltage and current RMS calcula-

tions.

7.1.2 Offset Calibration Sequence

Since the voltage and current channels have indepen-

dent offset and gain registers, system offset and/or

gain can be performed on either channel without the

calibration results from one channel affecting the oth-

er.

For DC and AC offset calibrations, the VIN± (V2IN± )

pins of the voltage and IIN± (I2IN± ) pins of the current

channels should be connected to their ground reference

level. (see Figure 14.)

The computational flow of the calibration sequences are

illustrated in Figure 13. The flow applies to both the volt-

age channel and current channel.

External

Connections

+

-

+

-

AIN+

AIN-

+

-

0V

XGAIN

7.1.1 Calibration Sequence

The CS5467 must be operating in its active state and

ready to accept valid commands. Refer to 5.15 Com-

mands on page 24. The calibration algorithms are de-

pendent on the value N in the Cycle Count Register (see

Figure 13). Upon completion, the results of the calibra-

tion are available in their corresponding register. The

DRDY bit in the Status Register will be set. If the DRDY

bit is to be output on the INT pin, the DRDY bit in the

Mask Register must be set. The initial values in the AC

gain and offset registers do affect the results of the cal-

ibration results.

+

-

CM

Figure 14. System Calibration of Offset

The AC offset registers must be set to the default

(0x000000).

7.1.2.1 DC Offset Calibration Sequence

Channel gain should be set to 1.0 when performing DC

offset calibration. Initiate a DC offset calibration. The DC

offset registers are updated with the negative of the av-

erage of the instantaneous samples collected over a

computational cycle. Upon completion of the DC offset

calibration the DC offset is stored in the corresponding

DC offset register. The DC offset value will be added to

7.1.1.1 Duration of Calibration Sequence

The value of the Cycle Count Register (N) determines

the number of conversions performed by the CS5467

during a given calibration sequence. For DC offset and

gain calibrations, the calibration sequence takes at least

Instantaneous

V, I, V2, I2

RMS

I_RMS, V_RMS

I2_RMS, V2_RMS

+

N

+

,

Filter

Modulator

In

X

+

N

÷

+

X

√

Σ

+

DC Offset

I_dcoff, V_dcoff

I2_dcoff, V2_dcoff

Gain

I_gn, V_gn

I2_gn, V2_gn

N

I_acoff, V_acoff

,

I2_acoff, V2_acoff

Σ

AC Offset

X

-.

N

÷

Inverse

X

-.

±06

RMS

= NAMES OF READABLE/WRITABLE REGISTERS.

Figure 13. Calibration Data Flow

DS714A1

39

ADVANCE RELEASE

CS5467

each instantaneous measurement to nullify the DC

component present in the system during conversion

commands.

measurement will be multiplied by its corresponding AC

gain value.

A typical rms calibration value which allows for reason-

able over-range margin would be 0.6 or 60% of the volt-

age and current channel’s maximum input voltage level.

7.1.2.2 AC Offset Calibration Sequence

Corresponding offset registers I

(I2

) and/or

acoff

Two examples of AC gain calibration and the updated

digital output codes of the channel’s instantaneous data

registers are shown in Figure 16 and 17. Figure 17

V

(V2

) should be cleared prior to initiating AC

acoff

offset calibrations. Initiate an AC offset calibration.The

AC offset registers are updated with an offset value that

reflects the RMS output level. Upon completion of the

AC offset calibration the AC offset is stored in the corre-

sponding AC offset register. The AC offset register val-

Before AC Gain Calibration (Vgn Register = 1)

250 mV

230 mV

0.9999...

0.92

Sinewave

Instantaneous Voltage

Register Values

ue is subtracted from each successive V

calculation.

and I

INPUT

SIGNAL

RMS

0 V

-0.92

-1.0000...

-230 mV

-250 mV

7.1.3 Gain Calibration Sequence

V_RMSRegister = ²³⁰_√2x¹/₂₅₀≈ 0.65054

/

When performing gain calibrations, a reference signal

should be applied to the VIN± (V2IN± ) pins of the volt-

age and IIN± (I2IN± ) pins of the current channels that

represents the desired maximum signal level. Figure 15

shows the basic setup for gain calibration.

After AC Gain Calibration (Vgn Register changed to approx. 0.9223)

250 mV

230 mV

0.92231

0.84853

Sinewave

External

Connections

INPUT

SIGNAL

Instantaneous Voltage

Register Values

0 V

+

-

+

-

-230 mV

-250 mV

IN+

-0.84853

-0.92231

Reference

Signal

+

-

XGAIN

V_RMSRegister = 0.600000

IN-

+

-

CM

Figure 16. Example of AC Gain Calibration

Before AC Gain Calibration (Vgain Register = 1)

Figure 15. System Calibration of Gain.

250 mV

230 mV

0.9999...

0.92

For gain calibrations, there is an absolute limit on the

RMS voltage levels that are selected for the gain cali-

bration input signals. The maximum value that the gain

registers can attain is 4. Therefore, if the signal level of

the applied input is low enough that it causes the

CS5467 to attempt to set either gain register higher than

4, the gain calibration result will be invalid and all

CS5467 results obtained while performing measure-

ments will be invalid.

DC Signal

Instantaneous Voltage

Register Values

INPUT

0 V

SIGNAL

-1.0000...

-250 mV

V_RMSRegister = ₂²₅³₀⁰= 0.92

After AC Gain Calibration (Vgain Register changed to approx. 0.65217)

If the channel gain registers are initially set to a gain oth-

er than 1.0, AC gain calibration should be used.

250 mV

0.65217

0.6000

230 mV

DC Signal

7.1.3.1 AC Gain Calibration Sequence

INPUT

SIGNAL

Instantaneous Voltage

Register Values

0 V

The corresponding gain register should be set to 1.0,

unless a different initial gain value is desired. Initiate an

AC gain calibration. The AC gain calibration algorithm

computes the RMS value of the reference signal applied

to the channel inputs. The RMS register value is then di-

vided into 0.6 and the quotient is stored in the corre-

-250 mV

-0.65217

V_RMSRegister = 0.600000

Figure 17. Example of AC Gain Calibration

sponding

gain

register.

Each

instantaneous

40

DS714A1

ADVANCE RELEASE

CS5467

shows that a positive (or negative) DC-level signal can

be used even though an AC gain calibration is being ex-

ecuted.

multiplying the AC offset register value that was cal-

culated in step 2 by the gain calculated in step 3 and

updating the AC offset register with the product.

However, an AC signal cannot be used for DC gain cal-

ibration.

7.2 Phase Compensation

The CS5467 is equipped with phase compensation to

cancel out phase shifts introduced by the measurement

element. Phase Compensation is set by bits PC[7:0] (for

channel 1) in the Configuration Register and bits

PC2[7:0] (for channel 2) in the Control Register

7.1.3.2 DC Gain Calibration Sequence

Initiate a DC gain calibration. The corresponding gain

register is restored to default (1.0). The DC gain calibra-

tion averages the channel’s instantaneous measure-

ments over one computation cycle (N samples). The

average is then divided into 1.0 and the quotient is

stored in the corresponding gain register

The default value of PC[7:0] (PC2[7:0]) is zero. With

MCLK = 4.096 MHz and K = 1, the phase compensa-

tion has a range of ± 5.4 degrees when the input signals

are 60 Hz. Under these conditions, each step of the

phase compensation register (value of one LSB) is ap-

proximately 0.04 degrees. For values of MCLK other

than 4.096 MHz, the range and step size should be

scaled by 4.096 MHz/(MCLK/K). For power line fre-

quencies other than 60Hz, the values of the range and

step size of the PC[7:0] (PC2[7:0]) bits can be deter-

mined by converting the above values from angular

measurement into the time domain (seconds), and then

computing the new range and step size (in degrees)

with respect to the new line frequency. To calculate the

phase shift induced between the voltage and the current

channel use the equation:

After the DC gain calibration, the instantaneous register

will read at full-scale whenever the DC level of the input

signal is equal to the level of the DC calibration signal

applied to the inputs during the DC gain calibration.The

HPF option should not be enabled if DC gain calibration

is utilized.

7.1.4 Order of Calibration Sequences

1. If the HPF option is enabled, any DC component that

may be present in the selected signal path will be re-

moved and a DC offset calibration is not required.

However, if the HPF option is disabled the DC offset

calibration sequence should be performed.

When using high-pass filters, it is recommended that

the DC Offset register for the corresponding channel

be set to zero. When performing DC offset calibra-

tion, the corresponding gain channel should be set to

one.

^Freq× ³⁶⁰^o× PC[7:0]

---------------------------------------------------

Phase =

(MCLK ⁄ K) ⁄ 8

Freq = Line Frequency [Hz]

PC[7:0] = 2’s Compliment number in the range of -128 < PC[7:0} < 127

2. If there is an AC offset in the V

or I

calcula-

RMS

tion, the AC offset calibration sequence should be

performed.

7.3 Active Power Offset

The Power Offset Register can be used to offset system

power sources that may be resident in the system, but

do not originate from the power line signal. These sourc-

es of extra energy in the system contribute undesirable

and false offsets to the power and energy measurement

results. After determining the amount of stray power, the

Power Offset Register can be set to cancel the effects

of this unwanted energy.

3. Perform the gain calibration sequence.

4. Finally, if an AC offset calibration was performed

(step 2), the AC offset may need to be adjusted to

compensate for the change in gain (step 3). This can

be accomplished by restoring zero to the AC offset

register and performing an AC offset calibration se-

quence. The adjustment could also be done by

DS714A1

41

ADVANCE RELEASE

CS5467

2

8. AUTO-BOOT MODE USING E PROM

2

When the CS5467 MODE pin is asserted (logic 1), the

CS5467 auto-boot mode is enabled. In auto-boot mode,

the CS5467 downloads the required commands and

8.2 Auto-boot Data for E PROM

Below is an example code set for an auto-boot se-

quence. This code is written into the E PROM by the us-

er. The serial data for such a sequence is shown below

in single-byte hexidecimal notation:

2

register data from an external serial E PROM, allowing

the CS5467 to begin performing energy measurements.

8.1 Auto-boot Configuration

-7E 00 00 01

Change to page 1.

-60 00 01 E0

Write Operation Mode Register, turn high-pass

filters on.

-42 7F C4 A9

Write value of 0x7FC4A9 to Current Gain

Register.

-46 FF B2 53

Write value of 0xFFB253 to Voltage Gain

Register.

-50 7F C4 A9

Write value of 0x7FC4A9 to Current 2 Gain

Register.

-54 FF B2 53

Write value of 0xFFB253 to Voltage 2 Gain

Register.

-7E 00 00 00

Change to page 0.

-74 00 00 04

A typical auto-boot serial connection between the

2

CS5467 and a E PROM is illustrated in Figure 18. In au-

to-boot mode, the CS5467’s CS and SCLK are config-

ured as outputs. The CS5467 asserts CS (logic 0),

provides a clock on SCLK, and sends a read command

2

to the E PROM on SDO. The CS5467 reads the us-

er-specified commands and register data presented on

2

the SDI pin. The E PROM’s programmed data is utilized

by the CS5467 to change the designated registers’ de-

fault values and begin registering energy.

VD+

E1

Pulse Output

Counter

E2

5 K

EEPROM

CS5467

SCLK

SCK

SDI

SO

SI

SDO

CS

5 K

MODE

CS

Unmask bit #2 (LSD) in the Mask Register.

-E8

Start continuous conversions

-78 00 01 00

Write STOP bit to Control Register, to terminate

auto-boot initialization sequence.

Connector to

Calibrator

2

Figure 18. Typical Interface of E PROM to CS5467

2

8.3 Which E PROMs Can Be Used?

Several industry-standard serial E PROMs that will suc-

cessfully run auto-boot with the CS5467 are listed be-

low:

Figure 18 also shows the external connections that

would be made to a calibrator device, such as a PC or

custom calibration board. When the metering system is

installed, the calibrator would be used to control calibra-

tion and/or to program user-specified commands and

2

•

Atmel AT25010, AT25020 or AT25040

National Semiconductor NM25C040M8 or NM25020M8

Xicor X25040SI

2

calibration values into the E PROM. The user-specified

commands/data will determine the CS5467’s exact op-

eration, when the auto-boot initialization sequence is

running. Any of the valid commands can be used.

These types of serial E PROMs expect a specific 8-bit

command (00000011) in order to perform a memory

read. The CS5467 has been hardware programmed to

2

transmit this 8-bit command to the E PROM at the be-

ginning of the auto-boot sequence.

42

DS714A1

ADVANCE RELEASE

CS5467

9. BASIC APPLICATION CIRCUITS

Figure 19 shows the CS5467 configured to measure

power in a single-phase, 3-wire system while operating

in a single-supply configuration. In this diagram, a cur-

rent transformer (CT) is used to sense the line current

and a voltage divider is used to sense the line voltage.

Ω

5 k

10 kΩ

L2

N

L1

Ω

10

500

0.1 µF

470 µF

0.1 µF

2 uF

3

18

VA+

VD+

9

VIN1+

C_V-

CS5467

C_Vdiff

R

1

2

C

V+

R_V-

21

2

10

13

VIN1-

PFMON

CPUCLK

XOUT

1

VIN2+

4.096 MHz

C_V-

C_Vdiff

R

2

Optional

Clock

Source

1

28

XIN

C

V+

R_V-

14

19

VIN2-

IIN1-

R_I-

23

1kΩ

RESET

CS

7

C_Idiff

CT

R_Burden

Serial

Data

Interface

27

6

SDI

1k

Ω

20

SDO

SCLK

INT

IIN1+

IIN2-

5

R_I+

24

R_Burden

R_I-

15

16

26

25

E2

E1

1kΩ

C_Idiff

CT

Pulse Output

Counter

IIN2+

R_I+

12

VREFIN

LOAD

11

VREFOUT

0.1 µF

AGND

17

DGND

4

Figure 19. Typical Connection Diagram (Single-phase, 3-wire – Direct Connect to Power Line)

DS714A1

43

ADVANCE RELEASE

CS5467

10.PACKAGE DIMENSIONS

28L SSOP PACKAGE DRAWING

N

D

1

E1

A2

A

E

∝

A1

b²

e

END VIEW

L

SEATING

PLANE

SIDE VIEW

1 2

3

TOP VIEW

INCHES

NOM

--

0.006

0.068

--

MILLIMETERS

NOTE

DIM

A

A1

A2

b

MIN

--

0.002

0.064

0.009

?

MAX

0.084

0.010

0.074

0.015

?

MIN

--

0.05

1.62

0.22

?

NOM

--

0.13

1.73

--

MAX

2.13

0.25

1.88

0.38

?

2,3

1

D

?

E

E1

e

L

∝

0.291

0.197

0.022

0.025

0°

0.307

0.209

0.026

0.03

4°

0.323

0.220

0.030

0.041

8°

7.40

5.00

0.55

0.63

0°

7.80

5.30

0.65

0.75

4°

8.20

5.60

0.75

1.03

8°

1

JEDEC #: MO-150

Controlling Dimension is Millimeters.

Notes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch

and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

4. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in

excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more

than 0.07 mm at least material condition.

5. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

44

DS714A1

ADVANCE RELEASE

CS5467

11. ORDERING INFORMATION

Model

Temperature

Package

CS5467-IS

CS5467-ISZ (lead free)

-40 to +85 °C

28-pin SSOP

12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Number

CS5467-IS

CS5467-ISZ (lead free)

Peak Reflow Temp

240 °C

MSL Rating*

Max Floor Life

2

3

365 Days

7 Days

260 °C

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

DS714A1

45

ADVANCE RELEASE

CS5467

13. REVISION HISTORY

Revision

Date

Changes

A1

MAR 2006

Advance Release

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

“Advance” product information describes products that are in development and subject to development changes.

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-

sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent

does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE

IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-

VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD

TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED

IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-

TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER

AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH

THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

46

DS714A1


型号：	CS5467-IS
厂家：	CIRRUS LOGIC
描述：	Four-channel Power/Energy IC 四通道功率/能量集成电路
文件：	总46页 (文件大小：708K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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