SCG4001 [CONNOR-WINFIELD]
Synchronous Clock Generators;
| 型号： | SCG4001 |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | Synchronous Clock Generators |
| 文件： | 总12页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCG4001
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Application
Features
The Connor-Winfield SCG4001 provides
high precision phase lock loop frequency
translation for the telecommunication
applications.
• ±32 ppm Absolute
Pull-in Range
• 3.3V High
Precision PLL
SCG4001 is well suited for use in line
cards, service termination cards and
similar functions to provide reliable
reference, phase locked, synchronization
for TDM, PDH, SONET and SDH network
equipment. The SCG4001 provides a jitter
filtered, wander following output signal
sychronized to a superior Stratum or peer
input reference signal.
• Tri-State
Capability
• Active Alarms
• Guaranteed Free
Run ±20ppm
• 1 sec. Acquisition
Time
Bulletin
SG043
The SCG4001 is designed to operate
with a STRATUM 4 reference
Page
1 of 12
Revision
P00
Date
08 AUG 02
Issued By
MBatts
General Description
The SCG4001 is a digital phase locked loop generating
a LVPECL outputs from an intrinsically low jitter voltage
controlled crystal oscillator. The LVPECL outputs may be
disabled. The jitter attenuated internal reference, divided
down from the output frequency, is also output to a pin.
The SCG4001 can only lock to an 8kHz reference. A
filtered reference output signal is available at the same
frequency. The unit has an acquisition time of about 1
second and it is tolerant of different reference duty cycles.
Further features include alarm outputs for Loss-of-
which will guarantee a 20 ppm accurate output.
Additionally the Free Run mode may be entered
manually.
The alarms and reference output may be put into
the tri-state high impedance condition for external
testing purposes.
The package dimensions are 1.025” x 1.0” x 0.429”
on a 6 layer FR4 board with castellated pins. Parts
are assembled using high temperature solder to
withstand 63/37 alloy, 180° C surface mount reflow
processes.
Reference (LOR) and Loss-of-Lock (LOL). During the
LOR alarm, the SCG4000 will also enter a Free Run state,
Functional Block Diagram
Figure 1
SCG4000 Series
Block Diagram
LOL Alarm Output
(Pin 11)
ALARM
DETECTION
LOR Alarm Output
(Pin 12)
Force Free Run
(Pin 13)
Q
(Pin 18)
Differential
FREE RUN
ANALOG
FILTER
VCXO
DIVIDER
DPFD
LVPECL
Outputs
Reference Input
(Pin 4)
CONTROL
QN
(Pin 16)
DIVIDER
CMOS
Reference Output
(Pin 7)
Select A
(Pin 5)
Select B
(Pin 6)
VCXO Enable
(Pin 1)
Absolute Maximum Rating
Table 1
Symbol
Vcc
Parameter
Minimum
3.0
Nominal
Maximum
3.6
Units
Notes
Power Supply Voltage
Input Voltage
Volts
V1
-0.5
5.5
Volts
Ts
Storage Temperature
-65
150
deg. C
Data Sheet #: SG043
Page 2 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Operating Specifications
Table 2
Symbol
Vcc
Icc
Parameter
Minimum
Nominal
Maximum
3.465
280
70
Units
Volts
mA
°C
Notes
1.0
Power Supply Voltage
Power Supply Current
Temperature Range
Free Run Accuracy
3.135
3.3
-
230
To
0
-
Ffr
-20
-32
-
-
20
ppm
ppm
Hz
Fcap
Fbw
Tjtol
Taq
Capture/pull-in range
Jitter Filter Bandwidth
Input Jitter Tolerance
Acquisition Time
-
32
-
10
-
-
6.25
-
µs
-
1
s
2.0
3.0
Trf
Output Rise and Fall Time (20% 80%)
100
225
350
ps
Features
Table 3
Parameter
Specifications
Notes
Alarms
LOR, LOL Status on seperate CMOS Outputs
TDEV
70 ps (typical)
800 ps (typical)
LVPECL
MTIE
VCXO Output Logic Type
Reference Output Logic Type
Package
CMOS
FR4 SM 1.025" x 1.0" x 0.429"
CMOS Input And Output Characteristics
Table 4
Symbol
VIH
Parameter
Minimum
Nominal
Maximum
Units
V
Notes
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
2
0
5.5
0.8
10
VIL
V
TIO
nS
pF
CO
Output Capacitance
10
VHO
VIO
High Level Output Voltage loh = 04mA
Low Level Output Voltage lo1 = 8mA
Input Reference Signal Pulse Width
2.4
Vcc Min.
Vcc Max.
0.4
TIR
12.5
nS
NOTES: 1.0: Requires external regulation and filter (22uF, 330 pF)
`
2.0: From a 20 ppm offset in reference frequency
3.0: 50Ω load biased to 1.3V
Data Sheet #: SG043
Page 3 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
LVPECL Output Characteristics
Table 5
Symbol
VOH
Parameter
Minimum
2.27
Nominal
2.34
Maximum
2.42
Units
V
Notes
High Level PECL Voltage
Low Level PECL Voltage
Output Capacitance
Differential Output Skew
VOL
1.49
1.51
1.68
V
CL
10
pF
ps
TSKEW
50
Output Jitter Specifications
Table 6
Jitter BW 10 Hz - 1 MHz
SONET Jitter BW 12 kHz - 20 MHz
Frequency (MHz)
125.0
pS (RMS)
20(typical)
m UI
pS (RMS)
1 (max), 0.3 (typical)
m UI
2.5 (typical)
0.125(max)
Output Programming
Alarm Status
Table 7
Table 9
Tristate Free Run Output
LOL Output LOR Output Alarm Output
0
1
0
0
X
1
Locked to reference selected (default)
Hi-Z Tristate condition
0
1
X
0
0
1
No alarm
Loss-of-Lock
Loss-of-Reference
Free run at nominal frequency
Pin Description
Table 8
Pin #
1
Connection
Enable/Disable
TCK
Description
Enable = 0, Disable = 1 for VCXO Ouputs, Default = 0 (for No Connect)
2
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
CMOS Reference Frequency Input
3
TDO
4
Reference In
Select A
5
Reference Frequency Select Pin, Default = 0 (for No Connect)
Reference Frequency Select Pin, Default = 0 (for No Connect)
Filtered Reference Output
6
Select B
7
Reference Out
Ground
8
Power Ground
9
Tri-State Enable
VCC
CMOS Output Tri-State enable (Hi-Z =1, Default = 0)
3.3V Supply Voltage.
10
11
12
13
14
15
16
17
18
Loss of Lock
Loss of Reference
Free Run
TDI
LOL Alarm Output
LOR Alarm Output
Force output frequency to Free Run (FR = 1, Default = 0)
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
VCXO differential LVPECL Output
TMS
VCXO Out
Signal Ground
VCXO Out
VCXO output ground (Shield)
VCXO differential LVPECL Output
Data Sheet #: SG043
Page 4 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Package Dimensions
Figure 2
Recommended Footprint Dimensions
Figure 3
Keep Out
Area
Data Sheet #: SG043
Page 5 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Tape and Reel Dimensions
Figure 4
Solder Profile
Figure 5
250
200
Temp
150
(Deg C)
100
50
0
1
2
3
4
5
6
7
8
Time (minutes)
Recommended Reflow Profile
Peak Temp:
217 Deg C
Max Rise Slope:
1.5 Deg C/Sec
Time Above 150 C: 100 Sec
Data Sheet #: SG043
Page 6 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Application
Figure 6
Typical Application of
Connor-Winfield’s
SCG4000 Series Timing Products
BITS
System
Signal
Line Cards
Input Select
Timing Card #1
S
A
B
A
CW’s SCG
4000
MUX
Clock out
RCV
Y
CW’s STM/MSTM module
Y
B
MUX
C
S
Timing Card #2
S
A
A
CW’s SCG
4000
Clock out
RCV
MUX
CW’s STM/MSTM module
Y
B
B
Y
MUX
C
S
System Select
Typical System Test Set-up
Figure 7
GPS or LORAN
Timing Source
This device supplies system time
information. It can be thought of as
supplying "absolute time" reference
information
Sample
M TIE Data for STM -S 3/M STM-S3
1.0E-6
T
re
y
f
picalresponse- 3000second
dat AP R 22 1998
kdh
tes
t
-
Jitterapplied
(
2
UI
@
10H
z)
e
Possible Choices Include
Stanford Research Model: FS700
Truetime Model XXX
100.0E-9
10
MTI
E
10.0E-9
1244-5.2 Mas
1244-5.2 Mas
1244-5.6 Mas
k
k
k
(A
(B
)
MHz
)
G
R253-5.4.4.3.2
1.0E-9
100
.0E-
3
1
.0E+
0
10.0E+0
10
0.0E+
0
1.0E+
3
10.0E+3
Observation Tim
e
(s
)
C
o
py
r
ight
1
9
9
8
Connor-Winf
ield
a
l
l
righ
ts
reserv
ed
Target System Under Test
External
Standards
Compliance
Documents
Reference
DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz
clock RZ with noise modulation
Arbitrary
Waveform
Generator
Input
Clock or BITS logic level
clock input (TTL, CMOS,
etc.)
MTIE, TDEV, Wander Transfer,
and Wander Generation Plots
Sample Wande
r
G
eneration
UI 10 Hz)
(
T
D
EV) for
S
TM/M STM-S 3
1.0E-6
Ty
ef dat
dh
p
i
calresponse
e A PR
-
300 second est itterapplied
0
t
-
J
(
2
@
r
k
221998
10
100.0E-9
MHz
. . . . ...
1
0.0E-9
TDE
V
G
G
R1244-Fig5.1
R1244-Fig5-3
1.0E-9
Arbitrary
Waveform
Generator
[Noise
100
.0E
-
12
0.0E
1
-
3
100.0E-
3
1.0E+0
Inte atio n Time (sec)
10.0E+0
100.0E+0
ight 1998 Connor-Winfielda lll rights re
1.0E+3
served
C
o
pyr
g
r
External
Reference
Input
Source]
Time-stamped ensemble
based on absolute time
reference (10MHz input)
10
MHz
DS1 rate [1.544 MHz] BITS Bipolar
Phase Error data output
DS-1, OC-3, OC-12 electrical or optical signals
External
Tektronix
SJ300E
10
Reference
HP53310A
Input
MHz
Modulation Analyzer / Time Interval Analyzer
Wander Analyzer data (IEEE-488)
External
Reference
Input
IEEE-488 Controller
Platform for software
HP 53305A Phase Analyzer
HP E1748A Sync
Measurement
TEKTRONIX SJ300E
Tektronix Wander Analyzer
Data Sheet #: SG043
Page 7 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4000 Series Typical MTIE
Figure 8
1.0E -9
100.0E -12
1.0E -3
10.0E -3
100.0E -3
1.0E +0
10.0E +0
100.0E +0
Observation W indow (Tau)
SCG4000 Series Typical TDEV
Figure 9
100.0E-12
10.0E-12
1.0E -3
10.0E-3
100.0E -3
1.0E +0
10.0E +0
Tau
Data Sheet #: SG043
Page 8 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG043
Page 9 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG043
Page 10 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG043
Page 11 of 12
Rev: P00
Date: 08/08/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Revision
Revision Date
Note
P00
08/08/02
Preliminary Release
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