BCM4339XKWBGT_技术文档

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Cypress Semiconductor Corporation

Document Number: 002-14784 Rev. *F

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Revised July 1, 2016

Preliminary Data Sheet

BCM4339

Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio

with Integrated Bluetooth 4.1 and FM Receiver

GENERAL DESCRIPTION

®

The Broadcom BCM4339 single-chip device provides

Using advanced design techniques and process

technology to reduce active and idle power, the

BCM4339 is designed to address the needs of mobile

devices that require minimal power consumption

and compact size. It includes a power management

unit which simplifies the system power topology and

allows for direct operation from a mobile platform

battery while maximizing battery life.

the highest level of integration for a mobile or

handheld wireless system with integrated single-

stream IEEE 802.11ac MAC/baseband/radio,

Bluetooth 4.1 and FM radio receiver. In IEEE 802.11ac

mode, the WLAN operation supports rates of MCS0–

MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80

MHz channels for data rates up to 433.3 Mbps. In

addition, all the rates specified in IEEE 802.11a/b/g/n

are supported. Included on-chip are 2.4 GHz and

5 GHz transmit amplifiers, and receive low-noise

amplifiers. Optional external PAs, LNAs, and antenna

diversity are also supported.

The BCM4339 implements highly sophisticated

enhanced collaborative coexistence hardware

mechanisms and algorithms, which ensure that

WLAN and Bluetooth collaboration is optimized for

maximum performance. In addition, coexistence

support for external radios (such as LTE cellular,

GPS, and WiMAX) is provided via an external

interface. As a result, enhanced overall quality for

simultaneous voice, video, and data transmission is

achieved.

For the WLAN section, several alternative host

interface options are included: an SDIO v3.0 interface

that can operate in 4b, 1b, or gSPI modes and a PCIe

Gen1 interface (3.0 compliant). For the Bluetooth

section, host interface options of a high-speed 4-wire

UART and USB 2.0 full-speed (12 Mbps) are

provided.

4339-DS106-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203

November 17, 2014

Figure 1: Functional Block Diagram

VIO VBAT

WL_REG_ON

5 GHz WLAN TX

FEM or

T/R

Switch

WLAN

Host I/F

PCIe

5 GHz WLAN RX

SDIO*/SPI

External

Coexistence I/F

COEX

2.4 GHz WLAN TX

FEM or

T/R

Switch

2.4 GHz WLAN/BT RX

CLK_REQ

BT_REG_ON

UART

CBF

BCM4339

Bluetooth TX

Bluetooth Host I/F

FM Rx Host I/F

USB 2.0

I²S

PCM

BT_DEV_WAKE

BT_HOST_WAKE

FM Rx

FM Audio Out

I²S

FM I/F

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

Printed in the U.S.A.

Broadcom^®, the pulse logo, Connecting everything^®, and the Connecting everything logo are among the

trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the

EU. Any other trademarks or trade names mentioned are the property of their respective owners.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,

intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,

pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES

THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL

WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-

INFRINGEMENT.

BCM4339 Preliminary Data Sheet

Revision History

FEATURES

•

Integrated ARMCR4^™processor with tightly coupled

memory for complete WLAN subsystem functionality,

minimizing the need to wake up the applications

processor for standard WLAN functions. This allows for

further minimization of power consumption, while

maintaining the ability to field upgrade with future

features. On-chip memory includes 768 KB SRAM and

640 KB ROM.

IEEE 802.11x Key Features

•

IEEE 802.11ac compliant.

Single-stream spatial multiplexing up to

433.3 Mbps data rate.

•

Supports 20, 40, and 80 MHz channels with

optional SGI (256 QAM modulation).

Full IEEE 802.11a/b/g/n legacy compatibility

with enhanced performance.

•

OneDriver^™software architecture for easy migration

from existing embedded WLAN and Bluetooth devices

as well as future devices.

Tx and Rx low-density parity check (LDPC)

support for improved range and power

efficiency.

Bluetooth and FM Key Features

•

Supports Rx space-time block coding

(STBC)

•

Complies with Bluetooth Core Specification Version 4.1

with provisions for supporting future specifications.

•

Supports IEEE 802.11ac/n beamforming.

•

Bluetooth Class 1 or Class 2 transmitter operation.

On-chip power amplifiers and low-noise

amplifiers for both bands.

Supports extended synchronous connections (eSCO),

for enhanced voice quality by allowing for retransmission

of dropped packets.

•

Support for optional front-end modules

(FEM) with external PAs and LNAs

•

Adaptive frequency hopping (AFH) for reducing radio

frequency interference.

Shared Bluetooth and WLAN receive signal

path eliminates the need for an external

power splitter while maintaining excellent

sensitivity for both Bluetooth and WLAN.

Interface support, host controller interface (HCI) using a

USB or high-speed UART interface and PCM for audio

data.

•

Internal fractional nPLL allows support for a

wide range of reference clock frequencies

•

USB 2.0 full-speed (12 Mbps) supported (FCFBGA and

WLCSP packages).

Supports IEEE 802.15.2 external

coexistence interface to optimize bandwidth

utilization with other co-located wireless

technologies such as LTE, GPS, or WiMAX

•

The FM unit supports HCI for communication.

Low power consumption improves battery life of

handheld devices.

•

Supports standard SDIO v3.0 (including

DDR50 mode at 50 MHz and SDR104 mode

at 208 MHz, 4-bit and 1-bit), and gSPI (48

MHz) host interfaces.

•

FM receiver: 65 MHz to 108 MHz FM bands; supports

the European radio data systems (RDS) and the North

American radio broadcast data system (RBDS)

standards.

•

Backward compatible with SDIO v2.0 host

interfaces.

•

Supports multiple simultaneous Advanced Audio

Distribution Profiles (A2DP) for stereo sound.

PCIe mode (FCBGA package only) complies

with PCI Express base specification revision

3.0 compliant Gen1 interface for ×1 lane and

power management base specification.

Automatic frequency detection for standard crystal and

TCXO values.

Supports serial flash interfaces.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 3

BCM4339 Preliminary Data Sheet

Revision History

FEATURES

• Security:

General Features

– WPA^™and WPA2^™(Personal) support for powerful

encryption and authentication

•

Supports battery voltage range from 3.0V to

5.25V supplies with internal switching

regulator.

– AES and TKIP in hardware for faster data encryption

and IEEE 802.11i compatibility

– Reference WLAN subsystem provides Cisco^®

Compatible Extensions (CCX, CCX 2.0, CCX 3.0,

CCX 4.0, CCX 5.0)

•

Programmable dynamic power management

OTP: 502 bytes of user-accessible memory

GPIOs: 12 on FCFBGA, nine on WLBGA,

and 16 on WLCSP

•

Package options:

– Reference WLAN subsystem provides Wi-Fi

Protected Setup (WPS)

– 160 ball FCFBGA (8 mm x 8 mm, 0.4 mm

pitch)

•

Worldwide regulatory support: Global products

supported with worldwide homologated design.

– 145 ball WLBGA (4.87 mm × 5.413 mm,

0.4 mm pitch)

– 286 bump WLCSP (4.87 mm × 5.413 mm,

0.2 mm pitch)

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 4

BCM4339 Preliminary Data Sheet

Revision History

Revision

Date

Change Description

4339-DS106-R

11/17/14

Updated:

•

Table 55: “SDIO Bus Input Timing Parameters (SDR Modes),” on

page 163.

4339-DS105-R

05/28/14

Updated:

•

The Features listed in the front matter of the document.

By changing all instances of Bluetooth 4.0 to Bluetooth 4.1

throughout the document.

•

By removing the word draft after all instances of IEEE 802.11ac

throughout the document.

•

“Features” on page 22.

“External 32.768 kHz Low-Power Oscillator” on page 34.

“Advanced Bluetooth/WLAN Coexistence” on page 46.

“SDIO v3.0” on page 73.

Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions,”

on page 105 by fixing an incorrect WLBGA ball. The second

instance of M12 was changed to M10.

•

Table 21: “WLAN GPIO Functions and Strapping Options,” on

page 114.

Table 24: “Host Interface Selection (WLBGA and WLCSP

Packages),” on page 115

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 5

BCM4339 Preliminary Data Sheet

Revision History

Revision

Date

Change Description

4339-DS104-R

04/02/14

Updated:

•

The cover page and the general features on page 6.

By deleting the HSIC interface throughout, leaving pin and signal

names unchanged.

•

By changing to PCI Express Base Specification (revision 3.0

compliant Gen1 interface) throughout.

•

“External Frequency Reference” on page 37.

Table 2: “Crystal Oscillator and External Clock — Requirements

and Performance,” on page 37.

•

“Frequency Selection” on page 39.

Figure 10: “Startup Signaling Sequence,” on page 48.

Figure 22: “UART Timing,” on page 66.

“One-Time Programmable Memory” on page 76.

Figure 50: “160-Ball FCFBGA (Top View),” on page 103 by

changing BT_VDDO to BT_VDDIO.

•

Figure 54: “286-Bump WLCSP (Bottom View),” on page 107.

Table 19: “286-Bump WLCSP Coordinates,” on page 108 by

changing BT_VDDO to BT_VDDIO.

•

Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions,”

on page 117 by changing BT_VDDO to BT_VDDIO and adding a

note to the GPIO pin description.

•

Table 31: “I/O States,” on page 134.

Table 34: “ESD Specifications,” on page 139.

Table 35: “Recommended Operating Conditions and DC

Characteristics,” on page 140 by changing C_INto C_OUT

.

•

Table 36: “Bluetooth Receiver RF Specifications,” on page 144 by

deleting what was footnote e, altering footnote b, and adding

footnote b to one additional place.

•

“Introduction” on page 155.

RSSI accuracy in Table 42: “WLAN 2.4 GHz Receiver

Performance Specifications,” on page 157 and Table 44: “WLAN

5 GHz Receiver Performance Specifications,” on page 164.

•

Table 43: “WLAN 2.4 GHz Transmitter Performance

Specifications,” on page 162 and the note preceding it.

Table 45: “WLAN 5 GHz Transmitter Performance

Specifications,” on page 168 and the note preceding it.

Section 18: “Internal Regulator Electrical Specifications,” on page

170.

•

“WLAN Current Consumption” on page 175.

Figure 65: “SDIO Bus Output Timing (SDR Modes up to 100

MHz),” on page 183.

•

Figure 66: “SDIO Bus Output Timing (SDR Modes 100 MHz to

208 MHz),” on page 183.

4339-DS103-R

11/08/13

Updated:

•

BT_VDDO to BT_VDDIO throughout the document.

Table 34: “ESD Specifications,” on page 140.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 6

BCM4339 Preliminary Data Sheet

Revision History

Revision

Date

Change Description

4339-DS102-R

07/02/13

Updated:

•

Figure 1: “Functional Block Diagram,” on page 2.

Figure 2: “BCM4339 Block Diagram,” on page 22.

Figure 5: “Typical Power Topology for BCM4339,” on page 29.

Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions,”

on page 118.

•

Table 35: “Recommended Operating Conditions and DC

Characteristics,” on page 141 by changing DC supply voltage for

VBAT from 4.8V to 5.25V.

Table 47: “Core Buck Switching Regulator (CBUCK)

Specifications,” on page 171 by changing input supply voltage

(DC) Max from 4.8V to 5.25V.

•

Table 48: “LDO3P3 Specifications,” on page 172 by changing

input supply voltage, VIN Max from 4.8V to 5.25V.

Table 49: “BTLDO2P5 Specifications,” on page 173 by changing

input supply voltage Max from 4.8V to 5.25V.

Table 52: “Typical WLAN Power Consumption (External PA

configuration),” on page 176.

Table 53: “Bluetooth BLE and FM Current Consumption,” on page

178.

Section 24: “Ordering Information,” on page 202.

4339-DS101-R

03/12/13

Updated:

•

Package option dimensions on page 4.

Table 19: “286-Bump WLCSP Coordinates,” on page 109 by

replacing the PACKAGEOPTION_0 through

PACKAGEOPTION_3 signal names with VSSC.

•

The Power Rail column in Table 31: “I/O States,” on page 135.

Table 32: “Absolute Maximum Ratings,” on page 139.

Table 35: “Recommended Operating Conditions and DC

Characteristics,” on page 141.

•

Table 43: “WLAN 2.4 GHz Transmitter Performance

Specifications,” on page 163.

Table 45: “WLAN 5 GHz Transmitter Performance

Specifications,” on page 169.

•

“WLAN Current Consumption” on page 176.

Table 53: “Bluetooth BLE and FM Current Consumption,” on page

178.

•

Figure 77: “145-Ball WLBGA Package Mechanical Information,”

on page 198.

•

Section 24: “Ordering Information,” on page 202.

4339-DS100-R

02/15/13

Initial release.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 7

BCM4339 Preliminary Data Sheet

Table of Contents

About This Document ................................................................................................................................ 18

Purpose and Audience.......................................................................................................................... 18

Acronyms and Abbreviations................................................................................................................. 18

Document Conventions......................................................................................................................... 18

References............................................................................................................................................ 18

Technical Support ...................................................................................................................................... 19

Section 1: Overview .......................................................................................................... 20

Overview...................................................................................................................................................... 20

Features....................................................................................................................................................... 22

Standards Compliance...............................................................................................................................23

Mobile Phone Usage Model....................................................................................................................... 24

Section 2: Power Supplies and Power Management ..................................................... 25

Power Supply Topology............................................................................................................................. 25

PMU Features.............................................................................................................................................. 25

WLAN Power Management........................................................................................................................ 27

PMU Sequencing ........................................................................................................................................ 28

Power-Off Shutdown.................................................................................................................................. 29

Power-Up/Power-Down/Reset Circuits..................................................................................................... 29

Section 3: Frequency References.................................................................................... 30

Crystal Interface and Clock Generation ................................................................................................... 30

External Frequency Reference.................................................................................................................. 31

Frequency Selection .................................................................................................................................. 33

External 32.768 kHz Low-Power Oscillator .............................................................................................. 34

Section 4: Bluetooth + FM Subsystem Overview ........................................................... 35

Features....................................................................................................................................................... 35

Bluetooth Radio.......................................................................................................................................... 37

Transmit ................................................................................................................................................ 37

Digital Modulator ................................................................................................................................... 37

Digital Demodulator and Bit Synchronizer............................................................................................. 37

Power Amplifier..................................................................................................................................... 37

Receiver................................................................................................................................................ 38

Digital Demodulator and Bit Synchronizer............................................................................................. 38

Receiver Signal Strength Indicator........................................................................................................ 38

Local Oscillator Generation................................................................................................................... 38

Calibration ............................................................................................................................................. 38

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 8

BCM4339 Preliminary Data Sheet

Table of Contents

Section 5: Bluetooth Baseband Core .............................................................................. 39

Bluetooth 4.1 Features...............................................................................................................................39

Bluetooth Low Energy ...............................................................................................................................39

Link Control Layer...................................................................................................................................... 40

Test Mode Support..................................................................................................................................... 40

Bluetooth Power Management Unit.......................................................................................................... 41

RF Power Management ........................................................................................................................ 41

Host Controller Power Management ..................................................................................................... 41

BBC Power Management...................................................................................................................... 43

FM Power Management........................................................................................................................ 43

Wideband Speech................................................................................................................................. 43

Packet Loss Concealment..................................................................................................................... 44

Audio Rate-Matching Algorithms........................................................................................................... 44

Codec Encoding.................................................................................................................................... 45

Multiple Simultaneous A2DP Audio Streams........................................................................................ 45

FM Over Bluetooth ................................................................................................................................ 45

Burst Buffer Operation........................................................................................................................... 45

Adaptive Frequency Hopping.................................................................................................................... 45

Advanced Bluetooth/WLAN Coexistence................................................................................................. 46

Fast Connection (Interlaced Page and Inquiry Scans) ........................................................................... 46

Section 6: Microprocessor and Memory Unit for Bluetooth.......................................... 47

RAM, ROM, and Patch Memory................................................................................................................. 47

Reset............................................................................................................................................................ 47

Section 7: Bluetooth Peripheral Transport Unit ............................................................. 48

SPI Interface................................................................................................................................................ 48

SPI/UART Transport Detection.................................................................................................................. 48

PCM Interface.............................................................................................................................................. 49

Slot Mapping ......................................................................................................................................... 49

Frame Synchronization ......................................................................................................................... 49

Data Formatting..................................................................................................................................... 49

Wideband Speech Support ................................................................................................................... 50

Multiplexed Bluetooth and FM Over PCM............................................................................................. 50

Burst PCM Mode................................................................................................................................... 50

PCM Interface Timing............................................................................................................................ 51

Short Frame Sync, Master Mode ................................................................................................... 51

Short Frame Sync, Slave Mode ..................................................................................................... 52

Long Frame Sync, Master Mode.................................................................................................... 53

Long Frame Sync, Slave Mode...................................................................................................... 54

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Table of Contents

Short Frame Sync, Burst Mode...................................................................................................... 55

Long Frame Sync, Burst Mode ...................................................................................................... 56

USB Interface.............................................................................................................................................. 57

Features................................................................................................................................................ 57

Operation............................................................................................................................................... 57

USB Hub and UHE Support .................................................................................................................. 58

USB Full-Speed Timing......................................................................................................................... 58

UART Interface............................................................................................................................................ 59

I²S Interface................................................................................................................................................. 61

I²S Timing.............................................................................................................................................. 62

Section 8: FM Receiver Subsystem................................................................................. 64

FM Radio ..................................................................................................................................................... 64

Digital FM Audio Interfaces ....................................................................................................................... 64

FM Over Bluetooth ..................................................................................................................................... 64

eSCO............................................................................................................................................................ 64

Wide Band Speech Link............................................................................................................................. 65

A2DP............................................................................................................................................................ 65

Autotune and Search Algorithms ............................................................................................................. 65

Audio Features ........................................................................................................................................... 66

RDS/RBDS................................................................................................................................................... 69

Section 9: WLAN Global Functions ................................................................................. 70

WLAN CPU and Memory Subsystem........................................................................................................ 70

One-Time Programmable Memory............................................................................................................ 70

GPIO Interface............................................................................................................................................. 71

External Coexistence Interface ................................................................................................................. 71

UART Interface............................................................................................................................................ 72

JTAG Interface............................................................................................................................................ 72

SPROM Interface (FCBGA Package only) ............................................................................................... 72

Section 10: WLAN Host Interfaces................................................................................... 73

SDIO v3.0..................................................................................................................................................... 73

SDIO Pins.............................................................................................................................................. 73

Generic SPI Mode....................................................................................................................................... 75

SPI Protocol .......................................................................................................................................... 76

Command Structure....................................................................................................................... 77

Write............................................................................................................................................... 77

Write/Read ..................................................................................................................................... 77

Read............................................................................................................................................... 77

Status............................................................................................................................................. 78

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Table of Contents

gSPI Host-Device Handshake............................................................................................................... 80

Boot-Up Sequence................................................................................................................................ 80

PCI Express Interface (FCBGA Package Only)........................................................................................ 83

Transaction Layer Interface................................................................................................................... 84

Data Link Layer..................................................................................................................................... 84

Physical Layer....................................................................................................................................... 84

Logical Subblock................................................................................................................................... 84

Scrambler/Descrambler......................................................................................................................... 84

8B/10B Encoder/Decoder...................................................................................................................... 85

Elastic FIFO........................................................................................................................................... 85

Electrical Subblock................................................................................................................................ 85

Configuration Space.............................................................................................................................. 85

Section 11: Wireless LAN MAC and PHY ........................................................................ 86

IEEE 802.11ac MAC .................................................................................................................................... 86

PSM ............................................................................................................................................... 87

WEP............................................................................................................................................... 87

TXE................................................................................................................................................ 88

RXE................................................................................................................................................ 88

IFS.................................................................................................................................................. 88

TSF ................................................................................................................................................ 89

NAV................................................................................................................................................ 89

MAC-PHY Interface........................................................................................................................ 89

IEEE 802.11ac PHY..................................................................................................................................... 90

Section 12: WLAN Radio Subsystem ............................................................................. 92

Receiver Path.............................................................................................................................................. 92

Transmit Path.............................................................................................................................................. 92

Calibration................................................................................................................................................... 92

Section 13: Pinout and Signal Descriptions ................................................................... 94

Ball Maps..................................................................................................................................................... 94

Pin Lists....................................................................................................................................................... 97

Signal Descriptions.................................................................................................................................. 105

WLAN GPIO Signals and Strapping Options ......................................................................................... 114

Multiplexed Bluetooth GPIO Signals................................................................................................... 116

GPIO/SDIO Alternative Signal Functions ............................................................................................... 118

I/O States................................................................................................................................................... 119

Section 14: DC Characteristics ...................................................................................... 122

Absolute Maximum Ratings .................................................................................................................... 122

Environmental Ratings ............................................................................................................................ 123

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Table of Contents

Electrostatic Discharge Specifications .................................................................................................. 123

Recommended Operating Conditions and DC Characteristics ........................................................... 124

Section 15: Bluetooth RF Specifications ...................................................................... 126

Section 16: FM Receiver Specifications........................................................................ 133

Section 17: WLAN RF Specifications ............................................................................ 138

Introduction............................................................................................................................................... 138

2.4 GHz Band General RF Specifications............................................................................................... 138

WLAN 2.4 GHz Receiver Performance Specifications .......................................................................... 139

WLAN 2.4 GHz Transmitter Performance Specifications ..................................................................... 143

WLAN 5 GHz Receiver Performance Specifications ............................................................................. 145

WLAN 5 GHz Transmitter Performance Specifications ........................................................................ 149

General Spurious Emissions Specifications ......................................................................................... 150

Section 18: Internal Regulator Electrical Specifications ............................................. 151

Core Buck Switching Regulator.............................................................................................................. 151

3.3V LDO (LDO3P3) .................................................................................................................................. 152

2.5V LDO (BTLDO2P5) ............................................................................................................................. 153

CLDO ......................................................................................................................................................... 154

LNLDO ....................................................................................................................................................... 155

Section 19: System Power Consumption...................................................................... 156

WLAN Current Consumption................................................................................................................... 156

Bluetooth and FM Current Consumption............................................................................................... 158

Section 20: Interface Timing and AC Characteristics.................................................. 159

SDIO/gSPI Timing..................................................................................................................................... 159

SDIO Default Mode Timing ................................................................................................................. 159

SDIO High-Speed Mode Timing.......................................................................................................... 161

SDIO Bus Timing Specifications in SDR Modes ................................................................................. 162

Clock Timing ................................................................................................................................ 162

Device Input Timing ..................................................................................................................... 163

Device Output Timing................................................................................................................... 164

SDIO Bus Timing Specifications in DDR50 Mode............................................................................... 166

Data Timing, DDR50 Mode.......................................................................................................... 167

gSPI Signal Timing.............................................................................................................................. 168

PCI Express Interface Parameters.......................................................................................................... 169

JTAG Timing ............................................................................................................................................. 171

Section 21: Power-Up Sequence and Timing ............................................................... 172

Sequencing of Reset and Regulator Control Signals ........................................................................... 172

Description of Control Signals............................................................................................................. 172

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Table of Contents

Control Signal Timing Diagrams.......................................................................................................... 173

Section 22: Package Information................................................................................... 175

Package Thermal Characteristics........................................................................................................... 175

Junction Temperature Estimation and PSI_JTVersus THETA_JC........................................................... 175

Environmental Characteristics................................................................................................................ 175

Section 23: Mechanical Information .............................................................................. 176

Section 24: Ordering Information .................................................................................. 181

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 13

BCM4339 Preliminary Data Sheet

List of Figures

Figure 1: Functional Block Diagram................................................................................................................... 2

Figure 2: BCM4339 Block Diagram ................................................................................................................. 21

Figure 3: Typical Power Topology for BCM4339 ............................................................................................. 26

Figure 4: Recommended Oscillator Configuration ........................................................................................... 30

Figure 5: Recommended Circuit to Use with an External Reference Clock..................................................... 31

Figure 6: Startup Signaling Sequence ............................................................................................................. 42

Figure 7: CVSD Decoder Output Waveform Without PLC............................................................................... 44

Figure 8: CVSD Decoder Output Waveform After Applying PLC..................................................................... 44

Figure 9: Functional Multiplex Data Diagram................................................................................................... 50

Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 51

Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 52

Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 53

Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 54

Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)......................................................... 55

Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 56

Figure 16: USB Compounded Device Configuration ....................................................................................... 57

Figure 17: USB Full-Speed Timing .................................................................................................................. 59

Figure 18: UART Timing .................................................................................................................................. 60

Figure 19: I²S Transmitter Timing.................................................................................................................... 63

Figure 20: I²S Receiver Timing........................................................................................................................ 63

Figure 21: Example Blend/Switch Usage......................................................................................................... 66

Figure 22: Example Blend/Switch Separation.................................................................................................. 67

Figure 23: Example Soft Mute Characteristic .................................................................................................. 68

Figure 24: Broadcom GCI or BT-SIG Mode LTE Coexistence Interface for BCM4339 ................................... 71

Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 74

Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 74

Figure 27: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 75

Figure 28: gSPI Write Protocol ........................................................................................................................ 76

Figure 29: gSPI Read Protocol ........................................................................................................................ 76

Figure 30: gSPI Command Structure............................................................................................................... 77

Figure 31: gSPI Signal Timing Without Status (32-bit Big Endian).................................................................. 78

Figure 32: gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) ..................................... 79

Figure 33: WLAN Boot-Up Sequence.............................................................................................................. 82

Figure 34: PCI Express Layer Model............................................................................................................... 83

Figure 35: WLAN MAC Architecture ................................................................................................................ 86

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 14

BCM4339 Preliminary Data Sheet

List of Figures

Figure 36: WLAN PHY Block Diagram............................................................................................................. 91

Figure 37: Radio Functional Block Diagram .................................................................................................... 93

Figure 38: 160-Ball FCFBGA (Top View)......................................................................................................... 94

Figure 39: 145-Ball WLBGA (Top View) .......................................................................................................... 95

Figure 40: 286-Bump WLCSP (Bottom View).................................................................................................. 96

Figure 41: Port Locations for Bluetooth Testing............................................................................................. 126

Figure 42: Port Locations Showing Optional ePA and eLNA (Applies to 2.4 GHz and 5 GHz) ..................... 138

Figure 43: SDIO Bus Timing (Default Mode) ................................................................................................. 159

Figure 44: SDIO Bus Timing (High-Speed Mode).......................................................................................... 161

Figure 45: SDIO Clock Timing (SDR Modes) ................................................................................................ 162

Figure 46: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 163

Figure 47: SDIO Bus Output Timing (SDR Modes up to 100 MHz)............................................................... 164

Figure 48: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)..................................................... 164

Figure 49: ∆tOP Consideration for Variable Data Window (SDR 104 Mode) ................................................ 165

Figure 50: SDIO Clock Timing (DDR50 Mode).............................................................................................. 166

Figure 51: SDIO Data Timing (DDR50 Mode) ............................................................................................... 167

Figure 52: gSPI Timing .................................................................................................................................. 168

Figure 53: WLAN = ON, Bluetooth = ON ....................................................................................................... 173

Figure 54: WLAN = OFF, Bluetooth = OFF.................................................................................................... 173

Figure 55: WLAN = ON, Bluetooth = OFF ..................................................................................................... 174

Figure 56: WLAN = OFF, Bluetooth = ON .................................................................................................... 174

Figure 57: 160-Ball FCFBGA Package Mechanical Information.................................................................... 176

Figure 58: 145-Ball WLBGA Package Mechanical Information ..................................................................... 177

Figure 59: WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up............................ 178

Figure 60: 286-Bump WLCSP Package Mechanical Information .................................................................. 179

Figure 61: WLCSP Keep-out Areas for PCB Layout—Bottom View with Bumps Facing Up......................... 180

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

List of Tables

Table 1: Power-Up/Power-Down/Reset Control Signals.................................................................................. 29

Table 2: Crystal Oscillator and External Clock—Requirements and Performance ......................................... 31

Table 3: External 32.768 kHz Sleep Clock Specifications ............................................................................... 34

Table 4: Power Control Pin Description........................................................................................................... 41

Table 5: SPI to UART Signal Mapping............................................................................................................. 48

Table 6: PCM Interface Timing Specifications (Short Frame Sync, Master Mode).......................................... 51

Table 7: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)............................................ 52

Table 8: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) .......................................... 53

Table 9: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) ............................................ 54

Table 10: PCM Burst Mode (Receive Only, Short Frame Sync)...................................................................... 55

Table 11: PCM Burst Mode (Receive Only, Long Frame Sync) ...................................................................... 56

Table 12: USB Full-Speed Timing Specifications ............................................................................................ 59

Table 13: Example of Common Baud Rates.................................................................................................... 60

Table 14: UART Timing Specifications ............................................................................................................ 60

Table 15: Timing for I²S Transmitters and Receivers...................................................................................... 62

Table 16: SDIO Pin Description....................................................................................................................... 73

Table 17: gSPI Status Field Details ................................................................................................................. 79

Table 18: gSPI Registers................................................................................................................................. 80

Table 19: 286-Bump WLCSP Coordinates ...................................................................................................... 97

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions.................................................................... 105

Table 21: WLAN GPIO Functions and Strapping Options ............................................................................. 114

Table 22: SDIO/gSPI I/O Voltage Selection (All Packages) .......................................................................... 114

Table 23: Host Interface Selection (FCBGA Package only) .......................................................................... 115

Table 24: Host Interface Selection (WLBGA and WLCSP Packages)........................................................... 115

Table 25: OTP/SPROM Select ...................................................................................................................... 115

Table 26: GPIO Multiplexing Matrix ............................................................................................................... 116

Table 27: Multiplexed GPIO Signals.............................................................................................................. 117

Table 28: BCM4339 GPIO/SDIO Alternative Signal Functions .................................................................... 118

Table 29: I/O States....................................................................................................................................... 119

Table 30: Absolute Maximum Ratings ........................................................................................................... 122

Table 31: Environmental Ratings................................................................................................................... 123

Table 32: ESD Specifications ........................................................................................................................ 123

Table 33: Recommended Operating Conditions and DC Characteristics...................................................... 124

Table 34: Bluetooth Receiver RF Specifications............................................................................................ 127

Table 35: Bluetooth Transmitter RF Specifications........................................................................................ 130

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BCM4339 Preliminary Data Sheet

List of Tables

Table 36: Local Oscillator Performance......................................................................................................... 132

Table 37: BLE RF Specifications ................................................................................................................... 132

Table 38: FM Receiver Specifications ........................................................................................................... 133

Table 39: 2.4 GHz Band General RF Specifications...................................................................................... 138

Table 40: WLAN 2.4 GHz Receiver Performance Specifications .................................................................. 139

Table 41: WLAN 2.4 GHz Transmitter Performance Specifications .............................................................. 143

Table 42: WLAN 5 GHz Receiver Performance Specifications ..................................................................... 145

Table 43: WLAN 5 GHz Transmitter Performance Specifications ................................................................. 149

Table 44: General Spurious Emissions Specifications .................................................................................. 150

Table 45: Core Buck Switching Regulator (CBUCK) Specifications.............................................................. 151

Table 46: LDO3P3 Specifications.................................................................................................................. 152

Table 47: BTLDO2P5 Specifications ............................................................................................................. 153

Table 48: CLDO Specifications...................................................................................................................... 154

Table 49: LNLDO Specifications.................................................................................................................... 155

Table 50: Typical WLAN Current Consumption (BCM4339 Current Only) .................................................... 156

Table 51: Bluetooth BLE and FM Current Consumption................................................................................ 158

Table 52: SDIO Bus Timing Parameters (Default Mode)............................................................................... 159

Table 53: SDIO Bus Timing Parameters (High-Speed Mode) ....................................................................... 161

Table 54: SDIO Bus Clock Timing Parameters (SDR Modes)....................................................................... 162

Table 55: SDIO Bus Input Timing Parameters (SDR Modes)........................................................................ 163

Table 56: SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)............................................. 164

Table 57: SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) .................................. 165

Table 58: SDIO Bus Clock Timing Parameters (DDR50 Mode) .................................................................... 166

Table 59: SDIO Bus Timing Parameters (DDR50 Mode) .............................................................................. 167

Table 60: gSPI Timing Parameters................................................................................................................ 168

Table 61: PCI Express Interface Parameters ................................................................................................ 169

Table 62: JTAG Timing Characteristics ......................................................................................................... 171

Table 63: Package Thermal Characteristics.................................................................................................. 175

Broadcom^®

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BCM4339 Preliminary Data Sheet

About This Document

Purpose and Audience

This data sheet provides details on the functional, operational, and electrical characteristics for the Broadcom^®

BCM4339. It is intended for hardware design, application, and OEM engineers.

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and

other terms used in Broadcom documents, go to http://www.broadcom.com/press/glossary.php.

Document Conventions

The following conventions may be used in this document:

Convention

Description

Bold

User input and actions: for example, type exit, click OK, press ALT+C

Monospace

Code: #include <iostream>

HTML: <td rowspan = 3>

Command line commands and parameters: wl [-l] <command>

< >

[ ]

Placeholders for required elements: enter your <username> or wl <command>

Indicates optional command-line parameters: wl [-l]

Indicates bit and byte ranges (inclusive): [0:3] or [7:0]

References

The references in this section may be used in conjunction with this document.

Note: Broadcom provides customer access to technical documentation and software through its

Customer Support Portal (CSP) and Downloads & Support site (see Technical Support).

For Broadcom documents, replace the “xx” in the document number with the largest number available in the

repository to ensure that you have the most current version of the document.

Document (or Item) Name

Number

Source

[1] Bluetooth MWS Coexistence 2-wire Transport Interface –

www.bluetooth.com

Specification

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 18

BCM4339 Preliminary Data Sheet

Technical Support

Broadcom provides customer access to a wide range of information, including technical documentation,

schematic diagrams, product bill of materials, PCB layout information, and software updates through its

customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering

support representative.

In addition, Broadcom provides other product support through its Downloads & Support site

(http://www.broadcom.com/support/).

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Overview

Section 1: Overview

Overview

The Broadcom^®BCM4339 single-chip device provides the highest level of integration for a mobile or handheld

wireless system, with integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio, Bluetooth 4.1 + enhanced data

rate (EDR), and FM receiver.

It provides a small form-factor solution with minimal external components to drive down cost for mass volumes

and allows for handheld device flexibility in size, form, and function. Comprehensive power management

circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal

power consumption and reliable operation.

The following figure shows the interconnect of all the major physical blocks in the BCM4339 and their associated

external interfaces, which are described in greater detail in the following sections.

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BCM4339 Preliminary Data Sheet

Features

The BCM4339 supports the following features:

•

IEEE 802.11a/b/g/n/ac dual-band radio with virtual-simultaneous dual-band operation

Bluetooth v4.1 + EDR with integrated Class 1 PA

Concurrent Bluetooth, FM (RX) RDS/RBDS, and WLAN operation

On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality

WLAN host interface options:

– SDIO v3.0 (1-bit/4-bit)—up to 208 MHz clock rate in SDR104 mode

– gSPI—up to 48 MHz clock rate

•

BT host digital interface (which can be used concurrently with the above interfaces):

– UART (up to 4 Mbps)

•

BT supports full-speed USB version 1.1 for FCBGA package.

ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN

receptions

•

I²S/PCM for FM/BT audio, HCI for FM block control

HCI high-speed UART (H4, H4+, H5) transport support

Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air

coding, both through I²S and PCM interface)

•

Bluetooth SmartAudio^®technology improves voice and music quality to headsets

Bluetooth low-power inquiry and page scan

Bluetooth Low Energy (BLE) support

Bluetooth Packet Loss Concealment (PLC)

Bluetooth Wide Band Speech (WBS)

FM advanced internal antenna support

FM auto search/tuning functions

FM multiple audio routing options: I²S, PCM, eSCO, and A2DP

FM mono-stereo blend and switch, and soft mute support

FM audio pause detection support

Audio rate-matching algorithms

Multiple simultaneous A2DP audio streams

FM over Bluetooth operation and on-chip stereo headset emulation (SBC)

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Standards Compliance

The BCM4339 supports the following standards:

•

Bluetooth 2.1 + EDR

Bluetooth 3.0

Bluetooth 4.1 (Bluetooth Low Energy)

65 MHz to 108 MHz FM bands (US, Europe, and Japan)

IEEE802.11ac single-stream mandatory and optional requirements for 20 MHz, 40 MHz, and 80 MHz

channels

•

IEEE 802.11n—Handheld Device Class (Section 11)

IEEE 802.11a

IEEE 802.11b

IEEE 802.11g

IEEE 802.11d

IEEE 802.11h

IEEE 802.11i

Security:

– WEP

– WPA^™Personal

– WPA2^™Personal

– WMM

– WMM-PS (U-APSD)

– WMM-SA

– AES (Hardware Accelerator)

– TKIP (HW Accelerator)

– CKIP (SW Support)

•

Proprietary Protocols:

– CCXv2

– CCXv3

– CCXv4

– CCXv5

IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Mobile Phone Usage Model

The BCM4339 will support the following future drafts/standards:

•

IEEE 802.11r—Fast Roaming (between APs)

IEEE 802.11w—Secure Management Frames

IEEE 802.11 Extensions:

– IEEE 802.11e QoS Enhancements (as per the WMM^®specification is already supported)

– IEEE 802.11h 5 GHz Extensions

– IEEE 802.11i MAC Enhancements

– IEEE 802.11k Radio Resource Measurement

Mobile Phone Usage Model

The BCM4339 incorporates a number of unique features to simplify integration into mobile phone platforms. Its

flexible PCM and UART interfaces enable it to transparently connect with existing platform circuits. In addition,

the TCXO and LPO inputs allow the use of existing handset features to further minimize the size, power, and

cost of the complete system.

•

The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid

interfacing to single or multiple external codec devices.

The UART interface supports hardware flow control with tight integration to power-control sideband

signaling to support the lowest power operation.

The crystal oscillator interface accommodates any of the typical reference frequencies used by mobile

platform architectures.

•

FM digital interfaces can use either I²S or PCM.

The highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions

output regardless of the state of operation. It has been fully characterized in the global cellular bands.

•

The transceiver design has excellent blocking and intermodulation performance in the presence of a

cellular transmission (LTE, GSM^®, GPRS, CDMA, WCDMA, or iDEN).

The BCM4339 is designed to directly interface with new and existing handset platform designs.

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Power Supplies and Power Management

Section 2: Power Supplies and Power

Management

Power Supply Topology

One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the

BCM4339. All regulators are programmable via the PMU. These blocks simplify power supply design for

Bluetooth, WLAN, and FM functions in embedded designs.

A single VBAT (3.0V to 5.25V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional

voltages being provided by the regulators in the BCM4339.

Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the

respective section out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are

deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted.

The CLDO and LNLDO may be turned off and on based on the dynamic demands of the digital baseband.

The BCM4339 allows for an extremely low power-consumption mode by completely shutting down the CBUCK,

CLDO, and LNLDO regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators

that are supplied by the system VIO supply) provide the BCM4339 with all the voltages it requires, further

reducing leakage currents.

PMU Features

•

VBAT to 1.35V (275 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator

VBAT to 3.3V (200 mA nominal, 450 mA maximum) LDO3P3

VBAT to 2.5V (15 mA nominal, 70 mA maximum) BTLDO2P5

1.35V to 1.2V (100 mA nominal, 150 mA maximum) LNLDO

1.35V to 1.2V (175 mA nominal, 300 mA maximum) CLDO with bypass mode for deep-sleep

Additional internal LDOs (not externally accessible)

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November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

WLAN Power Management

The BCM4339 has been designed with the stringent power consumption requirements of mobile devices in

mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell

libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM4339 integrated

RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is

leakage current only. Additionally, the BCM4339 includes an advanced WLAN power management unit (PMU)

sequencer. The PMU sequencer provides significant power savings by putting the BCM4339 into various power

management states appropriate to the current environment and activities that are being performed. The power

management unit enables and disables internal regulators, switches, and other blocks based on a computation

of the required resources and a table that describes the relationship between resources and the time needed to

enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters

(running at the 32.768 kHz LPO clock frequency) in the PMU sequencer are used to turn on and turn off

individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the

current mode. Slower clock speeds are used wherever possible.

The BCM4339 WLAN power states are described as follows:

•

Active mode— All WLAN blocks in the BCM4339 are powered up and fully functional with active carrier

sensing and frame transmission and receiving. All required regulators are enabled and put in the most

efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.

Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of

the BCM4339 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are

shut down to reduce active power consumption to the minimum. The 32.768 kHz LPO clock is available

only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip

and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.

•

Deep-sleep mode—Most of the chip, including both analog and digital domains, and most of the regulators

are powered off. Logic states in the digital core are saved and preserved into a retention memory in the

always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU

timers, an external interrupt, or a host resume through the SDIO bus, logic states in the digital core are

restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.

Power-down mode—The BCM4339 is effectively powered off by shutting down all internal regulators. The

chip is brought out of this mode by external logic reenabling the internal regulators.

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BCM4339 Preliminary Data Sheet

PMU Sequencing

The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various

system resources based on a computation of the required resources and a table that describes the relationship

between resources and the time needed to enable and disable them.

Resource requests may come from several sources: clock requests from cores, the minimum resources defined

in the ResourceMin register, and the resources requested by any active resource request timers. The PMU

sequencer maps clock requests into a set of resources required to produce the requested clocks.

Each resource is in one of four states (enabled, disabled, transition_on, and transition_off) and has a timer that

contains 0 when the resource is enabled or disabled and a nonzero value in the transition states. The timer is

loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be

enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state

changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can

go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go

immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the

immediate transition or the timer load-decrement sequence.

During each clock cycle, the PMU sequencer performs the following actions:

•

Computes the required resource set based on requests and the resource dependency table.

Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the

ResourcePending bit for the resource and inverts the ResourceState bit.

•

Compares the request with the current resource status and determines which resources must be enabled

or disabled.

Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no

powered up dependents.

Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its

dependencies enabled.

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Power-Off Shutdown

The BCM4339 provides a low-power shutdown feature that allows the device to be turned off while the host, and

any other devices in the system, remain operational. When the BCM4339 is not needed in the system,

VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM4339 to be effectively

off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected

to the I/O.

During a low-power shut-down state, the provided VDDIO remains applied to the BCM4339, all outputs are

tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal

operation. This is done to prevent current paths or create loading on any digital signals in the system, and

enables the BCM4339 to be fully integrated in an embedded device and take full advantage of the lowest power-

savings modes.

When the BCM4339 is powered on from this state, it is the same as a normal power-up, and the device does

not retain any information about its state from before it was powered down.

Power-Up/Power-Down/Reset Circuits

The BCM4339 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the

internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals

and the required power-up sequences, see Section 21: “Power-Up Sequence and Timing,” on page 172.

Table 1: Power-Up/Power-Down/Reset Control Signals

Signal

Description

WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also

OR-gated with the BT_REG_ON input to control the internal BCM4339 regulators. When this

pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is

low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the

regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by

default. It can be disabled through programming.

BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down

the internal BCM4339 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators

will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default.

It can be disabled through programming.

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Frequency References

Section 3: Frequency References

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative,

an external frequency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower

power mode timing.

Crystal Interface and Clock Generation

The BCM4339 can use an external crystal to provide a frequency reference. The recommended configuration

for the crystal oscillator, including all external components, is shown in Figure 4. Consult the reference

schematics for the latest configuration and recommended components.

Figure 4: Recommended Oscillator Configuration

C *

WRF_XTAL_IN

37.4 MHz

C *

X ohms *

WRF_XTAL_OUT

* Values determined by crystal drive

level. See reference schematics for details.

A fractional-N synthesizer in the BCM4339 generates the radio frequencies, clocks, and data/packet timing,

enabling the BCM4339 to operate using a wide selection of frequency references.

For SDIO applications, the recommended default frequency reference is a 37.4 MHz crystal. The signal

characteristics for the crystal interface are listed in Table 2 on page 31.

Note: Although the fractional-N synthesizer can support alternative reference frequencies,

frequencies other than the default require support to be added in the driver, plus additional extensive

system testing. Contact Broadcom for details.

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

External Frequency Reference

As an alternative to a crystal, an external precision frequency reference can be used. The recommended default

frequency is 37.4 MHz. This must meet the phase noise requirements listed in Table 2.

If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling

capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned off when the

BCM4339 goes into sleep mode. When the clock buffer turns on and off, there will be a small impedance

variation. Power must be supplied to the WRF_XTAL_BUCK_VDD1P5 pin.

Figure 5: Recommended Circuit to Use with an External Reference Clock

1000 pF

Reference

WRF_XTAL_IN

Clock

NC

WRF_XTAL_OUT

Table 2: Crystal Oscillator and External Clock—Requirements and Performance

External Frequency

Crystal^a

Reference^{b c}

Parameter

Conditions/Notes

Min. Typ. Max. Min. Typ. Max. Units

Frequency

2.4 GHz and 5 GHz bands,

IEEE 802.11ac operation

35

37.4 38.4

37.4 38.4 35

Ranges between 19 MHz and 38.4 MHz^d

–

37.4

–

MHz

Frequency

5 GHz band, IEEE 802.11n

operation only

19

37.4 38.4 MHz

2.4 GHz band IEEE 802.11n

operation, and both bands

legacy 802.11a/b/g operation

only

Frequency tolerance Without trimming

over the lifetime of the

equipment, including

temperature^e

–20

–

20

–20

–

20

ppm

pF

Crystal load

capacitance

–

12

–

ESR

–

60

–

Ω

Drive level

External crystal must be able to 200

tolerate this drive level.

µW

Input impedance

(WRF_XTAL_IN)

Resistive

–

30k

–

100k

–

Ω

Capacitive

7.5

–

7.5

0.2

pF

V

WRF_XTAL_IN

input low level

DC-coupled digital signal

0

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

External Frequency Reference

Table 2: Crystal Oscillator and External Clock—Requirements and Performance (Cont.)

External Frequency

Reference^{b c}

Crystal^a

Parameter

Conditions/Notes

Min. Typ. Max. Min. Typ. Max. Units

WRF_XTAL_IN

input high level

DC-coupled digital signal

–

1.0

–

1.26

V

WRF_XTAL_IN

input voltage

AC-coupled analog signal

–

1000

–

1200 mV_p-p

(see Figure 5)

Duty cycle

37.4 MHz clock

–

40

–

50

–

60

%

Phase noise^f

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–129 dBc/Hz

–136 dBc/Hz

–

(IEEE 802.11b/g)

Phase noise^f

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–137 dBc/Hz

–144 dBc/Hz

(IEEE 802.11a)

Phase noise^f

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–134 dBc/Hz

–141 dBc/Hz

(IEEE 802.11n,

2.4 GHz)

Phase noise^f

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–142 dBc/Hz

–149 dBc/Hz

(IEEE 802.11n,

5 GHz)

Phase noise^f

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–148 dBc/Hz

–155 dBc/Hz

(IEEE 802.11ac,

5 GHz)

a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.

b. See “External Frequency Reference” on page 31 for alternative connection methods.

c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the

reference clock frequency in MHz.

d. The frequency step size is approximately 80 Hz.

e. It is the responsibility of the equipment designer to select oscillator components that comply with these

specifications.

f. Assumes that external clock has a flat phase-noise response above 100 kHz.

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Frequency Selection

Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not

only the standard mobile platform reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, and 38.4 MHz, but

also other frequencies in this range with an approximate resolution of 80 Hz. The BCM4339 must have the

reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all

bit timing is derived from the reference frequency.

Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies

other than the default require support to be added in the driver plus additional, extensive system

testing. Contact Broadcom for details.

The reference frequency for the BCM4339 may be set in the following ways:

•

Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal

frequency.

•

Autodetect any of the standard handset reference frequencies using an external LPO clock.

For applications such as handsets and portable smart communication devices, where the reference frequency

is one of the standard frequencies commonly used, the BCM4339 automatically detects the reference frequency

and programs itself to the correct reference frequency. In order for automatic frequency detection to work

correctly, the BCM4339 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed

in Table 3 on page 34 and is present during power-on reset.

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BCM4339 Preliminary Data Sheet

External 32.768 kHz Low-Power Oscillator

The BCM4339 uses a secondary low-frequency clock for low-power-mode timing. Either the internal low-

precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is

approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications.

However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power

save mode that is incurred by the need to wake up earlier to avoid missing beacons.

Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the

requirements listed in Table 3.

Table 3: External 32.768 kHz Sleep Clock Specifications

Parameter

LPO Clock

Units

Nominal input frequency

Frequency accuracy

Duty cycle

32.768

kHz

ppm

%

±200

30–70

Input signal amplitude

Signal type

200–1800

mV, p-p

–

Square-wave or sine-wave

Input impedance^a

>100k

<5

Ω

pF

Clock jitter (during initial start-up)

<10,000

ppm

a. When power is applied or switched off.

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BCM4339 Preliminary Data Sheet

Bluetooth + FM Subsystem Overview

Section 4: Bluetooth + FM Subsystem

Overview

The Broadcom BCM4339 is a Bluetooth 4.1 + EDR-compliant, baseband processor/2.4 GHz transceiver with

an integrated FM/RDS/RBDS receiver. It features the highest level of integration and eliminates all critical

external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth plus

FM radio solution.

The BCM4339 is the optimal solution for any Bluetooth voice and/or data application that also requires an FM

radio receiver. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high-speed

UART and PCM for audio. The FM subsystem supports the HCI control interface, analog output, as well as I²S

and PCM interfaces. The BCM4339 incorporates all Bluetooth 4.1 features including Secure Simple Pairing,

Sniff Subrating, and Encryption Pause and Resume.

The BCM4339 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent

mobile phone temperature applications and the tightest integration into handsets and portable devices. It is fully

compatible with any of the standard TCXO frequencies and provides full radio compatibility to operate

simultaneously with GPS, WLAN, and cellular radios.

The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.

Features

Major Bluetooth features of the BCM4339 include:

•

Supports key features of upcoming Bluetooth standards

Fully supports Bluetooth Core Specification version 4.1 + (Enhanced Data Rate) EDR features:

– Adaptive Frequency Hopping (AFH)

– Quality of Service (QoS)

– Extended Synchronous Connections (eSCO)—Voice Connections

– Fast Connect (interlaced page and inquiry scans)

– Secure Simple Pairing (SSP)

– Sniff Subrating (SSR)

– Encryption Pause Resume (EPR)

– Extended Inquiry Response (EIR)

– Link Supervision Timeout (LST)

•

UART baud rates up to 4 Mbps

Supports Bluetooth 4.1 packet types

Supports maximum Bluetooth data rates over HCI UART

BT supports full-speed USB version 1.1 in the FCBGA package

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BCM4339 Preliminary Data Sheet

Features

•

Multipoint operation with up to seven active slaves

– Maximum of seven simultaneous active ACL links

– Maximum of three simultaneous active SCO and eSCO connections with scatternet support

Trigger Broadcom fast connect (TBFC)

•

Narrowband and wideband packet loss concealment

Scatternet operation with up to four active piconets with background scan and support for scatter mode

High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and

BT_HOST_WAKE signaling (see “Host Controller Power Management” on page 41)

•

Channel quality driven data rate and packet type selection

Standard Bluetooth test modes

Extended radio and production test mode features

Full support for power savings modes

– Bluetooth clock request

– Bluetooth standard sniff

– Deep-sleep modes and software regulator shutdown

•

TCXO input and autodetection of all standard handset clock frequencies. Also supports a low-power

crystal, which can be used during power save mode for better timing accuracy.

Major FM Radio Features Include:

•

65 MHz to 108 MHz FM bands supported (US, Europe, and Japan)

FM subsystem control using the Bluetooth HCI interface

FM subsystem operates from reference clock inputs.

Improved audio interface capabilities with full-featured bidirectional PCM and I²S

I²S can be master or slave.

FM Receiver-Specific Features Include:

•

Excellent FM radio performance with 1 µV sensitivity for 26 dB (S+N)/N

Signal-dependent stereo/mono blending

Signal-dependent soft mute

Auto search and tuning modes

Audio silence detection

RSSI, IF frequency, status indicators

RDS and RBDS demodulator and decoder with filter and buffering functions

Automatic frequency jump

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BCM4339 Preliminary Data Sheet

Bluetooth Radio

The BCM4339 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless

systems. It has been designed to provide low-power, low-cost, robust communications for applications operating

in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification

and EDR specification and meets or exceeds the requirements to provide the highest communication link

quality.

Transmit

The BCM4339 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated

in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path

performs signal filtering, I/Q upconversion, output power amplification, and RF filtering. The transmitter path also

incorporates /4-DQPSK and 8-DPSK modulations for 2 Mbps and 3 Mbps EDR support, respectively. The

transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be

adjusted to provide Bluetooth Class 1 or Class 2 operation.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and

8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation

characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency

tracking and bit-synchronization algorithm.

Power Amplifier

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated

design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA

combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory

harmonic and spurious requirements. For integrated handset applications in which Bluetooth is integrated next

to the cellular radio, external filtering can be applied to achieve near-thermal-noise levels for spurious and

radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator

(TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and

temperature.

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BCM4339 Preliminary Data Sheet

Bluetooth Radio

Receiver

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital

demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic

range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The

front-end topology, with built-in out-of-band attenuation, enables the BCM4339 to be used in most applications

with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated

close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by

the cellular transmit signal.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency

tracking and bit synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the BCM4339 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband,

so that the controller can determine whether the transmitter should increase or decrease its output power.

Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum

available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during

PA operation. The BCM4339 uses an internal RF and IF loop filter.

Calibration

The BCM4339 radio transceiver features an automated calibration scheme that is fully self contained in the

radio. No user interaction is required during normal operation or during manufacturing to provide the optimal

performance. Calibration optimizes the performance of all the major blocks within the radio to within 2% of

optimal conditions, including gain and phase characteristics of filters, matching between key components, and

key gain blocks. This takes into account process variation and temperature variation. Calibration occurs during

normal operation during the settling time of the hops and calibrates for temperature variations as the device

cools and heats during normal operation in its environment.

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BCM4339 Preliminary Data Sheet

Bluetooth Baseband Core

Section 5: Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance

Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It

also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions,

monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages

connection status indicators, and composes and decodes HCI packets. In addition to these functions, it

independently handles HCI event types, and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability

and security of the TX/RX data:

•

Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data dewhitening in the receiver.

•

Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and

data whitening in the transmitter.

Bluetooth 4.1 Features

The BBC supports all Bluetooth 4.1 features, with the following benefits:

•

Dual-mode bluetooth Low Energy (BT and BLE operation)

Extended Inquiry Response (EIR): Shortens the time to retrieve the device name, specific profile, and

operating mode.

•

Encryption Pause Resume (EPR): Enables the use of Bluetooth technology in a much more secure

environment.

Sniff Subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which

subsequently extends battery life.

Secure Simple Pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no

user interaction required.

Link Supervision Time Out (LSTO): Additional commands added to HCI and Link Management Protocol

(LMP) for improved link time-out supervision.

QoS enhancements: Changes to data traffic control, which results in better link performance. Audio, human

interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data

(ED) and packet boundary flag (PBF) enhancements.

Bluetooth Low Energy

The BCM4339 supports the Bluetooth Low Energy operating mode.

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BCM4339 Preliminary Data Sheet

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the

link control unit (LCU). This layer consists of the command controller that takes commands from the software,

and other controllers that are activated or configured by the command controller to perform the link control tasks.

Each task performs a different state in the Bluetooth Link Controller.

•

Major states:

– Standby

– Connection

Substates:

– Page

•

– Page Scan

– Inquiry

– Inquiry Scan

– Sniff

Test Mode Support

The BCM4339 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth

System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced

hopping sequence.

In addition to the standard Bluetooth Test Mode, the BCM4339 also supports enhanced testing features to

simplify RF debugging, qualification, and type-approval testing. These features include:

•

Fixed-frequency carrier-wave (unmodulated) transmission

– Simplifies some type-approval measurements (Japan)

– Aids in transmitter performance analysis

•

Fixed-frequency constant-receiver mode

– Receiver output directed to I/O pin

– Allows for direct BER measurements using standard RF test equipment

– Facilitates spurious emissions testing for receive mode

Fixed frequency constant transmission

•

– Eight-bit fixed pattern or PRBS-9

– Enables modulated signal measurements with standard RF test equipment

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BCM4339 Preliminary Data Sheet

Bluetooth Power Management Unit

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by

either software through power management registers or packet handling in the baseband core. The power

management functions provided by the BCM4339 are:

•

RF Power Management

Host Controller Power Management

“BBC Power Management” on page 43

“FM Power Management” on page 43

RF Power Management

The BBC generates power-down control signals to the 2.4 GHz transceiver for the transmit path, receive path,

PLL, and power amplifier. The transceiver then processes the power-down functions accordingly.

Host Controller Power Management

When running in UART mode, the BCM4339 may be configured so that dedicated signals are used for power

management handshaking between the BCM4339 and the host. The basic power saving functions supported

by those handshaking signals include the standard Bluetooth defined power savings modes and standby modes

of operation.

Table 4 describes the power-control handshake signals used with the UART interface.

Table 4: Power Control Pin Description

Signal

Mapped to Pin

Type Description

BT_DEV_WAKE BT_GPIO_0

I

Bluetooth device wake-up: Signal from the host to the

BCM4339 indicating that the host requires attention.

•

Asserted: The Bluetooth device must wake-up or remain

awake.

•

Deasserted: The Bluetooth device may sleep when sleep

criteria are met.

The polarity of this signal is software configurable and can be

asserted high or low.

BT_HOST_WAK BT_GPIO_1

E

O

Host wake up. Signal from the BCM4339 to the host

indicating that the BCM4339 requires attention.

•

Asserted: host device must wake-up or remain awake.

Deasserted: host device may sleep when sleep criteria

are met.

The polarity of this signal is software configurable and can be

asserted high or low.

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BCM4339 Preliminary Data Sheet

Bluetooth Power Management Unit

Table 4: Power Control Pin Description (Cont.)

Signal

Mapped to Pin

Type Description

O The BCM4339 asserts CLK_REQ when either the Bluetooth

CLK_REQ

BT_CLK_REQ_OUT

WL_CLK_REQ_OUT

or WLAN block wants the host to turn on the reference clock.

The CLK_REQ polarity is active-high. Add an external 100

kΩ pull-down resistor to ensure the signal is deasserted

when the BCM4339 powers up or resets when VDDIO is

present.

Note: Pad function Control Register is set to 0 for these pins. See “DC Characteristics” on page 122 for more

details.

Figure 6: Startup Signaling Sequence

LPO

Host IOs

VDDIO

unconfigured

Host IOs configured

T₁

HostResetX

BT_GPIO_0

(BT_DEV_WAKE)

BT_REG_ON

T₂

BTH IOs

unconfigured

BTH IOs configured

BT_GPIO_1

(BT_HOST_WAKE)

T₃

Host drives

this low.

BT_UART_CTS_N

BTH device drives this

low indicating

BT_UART_RTS_N

CLK_REQ_OUT

T₄

transport is ready.

T₅

Driven

Pulled

Notes :

ꢀꢁ T₁is the time for the host to settle its IOs after a reset.

ꢀꢁ T₂is the time for the host to drive BT_REG_ON high after the host IOs are configured.

ꢀꢁ T₃is the time for the BTH device to settle its IOs after a reset and the reference clock settling time has elapsed.

ꢀꢁ T₄is the time for the BTH device to drive BT_UART_RTS_N low after the host drives BT_UART_CTS_N low. This assumes

the BTH device has completed initialization.

ꢀꢁ T₅is the time for the BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. The CLK_REQ_OUT pin is used

in designs that have an external reference clock source from the host. It is irrelevant on clock-based designs where the

BTH device generates its own reference clock from an external crystal connected to its oscillator circuit.

ꢀꢁ The timing diagram assumes that VBAT is present.

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BCM4339 Preliminary Data Sheet

Bluetooth Power Management Unit

BBC Power Management

The following are low-power operations for the BBC:

•

Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.

Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the

BCM4339 runs on the low-power oscillator and wakes up after a predefined time period.

•

A low-power shutdown feature allows the device to be turned off while the host and any other devices in the

system remain operational. When the BCM4339 is not needed in the system, the RF and core supplies are

shut down while the I/O remains powered. This allows the BCM4339 to effectively be off while keeping the

I/O pins powered so they do not draw extra current from any other devices connected to the I/O.

During the low-power shut-down state, provided VDDIO remains applied to the BCM4339, all outputs are

tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal

operation. This is done to prevent current paths or create loading on any digital signals in the system and

enables the BCM4339 to be fully integrated in an embedded device to take full advantage of the lowest

power-saving modes.

Two BCM4339 input signals are designed to be high-impedance inputs that do not load the driving signal

even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN)

and the 32.768 kHz input (LPO). When the BCM4339 is powered on from this state, it is the same as a

normal power-up, and the device does not contain any information about its state from the time before it was

powered down.

FM Power Management

The BCM4339 FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC

subsystems. The FM subsystem power management scheme operates in conjunction with the Bluetooth RF and

BBC subsystems. The FM block does not have a low power state, it is either on or off.

Wideband Speech

The BCM4339 provides support for wideband speech (WBS) using on-chip SmartAudio technology. The

BCM4339 can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at

16 kHz (256 kbps rate) transferred over the PCM bus.

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BCM4339 Preliminary Data Sheet

Bluetooth Power Management Unit

Packet Loss Concealment

Packet Loss Concealment (PLC) improves apparent audio quality for systems with marginal link performance.

Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bitstream.

Packet loss can be mitigated in several ways:

•

Fill in zeros.

Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets).

Repeat the last frame (or packet) of the received bitstream and decode it as usual (frame repeat).

These techniques cause distortion and popping in the audio stream. The BCM4339 uses a proprietary waveform

extension algorithm to provide dramatic improvement in the audio quality. Figure 7 and Figure 8 show audio

waveforms with and without Packet Loss Concealment. Broadcom PLC and bit-error correction (BEC)

algorithms also support wideband speech.

Figure 7: CVSD Decoder Output Waveform Without PLC

Packet Loss Causes Ramp-down

Figure 8: CVSD Decoder Output Waveform After Applying PLC

Audio Rate-Matching Algorithms

The BCM4339 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio

stream jitter that may be present when the rate of audio data coming from the host is not the same as the

Bluetooth or FM audio data rates.

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BCM4339 Preliminary Data Sheet

Adaptive Frequency Hopping

Codec Encoding

The BCM4339 can support SBC and mSBC encoding and decoding for wideband speech.

Multiple Simultaneous A2DP Audio Streams

The BCM4339 has the ability to take a single audio stream and output it to multiple Bluetooth devices

simultaneously. This allows a user to share his or her music (or any audio stream) with a friend.

FM Over Bluetooth

FM over Bluetooth enables the BCM4339 to stream data from FM over Bluetooth without requiring the host to

be awake. This can significantly extend battery life for usage cases where someone is listening to FM radio on

a Bluetooth headset.

Burst Buffer Operation

The BCM4339 has a data buffer that can buffer data being sent over the HCI and audio transports, then send

the data at an increased rate. This mode of operation allows the host to sleep for the maximum amount of time,

dramatically reducing system current consumption.

Adaptive Frequency Hopping

The BCM4339 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and

channel map selection. The link quality is determined using both RF and baseband signal processing to provide

a more accurate frequency-hop map.

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BCM4339 Preliminary Data Sheet

Advanced Bluetooth/WLAN Coexistence

The BCM4339 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN

integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell

phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High

Fidelity BT Stereo.

Support is provided for platforms that share a single antenna between Bluetooth and WLAN. The BCM4339

radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna

applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has

superior performance versus implementations that need to arbitrate between Bluetooth and WLAN reception.

The BCM4339 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via

an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without

host processor involvement.

The BCM4339 also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC

to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP

transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been

implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including non-

WLAN 2.4 GHz interference).

The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information.

Fast Connection (Interlaced Page and Inquiry Scans)

The BCM4339 supports page scan and inquiry scan modes that significantly reduce the average inquiry

response and connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and

inquiry procedures.

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BCM4339 Preliminary Data Sheet

Microprocessor and Memory Unit for Bluetooth

Section 6: Microprocessor and Memory

Unit for Bluetooth

The Bluetooth microprocessor core is based on the ARM^®Cortex-M3^™32-bit RISC processor with embedded

ICE-RT debug and JTAG interface units. It runs software from the link control (LC) layer, up to the host controller

interface (HCI).

The ARM core is paired with a memory unit that contains 608 KB of ROM memory for program storage and boot

ROM, 192 KB of RAM for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during

power-on reset to enable the same device to be used in various configurations. At power-up, the lower-layer

protocol stack is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature

additions. These patches may be downloaded from the host to the BCM4339 through the UART transports. The

mechanism for downloading via UART is identical to the proven interface of the BCM4329 and BCM4330

devices.

RAM, ROM, and Patch Memory

The BCM4339 Bluetooth core has 192 KB of internal RAM which is mapped between general purpose scratch-

pad memory and patch memory and 608 KB of ROM used for the lower-layer protocol stack, test mode software,

and boot ROM. The patch memory capability enables feature additions and bug fixes to the ROM memory.

Reset

The BCM4339 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The

BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the

POR circuit is held in reset.

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BCM4339 Preliminary Data Sheet

Bluetooth Peripheral Transport Unit

Section 7: Bluetooth Peripheral Transport

Unit

SPI Interface

The BCM4339 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates

are possible. The physical interface between the SPI master and the BCM4339 contains the four SPI signals

(SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO) and one interrupt signal (SPI_INT). The SPI signals are muxed onto

the UART signals, see Table 5. The BCM4339 can be configured to accept active-low or active-high polarity on

the SPI_CSB chip-select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt

signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian.

Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and

the BCM4339. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require

flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI

master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should

be implemented in the higher layer protocols.

Table 5: SPI to UART Signal Mapping

SPI Signals

UART Signals

SPI_CLK

SPI_CSB

SPI_MISO

SPI_MOSI

SPI_INT

UART_CTS_N

UART_RTS_N

UART_RXD

UART_TXD

BT_HOST_WAKE

SPI/UART Transport Detection

The BT_HOST_WAKE (BT_GPIO1) pin is also used for BT transport detection. Transport detection occurs

during the power-up sequence. Either UART or SPI transport operation is selected based on the following pin

state:

•

If the BT_HOST_WAKE (BT_GPIO1) pin is pulled low by an external pull-down during power-up, the SPI

transport interface is selected.

•

If the BT_HOST_WAKE (BT_GPIO1) pin is not pulled low externally during power-up, then the default

internal pull-up is detected as a high and the UART transport interface is selected.

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BCM4339 Preliminary Data Sheet

PCM Interface

The BCM4339 supports two independent PCM interfaces that share pins with the I²S interfaces. The PCM

Interface on the BCM4339 can connect to linear PCM codec devices in master or slave mode. In master mode,

the BCM4339 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided

by another master on the PCM interface and are inputs to the BCM4339.

The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI

commands.

Slot Mapping

The BCM4339 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM

interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting

scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of

slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number

of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO

channel is always mapped to the same slot. The PCM data output driver tri-states its output on unused slots to

allow other devices to share the same PCM interface signals. The data output driver tristates its output after the

falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization

The BCM4339 supports both short- and long-frame synchronization in both master and slave modes. In short-

frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate

that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks

for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge

of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse

at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first

bit of the first slot.

Data Formatting

The BCM4339 may be configured to generate and accept several different data formats. For conventional

narrowband speech mode, the BCM4339 uses 13 of the 16 bits in each PCM frame. The location and order of

these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits

are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The

default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

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BCM4339 Preliminary Data Sheet

PCM Interface

Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are

transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured

in master mode for a 4 kHz sync rate with 16-bit samples, resulting in a 64 Kbps bit rate. The BCM4339 also

supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit

data at 16 kHz (256 Kbps rate) is transferred over the PCM bus.

Multiplexed Bluetooth and FM Over PCM

In this mode of operation, the BCM4339 multiplexes both FM and Bluetooth audio PCM channels over the same

interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command

from the host. The format of the data stream consists of three channels: a Bluetooth channel followed by two

FM channels (audio left and right). In this mode of operation, the bus data rate only supports 48 kHz operation

per channel with 16 bits sent for each channel.

This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I²S

data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data.

An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame.

To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can

be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 9 shows

the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate

additional SCO channels, the transport clock speed is increased. To change between modes of operation, the

transport must be halted and restarted in the new configuration.

Figure 9: Functional Multiplex Data Diagram

1 frame

BT SCO 1 Rx

BT SCO 1 Tx

BT SCO 2 Rx

BT SCO 2 Tx

BT SCO 3 Rx

FM right

FM left

PCM_OUT

PCM_IN

BT SCO 3 Tx

PCM_SYNC

PCM_CLK

CLK

16 bits per SCO frame

16 bits per frame

Each SCO channel duplicates the data 6 times. Each

WBS frame duplicates the data 3 times per frame

Burst PCM Mode

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty

cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to

24 MHz. This mode of operation is initiated with an HCI command from the host.

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BCM4339 Preliminary Data Sheet

PCM Interface

PCM Interface Timing

Short Frame Sync, Master Mode

Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

HIGH IMPEDANCE

7

5

6

PCM_IN

Table 6: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

41

0

–

ns

25

–

ns

0

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

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BCM4339 Preliminary Data Sheet

PCM Interface

Short Frame Sync, Slave Mode

Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

PCM_OUT

9

HIGH IMPEDANCE

8

6

7

PCM_IN

Table 7: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

41

8

–

ns

–

ns

8

–

ns

0

25

–

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

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BCM4339 Preliminary Data Sheet

PCM Interface

Long Frame Sync, Master Mode

Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

HIGH IMPEDANCE

7

Bit 0

Bit 1

5

6

PCM_IN

Table 8: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

41

0

–

ns

25

–

ns

0

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

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BCM4339 Preliminary Data Sheet

PCM Interface

Long Frame Sync, Slave Mode

Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

PCM_OUT

9

Bit 0

HIGH IMPEDANCE

8

Bit 1

6

7

Bit 1

PCM_IN

Table 9: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

41

8

–

ns

–

ns

8

–

ns

0

25

–

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

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BCM4339 Preliminary Data Sheet

PCM Interface

Short Frame Sync, Burst Mode

Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

PCM_IN

Table 10: PCM Burst Mode (Receive Only, Short Frame Sync)

Ref No. Characteristics

Minimum Typical Maximum Unit

1

2

3

4

5

6

7

PCM bit clock frequency

–

24

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

20.8

8

–

ns

–

ns

8

–

ns

8

–

ns

PCM_IN hold

8

–

ns

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BCM4339 Preliminary Data Sheet

PCM Interface

Long Frame Sync, Burst Mode

Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

Bit 0

PCM_IN

Bit 1

Table 11: PCM Burst Mode (Receive Only, Long Frame Sync)

Ref No. Characteristics

Minimum Typical Maximum Unit

1

2

3

4

5

6

7

PCM bit clock frequency

–

24

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

20.8

8

–

ns

–

ns

8

–

ns

8

–

ns

PCM_IN hold

8

–

ns

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BCM4339 Preliminary Data Sheet

USB Interface

Features

The following USB interface features are supported:

•

USB Protocol, Revision 2.0, full-speed (12 Mbps) compliant including the hub

Optional hub compound device with up to three device cores internal to device

Bus or self-power, dynamic configuration for the hub

Global and selective suspend and resume with remote wakeup

Bluetooth HCI

HID, DFU, UHE (proprietary method to emulate an HID device at system bootup)

Integrated detach resistor

Operation

The BCM4339 can be configured to boot up as either a single USB peripheral or a USB hub with several USB

peripherals attached. As a single peripheral, the host detects a single USB Bluetooth device. In hub mode, the

host detects a hub with one to three of the ports already connected to USB devices (see Figure 16).

Figure 16: USB Compounded Device Configuration

Host

USB Compounded Device

Hub Controller

USB Device 1

HID Keyboard

USB Device 2

HID Mouse

USB Device 3

Bluetooth

Depending on the desired hub mode configuration, the BCM4339 can boot up showing the three ports

connected to logical USB devices internal to the BCM4339: a generic Bluetooth device, a mouse, and a

keyboard. In this mode, the mouse and keyboard are emulated devices, since they connect to real HID devices

via a Bluetooth link. The Bluetooth link to these HID devices is hidden from the USB host. To the host, the mouse

and/or keyboard appear to be directly connected to the USB port. This Broadcom proprietary architecture is

called USB HID Emulation (UHE).

The USB device, configuration, and string descriptors are fully programmable, allowing manufacturers to

customize the descriptors, including vendor and product IDs, the BCM4339 uses to identify itself on the USB

port. To make custom USB descriptor information available at boot time, stored it in external NVRAM.

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BCM4339 Preliminary Data Sheet

USB Interface

Despite the mode of operation (single peripheral or hub), the Bluetooth device is configured to include the

following interfaces:

Interface 0

Interface 1

Interface 2

Contains a Control endpoint (Endpoint 0x00) for HCI commands, a Bulk In Endpoint (Endpoint

0x82) for receiving ACL data, a Bulk Out Endpoint (Endpoint 0x02) for transmitting ACL data,

and an Interrupt Endpoint (Endpoint 0x81) for HCI events.

Contains Isochronous In and Out endpoints (Endpoints 0x83 and 0x03) for SCO traffic. Several

alternate Interface 1 settings are available for reserving the proper bandwidth of isochronous

data (depending on the application).

Contains Bulk In and Bulk Out endpoints (Endpoints 0x84 and 0x04) used for proprietary testing

and debugging purposes. These endpoints can be ignored during normal operation.

USB Hub and UHE Support

The BCM4339 supports the USB hub and device model (USB, Revision 2.0, full-speed compliant). Optional

mouse and keyboard devices utilize Broadcom’s proprietary USB HID Emulation (UHE) architecture, which

allows these devices appear as standalone HID devices even though connected through a Bluetooth link.

The presence of UHE devices requires the hub to be enabled. The BCM4339 cannot appear as a single

keyboard or a single mouse device without the hub. Once either mouse or keyboard UHE device is enabled, the

hub must also be enabled.

When the hub is enabled, the BCM4339 handles all standard USB functions for the following devices:

•

HID keyboard

HID mouse

Bluetooth

All hub and device descriptors are firmware-programmable. This USB compound device configuration (see

Figure 16 on page 57) supports up to three downstream ports. This configuration can also be programmed to a

single USB device core. The device automatically detects activity on the USB interface when connected.

Therefore, no special configuration is needed to select HCI as the transport.

The hub’s downstream port definition is as follows:

•

Port 1 USB lite device core (for HID applications)

Port 2 USB lite device core (for HID applications)

Port 3 USB full device core (for Bluetooth applications)

When operating in hub mode, all three internal devices do not have to be enabled. Each internal USB device

can be optionally enabled. The configuration record in NVRAM determines which devices are present.

USB Full-Speed Timing

Table 12 shows timing specifications for the VDD_USB = 3.3V, V_SS= 0V, and T_A= 0°C to 85°C operating

temperature range.

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BCM4339 Preliminary Data Sheet

UART Interface

Table 12: USB Full-Speed Timing Specifications

Reference Characteristics

Minimum

Maximum

Unit

1

2

3

4

Transition rise time

Transition fall time

4

20

ns

4

20

ns

Rise/fall timing matching

Full-speed data rate

90

111

%

12 – 0.25%

12 + 0.25%

Mb/s

Figure 17: USB Full-Speed Timing

2

1

D+

D-

90%

V_CRS

10%

UART Interface

The BCM4339 shares a single UART for Bluetooth and FM. The UART is a standard 4-wire interface (RX, TX,

RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud

rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through

a vendor-specific UART HCI command.

UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is

conducted through the AHB interface through either DMA or the CPU. The UART supports the Bluetooth 4.1

UART HCI specification: H4, a custom Extended H4, and H5. The default baud rate is 115.2 Kbaud.

The UART supports the 3-wire H5 UART transport, as described in the Bluetooth specification (“Three-wire

UART Transport Layer”). Compared to H4, the H5 UART transport reduces the number of signal lines required

by eliminating the CTS and RTS signals.

The BCM4339 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line

Input Protocol (SLIP). It can also perform wake-on activity. For example, activity on the RX or CTS inputs can

wake the chip from a sleep state.

Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic

baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate

during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust

the contents of the baud rate registers. The BCM4339 UARTs operate correctly with the host UART as long as

the combined baud rate error of the two devices is within ±2%.

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BCM4339 Preliminary Data Sheet

UART Interface

Table 13: Example of Common Baud Rates

Desired Rate

Actual Rate

Error (%)

4000000

3692000

3000000

2000000

1500000

1444444

921600

460800

230400

115200

57600

4000000

3692308

3000000

2000000

1500000

1454544

923077

461538

230796

115385

57692

0.00

0.01

0.00

0.70

0.16

0.17

0.16

0.00

0.16

0.00

0.16

0.00

38400

28800

28846

19200

14400

14423

9600

Figure 18: UART Timing

UART_CTS_N

1

2

UART_TXD

Midpoint of STOP bit

UART_RXD

3

UART_RTS_N

Table 14: UART Timing Specifications

Min.

Ref No. Characteristics

Typ.

Max.

Unit

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

–

1.5

0.5

Bit period

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N high

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BCM4339 Preliminary Data Sheet

I²S Interface

The BCM4339 supports two independent I²S digital audio ports: one for Bluetooth audio, and one for high-

fidelity FM audio. The I²S interface for FM audio supports both master and slave modes. The I²S signals are:

•

I²S clock: I²S SCK

I²S Word Select: I²S WS

I²S Data Out: I²S SDO

I²S Data In: I²S SDI

I²S SCK and I²S WS become outputs in master mode and inputs in slave mode, while I²S SDO always stays

as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data

is aligned with the MSB of the I²S bus, per the I²S specification. The MSB of each data word is transmitted one

bit clock cycle after the I²S WS transition, synchronous with the falling edge of bit clock. Left-channel data is

transmitted when I²S WS is low, and right-channel data is transmitted when I²S WS is high. Data bits sent by

the BCM4339 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the

rising edge of I2S_SSCK.

The clock rate in master mode is either of the following:

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

The master clock is generated from the input reference clock using a N/M clock divider.

In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.

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BCM4339 Preliminary Data Sheet

I²S Interface

2

I S Timing

Note: Timing values specified in Table 15 are relative to high and low threshold levels.

Table 15: Timing for I²S Transmitters and Receivers

Transmitter

Lower LImit Upper Limit

Receiver

Lower Limit Upper Limit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Notes

a

Clock Period T

T_tr

–

T_r

–

Master Mode: Clock generated by transmitter or receiver

b

HIGH t_HC

LOWt_LC

0.35T_tr

–

0.35T_tr

–

Slave Mode: Clock accepted by transmitter or receiver

c

d

HIGH t_HC

–

0.35T_tr

–

0.35T_tr

–

LOW t_LC

Rise time t_RC

0.15T_tr

Transmitter

Delay t_dtr

e

d

–

0

–

0.8T

–

Hold time t_htr

Receiver

f

Setup time t_sr

Hold time t_hr

–

0.2T_r

0

–

a. The system clock period T must be greater than T_trand T_rbecause both the transmitter and receiver have to be

able to handle the data transfer rate.

b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space

ratio. For this reason, t_HCand t_LCare specified with respect to T.

c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that

they can detect the signal. So long as the minimum periods are greater than 0.35T_r, any clock that meets the

requirements can be used.

d. Because the delay (t_dtr) and the maximum transmitter speed (defined by T_tr) are related, a fast transmitter driven

by a slow clock edge can result in t_dtrnot exceeding t_RCwhich means t_htrbecomes zero or negative. Therefore,

the transmitter has to guarantee that t_htris greater than or equal to zero, so long as the clock rise-time t_RCis not

more than t_RCmax, where t_RCmaxis not less than 0.15T_tr.

e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the

clock signal and T, always giving the receiver sufficient setup time.

f. The data setup and hold time must not be less than the specified receiver setup and hold time.

Note: The time periods specified in Figure 19 and Figure 20 are defined by the transmitter speed. The

receiver specifications must match transmitter performance.

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BCM4339 Preliminary Data Sheet

I²S Interface

Figure 19: I²S Transmitter Timing

T

t_RC

*

t_LC> 0.35T

t_HC> 0.35T

V_H= 2.0V

V_L= 0.8V

SCK

t_htr> 0

t_otr< 0.8T

SD and WS

T = Clock period

T

_tr= Minimum allowed clock period for transmitter

T = T_tr

* t_RCis only relevant for transmitters in slave mode.

Figure 20: I²S Receiver Timing

T

t_LC> 0.35T

t_HC> 0.35

V_H= 2.0V

V_L= 0.8V

SCK

t_sr> 0.2T

t_hr> 0

SD and WS

T = Clock period

T_r= Minimum allowed clock period for transmitter

T > T_r

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BCM4339 Preliminary Data Sheet

FM Receiver Subsystem

Section 8: FM Receiver Subsystem

FM Radio

The BCM4339 includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from

65 MHz to 108 MHz. The receiver is controlled through commands on the HCI. FM received audio is available

in analog form or in digital form through I²S or PCM. The FM radio operates from the external clock reference.

Digital FM Audio Interfaces

The FM audio can be transmitted via the shared PCM and I²S pins, and the sampling rate is programmable.

The BCM4339 supports a three-wire PCM or I²S audio interface in either master or slave configuration. The

master or slave configuration is selected using vendor specific commands over the HCI interface. In addition,

multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master mode, the clock

rate is either of the following:

•

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

In slave mode, any clock rate is supported up to a maximum of 3.072 MHz.

FM Over Bluetooth

The BCM4339 can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS,

and A2DP. In all of the above modes, once the link has been set up, the host processor can enter sleep mode

while the BCM4339 continues to stream FM audio to the remote Bluetooth device, allowing the system current

consumption to be minimized.

eSCO

In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is then sent through

the Bluetooth eSCO link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections

must be used to transport stereo.

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BCM4339 Preliminary Data Sheet

Wide Band Speech Link

In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is then sent through

the Bluetooth wideband speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice

connections must be used to transport stereo.

A2DP

In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a

remote Bluetooth device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP

“lite” stack is implemented in the BCM4339 to support this use case, which eliminates the need to route the SBC-

encoded audio back to the host to create the A2DP packets.

Autotune and Search Algorithms

The BCM4339 supports a number of FM search and tune functions that allows the host to implement many

convenient user functions, which are accessed through the Broadcom FM stack.

•

Tune to Play—Allows the FM receiver to be programmed to a specific frequency.

Search for SNR > Threshold—Checks the power level of the available channel and the estimated SNR of

the channel to help achieve precise control of the expected sound quality for the selected FM channel.

Specifically, the host can adjust its SNR requirements to retrieve a signal with a specific sound quality, or

adjust this to return the weakest channels.

•

Alternate Frequency Jump—Allows the FM receiver to automatically jump to an alternate FM channel that

carries the same information, but has a better SNR. For example, when traveling, a user may pass through

a region where a number of channels carry the same station. When the user passes from one area to the

next, the FM receiver can automatically switch to another channel with a stronger signal to spare the user

from having to manually change the channel to continue listening to the same station.

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BCM4339 Preliminary Data Sheet

Audio Features

A number of features are implemented in the BCM4339 to provide the best possible audio experience for the

user.

•

Mono/Stereo Blend or Switch—The BCM4339 provides automatic control of the stereo or mono settings

based on the FM signal carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio

SNR based on the FM channel condition. Two modes of operation are supported:

– Blend: In this mode, fine control of stereo separation is used to achieve optimal audio quality over a

wide range of input C/N. The amount of separation is fully programmable. In Figure 21, the separation is

programmed to maintain a minimum 50 dB SNR across the blend range.

– Extended blend: In this mode, stereo separation is maximized across a wide range of input CNR.

Broadcom static suppression typically gives a static-free user experience to within 3 dB of ultimate

sensitivity.

Figure 21: Example Blend/Switch Usage

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BCM4339 Preliminary Data Sheet

Audio Features

– Switch—In this mode, the audio switches from full stereo to full mono at a predetermined level to

maintain optimal audio quality. The stereo-to-mono switch point and the mono-to-stereo switch points

are fully programmable to provide the desired amount of audio SNR. In Figure 22, the switch point is

programmed to switch to mono to maintain a 40 dB SNR.

Figure 22: Example Blend/Switch Separation

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BCM4339 Preliminary Data Sheet

Audio Features

•

Soft Mute—Improves the user experience by dynamically muting the output audio proportionate to the FM

signal C/N. This prevents the user from being assaulted with a blast of static. The mute characteristic is

fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic

is shown in Figure 23.

Figure 23: Example Soft Mute Characteristic

•

High Cut—A programmable high-cut filter is provided to reduce the amount of high-frequency noise

caused by static in the output audio signal. Like the soft mute circuit, it is fully programmable to allow for

any amount of high cut based on the FM signal C/N.

Audio Pause Detect—The FM receiver monitors the magnitude of the audio signal and notifies the host

through an interrupt when the magnitude of the signal has fallen below the threshold set for a

programmable period. This feature can be used to provide alternate frequency jumps during periods of

silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause

detection block to provide more robust presence-to-silence detection and silence-to-presence detection.

•

Automatic Antenna Tuning—The BCM4339 has an on-chip automatic antenna tuning network. When used

with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching

component to obtain the highest signal strength for the desired frequency. The high-Q nature of this

matching network simultaneously provides out-of-band blocking protection as well as a reduction of

radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external

wire antennas.

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BCM4339 Preliminary Data Sheet

RDS/RBDS

The BCM4339 integrates a RDS/RBDS modem and codec, the decoder includes programmable filtering and

buffering functions, and the encoder includes the option to encode messages to PS or RT frame format with

programmable scrolling in PS mode. The RDS/RBDS data can be read out in receive mode or delivered in

transmit mode through either the HCI interface.

In addition, the RDS/RBDS functionality supports the following:

Receive

•

Block decoding, error correction and synchronization

Flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and

loss of sync. (It is possible to set up the BCM4339 such that synch is achieved when a minimum of two

good blocks (error free) are decoded in sequence. The number of good blocks required for sync is

programmable.)

•

Storage capability up to 126 blocks of RDS data

Full or partial block B match detect and interrupt to host

Audio pause detection with programmable parameters

Program Identification (PI) code detection and interrupt to host

Automatic frequency jump

Block E filtering

Soft mute

Signal dependent mono/stereo blend

Programmable pre-emphasis

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BCM4339 Preliminary Data Sheet

WLAN Global Functions

Section 9: WLAN Global Functions

WLAN CPU and Memory Subsystem

The BCM4339 WLAN section includes an integrated ARM Cortex-R4^™32-bit processor with internal RAM and

ROM. The ARM Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-

cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response

features. Delivering more than 30% performance gain over ARM7TDMI, the ARM Cortex-R4 implements the

ARM v7-R architecture with support for the Thumb^®-2 instruction set.

At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available,

outperforming 8- and 16-bit devices on MIPS/µW. It supports integrated sleep modes.

Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin

overhead, and reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode

and System buses), and extensive debug features including real time trace of program execution.

On-chip memory for the CPU includes 768 KB SRAM and 640 KB ROM.

One-Time Programmable Memory

Various hardware configuration parameters may be stored in an internal One-Time Programmable (OTP)

memory, which is read by the system software after device reset. In addition, customer-specific parameters,

including the system vendor ID and the MAC address can be stored, depending on the specific board design.

Customer accessible OTP memory is 502 bytes.

The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be

reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with

the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively

program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle.

Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file,

which is provided with the reference board design package.

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BCM4339 Preliminary Data Sheet

GPIO Interface

The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the BCM4339

that can be used to connect to various external devices:

•

FCBGA package – 12 GPIOs

WLBGA package – 9 GPIOs

WLCSP package – 16 GPIOs

Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either

input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other

functions (see Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118).

External Coexistence Interface

An external handshake interface is available to enable signaling between the device and an external co-located

wireless device, such as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum

performance.

Figure 24 shows the LTE coexistence interface. See Table 28: “BCM4339 GPIO/SDIO Alternative Signal

Functions,” on page 118 for details on multiplexed signals such as the GPIO pins.

See Table 13: “Example of Common Baud Rates,” on page 60 for UART baud rates.

Figure 24: Broadcom GCI or BT-SIG Mode LTE Coexistence Interface for BCM4339

BCM4339

LTE\IC

SECI_OUT/BT_TXD

UART_IN

GCI

WLAN

BTFM

SECI_IN/BT_TXD

UART_OUT

NOTES:

SECI_OUT/BT_TXD and SECI_IN/BT_RXD, on the BCM4339, are multiplexed on the GPIOs.

The 2-wire LTE coexistence interface is intended for future compatibility with the BT SIG2-

wire interface that is being standardized for Core4.1.

ORing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by

setting the GPIO mask registers appropriately.

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BCM4339 Preliminary Data Sheet

UART Interface

One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins (see

Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118). Provided primarily for debugging

during development, this UART enables the BCM4339 to operate as RS-232 data termination equipment (DTE)

for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550

UART, and provides a FIFO size of 64 × 8 in each direction.

JTAG Interface

The BCM4339 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and

PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist

customers by using proprietary debug and characterization test tools during board bringup. Therefore, it is highly

recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.

See Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118 for JTAG pin assignments.

SPROM Interface (FCBGA Package only)

For use only with the PCIe Interface in the FCBGA package, various hardware configuration parameters may

be stored in an external SPROM instead of the OTP. The SPROM is read by system software after device reset.

In addition, depending on the board design, customer-specific parameters may be stored in SPROM.

The four SPROM control signals —SPROM_CS, SPROM_CLK, SPROM_DIN, and SPROM_DOUT are

multiplexed on the SDIO interface (see Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on

page 118 for additional details). By default, the SPROM interface supports 2 kbit serial SPROMs, and it can also

support 4 kbit and 16 kbit serial SPROMs by using the appropriate strapping option.

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BCM4339 Preliminary Data Sheet

WLAN Host Interfaces

Section 10: WLAN Host Interfaces

SDIO v3.0

The BCM4339 WLAN section supports SDIO version 3.0, including the new UHS-I modes:

•

DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).

HS: High speed up to 50 MHz (3.3V signaling).

SDR12: SDR up to 25 MHz (1.8V signaling).

SDR25: SDR up to 50 MHz (1.8V signaling).

SDR50: SDR up to 100 MHz (1.8V signaling).

SDR104: SDR up to 208 MHz (1.8V signaling).

DDR50: DDR up to 50 MHz (1.8V signaling).

Note: The BCM4339 is backward compatible with SDIO v2.0 host interfaces.

The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an

interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks

from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 21 on

page 114 WLAN GPIO Functions and Strapping Options.

The following three functions are supported:

•

Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B)

Function 1 Backplane Function to access the internal system-on-chip (SoC) address space

(Max. BlockSize/ByteCount = 64B)

•

Function 2 WLAN Function for efficient WLAN packet transfer through DMA

(Max. BlockSize/ByteCount = 512B)

SDIO Pins

Table 16: SDIO Pin Description

SD 4-Bit Mode

Data line 0

SD 1-Bit Mode

gSPI Mode

Data output

DATA0

DATA1

DATA2

DATA3

CLK

DATA Data line

DO

IRQ

NC

CS

Data line 1 or Interrupt IRQ

Data line 2 or Read Wait RW

Interrupt

Read Wait

Not used

Clock

Interrupt

Not used

Card select

Data line 3

Clock

N/C

CLK

SCLK Clock

DI Data input

CMD

Command line

CMD Command line

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BCM4339 Preliminary Data Sheet

SDIO v3.0

Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode)

CLK

CMD

SD Host

BCM4339

DAT[3:0]

Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode)

CLK

CMD

DATA

SD Host

BCM4339

IRQ

RW

Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on

the four DATA lines and the CMD line. This requirement must be met during all operating states either

through the use of external pull-up resistors or through proper programming of the SDIO host’s internal

pull-ups.

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

In addition to the full SDIO mode, the BCM4339 includes the option of using the simplified generic SPI (gSPI)

interface/protocol. Characteristics of the gSPI mode include:

•

Supports up to 48 MHz operation

Supports fixed delays for responses and data from device

Supports alignment to host gSPI frames (16 or 32 bits)

Supports up to 2 KB frame size per transfer

Supports little endian (default) and big endian configurations

Supports configurable active edge for shifting

Supports packet transfer through DMA for WLAN

gSPI mode is enabled using the strapping option pins strap_host_ifc_[3:1].

Figure 27: Signal Connections to SDIO Host (gSPI Mode)

SCLK

DI

DO

SD Host

BCM4339

IRQ

CS

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November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

SPI Protocol

The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianness is supported in both modes.

Figure 28 and Figure 29 show the basic write and write/read commands.

Figure 28: gSPI Write Protocol

Figure 29: gSPI Read Protocol

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November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

Command Structure

The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 30.

Figure 30: gSPI Command Structure

BCM_SPID Command Structure

27

31 30 29 28

11 10

0

C

A

F1 F 0

Address – 17 bits

P acket length - 11bits *

*11’h0 = 2048 by tes

F unction N o: 00 – F unc 0Ϭ͗ꢀꢁůůꢀ^W/ꢀƐƉĞĐŝĮĐꢀƌĞŐŝƐƚĞƌƐ

01 – F unc 1: Registers and meories belonging to other blocks in the chip (64 bytes max)

10 – F unc 2: DMA channel 1. WLAN packets up to 2048 bytes.

11 – F unc 3ϯ͗ꢀꢂDꢁꢀĐŚĂŶŶĞůꢀϮꢀ;ŽƉƟŽŶĂůͿ͘ꢀWĂĐŬĞƚƐꢀƵƉꢀƚŽꢀϮϬϰϴꢀďǇƚĞƐ͘

Acce ss : 0 – F ixed add ress

1 – Incremental add ress

C ommand : 0 – R ead

1 – Write

Write

The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS

going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data

on the active edge.

Write/Read

The host reads on the rising edge of the clock requiring data from the device to be made available before the

first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to

represent the first bit of the following data word. This allows data to be ready for the first clock edge without

relying on asynchronous delays.

Read

The read command always follows a separate write to set up the WLAN device for a read. This command differs

from the write/read command in the following respects: a) chip selects go high between the command/address

and the data and b) the time interval between the command/address is not fixed.

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

Status

The gSPI interface supports status notification to the host after a read/write transaction. This status notification

provides information about any packet errors, protocol errors, information about available packet in the RX

queue, etc. The status information helps in reducing the number of interrupts to the host. The status-reporting

feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write

transactions with and without status notification are as shown in Figure 31 and Figure 32 on page 79. See

Table 17 on page 79 for information on status field details.

Figure 31: gSPI Signal Timing Without Status (32-bit Big Endian)

Write

cs

sclk

mosi

CC3311 CC3300

CC11

Command 32 bits

CC00 DD3311 DD3300

DD11 DD00

Write Data 16*n bits

Write-Read

cs

sclk

mosi

miso

CC3311 CC3300

CC00

DD3311 DD3300

DD00

DD11

Response

Delay

Command

32 bits

Read Data 16*n bits

cs

Read

sclk

mosi

miso

CC3311 CC3300

DD3311 DD3300

DD00

Command

32 bits

Response

Delay

Read Data

16*n bits

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November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

Figure 32: gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian)

cs

sclk

Write

mosi

CC3311

CC11

CC00 DD3311

DD11

DD00

SS3311

SS11

SS00

miso

Command 32 bits

Write Data 16*n bits

Status 32 bits

Write-Read

cs

sclk

mosi

miso

CC3311

CC00

SS3311

SS00

DD3311

DD11

DD00

Read Data 16*n bits

Status 32 bits

Command 32 bits

Read

cs

sclk

mosi

miso

CC3311

CC00

DD3311

DD11

DD00 SS3311

SS00

Command 32 bits

Read Data 16*n bits

Status 32 bits

Table 17: gSPI Status Field Details

Description

Bit

Name

0

1

Data not available

Underflow

The requested read data is not available

FIFO underflow occurred due to current (F2, F3) read

command

2

Overflow

FIFO overflow occurred due to current (F1, F2, F3) write

command

3

F2 interrupt

F2 channel interrupt

4

F3 interrupt

F3 channel interrupt

5

F2 RX Ready

F2 FIFO is ready to receive data (FIFO empty)

F3 FIFO is ready to receive data (FIFO empty)

–

6

F3 RX Ready

7

Reserved

8

F2 Packet Available

F2 Packet Length

F3 Packet Available

F3 Packet Length

Packet is available/ready in F2 TX FIFO

Length of packet available in F2 FIFO

Packet is available/ready in F3 TX FIFO

Length of packet available in F3 FIFO

9:19

20

21:31

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

gSPI Host-Device Handshake

To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing

to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the

BCM4339 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is

awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device

can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting

an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and

then take necessary actions.

Boot-Up Sequence

After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to

poll with a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host

gets a response back with the correct register content, it implies that the device has powered up and is out of

reset. After that, the host needs to set the wakeup-WLAN bit (F0 reg 0x00 bit 7). The wakeup-WLAN issues a

clock request to the PMU.

For the first time after power-up, the host must wait for the availability of low power clock inside the device. Once

that is available, the host must write to a PMU register to set the crystal frequency, which turns on the PLL. After

the PLL is locked, the chipActive interrupt is issued to the host. This interrupt indicates the device awake/ready

status. See Table 18 for information on gSPI registers.

In Table 18, the following notation is used for register access:

•

R: Readable from host and CPU

W: Writable from host

U: Writable from CPU

Table 18: gSPI Registers

Address Register

Bit Access Default Description

x0000

Word length

0

1

4

R/W/U

0

1

0: 16 bit word length

1: 32 bit word length

Endianness

0: Little Endian

1: Big Endian

High-speed mode

0: Normal mode. RX and TX at different edges.

1: High speed mode. RX and TX on same edge

(default).

Interrupt polarity

Wake-up

5

7

R/W/U

R/W

1

0

0: Interrupt active polarity is low

1: Interrupt active polarity is high (default)

A write of 1 will denote a wake-up command from

the host to the device. This will be followed by an F2

Interrupt from the gSPI device to the host, indicating

device awake status.

x0001

Response delay

7:0 R/W/U 8‘h04

Configurable read response delay in multiples of 8

bits

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

Table 18: gSPI Registers (Cont.)

Bit Access Default Description

Address Register

x0002

Status enable

0

1

2

R/W

1

0

0: no status sent to host after read/write

1: status sent to host after read/write

0: do not interrupt if status is sent

1: interrupt host even if status is sent

0: response delay applicable to F1 read only

1: response delay applicable to all function read

–

Interrupt with status

Response delay for

all

x0003

x0004

Reserved

–

0

–

0

Interrupt register

R/W

Requested data not available; Cleared by writing a

1 to this location

1

2

5

6

7

5

6

7

R

0

F2/F3 FIFO underflow due to last read

F2/F3 FIFO overflow due to last write

F2 packet available

F3 packet available

F1 overflow due to last write

F1 Interrupt

x0005

Interrupt register

F2 Interrupt

F3 Interrupt

x0006–

x0007

Interrupt enable

register

15:0 R/W/U 16'hE0E7 Particular Interrupt is enabled if a corresponding bit

is set

x0008–

x000B

Status register

31:0 R

32'h0000 Same as status bit definitions

x000C– F1 info register

x000D

0

1

R

1

F1 enabled

0

F1 ready for data transfer

F1 max packet size

F2 enabled

13:2 R/U

12'h40

x000E– F2 info register

x000F

0

1

R/U

R

1

0

F2 ready for data transfer

15:2 R/U

14'h800 F2 max packet size

x0010–

x0011

F3 info register

0

1

R/U

R

1

0

F3 enabled

F3 ready for data transfer

15:2 R/U

31:0 R

14'h800 F3 max packet size

x0014–

x0017

Test–Read only

register

32'hFEE This register contains a predefined pattern, which

DBEAD the host can read and determine if the gSPI

interface is working properly.

x0018–

x001B

Test–R/W register

31:0 R/W/U 32'h0000 This is a dummy register where the host can write

0000

some pattern and read it back to determine if the

gSPI interface is working properly.

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BCM4339 Preliminary Data Sheet

Generic SPI Mode

Figure 33 shows the WLAN boot-up sequence from power-up to firmware download.

Figure 33: WLAN Boot-Up Sequence

VBAT*

VDDIO

WL_REG_ON

< 950 µs

VDDC

(from internal PMU)

< 104 ms

Internal POR

After a fixed delay following Internal POR and WL_REG_ON going high,

the device responds to host F0 (address 0x14) reads.

< 4 ms

Device requests for reference clock

8 ms

After 8 ms the reference clock is

assumed to be up. Access to PLL

registers is possible.

Host Interaction:

Host polls F0 (address 0x14) until it reads a

predefined pattern.

Host sets wake-up-wlan bit and

waits 8 ms, the maximum time for

reference clock availability.

After 8 ms, host programs PLL

registers to set crystal frequency

Chip active interrupt is asserted after the PLL locks

Host downloads

code.

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

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BCM4339 Preliminary Data Sheet

PCI Express Interface (FCBGA Package Only)

The PCI Express (PCIe^™) core on the BCM4339 is a high-performance serial I/O interconnect that is protocol

compliant and electrically compatible with the PCI Express Base Specification (revision 3.0 compliant Gen1

interface). This core contains all the necessary blocks, including logical and electrical functional subblocks to

perform PCIe functionality and maintain high-speed links, using existing PCI system configuration software

implementations without modification.

Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as

shown in Figure 34. A configuration or link management block is provided for enumerating the PCIe

configuration space and supporting generation and reception of System Management Messages by

communicating with PCIe layers.

Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication

between the host and BCM4339 device. The transmit side processes outbound packets while the receive side

processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for

transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to

indicate the packet type and any other optional fields.

Figure 34: PCI Express Layer Model

HW/SW Interface

Transaction

Layer

Transaction

Layer

Data Link

Layer

Data Link

Layer

Physical Layer

Logical Subblock

Electrical Subblock

TX

RX

TX

RX

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BCM4339 Preliminary Data Sheet

PCI Express Interface (FCBGA Package Only)

Transaction Layer Interface

The PCIe core employs a packet-based protocol to transfer data between the host and BCM4339 device,

delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer. The

Transaction layer is primarily responsible for assembly and disassembly of Transaction Layer Packets (TLPs).

TLP structure contains header, data payload, and End-to-End CRC (ECRC) fields, which are used to

communicate transactions, such as read and write requests and other events.

A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication

between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries.

Data Link Layer

The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its

primary responsibility is to provide reliable, efficient mechanism for the exchange of TLPs between two directly

connected components on the link. Services provided by the data link layer include data exchange, initialization,

error detection and correction, and retry services.

Data Link Layer Packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the

mechanism used to transfer link management information between data link layers of the two directly connected

components on the link, including TLP acknowledgement, power management, and flow control.

Physical Layer

The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed

signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks.

Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between

the host and BCM4339 device. The transmit section prepares outgoing information passed from the data link

layer for transmission, and the receiver section identifies and prepares received information before passing it to

the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a

specific format.

Logical Subblock

The logical sub block primary functions are to prepare outgoing data from the data link layer for transmission

and identify received data before passing it to the data link layer.

Scrambler/Descrambler

This PCIe PHY component generates pseudo-random sequence for scrambling of data bytes and the idle

sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive

side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and

recovery for testing and debugging purposes.

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BCM4339 Preliminary Data Sheet

PCI Express Interface (FCBGA Package Only)

8B/10B Encoder/Decoder

The PCIe core on the BCM4339 uses an 8b/10b encoder/decoder scheme to provide DC balancing,

synchronizing clock and data recovery, and error detection. The transmission code is specified in the ANSI

X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4.

Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a

6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to

encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are

concatenated to form a 10-bit symbol, which is then transmitted serially. Special Symbols are used for link

management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.

Elastic FIFO

An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock

domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a

result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively

adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique

reduces the elastic FIFO size and the average receiver latency by half.

Electrical Subblock

The high-speed signals utilize the Common Mode Logic (CML) signaling interface with on-chip termination and

de-emphasis for best-in-class signal integrity. A de-emphasis technique is employed to reduce the effects of

Intersymbol Interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case

channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to

receive data with acceptable Bit-Error Rate (BER).

To further minimize ISI, multiple bits of the same polarity that are output in succession are de-emphasized.

Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for

maximum interoperability while minimizing the complexity of controlling the de-emphasis values. The high-

speed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the

receiver. The range of AC capacitance allowed is 75 nF to 200 nF.

Configuration Space

The PCIe function in the BCM4339 implements the configuration space as defined in the PCI Express Base

Specification (revision 3.0 compliant Gen1 interface).

Broadcom^®

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BCM4339 Preliminary Data Sheet

Wireless LAN MAC and PHY

Section 11: Wireless LAN MAC and PHY

IEEE 802.11ac MAC

The BCM4339 WLAN MAC is designed to support high-throughput operation with low-power consumption. It

does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over

both networks. In addition, several power saving modes have been implemented that allow the MAC to consume

very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC

is shown in Figure 35.

The following sections provide an overview of the important modules in the MAC.

Figure 35: WLAN MAC Architecture

Embedded CPU Interface

Host Registers, DMA Engines

TX-FIFO

32 KB

RX-FIFO

10 KB

PSM

PMQ

PSM

UCODE

Memory

IFS

Backoff, BTCX

WEP

TKIP, AES, WAPI

TSF

SHM

BUS

IHR

NAV

BUS

Shared Memory

6 KB

RXE

RX A-MPDU

TXE

TX A-MPDU

EXT- IHR

MAC-PHY Interface

The BCM4339 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base

standard, and amended by IEEE 802.11n. The key MAC features include:

•

Enhanced MAC for supporting IEEE 802.11ac features

Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT)

Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and

multiphase PSMP operation

•

Support for immediate ACK and Block-ACK policies

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 86

BCM4339 Preliminary Data Sheet

IEEE 802.11ac MAC

•

Interframe space timing support, including RIFS

Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges

Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification

Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon

transmission time (TBTT) generation in hardware

•

Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key

management

•

Support for coexistence with Bluetooth and other external radios

Programmable independent basic service set (IBSS) or infrastructure basic service set functionality

Statistics counters for MIB support

PSM

The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control

to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for

flow control operations, which are predominant in implementations of communication protocols. The instruction

set and fundamental operations are simple and general, which allows algorithms to be optimized until very late

in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications.

The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for

instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the

SHM bus). The PSM also uses a scratch-pad memory (similar to a register bank) to store frequently accessed

and temporary variables.

The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers

(IHR). These IHRs are co-located with the hardware functions they control, and are accessed by the PSM via

the IHR bus.

The PSM fetches instructions from the microcode memory using an address determined by the program

counter, instruction literal, or a program stack. For ALU operations the operands are obtained from shared

memory, scratch-pad, IHRs, or instruction literals, and the results are written into the shared memory, scratch-

pad, or IHRs.

There are two basic branch instructions: conditional branches and ALU based branches. To better support the

many decision points in the IEEE 802.11 algorithms, branches can depend on either a readily available signals

from the hardware modules (branch condition signals are available to the PSM without polling the IHRs), or on

the results of ALU operations.

WEP

The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the

encryption and decryption, and MIC computation and verification. The accelerators implement the following

cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP.

The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to

be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the

TXE to encrypt and compute the MIC on transmit frames, and the RXE to decrypt and verify the MIC on receive

frames.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 87

BCM4339 Preliminary Data Sheet

IEEE 802.11ac MAC

TXE

The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to

store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the

frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms.

The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical

queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel

access information from the IFS module to schedule a queue from which the next frame is transmitted. Once

the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from

the IFS module.

The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for

transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad

delimiters as needed.

RXE

The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to

drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with

the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO.

The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames

based on several criteria such as receiver address, BSSID, and certain frame types.

The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers,

and disaggregate them into component MPDUS.

IFS

The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also

contains multiple backoff engines required to support prioritized access to the medium as specified by WMM.

The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by

the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this

information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a

TXOP).

The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine

whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified,

so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the

same time, the hardware resolves the conflict based on policies provided by the PSM.

The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating

under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A

sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over

which the MAC remains in this suspended state. Once the timer expires the MAC is restored to its functional

state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF is synchronized to

the network.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 88

BCM4339 Preliminary Data Sheet

IEEE 802.11ac MAC

The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.

TSF

The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the

target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of

adopting timestamps received from beacon and probe response frames in order to maintain synchronization

with the network.

The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such

as uplink and downlink transmission times used in PSMP.

NAV

The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed

through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms

specified in the standard.

The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based

on received frames. This timing information is provided to the IFS module, which uses it as a virtual carrier-

sense indication.

MAC-PHY Interface

The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition,

there is an programming interface, which can be controlled either by the host or the PSM to configure and control

the PHY.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 89

BCM4339 Preliminary Data Sheet

IEEE 802.11ac PHY

The BCM4339 WLAN Digital PHY is designed to comply with IEEE 802.11ac and IEEE 802.11a/b/g/n single-

stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for

low-power, high-performance handheld applications.

The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other

impairments. It incorporates optimized implementations of the filters, FFT and Viterbi decoder algorithms.

Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for

carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. The

PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to

provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been

designed for shared single antenna systems between WL and BT to support simultaneous RX-RX.

The key PHY features include:

•

Programmable data rates from MCS0–9 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in

IEEE 802.11ac

•

Supports Optional Short GI mode in TX and RX

TX and RX LDPC for improved range and power efficiency

Supports optional space-time block code (STBC) receive of two space-time streams for improved

throughput and range in fading channel environments.

•

All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse

operations in the receive direction.

•

Supports IEEE 802.11h/k for worldwide operation

Advanced algorithms for low power, enhanced sensitivity, range, and reliability

Algorithms to improve performance in presence of Bluetooth

Automatic gain control scheme for blocking and non blocking application scenario for cellular applications

Closed loop transmit power control

Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities

On-the-fly channel frequency and transmit power selection

Supports per packet RX antenna diversity

Available per-packet channel quality and signal strength measurements

Designed to meet FCC and other worldwide regulatory requirements

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 90

BCM4339 Preliminary Data Sheet

IEEE 802.11ac PHY

Figure 36: WLAN PHY Block Diagram

CCK/DSSS Demodulate

Filters and Radio

Comp

Frequency and

Timing Synch

Descramble and

Deframe

OFDM Demodulate

Viterbi Decoder

Carrier Sense, AGC, and

Rx FSM

Buffers

MAC

Radio Control Block

FFT/IFFT

Interface

AFE and

Radio

Tx FSM

Modulation and

Coding

Common Logic Block

Frame and

Scramble

Filters and Radio Comp

PA Comp

Modulate/Spread

COEX

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 91

BCM4339 Preliminary Data Sheet

WLAN Radio Subsystem

Section 12: WLAN Radio Subsystem

The BCM4339 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in

2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust

communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII

bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions.

Ten RF control signals are available to drive external RF switches and support optional external power amplifiers

and low-noise amplifiers for each band. See the reference board schematics for further details.

A block diagram of the radio subsystem is shown in Figure 37 on page 93. Note that integrated on-chip baluns

(not shown) convert the fully differential transmit and receive paths to single-ended signal pins.

Receiver Path

The BCM4339 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. An on-chip

low-noise amplifier (LNA) in the 2.4 GHz path is shared between the Bluetooth and WLAN receivers, while the

5 GHz receive path has a dedicated on-chip LNA. Control signals are available that can support the use of

optional LNAs for each band, which can increase the receive sensitivity by several dB.

Transmit Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5-GHz U-NII bands, respectively. Linear

on-chip power amplifiers are included, which are capable of delivering high output powers while meeting

IEEE 802.11ac and IEEE 802.11a/b/g/n specifications without the need for external PAs. When using the

internal PAs, closed-loop output power control is completely integrated. As an option, external PAs can be used

for even higher output power, in which case the closed-loop output power control is provided by means of a-

band and g-band TSSI inputs from external power detectors.

Calibration

The BCM4339 features dynamic and automatic on-chip calibration to continually compensate for temperature

and process variations across components. These calibration routines are performed periodically in the course

of normal radio operation. Examples of some of the automatic calibration algorithms are baseband filter

calibration for optimum transmit and receive performance, and LOFT calibration for carrier leakage reduction.

In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip. No per-board calibration

is required in manufacturing test, which helps to minimize the test time and cost in large volume production.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 92

BCM4339 Preliminary Data Sheet

Calibration

Figure 37: Radio Functional Block Diagram

WL DAC

WL PA

WL PAD

WL PGA

WL TXLPF

WL TX G-Mixer

WL DAC

WL A-PA

WL A-PAD

WL A-PGA

WL TXLPF

WL TX A-Mixer

WL RX A-Mixer

Voltage

Regulators

WLAN BB

WL ADC

WL A-LNA11

WL A-LNA12

WL RXLPF

MUX

WL ADC

SLNA

WL G-LNA12

WL RXLPF

WL RX G-Mixer

WL ATX

WL ARX

WL GTX

WL GRX

CLB

WL LOGEN

WL PLL

Gm

BT LNA GM

Shared XO

BT RX

BT TX

BT LOGEN

BT PLL

LPO/Ext LPO/RCAL

BT ADC

BT RXLPF

BT ADC

BT LNA Load

BT PA

BT RX Mixer

BT BB

BT FM

BT DAC

BT TX Mixer

BT TXLPF

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 93

BCM4339 Preliminary Data Sheet

Ball Maps

Figure 40: 286-Bump WLCSP (Bottom View)

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 96

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19 contains the 286-bump WLCSP coordinates.

Table 19: 286-Bump WLCSP Coordinates

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

1

SR_PVSS

2275.005

1992.162

1709.319

2133.584

1850.741

1567.898

1992.162

1709.319

1850.741

1567.898

2275.005

1992.162

1709.319

2133.584

1850.741

2275.005

1992.162

1709.319

2133.584

1850.741

1567.898

2275.005

1992.162

1709.319

2133.584

1850.741

2275.005

1992.162

1709.319

2133.584

1850.741

1567.898

2275.005

2003.355

1861.934

1720.512

1579.091

1437.669

1296.248

1154.826

1013.405

871.983

730.562

589.140

447.719

306.297

–2275.005

–1992.162

–1709.319

–2133.584

–1850.741

–1567.898

–1992.162

–1709.319

–1850.741

–1567.898

–2275.005

–1992.162

–1709.319

–2133.584

–1850.741

–2275.005

–1992.162

–1709.319

–2133.584

–1850.741

–1567.898

–2275.005

–1992.162

–1709.319

–2133.584

–1850.741

–2275.005

–1992.162

–1709.319

–2133.584

–1850.741

–1567.898

–2275.005

2003.355

1861.934

1720.512

1579.091

1437.669

1296.248

1154.826

1013.405

871.983

730.562

589.140

447.719

306.297

2

SR_PVSS

3

WL_REG_ON

SR_PVSS

4

5

SR_PVSS

6

SR_VLX

7

SR_VLX

8

SR_VLX

9

SR_VLX

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

SR_VLX

SR_VDDBATP5V

SR_VLX

SR_VDDBATP5V

SR_VDDBATA5V

LDO_VDD1P5

VOUT_CLDO

LDO_VDD1P5

VOUT_CLDO

PMU_AVSS

VOUT_3P3

LDO_VDD1P5

VOUT_LNLDO

VOUT_3P3

LDO_VDD1P5

LDO_VDDBAT5V

VOUT_3P3

VOUT_3P3_SENSE

LDO_VDDBAT5V

VSSC

BT_REG_ON

VOUT_BTLDO2P5

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 97

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

LDO_VDDBAT5V

VSSC

1992.162

1709.319

2133.584

1850.741

1567.898

2000.397

2252.010

2264.169

1548.201

1931.412

1659.396

1944.471

2063.397

1800.498

1794.801

1784.397

2136.414

1653.744

1583.904

1393.104

632.001

306.297

–1992.162

–1709.319

–2133.584

–1850.741

–1567.898

–2000.397

–2252.010

–2264.169

–1548.201

–1931.412

–1659.396

–1944.471

–2063.397

–1800.498

–1794.801

–1784.397

–2136.414

–1653.744

–1583.904

–1393.104

–632.001

306.297

164.876

–45.054

–55.251

306.297

LDO_VDDBAT5V

PMU_VDDIO

LPO_IN

164.876

–45.054

HUSB_DN

–55.251

HUSB_DP

–255.429

–773.253

–980.847

–597.546

–623.367

–268.848

–434.448

–223.146

–839.853

–959.733

–991.854

–1213.488

–1114.101

–1226.646

–1166.652

–1334.853

–1650.546

–1363.752

–966.654

–1449.099

–1031.652

–1226.646

–704.151

–211.653

–464.652

–519.930

–1354.050

–1453.950

–1131.651

–1331.649

–255.429

–773.253

–980.847

–597.546

–623.367

–268.848

–434.448

–223.146

–839.853

–959.733

–991.854

–1213.488

–1114.101

–1226.646

–1166.652

–1334.853

–1650.546

–1363.752

–966.654

–1449.099

–1031.652

–1226.646

–704.151

–211.653

–464.652

–519.930

–1354.050

–1453.950

–1131.651

–1331.649

BT_I2S_DO

BT_I2S_DI

BT_I2S_CLK

BT_I2S_WS

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_IN

BT_PCM_OUT

BT_UART_CTS_N

BT_UART_RTS_N

BT_UART_RXD

BT_UART_TXD

BT_TM1

BT_VDDC_ISO_1

CLK_REQ

859.998

–859.998

2156.196

1652.097

1925.202

859.998

–2156.196

–1652.097

–1925.202

–859.998

BT_DEV_WAKE

BT_HOST_WAKE

BT_GPIO_2

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

BT_VDDIO

1688.097

470.001

–1688.097

–470.001

1139.997

1358.481

1489.998

1475.499

1265.574

933.699

–1139.997

–1358.481

–1489.998

–1475.499

–1265.574

–933.699

BT_VDDIO

BT_VDDC_ISO_2

BT_VDDC

1482.501

294.996

–1482.501

–294.996

BT_VDDC

294.996

–294.996

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 98

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

71

BT_VDDC

294.996

–931.653

–294.996

–864.903

–1067.997

–1139.997

–1479.864

–1569.797

–1597.593

–1756.686

–1769.795

–1797.591

–2045.451

–2080.781

–2118.860

–2245.449

–2261.469

–2274.852

–99.975

–931.653

72

BT_VDDC

864.903

–482.949

73

BT_VDDC

1067.997

1139.997

1479.864

1569.797

1597.593

1756.686

1769.795

1797.591

2045.451

2080.781

2118.860

2245.449

2261.469

2274.852

99.975

–482.949

74

BT_VDDC

–1026.648

–2546.550

–1888.101

–2333.169

–2533.167

–1888.101

–2333.169

–1548.549

–1760.319

–2546.550

–1960.317

–1760.319

–1548.549

–2444.675

–2086.889

–1842.066

–2042.064

–2291.099

–2422.625

–2525.544

–2491.097

–2116.746

–2501.330

–1842.066

–2042.064

–2500.155

–2240.766

–2150.537

–2411.789

–1753.146

–1572.417

–2098.656

–2561.652

–2570.652

–1026.648

–2546.550

–1888.101

–2333.169

–2533.167

–1888.101

–2333.169

–1548.549

–1760.319

–2546.550

–1960.317

–1760.319

–1548.549

–2444.675

–2086.889

–1842.066

–2042.064

–2291.099

–2422.625

–2525.544

–2491.097

–2116.746

–2501.330

–1842.066

–2042.064

–2500.155

–2240.766

–2150.537

–2411.789

–1753.146

–1572.417

–2098.656

–2561.652

–2570.652

75

FM_RFAUX

76

FM_IFVSS

77

FM_LNAVSS

FM_RFIN

78

79

FM_IFVDD

80

FM_LNAVDD

FM_DAC_VSS

FM_DAC_AVDD

FM_VCOVSS

FM_PLLVDD

FM_DAC_VOUT2

FM_DAC_VOUT1

FM_VCOVDD

FM_PLLVSS

BT_IFVSS

81

82

83

84

85

86

87

88

89

90

BT_IFVDD

99.975

–99.975

91

BT_AGPIO

99.975

–99.975

92

BT_PAVDD

281.860

–281.860

–461.505

–661.503

–873.183

–1005.281

–1174.454

–1208.352

–1352.595

2275.490

2251.986

2119.686

1902.494

1800.006

1600.008

93

BT_RF

461.505

94

BT_PAVSS

661.503

95

BT_LNAVSS

BT_LNAVDD

BT_PLLVSS

BT_PLLVDD

BT_VCOVDD

BT_VCOVSS

WRF_LNA_5G_GND1P2

WRF_RFIN_5G

WRF_RX5G_GND1P2

WRF_LOGEN_GND1P2

873.183

96

1005.281

1174.454

1208.352

1352.595

–2275.490

–2251.986

–2119.686

–1902.494

97

98

99

100

101

102

103

104

105

106

107

WRF_PA5G_VBAT_GND3P3 –1800.006

WRF_RFOUT_5G –1800.006

WRF_PA5G_VBAT_VDD3P3 –1600.008

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 99

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

WRF_PADRV_VBAT_GND3P3 –1400.010

WRF_PA5G_VBAT_GND3P3 –1400.010

WRF_PA5G_VBAT_VDD3P3 –1400.010

WRF_PA2G_VBAT_GND3P3 –1125.249

WRF_PADRV_VBAT_VDD3P3 –1089.249

WRF_PA2G_VBAT_VDD3P3 –1000.014

WRF_PA2G_VBAT_VDD3P3 –800.016

–1671.660

–2098.656

–2552.652

–1987.776

–1666.260

–2552.652

–2570.652

–2552.652

–2017.656

–1761.939

–2471.652

–2071.656

–1590.174

–943.668

–759.168

–1125.594

–1271.664

–471.672

–1047.744

–847.746

–647.748

–1047.744

–847.746

–1089.662

–889.668

–1271.664

–980.154

–353.066

–554.598

–353.066

–1185.062

–985.064

–753.062

–553.063

–52.326

1400.010

1125.249

1089.249

1000.014

800.016

–1671.660

–2098.656

–2552.652

–1987.776

–1666.260

–2552.652

–2570.652

–2552.652

–2017.656

–1761.939

–2471.652

–2071.656

–1590.174

–943.668

–759.168

–1125.594

–1271.664

–471.672

–1047.744

–847.746

–647.748

–1047.744

–847.746

–1089.662

–889.668

–1271.664

–980.154

–353.066

–554.598

–353.066

–1185.062

–985.064

–753.062

–553.063

–52.326

WRF_RFOUT_2G

–600.018

600.018

WRF_PA2G_VBAT_GND3P3 –542.224

542.224

WRF_RX2G_GND1P2

WRF_RFIN_2G

–302.509

–200.022

–165.822

–200.022

–279.173

–338.919

–661.308

–856.014

–1032.414

–1066.853

–1166.852

–1266.851

302.509

200.022

WRF_LNA_2G_GND1P2

WRF_RX2G_GND1P2

WRF_TSSI_A

200.022

165.822

200.022

WRF_GPIO_OUT

279.173

WRF_LOGENG_GND1P2

WRF_AFE_GND1P2

WRF_TX_GND1P2

WRF_VCO_GND1P2

WRF_BUCK_VDD1P5

WRF_BUCK_GND1P5

WRF_BUCK_VDD1P5

338.919

661.308

856.014

1032.414

1066.853

1166.852

1266.851

1503.344

1627.031

1854.006

1922.892

1950.522

2000.004

2199.998

2200.002

2205.429

2005.431

WRF_SYNTH_VBAT_VDD3P3 –1503.344

WRF_MMD_GND1P2

WRF_MMD_VDD1P2

WRF_CP_GND1P2

WRF_XTAL_VDD1P5

WRF_XTAL_GND1P2

WRF_XTAL_IN

–1627.031

–1854.006

–1922.892

–1950.522

–2000.004

–2199.998

–2200.002

–2205.429

–2005.431

WRF_PFD_VDD1P2

WRF_PFD_GND1P2

WRF_XTAL_VDD1P2

WRF_XTAL_OUT

BBPLLAVDD1P2

BBPLLAVSS

–57.348

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 100

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

RF_SW_CTRL_0

RF_SW_CTRL_1

RF_SW_CTRL_2

RF_SW_CTRL_3

RF_SW_CTRL_4

RF_SW_CTRL_5

RF_SW_CTRL_6

RF_SW_CTRL_7

RF_SW_CTRL_8

RF_SW_CTRL_9

OTP_VDD33

VDDIO_RF

–1831.200

–2072.022

–1691.052

–1895.118

–1809.960

–1617.639

–2129.154

–1573.278

–1749.264

–1944.888

–1400.001

–1399.398

–1400.001

–2055.795

–1943.295

–1689.455

–2280.795

–2168.295

–1830.795

–1576.959

–2168.295

–1943.295

–1689.455

–2280.795

–1830.795

–2055.795

–1269.996

–1040.001

–830.004

318.141

1831.200

2072.022

1691.052

1895.118

1809.960

1617.639

2129.154

1573.278

1749.264

1944.888

1400.001

1399.398

1400.001

2055.795

1943.295

1689.455

2280.795

2168.295

1830.795

1576.959

2168.295

1943.295

1689.455

2280.795

1830.795

2055.795

1269.996

1040.001

830.004

318.141

449.946

517.221

544.410

772.110

713.790

817.452

922.392

449.946

517.221

544.410

772.110

713.790

817.452

922.392

1019.259

972.936

1019.259

972.936

808.353

343.350

VDDIO_RF

543.348

NC

2207.556

2041.056

2207.556

2041.056

2207.556

2374.758

2541.258

1963.350

2168.352

1963.350

2168.352

1963.350

2168.352

1763.352

1963.350

1568.349

2207.556

2041.056

2207.556

2041.056

2207.556

2374.758

2541.258

1963.350

2168.352

1963.350

2168.352

1963.350

2168.352

1763.352

1963.350

1568.349

PAD_PLL_AVDD1P2

NC

PAD_PLL_AVSS

NC

PAD_PLL_AVSS

NC

PAD_RXTX_AVDD1P2

PAD_RXTX_AVSS

NC

SDIO_CLK

SDIO_CMD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

VDDIO_SD

STROBE

–735.000

735.000

–1040.001

–830.004

1040.001

830.004

–545.001

545.001

DATA

–240.000

240.000

RREFHSIC

–805.002

805.002

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 101

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

AGND12PLL

DVDD12HSIC2

AVDD12PLL

DVDD12HSIC

NC

–605.004

–394.998

–605.004

–394.998

–15.000

4.998

1553.346

1763.352

1553.346

2168.352

1768.347

1968.354

1768.347

2168.352

1568.349

1908.351

1568.349

1708.353

1508.346

1568.349

1348.353

1073.349

1338.354

1738.350

1538.352

1973.349

2168.352

668.349

605.004

1553.346

1763.352

1553.346

2168.352

1768.347

1968.354

1768.347

2168.352

1568.349

1908.351

1568.349

1708.353

1508.346

1568.349

1348.353

1073.349

1338.354

1738.350

1538.352

1973.349

2168.352

668.349

394.998

605.004

394.998

15.000

NC

–4.998

NC

–5.001

5.001

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_14

GPIO_13

GPIO_15

JTAG_SEL

VSSC

239.997

290.001

284.997

675.003

485.004

675.003

689.997

920.001

820.002

1119.999

1180.002

1119.999

699.996

900.003

605.001

384.996

605.001

–2120.001

–1920.003

–1689.999

–1490.001

–1249.998

–239.997

–290.001

–284.997

–675.003

–485.004

–675.003

–689.997

–920.001

–820.002

–1119.999

–1180.002

–1119.999

–699.996

–900.003

–605.001

–384.996

–605.001

2120.001

1920.003

1689.999

1490.001

1249.998

VSSC

468.351

VSSC

468.351

VSSC

668.349

VDDIO

1148.346

1368.351

948.348

1148.346

1368.351

948.348

VDDIO

VDDC_PHY

VDDC

1213.353

–71.649

1213.353

–71.649

VDDC

–71.649

VDDC_PHY

128.349

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 102

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

VDDC_PHY

VDDC

–840.003

–639.996

–269.997

–195.000

4.998

578.349

628.353

828.351

1568.349

1768.347

1268.352

–6.651

840.003

639.996

269.997

195.000

–4.998

578.349

628.353

828.351

1568.349

1768.347

1268.352

–6.651

VDDC

VDDC_PHY

VDDC

VDDC_SUBCORE

VDDC

4.998

193.347

393.354

628.353

828.351

1028.349

1568.349

1268.352

–216.648

1148.346

948.348

–211.653

–11.646

–24.588

1263.348

1563.354

1263.348

1763.352

–71.649

1263.348

–71.649

1563.354

–71.649

128.349

328.347

828.351

1028.349

1368.351

–4.998

193.347

393.354

628.353

828.351

1028.349

1568.349

1268.352

–216.648

1148.346

948.348

–211.653

–11.646

4.998

–4.998

4.998

–4.998

VDDC

4.998

–4.998

VDDC_SUBCORE

VDDC

4.998

–4.998

4.998

–4.998

4.998

–4.998

120.000

319.998

405.003

689.997

890.004

1090.002

1396.119

–1374.999

–1269.996

–1175.001

–1269.996

–1249.998

–975.003

–1050.000

–1040.001

–840.003

–805.002

–120.000

–319.998

–405.003

–689.997

–890.004

–1090.002

–1396.119

1374.999

1269.996

1175.001

1269.996

1249.998

975.003

1050.000

1040.001

840.003

805.002

VDDC

VDDC_SUBCORE

VDDC

VDDC_SUBCORE

VSSC

–24.588

1263.348

1563.354

1263.348

1763.352

–71.649

1263.348

–71.649

1563.354

–71.649

128.349

328.347

828.351

1028.349

1368.351

VSSC

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 103

BCM4339 Preliminary Data Sheet

Pin Lists

Table 19: 286-Bump WLCSP Coordinates (Cont.)

Pack age Bump Side View

(0,0 center of die)

Package Top Side View

(0,0 center of die)

Bump#

Signal Name

X

Y

X

Y

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

VSSC

–639.996

–439.998

94.998

828.351

1028.349

128.349

328.734

–71.649

–606.654

–806.652

193.347

1028.349

628.353

828.351

–1457.550

–446.652

393.354

193.347

–1457.550

–806.652

–446.652

468.351

668.349

–6.651

639.996

828.351

639.996

1028.349

128.349

328.734

–71.649

–606.654

–806.652

193.347

1028.349

628.353

828.351

–1457.550

–446.652

393.354

193.347

–1457.550

–806.652

–446.652

468.351

668.349

–6.651

439.998

–94.998

94.998

–94.998

204.996

133.104

305.004

204.996

499.998

457.401

499.998

505.002

499.998

699.996

660.603

900.003

1090.002

1100.001

1229.997

1290.000

–204.996

–133.104

–305.004

–204.996

–499.998

–457.401

–499.998

–505.002

–499.998

–699.996

–660.603

–900.003

–1090.002

–1100.001

–1229.997

–1290.000

–806.652

–606.654

–6.651

–806.652

–606.654

–6.651

–1457.550

68.346

–1457.550

68.346

–211.653

668.349

508.347

308.349

–211.653

668.349

508.347

308.349

–211.653

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 104

BCM4339 Preliminary Data Sheet

Signal Descriptions

The signal name, type, and description of each pin in the BCM4339 is listed in Table 20. The symbols shown

under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down

characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

WLAN and Bluetooth RF Signal Interface

N7

W10

118

WRF_RFIN_2G

I

2.4 GHz Bluetooth and WLAN

receiver shared input.

N5

W8

93

BT_RF_TX

O

I

Bluetooth PA output.

N12

N8

W18

W12

W16

V11

102

115

106

121

WRF_RFIN_5G

WRF_RFOUT_2G

WRF_RFOUT_5G

WRF_TSSI_A

5 GHz WLAN receiver input.

2.4 GHz WLAN PA output.

5 GHz WLAN PA output.

O

I

N11

J7

5 GHz TSSI input from an

optional external power

amplifier/power detector.

H7

V10

122

WRF_RES_EXT/

WRF_GPIO_OUT/

WRF_TSSI_G

I/O GPIO or 2.4 GHz TSSI input

from an optional external power

amplifier/power detector.

RF Switch Control Lines

F12

F11

E12

E11

D12

F8

J19

J17

J18

G19

H17

G17

G18

J16

G16

H16

145

146

147

148

149

150

151

152

153

154

RF_SW_CTRL_0

RF_SW_CTRL_1

RF_SW_CTRL_2

RF_SW_CTRL_3

RF_SW_CTRL_4

RF_SW_CTRL_5

RF_SW_CTRL_6

RF_SW_CTRL_7

RF_SW_CTRL_8

RF_SW_CTRL_9

O

Programmable RF switch

control lines. The control lines

are programmable via the

driver and NVRAM file.

H9

G7

E10

F5

WLAN PCI Express Interface

–

A19

–

PCIE_CLKREQ_L

OD PCIe clock request signal which

indicates when the REFCLK to

the PCIe interface can be

gated.

1 = the clock can be gated

0 = the clock is required

–

B16

–

PERST_L

I (PU) PCIe System Reset. This input

is the PCIe reset as defined in

the PCIe base specification

version 1.1.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 105

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

–

B13

C13

A18

B18

–

PAD_RDN0

I

Receiver differential pair (x1

lane).

PAD_RDP0

PAD_REFCLKN

PAD_REFCLKP

PCIE Differential Clock inputs

(negative and positive). 100

MHz differential.

–

B15

B14

B19

–

PAD_TDN0

PAD_TDP0

PCI_PME_L

O

Transmitter differential pair (x1

lane).

OD PCI power management event

output. Used to request a

change in the device or system

power state. The assertion and

deassertion of this signal is

asynchronous to the PCIe

reference clock. This signal has

an open-drain output structure,

as per the PCI Bus Local Bus

Specification, revision 2.3.

–

PAD_TESTP

PAD_TESTN

–

PCIe test pin.

WLAN SDIO Bus Interface

Note: These signals can also have alternate functionality depending on package and host interface mode.

Refer to Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118 for additional details.

B11

B12

B10

C10

D10

C11

B11

C11

C10

A11

C9

171

172

173

174

175

176

SDIO_CLK

I

SDIO clock input.

SDIO_CMD

I/O SDIO command line.

I/O SDIO data line 0.

I/O SDIO data line 1.

I/O SDIO data line 2.

I/O SDIO data line 3.

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

B9

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 106

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

WLAN GPIO Interface

Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific

functions. See Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118 for additional

details.

B6

C6

D6

B5

C5

D5

C4

D4

H1

–

D9

C16

C8

A7

B5

A5

C7

B7

E8

–

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_14

GPIO_13

GPIO_15

I/O Programmable GPIO pins.

Note: These GPIO signals can

be configured by software: as

either inputs or outputs, to have

internal pull-ups or pull-downs

enabled or disabled, and to use

either a high or low polarity

upon assertion.

I/O

–

A3

D8

D6

–

JTAG Interface

E5

C6

205

JTAG_SEL

I/O JTAG select. Pull high to select

the JTAG interface. If the JTAG

interface is not used, this pin

may be left floating or

connected to ground.

Note:SeeTable 28: “BCM4339

GPIO/SDIO Alternative Signal

Functions,” on page 118 for the

JTAG signal pins.

Clocks

H12

J12

B4

P19

R19

J7

138

142

39

WRF_XTAL_IN

WRF_XTAL_OUT

LPO_IN

I

O

I

XTAL oscillator input.

XTAL oscillator output.

External sleep clock input

(32.768 kHz).

H3

W3

56

CLK_REQ

O

Reference clock request

(shared by BT and WLAN).

FM Transceiver and SFLASH

–

N3

P3

49

46

BT_SF_MOSI

BT_SF_CLK

I/O SFLASH_SI

I/O SFLASH_CLK

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 107

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

–

R1

R2

–

47

48

78

75

86

BT_SF_CSN

BT_SF_MISO

FM_RFIN

I/O SFLASH_CSN

I/O SFLASH_SO

–

N2

–

I

FM Radio antenna port.

–

FM_RFAUX

FM radio auxiliary antenna port.

FM DAC output 1.

K1

–

FM_DAC_VOUT1/

FM_AOUT1

O

L1

–

85

FM_DAC_VOUT2/

FM_AOUT2

O

FM DAC output 2.

Bluetooth PCM

G2

–

46

BT_PCM_CLK/BT_PCMCLK I/O PCM clock; can be master

(output) or slave (input).

G1

J3

–

48

49

47

BT_PCM_IN

I

PCM data input.

PCM data output.

BT_PCM_OUT

BT_PCM_SYNC

O

H2

I/O PCM sync; can be master

(output) or slave (input).

Bluetooth USB Interface

–

N1

40

41

HUSB_DN

HUSB_DP

I/O USB (Host) data negative.

Negative terminal of the USB

transceiver.

–

N2

I/O USB (Host) data positive.

Positive terminal of the USB

transceiver.

Bluetooth UART

E6

T3

50

51

BT_UART_CTS_N/

BT_UART_CTS

I

UART clear-to-send. Active-low

clear-to-send signal for the HCI

UART interface.

F6

V1

BT_UART_RTS_N/

BT_UART_RTS/BT_LED

O

UART request-to-send. Active-

low request-to-send signal for

the HCI UART interface. BT

LED control pin.

G6

F7

W1

W2

52

53

BT_UART_RXD/

BT_RFDISABLE2

I

UART serial input. Serial data

input for the HCI UART

interface. BT RF disable pin 2.

BT_UART_TXD

O

UART serial output. Serial data

output for the HCI UART

interface.

Bluetooth/FM I2S

I²S clock, can be master

(output) or slave (input).

J6

R3

44

BT_I2S_CLK

I/O

I²S data output.

I²S data input.

K6

K5

U2

U3

42

43

BT_I2S_DO

BT_I2S_DI

I/O

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 108

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

I²S WS; can be master (output)

or slave (input).

H6

U1

45

BT_I2S_WS

I/O

Bluetooth Test Mode

U1

Bluetooth GPIO

–

55

BT_TM1

I/O ARM JTAG mode.

–

59

60

61

62

91

BT_GPIO_2

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

BT_AGPIO

I/O Bluetooth general-purpose I/O.

I/O BT analog GPIO pin.

–

C19

–

M6

–

Miscellaneous

B3 D5

3

WL_REG_ON

I

Used by PMU to power up or

power down the internal

BCM4339 regulators used by

the WLAN section. Also, when

deasserted, this pin holds the

WLAN section in reset. This pin

has an internal 200 kΩ pull-

down resistor that is enabled by

default. It can be disabled

through programming.

D3

C5

32

BT_REG_ON

I

Used by PMU to power up or

power down the internal

BCM4339 regulators used by

the Bluetooth/FM section. Also,

when deasserted, this pin holds

the Bluetooth/FM section in

reset. This pin has an internal

200 kΩ pull-down resistor that

is enabled by default. It can be

disabled through programming.

K3

J2

M3

V3

–

57

BT_DEV_WAKE

I/O Bluetooth DEV_WAKE.

I/O Bluetooth HOST_WAKE.

58

BT_HOST_WAKE

B8

179

HSIC_STROBE/STROBE

I/O Unsupported. This pin can be

connected to ground or left

unconnected (no-connect).

B7

B9

–

180

181

HSIC_DATA/DATA

RREFHSIC

I/O Unsupported. This pin can be

connected to ground or left

unconnected (no-connect).

I

Unsupported. Leave this pin

unconnected (no-connect).

Integrated Voltage Regulators

C2

C1

C3

15

SR_VDDBATA5V

SR_VDDBATP5V

I

Quiet VBAT.

Power VBAT.

B1, B2, C1 11, 12, 14

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 109

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

B2

A2, B2

6–10, 13

SR_VLX

O

Cbuck switching regulator

output. Refer to Table 45 on

page 151 for details of the

inductor and capacitor required

on this output.

D1

F2

F1, F2

L1

16, 19, 23, LDO_VDD1P5

26

I

LNLDO input.

27, 30, 34, LDO_VDDBAT5V

36

LDO VBAT.

H11

N19

136

WRF_XTAL_VDD1P5/

XTAL LDO input (1.35V).

WRF_XTAL_BUCK_VDD1P

5

K12

T19

141

WRF_XTAL_VDD1P2/

WRF_XTAL_OUT_VDD1P2

O

XTAL LDO output (1.2V).

E2

D2

F1

E1

–

K2

G2

J2

24

VOUT_LNLDO

VOUT_CLDO

O

Output of LNLDO.

Output of core LDO.

Output of BT LDO.

LDO 3.3V output.

17, 18, 20

33

VOUT_BTLDO2P5

VOUT_3P3

H1

H2

22, 25, 28

29

VOUT_3P3_SENSE

Voltage sense pin for LDO 3.3V

output.

Bluetooth Supplies

N6

N4

V8

92

96

BT_PAVDD/BT_PAVDD2P5 PWR Bluetooth PA power supply.

W5

BT_LNAVDD/

PWR Bluetooth LNA power supply.

BT_LNAVDD1P2

L4

M4

N3

–

W6

V6

V5

–

90

98

99

55

66

BT_IFVDD/BT_IFVDD1P2

PWR Bluetooth IF block power

supply.

BT_PLLVDD/

BT_PLLVDD1P2

PWR Bluetooth RF PLL power

supply.

BT_VCOVDD/

BT_VCOVDD1P2

PWR Bluetooth RF power supply.

BT_VDDC_ISO_1

PWR Core supply for power-on/off

island VDDC_G.

–

BT_VDDC_ISO_2

PWR Core supply for power-on/off

island VDDB.

FM Transceiver Supplies

–

87

80

–

FM_VCOVDD

PWR FM VCO supply.

–

FM_LNAVDD

PWR FM LNA power supply.

PWR FM LNA VCO power supply.

PWR FM PLL power supply.

N1

L2

FM_LNAVCOVDD1P2

84

FM_PLLVDD/

FM_PLLVDD1P2

–

79

82

FM_IFVDD

PWR FM IF power supply.

FM_DAC_AVDD

PWR FM DAC power supply.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 110

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

J1

–

FM_AUDIOVDD1P2

PWR FM Audio power supply.

WLAN Supplies

–

L15

127, 128,

130, 131

WRF_BUCK_VDD1P5

PWR Internal capacitor-less LDO

supply.

H8

K9

L9

–

WRF_WL_LNLDOIN_VDD1 PWR LNLDO 1.35V supply.

P5

V19

V14

132

112

WRF_SYNTH_VBAT_VDD3 PWR Synth VDD 3.3V supply.

P3

WRF_PADRV_VBAT_VDD3 PWR PA Driver VBAT supply.

P3

N10

N9

V15

V13

U18

T18

107, 110

113, 114

134

WRF_PA5G_VBAT_VDD3P3 PWR 5 GHz PA 3.3V VBAT supply.

WRF_PA2G_VBAT_VDD3P3 PWR 2 GHz PA 3.3V VBAT supply.

K10

K11

WRF_MMD_VDD1P2

WRF_PFD_VDD1P2

PWR 1.2V supply.

139

Miscellaneous Supplies

–

L18

155

OTP_VDD33

PWR OTP 3.3V supply.

C7, C12,

E10, E11,

213–241

VDDC/WL_VDDC

PWR 1.2V core supply for WLAN.

G4, G5, G8 G14, H14,

K7

F3

B3

210–212

VDDIO /VDDIO2

PWR 1.8V–3.3V supply for WLAN.

Must be directly connected to

PMU_VDDIO and BT_VDDIO

on the PCB.

H5, J4

–

L7, M7

L2

67–74

37, 38

BT_VDDC

PWR 1.2V core supply for BT.

PMU_VDDIO

PWR 1.8V–3.3V supply for PMU

controls. Must be directly

connected to VDDIO and

BT_VDDIO on the PCB.

H4

L3

63–65

BT_VDDIO

PWR 1.8V–3.3V supply for BT. Must

be directly connected to

PMU_VDDIO and VDDIO on

the PCB.

D9

E7

C8

A9

K17

–

177, 178

156, 157

184

VDDIO_SD

VDDIO_RF

PWR 1.8V–3.3V supply for SDIO

pads.

PWR IO supply for RF switch control

pads (3.3V).

AVDD12PLL/

HSIC_AVDD12PLL

PWR HSIC is not supported. Connect

this pin to ground to minimize

leakage.

C9

–

185

DVDD12HSIC/

HSIC_DVDD12

PWR HSIC is not supported. Connect

this pin to ground to minimize

leakage.

G12

–

L19

143

159

BBPLL_AVDD1P2

PLL_AVDD1P2

PWR 1.2V supply for baseband PLL.

PWR 1.2V supply for PCIe PLL.

D18

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 111

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

–

D19

167

AVDD1P2

PWR 1.2V supply for PCIe.

Ground

H10

L12

126

WRF_VCO_GND1P2/

WRF_VCO_GND

GND VCO/LOGEN ground.

–

183

124

129

DVDD12HSIC2

GND Supply for DVDD12HSIC2.

GND AFE ground.

K7

J8

R12

M12

WRF_AFE_GND1P2

WRF_BUCK_GND1P5

GND Internal capacitor-less LDO

ground.

M7

T10

T15

R13

R14

119

101

125

108

WRF_LNA_2G_GND1P2

WRF_LNA_5G_GND1P2

WRF_TX_GND1P2

GND 2 GHz internal LNA ground.

GND 5 GHz internal LNA ground.

GND TX ground.

M12

L8

L10

WRF_PADRV_VBAT_GND3 GND PAD ground.

P3

G11

L7

L12

–

M15, P18

P11

137

WRF_XTAL_GND1P2

WRF_RX2G_GND1P2

WRF_RX5G_GND1P2

WRF_LOGEN_GND1P2

WRF_LOGENG_GND1P2

WRF_LO_GND1P2_1

WRF_LO_GND1P2_2

GND XTAL ground.

GND RX 2GHz ground.

GND RX 5GHz ground.

GND LOGEN ground.

GND LO ground.

117, 120

103

T16

R15

104

–

M11

123

L11

K8

–

GND LO ground.

U15, V16

105, 109

WRF_PA5G_VBAT_GND3P GND 5 GHz PA ground.

3

–

R11, V12

111, 116

WRF_PA2G_VBAT_GND3P GND 2 GHz PA ground.

3

M11

M10

M9

–

WRF_PA_VBAT_GND3P3_1 GND PA ground.

WRF_PA_VBAT_GND3P3_2 GND PA ground.

WRF_PA_VBAT_GND3P3_3 GND PA ground.

WRF_PA_VBAT_GND3P3_4 GND PA ground.

–

M8

–

J9

P14

N15

133

135

WRF_MMD_GND1P2

GND Ground.

J11

WRF_CP_GND1P2/

WRF_CP_GND

J10

P15

140

WRF_PFD_GND1P2

GND Ground.

D7, D11,

H9–H12,

31, 35, 161, VSSC

GND Core ground for WLAN and BT.

E3, E8, J5, J8, J12, K8, 163, 168,

K4

K12, L8, L11, 242–286

M8–M10

B1

C3

D8

D1, E1, E2 1, 2, 4, 5

SR_PVSS

GND Power ground.

GND Quiet ground.

GND PLL ground.

H8

–

21

PMU_AVSS

182

AGND12PLL/

HSIC_AGNDPLL

M5

T8

94

BT_PAVSS

GND Bluetooth PA ground.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 112

BCM4339 Preliminary Data Sheet

Signal Descriptions

Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)

WLBGA

Ball#

FCFBGA

Ball#

WLCSP

Bump#

Signal Name

Type Description

–

R8

95

BT_LNAVSS

BT_IFVSS

GND Bluetooth LNA ground.

GND Bluetooth IF block ground.

GND Bluetooth PLL ground.

GND Bluetooth VCO ground.

GND FM VCO Ground.

GND FM LNA Ground.

L6

L5

M3

M1

M2

L3

–

R9

89

R7

97

BT_PLLVSS

BT_VCOVSS

FM_VCOVSS

FM_LNAVSS

FM_PLLVSS

FM_IFVSS

P8

100

83

–

77

–

88

GND FM PLL Ground.

–

76

GND FM IF ground.

–

81

FM_DAC_VSS

FM_AUDIOVSS

GND FM DAC ground.

K2

G10

–

GND FM Audio Ground.

L13

144

–

AVSS_BBPLL/BBPLLAVSS GND Baseband PLL ground.

D13, D16

PCIE_VSS

VSSC

GND PCIe ground.

GND Ground.

–

209

208

207

206

–

VSSC

–

VSSC

–

VSSC

No Connect

A2, A3, A4, F5, G5, W19 158, 160,

NC

–

No connect

A6, A7, A9,

A10, A11

162, 164,

165, 166,

169, 170,

186, 187,

188

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 113

BCM4339 Preliminary Data Sheet

WLAN GPIO Signals and Strapping Options

The pins listed in Table 21 are sampled at power-on reset (POR) to determine the various operating modes.

Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR,

each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping

option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change

the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kꢀ resistor or less.

Note: Refer to the reference board schematics for more information.

Table 21: WLAN GPIO Functions and Strapping Options

FCBGA

Pin #

WLBGA

Pin #

WLCSP

Pin #

Default

Function

Pin Name

Description

SDIO_SEL^a

GPIO_7

B7

D4

196

1

GPIO_8

E8

H1

–

197

202

171

0

1

SDIO_PADVDDIO

PCIE_DISABLE

GPIO_14

SDIO_CLK

A3

CPU-LESS/SPROM_DISABLE^a

SPI_SEL^a

B11

SDIO_DATA_2

C9

D10

175

1

a. See Table 22, Table 23, and Table 24.

Table 22: SDIO/gSPI I/O Voltage Selection (All Packages)

SDIO_SEL

SPI_SEL

SDIO_PADVDDIO

Mode

1

0

X

1

0

1

0

1

X

1.8V I/O

3.3V I/O

1.8V I/O

3.3V I/O

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 114

BCM4339 Preliminary Data Sheet

WLAN GPIO Signals and Strapping Options

Table 23: Host Interface Selection (FCBGA Package only)

SPROM_DISABL

PCIE_DISABLE E^a

SDIO_SEL SPI_SEL

Mode

1

0

X

1

0

1

0

1

0

X

0

SDIO and PCIe mode

SDIO mode

gSPI and PCIe mode

gSPI mode

PCIe mode with SPROM on the SDIO pins^b

PCIe mode (no SPROM)

0

1

a. SPROM_DISABLE strapping is valid only in the FCBGA package and only used if SDIO/gSPI is disabled.

b. SPROM is only available for PCIe mode.

Table 24: Host Interface Selection (WLBGA and WLCSP Packages^a)

SDIO_SEL

SPI_SEL

CPULESS

Mode

1

0

X

1

0

X

0

1

SDIO Mode (3.3V or 1.8V I/O)

gSPI Mode (3.3V or 1.8V I/O)

Unsupported

a. PCIe and SPROM modes are not available in the WLBGA and WLCSP packages.

Table 25: OTP/SPROM Select

Mode

SDIO CIS

PCIE Configuration

PCIe Disabled

From OTP if OTP is programmed;

ELSE default CIS.

–

PCIe Enabled

Default CIS

From SPROM if SPROM is present;

ELSE from OTP (if programmed);

ELSE default configuration.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 115

BCM4339 Preliminary Data Sheet

WLAN GPIO Signals and Strapping Options

Multiplexed Bluetooth GPIO Signals

The Bluetooth GPIO pins (BT_GPIO_0 to BT_GPIO_7) are multiplexed pins and can be programmed to be used

as GPIOs or for other Bluetooth interface signals such as I²S. The specific function for a given BT_GPIO_X pin

is chosen by programming the Pad Function Control register for that specific pin. Table 26 shows the possible

options for each BT_GPIO_X pin. Note that each BT_GPIO_X pin's Pad Function Control register setting is

independent (BT_GPIO_1 can be set to pad function 7 at the same time that BT_GPIO_3 is set to pad

function 0). When the Pad Function Control register is set to 0, the BT_GPIOs do not have specific functions

assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind

the BCM4339's PCM and I²S interface pins.

Table 26: GPIO Multiplexing Matrix

Pad Function Control Register Setting

Pin Name

0

1

2

3

4

5

6

7

15

BT_UART_CTS_ UART_CTS_N –

N

–

A_GPIO[1]

–

BT_UART_RTS_ UART_RTS_N –

N

–

A_GPIO[0]

–

BT_UART_RXD UART_RXD

–

GPIO[5]

GPIO[4]

–

BT_UART_TXD

BT_PCM_IN

UART_TXD

A_GPIO[3]

–

PCM_IN

HCLK

I2S_SSDI/

MSDI

SF_MISO

BT_PCM_OUT

A_GPIO[2]

PCM_OUT PCM_OUT LINK_IND

–

I2S_MSDO –

I2S_MWS

I2S_SSDO SF_MOSI

BT_PCM_SYNC A_GPIO[1]

PCM_SYNC PCM_SYN HCLK

C

INT_LPO

–

I2S_SWS

I2S_SSCK

STATUS

SF_SPI_CS

N

BT_PCM_CLK

A_GPIO[0]

PCM_CLK

–

I2S_MSCK –

SF_SPI_CL

K

BT_I2S_DO

BT_I2S_DI

A_GPIO[5]

A_GPIO[6]

PCM_OUT

PCM_IN

–

I2S_SSDO I2S_MSDO –

–

HCLK

I2S_SSDI/

MSDI

–

TX_CON_FX –

BT_I2S_WS

BT_I2S_CLK

GPIO[7]

GPIO[6]

GPIO[5]

PCM_SYNC

PCM_CLK

HCLK

–

LINK_IND

–

I2S_MWS

–

I2S_SWS

I2S_SSCK

CLK_REQ

–

INT_LPO

I2S_MSCK –

a

I2S_MSCK I2S_SSCK

I2S_MSDO I2S_SSDO

I2S_MWS I2S_SWS

–

BT_GPIO_5

a

GPIO[4]

GPIO[3]

GPIO[2]

LINK_IND

–

BT_GPIO_4

a

–

BT_GPIO_3

a

–

I2S_SSDI/

MSDI

BT_GPIO_2

BT_GPIO_1

BT_GPIO_0

CLK_REQ

GPIO[1]

GPIO[0]

–

CLASS1[2]

–

clk_12p288

–

WL/

A_GPIO[7]

BT_CLK_REQ

a. Available only in the WLCSP package.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 116

BCM4339 Preliminary Data Sheet

WLAN GPIO Signals and Strapping Options

The multiplexed GPIO signals are described in Table 27.

Table 27: Multiplexed GPIO Signals

Description

Pin Name

Type

UART_CTS_N

UART_RTS_N

UART_RXD

UART_TXD

PCM_IN

I

Host UART clear to send.

O

I

Device UART request to send.

Device UART receive data.

O

I

Host UART transmit data.

PCM data input.

PCM_OUT

PCM_SYNC

PCM_CLK

O

I/O

O

PCM data output.

PCM sync signal, can be master (output) or slave (input).

PCM clock, can be master (output) or slave (input).

General-purpose I/O.

GPIO[7:0]

A_GPIO[7:0]

I2S_MSDO

A group general-purpose I/O.

I²S master data output.

I²S master word select.

I²S master clock.

I2S_MWS

O

I

I2S_MSCK

I2S_SSCK

I2S_SSDO

I2S_SWS

I²S slave clock.

I²S slave data output.

I²S slave word select.

O

I

I²S slave/master data input.

I2S_SSDI/MSDI

I

STATUS

O

I

Signals Bluetooth priority status.

TX_CON_FX

RF_ACTIVE

LINK_IND

WLAN-BT coexist. Transmission confirmation; permission for BT to transmit.

WLAN-BT coexist. Asserted (logic high) during local BT RX and TX slots.

BT receiver/transmitter link indicator.

O

I

CLK_REQ

SF_SPI_CLK

SF_MISO

WLAN/BT clock request output.

SFlash SCLK: serial clock (output from master).

SFlash MISO; SOMI: master input, slave output (output from slave).

SFlash MOSI; SIMO: master output, slave input (output from master).

SFlash SS: slave select (active low, output from master).

SF_MOSI

O

SF_SPI_CSN

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 117

BCM4339 Preliminary Data Sheet

DC Characteristics

Section 14: DC Characteristics

Absolute Maximum Ratings

Caution! The absolute maximum ratings in Table 30 indicate levels where permanent damage to the

device can occur, even if these limits are exceeded for only a brief duration. Functional operation is

not guaranteed under these conditions. Operation at absolute maximum conditions for extended

periods can adversely affect long-term reliability of the device.

Table 30: Absolute Maximum Ratings

Rating

Symbol

Value

Unit

DC supply for VBAT and PA driver supply^a

DC supply voltage for digital I/O

DC supply voltage for RF switch I/Os

DC input supply voltage for CLDO and LNLDO

DC supply voltage for RF analog

DC supply voltage for core

VBAT

–0.5 to +6.0

V

VDDIO

VDDIO_RF

–

–0.5 to 3.9

–0.5 to 1.575

–0.5 to 1.32

–0.5 to 3.63

–0.5

V

VDD1P2

VDDC

–

WRF_TCXO_VDD

Maximum undershoot voltage for I/O^b

V_undershoot

Maximum overshoot voltage for I/O^b

Maximum junction temperature

V_overshoot

T_j

VDDIO + 0.5

125

V

°C

a. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative

duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V (for up to 250 seconds),

cumulative duration over the lifetime of the device, are allowed.

b. Duration not to exceed 25% of the duty cycle.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 122

BCM4339 Preliminary Data Sheet

Environmental Ratings

The environmental ratings are shown in Table 31.

Table 31: Environmental Ratings

Characteristic

Value

Units

Conditions/Comments

Functional operation^a

Ambient Temperature (T_A)

–30 to +85

°C

Storage Temperature

Relative Humidity

–40 to +125

Less than 60

Less than 85

°C

%

–

Storage

Operation

a. Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification

tables for details.

Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and

heel grounding straps to discharge static electricity is required when handling these devices. Always store

unused material in its antistatic packaging.

Table 32: ESD Specifications

Pin Type

Symbol

Condition

ESD Rating

Unit

ESD, Handling

Reference:

ESD_HAND_HBM Human body model contact discharge ±1000

per JEDEC EID/JESD22-A114

V

NQY00083, Section

3.4, Group D9, Table

B

CDM

ESD_HAND_CDM Charged device model contact

discharge per JEDEC EIA/JESD22-

C101

±300

V

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 123

BCM4339 Preliminary Data Sheet

Recommended Operating Conditions and DC Characteristics

Caution! Functional operation is not guaranteed outside of the limits shown in Table 33 and operation

outside these limits for extended periods can adversely affect long-term reliability of the device.

Table 33: Recommended Operating Conditions and DC Characteristics

Value

Parameter

Symbol

Minimum Typical Maximum Unit

3.0^a

1.14

5.25^b

1.26

1.98

DC supply voltage for VBAT

VBAT

–

V

DC supply voltage for core

VDD

1.2

1.8

V

DC supply voltage for RF blocks in chip

DC supply voltage for TCXO input buffer

VDD1P2

WRF_TCXO_VD 1.62

D

DC supply voltage for digital I/O

VDDIO,

VDDIO_SD

1.71

–

3.63

V

DC supply voltage for RF switch I/Os

External TSSI input

VDDIO_RF

3.13

0.15

3.3

–

3.46

0.95

V

WRF_TSSI_A,

WRF_TSSI_G

Internal POR threshold

Vth_POR

0.4

–

0.7

V

SDIO Interface I/O Pins

For VDDIO_SD = 1.8V:

Input high voltage

VIH

VIL

1.27

–

V

Input low voltage

0.58

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO_SD = 3.3V:

Input high voltage

VOH

VOL

1.40

–

0.45

VIH

VIL

0.625 ×

VDDIO

–

V

Input low voltage

–

0.25 ×

VDDIO

Output high voltage @ 2 mA

Output low voltage @ 2 mA

VOH

VOL

0.75 ×

VDDIO

–

0.125 ×

VDDIO

Other Digital I/O Pins

For VDDIO = 1.8V:

Input high voltage

VIH

VIL

0.65 ×

VDDIO

–

V

Input low voltage

–

0.35 ×

VDDIO

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 124

BCM4339 Preliminary Data Sheet

Recommended Operating Conditions and DC Characteristics

Table 33: Recommended Operating Conditions and DC Characteristics (Cont.)

Value

Parameter

Output high voltage @ 2 mA

Symbol

Minimum Typical Maximum Unit

VOH

VDDIO –

0.45

–

V

Output low voltage @ 2 mA

For VDDIO = 3.3V:

VOL

–

0.45

V

Input high voltage

VIH

VIL

2.00

–

V

Input low voltage

0.80

–

Output high voltage @ 2 mA

VOH

VDDIO –

0.4

Output low Voltage @ 2 mA

VOL

VOH

–

0.40

V

RF Switch Control Output Pins^c

For VDDIO_RF = 3.3V:

Output high voltage @ 2 mA

VDDIO –

0.4

–

V

Output low voltage @ 2 mA

Output capacitance

VOL

–

0.40

5

V

C_OUT

pF

a. The BCM4339 is functional across this range of voltages. Optimal RF performance specified in the data sheet,

however, is guaranteed only for 3.13V < VBAT < 4.8V.

b. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative

duration over the lifetime of the device are allowed. Voltage transients as high as 5.5V (for up to 250 seconds),

cumulative duration over the lifetime of the device are allowed.

c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 125

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Section 15: Bluetooth RF Specifications

Unless otherwise stated, limit values apply for the conditions specified in Table 31: “Environmental Ratings,” on

page 123 and Table 33: “Recommended Operating Conditions and DC Characteristics,” on page 124. Typical

values apply for the following conditions:

•

VBAT = 3.6V

Ambient temperature +25°C

Figure 41: Port Locations for Bluetooth Testing

BCM4339

RF Switch

(0.5 dB typical insertion loss)

WLAN Tx

BT Tx

Filter

WLAN/BT Rx

Antenna

Port

RF Port

Chip

Port

Note: All Bluetooth specifications are measured at the chip port unless otherwise specified.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 126

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Table 34: Bluetooth Receiver RF Specifications

Conditions Minimum Typical

Parameter

Maximum Unit

Note: The specifications in this table are measured at the chip port output unless otherwise specified.

General

Frequency range

RX sensitivity

–

2402

–

2480

MHz

dBm

GFSK, 0.1% BER, 1 Mbps –

–93.5

–95.5

–

/4–DQPSK, 0.01% BER,

2 Mbps

–

8–DPSK, 0.01% BER,

3 Mbps

–89.5

–

dBm

Input IP3

–

–16

–

dBm

Maximum input at antenna

–20

RX LO Leakage

2.4 GHz band

–

–90.0

–80.0

dBm

Interference Performance^a

C/I co-channel

GFSK, 0.1% BER

–

8

–

dB

C/I 1-MHz adjacent channel

C/I 2-MHz adjacent channel

–7

–38

–56

–31

–46

C/I  3-MHz adjacent channel GFSK, 0.1% BER

C/I image channel GFSK, 0.1% BER

C/I 1-MHz adjacent to image GFSK, 0.1% BER

channel

C/I co-channel

/4–DQPSK, 0.1% BER

–

9

–

dB

C/I 1-MHz adjacent channel

C/I 2-MHz adjacent channel

/4–DQPSK, 0.1% BER

–11

–39

–55

–23

–43

C/I  3-MHz adjacent channel /4–DQPSK, 0.1% BER

C/I image channel /4–DQPSK, 0.1% BER

C/I 1-MHz adjacent to image /4–DQPSK, 0.1% BER

channel

C/I co-channel

8–DPSK, 0.1% BER

–

17

–

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

–4

–37

–53

–16

–37

C/I  3-MHz adjacent channel 8–DPSK, 0.1% BER

C/I Image channel 8–DPSK, 0.1% BER

C/I 1-MHz adjacent to image 8–DPSK, 0.1% BER

channel

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 127

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Table 34: Bluetooth Receiver RF Specifications (Cont.)

Parameter

Conditions

Minimum Typical

Maximum Unit

Out-of-Band Blocking Performance (CW)

30–2000 MHz

0.1% BER

–

–10.0

–27

–

dBm

2000–2399 MHz

2498–3000 MHz

3000 MHz–12.75 GHz

–27

–10.0

Out-of-Band Blocking Performance, Modulated Interferer

GFSK (1 Mbps)^b

698–716 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–13.5

–13.8

–13.5

–14.3

–13.1

–18.1

–17.4

–19.4

–18.8

–19.7

–19.6

–20.4

–30.5

–

dBm

776–849 MHz

824–849 MHz

880–915 MHz

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD–SCDMA

WCDMA

Band 7

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

2500–2570 MHz ^e

2300-2400 MHz ^f

2570–2620 MHz ^c

2545–2575 MHz ^d

Band 40

Band 38

XGP Band

–

–34.0

–30.8

–29.5

–

dBm

DPSK (2 Mbps)^b

π/4

698–716 MHz

776–794 MHz

824–849 MHz

880–915 MHz

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–9.8

–

dBm

–9.7

–10.7

–11.4

–10.4

–10.2

–15.8

–15.4

–16.6

–16.4

–17.9

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 128

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Table 34: Bluetooth Receiver RF Specifications (Cont.)

Parameter

Conditions

Minimum Typical

Maximum Unit

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

WCDMA

TD-SCDMA

WCDMA

Band 7

–

–16.8

–18.6

–20.4

–31.9

–

dBm

2500–2570 MHz ^e

2300–2400 MHz ^f

2570-2620 MHz ^c

2545-2575 MHz ^d

Band 40

Band 38

XGP Band

–

–35.3

–31.8

–31.1

–

dBm

8DPSK (3 Mbps)^b

698–716 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–12.6

–12.7

–13.7

–12.8

–12.6

–18.1

–17.4

–19.1

–18.6

–19.3

–18.9

–20.4

–21.4

–31.0

–

dBm

776–794 MHz

824–849 MHz

880–915 MHz

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD-SCDMA

WCDMA

Band 7

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

2500–2570 MHz ^e

2300–2400 MHz ^f

2570–2620 MHz ^c

2545–2575 MHz ^d

Band 40

Band 38

XGP Band

–

–34.5

–31.2

–30.0

–

dBm

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 129

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Table 34: Bluetooth Receiver RF Specifications (Cont.)

Conditions Minimum Typical

Parameter

Maximum Unit

Spurious Emissions

30 MHz–1 GHz

1–12.75 GHz

–

–95

–62

–47

–

dBm

–70

dBm

851–894 MHz

925–960 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

–147

dBm/Hz

–

a. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined

in the version 4.1 specification.

b. Bluetooth reference level is taken at the 3 dB RX desense on each of the modulation schemes.

c. Interferer: 2380 MHz, BW=10 MHz; measured at 2480 MHz.

d. Interferer: 2355 MHz, BW=10 MHz; measured at 2480 MHz.

e. Interferer: 2560 MHz, BW=10 MHz; measured at 2480 MHz.

f. Interferer: 2360 MHz, BW=10 MHz; measured at 2402 MHz.

Table 35: Bluetooth Transmitter RF Specifications

Parameter

Conditions

Minimum Typical Maximum Unit

Note: The specifications in this table are measured at the chip port output unless otherwise specified.

General

Frequency range

2402

11.0

8.0

2

–

2480

MHz

dBm

dB

Basic rate (GFSK) TX power at Bluetooth

QPSK TX Power at Bluetooth

8PSK TX Power at Bluetooth

Power control step

13.0

10.0

4

–

8

Note: Output power is with TCA and TSSI enabled.

GFSK In-Band Spurious Emissions

–20 dBc BW

–

0.93

1

MHz

EDR In-Band Spurious Emissions

1.0 MHz < |M – N| < 1.5 MHz

M – N = the frequency range for –

–38

–31

–43

–26.0

–20.0

–40.0

dBc

which the spurious emission is

1.5 MHz < |M – N| < 2.5 MHz

–

dBm

measured relative to the

transmit center frequency.

|M – N|  2.5 MHz^a

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 130

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Table 35: Bluetooth Transmitter RF Specifications (Cont.)

Parameter

Conditions

Minimum Typical Maximum Unit

Out-of-Band Spurious Emissions

–36.0 ^{b, c}

30 MHz to 1 GHz

–

dBm

–30.0 ^{b, d, e}

–47.0

1 GHz to 12.75 GHz

–

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

–

dBm

–47.0

GPS Band Spurious Emissions

Spurious emissions

–

–103

–

dBm

Out-of-Band Noise Floor^f

65–108 MHz

FM RX

–

–147

–146

–145

–144

–141

–140

–

dBm/Hz

776–794 MHz

CDMA2000

cdmaOne, GSM850

E-GSM

869–960 MHz

925–960 MHz

1570–1580 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

GPS

GSM1800

GSM1900, cdmaOne, WCDMA –

WCDMA

Band 7

–

Band 40

Band 38

XGP Band

a. The typical number is measured at ±3 MHz offset.

b. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.

c. The spurious emissions during Idle mode are the same as specified in Table 35 on page 130.

d. Specified at the Bluetooth Antenna port.

e. Meets this specification using a front-end band-pass filter.

f. Transmitted power in cellular and FM bands at the Bluetooth Antenna port. See Figure 41 on page 126 for

location of the port.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 131

BCM4339 Preliminary Data Sheet

Bluetooth RF Specifications

Table 36: Local Oscillator Performance

Minimum Typical

Parameter

Maximum Unit

LO Performance

Lock time

–

72

–

s

Initial carrier frequency tolerance

±25

±75

kHz

Frequency Drift

DH1 packet

DH3 packet

DH5 packet

Drift rate

–

±8

5

±25

±40

20

kHz

kHz/50 µs

Frequency Deviation

00001111 sequence in payload^a

140

115

–

155

140

1

175

–

kHz

MHz

10101010 sequence in payload^b

Channel spacing

–

a. This pattern represents an average deviation in payload.

b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.

Table 37: BLE RF Specifications

Parameter

Conditions

Minimum Typical

Maximum Unit

Frequency range

RX sense^a

–

2402

2480

–

MHz

dBm

GFSK, 0.1% BER, 1 Mbps

–

–95.5

8.5

TX power^b

–

dBm

Mod Char: delta F1 average –

225

255

–

275

–

kHz

%

Mod Char: delta F2 max^c

–

99.9

Mod Char: ratio

–

0.8

0.95

–

%

a. Dirty TX is On.

b. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The

output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm specification

limit.

c. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 132

BCM4339 Preliminary Data Sheet

FM Receiver Specifications

Section 16: FM Receiver Specifications

Unless otherwise stated, limit values apply for the conditions specified inTable 31: “Environmental Ratings,” on

page 123 and Table 33: “Recommended Operating Conditions and DC Characteristics,” on page 124. Typical

values apply for the following conditions:

•

VBAT = 3.6V

Ambient temperature +25°C

Table 38: FM Receiver Specifications

Conditions^a

Typica

Minimum l

Parameter

Maximum Units

RF Parameters

Operating frequency^b

Sensitivity^c

Frequencies inclusive

65

–

0

108

–

MHz

FM only

SNR > 26 dB

dBµV

EMF

–

1

–

µV EMF

dBuV

–6

Receiver adjacent

channel selectivity^{c, d}

Measured for 30 dB SNR at the audio output with best tune.

Signal of interest: 23 dBµV EMF (14.1 µV EMF),

At ± 200 kHz.

At ± 400 kHz

–

51

62

53

–

dB

–

Intermediate signal plus Vin = 20 dBµV EMF (10 µV EMF)

noise-to-noise ratio (S+N)/

45

N^c

Intermodulation

performance^{c, d}

Blocker level increased until desired at

30 dB SNR

Wanted Signal: 33 dBµV EMF (45 µV

EMF)

–

55

–

dBc

Modulated Interferer: At f_Wanted

+ 400 kHz and +4 MHz

CW Interferer: At f_Wanted+ 800 kHz and

+ 8 MHz

AM suppression, mono^c

Vin = 23 dBµV EMF (14.1 µV EMF)

AM at 400 Hz with m = 0.3

No A-weighted or any other filtering

applied.

40

–

dB

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 133

BCM4339 Preliminary Data Sheet

FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Minimum l

Typica

Parameter

RDS

Conditions^a

Maximum Units

RDS Sensitivity^{e, f}

RDS deviation = 1.2 kHz

RDS deviation = 2 kHz

–

16

–

dBµV

EMF

–

6.3

10

12

–

µV EMF

dBuV

dBµV

EMF

–

4

6

–

µV EMF

dBuV

RDS selectivity^f

Wanted Signal: 33 dBµV EMF (45 µV EMF), 2 kHz RDS deviation with best tune

Interferer: ꢁf = 40 kHz, fmod = 1 kHz

± 200 kHz

± 300 kHz

± 400 kHz

–

49

52

–

dB

kꢀ

pF

–

RF input impedance

1.5

2.5

–

Antenna tuning capacitor

Maximum input level^c

–

30

113

SNR > 26 dB

–

dBµV

EMF

–

446

107

–55

mV EMF

dBuV

RF conducted emissions Local oscillator breakthrough measured –

dBm

(measured into a 50ꢀ

on the reference port

load)

869–894 MHz, 925–960 MHz,

1805–1880 MHz, 1930–1990 MHz.

GPS

–

7

–90

–

dBm

RF blocking levels at the GSM850, E-GSM (std), BW = 0.2 MHz, –

FM antenna input 40 dB 824–849 MHz

SNR (assumes a 50ꢀ at 880–915 MHz

the radio input and

excludes spurs)

GSM850, E-GSM (edge),

BW = 0.2 MHz,

824–849 MHz

–

–1

12

–

dBm

880–915 MHz

GSM DCS 1800, PCS 1900 (std/edge), –

BW = 0.2 MHz,

1710–1785 MHz

1850–1910 MHz

WCDMA: II(I), III(IV, X),

BW = 5 MHz,

–

1850–1980 MHz (1920–1980 MHz),

1710–1785 MHz (1710–1755 MHz,

1710–1770 MHz)

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 134

BCM4339 Preliminary Data Sheet

FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Minimum l

Typica

Parameter

Conditions^a

Maximum Units

WCDMA: V(VI), VIII, XII, XIII, XIV,

BW = 5 MHz,

–

5

–

dBm

824–849 MHz (830–840 MHz),

880–915 MHz

CDMA2000, cdma One,

BW = 1.25 MHz,

824–849 MHz,

–

0

–

dBm

887–925 MHz,

776–794 MHz

CDMA2000, cdma One,

BW = 1.25 MHz,

–

12

–

dBm

1850–1910 MHz,

1750–1780 MHz,

1920–1980 MHz

Bluetooth, BW = 1 MHz,

2402–2480 MHz

–

11

6

–

dBm

IEEE 802.11g/b, BW = 20 MHz,

2400–2483.5 MHz

IEEE 802.11a, BW = 20 MHz,

4915–5825 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

Band 7

–

11

–

dBm

Band 40

Band 38

XGP band

Tuning

Frequency step

Settling time

10

–

kHz

µs

Single-frequency switch in any direction –

to a frequency within the bands 88–

108 MHz or 76–90 MHz. Time measured

to within 5 kHz of the final frequency.

150

Search time

Total time for an automatic search to

sweep from 88–108 MHz or 76–90 MHz

(and reverse direction) assuming no

channels are found.

–

8

sec

General Audio

I²S audio output level^g

–14.5

–

–12.5

0

dBFS

Maximum audio output

level^h

Audio DAC output level^g

Maximum DAC audio

output level^h

72

–

88

–

mV rms

333

Audio DAC output level

differenceⁱ

–1

–

1

dB

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 135

BCM4339 Preliminary Data Sheet

FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Minimum l

Typica

Parameter

Conditions^a

Maximum Units

Left and right AC mute

FM input signal fully muted with DAC

enabled

60

80

–

dB

–

Left and right hard mute FM input signal fully muted with DAC

disabled

Soft mute attenuation and Muting is performed dynamically

start level

proportional to the FM wanted input

signal C/N. The muting characteristic is

fully programmable. Refer to “Audio

Features” on page 66 for further details.

Maximum signal plus

noise-to-noise ratio

–

69

64

–

dB

%

(S + N)/N, mono ⁱ

Maximum signal plus

noise-to-noise ratio

(S + N)/N, stereo^g

–

Total harmonic distortion, Vin = 66 dBµV EMF (2 mV EMF),

0.8

mono

∆f = 75 kHz, fmod = 400 Hz

∆f = 75 kHz, fmod = 1 kHz

∆f = 75 kHz, fmod = 3 kHz

∆f = 100 kHz, fmod = 1 kHz

–

0.8

1.0

1.5

%

Total harmonic distortion, Vin = 66 dBµV EMF (2 mV EMF)

stereo

∆f = 67.5 kHz, fmod = 1 kHz, ꢁf

Pilot = 7.5 kHz, L = R

Audio spurious productsⁱ

Range from 300 Hz to 15 kHz, with

respect to 1 kHz tone

–

–60

–

dBc

kHz

Hz

Audio bandwidth, upper (– Vin = 66 dBµV EMF (2 mV EMF)

15

–

3 dB point)

∆f = 8 kHz, for 50 µs

Audio bandwidth, lower (–

3 dB point)

20

0.5

Audio in-band ripple

100 Hz to 13 kHz,

–0.5

dB

Vin = 66 dBµV EMF (2 mV EMF)

∆f = 8 kHz, for 50 µs

Deemphasis time

constant tolerance

With respect to 50 and 75 µs

–

3

–

±5

83

%

RSSI range

With 1 dB resolution and ± 5 dB

accuracy at room temp

dBµV

EMF

1.41

–3

–

14100

77

µV EMF

dBuV

Stereo Decoder

Stereo channel separation Forced Stereo mode

Vin = 66 dBµV EMF (2 mV EMF),

–

48

–

dB

∆f = 67.5 kHz, fmod = 1 kHz,

ꢁf Pilot = 6.75 kHz

R = 0, L = 1

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 136

BCM4339 Preliminary Data Sheet

FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Minimum l

Typica

Parameter

Conditions^a

Maximum Units

Mono stereo blend and

switching

Blending and switching is dynamically

proportional to the FM wanted input

signal C/N. The blending and switching

characteristics are fully programmable.

Refer to “Audio Features” on page 66 for

further details.

Pilot suppression

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 75 kHz, fmod = 1 kHz

46

–

dB

Pause detection

Audio level at which a

pause is detected

Relative to 1 kHz tone, ∆f = 22.5 kHz

Four values in 3 dB steps

Four values

–

–21

20

–12

40

dB

ms

Audio pause duration

a. Following conditions are applied to all relevant tests unless otherwise indicated: Pre-emphasis and de-emphasis

of 50 us, R = L for mono, DAC Load > 20 kꢀ, BAF = 300 Hz to 15 kHz, and A-weighted filtering applied.

b. Contact Broadcom regarding applications that operate between 65 and 76 MHz.

c. Wanted Signal: ∆f = 22.5 kHz, and fmod = 1 kHz.

d. Interferer: ꢁf = 22.5 kHz, and fmod = 1 kHz.

e. RDS sensitivity numbers are for 87.5–108 MHz only.

f. Vin = ꢁf = 32 kHz, fmod = 1 kHz, ꢁf Pilot = 7.5 kHz, and 95% of blocks decoded with no errors after correction

g. Vin = 66 dBµV EMF (2 mV EMF), ∆f = 22.5 kHz, fmod = 1 kHz, and ꢁf Pilot = 6.75 kHz.

h. Vin = 66 dBµV EMF (2 mV EMF), ∆f = 100 kHz, fmod = 1 kHz, and ∆f Pilot = 6.75 kHz.

i. Vin = 66 dBµV EMF (2 mV EMF), ∆f = 22.5 kHz, and fmod = 1 kHz.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 137

BCM4339 Preliminary Data Sheet

WLAN RF Specifications

Section 17: WLAN RF Specifications

Introduction

The BCM4339 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the

5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radio.

Unless otherwise stated, limit values apply for the conditions specified inTable 31: “Environmental Ratings,” on

page 123 and Table 33: “Recommended Operating Conditions and DC Characteristics,” on page 124. Typical

values apply for the following conditions:

•

VBAT = 3.6V

Ambient temperature +25°C

Figure 42: Port Locations Showing Optional ePA and eLNA (Applies to 2.4 GHz and 5 GHz)

BCM4339

RF Switch

(0.5 dB typical insertion loss)

WLAN Tx

BT Tx

Filter

WLAN/BT Rx

Antenna

Port

RF Port

Chip

Port

2.4 GHz Band General RF Specifications

Table 39: 2.4 GHz Band General RF Specifications

Item

Condition

Including TX ramp down –

Including TX ramp up

DSSS/CCK modulations –

Minimum Typical

Maximum Unit

TX/RX switch time

RX/TX switch time

–

5

µs

–

2

Power-up and power-down ramp

time

< 2

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 138

BCM4339 Preliminary Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Note: The specifications in Table 40 are specified at the RF port and include the use of an external

FEM with LNA from Broadcom’s approved-vendor list (AVL), unless otherwise specified. Results with

FEMs that are not on Broadcom’s AVL are not guaranteed.

Table 40: WLAN 2.4 GHz Receiver Performance Specifications

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Frequency range

–

2400

–

2500

MHz

dBm

RX sensitivity IEEE 802.11b 1 Mbps DSSS

–

–98.4

–96.5

–93.7

–91.4

–95.5

–94.1

–93.2

–90.6

–87.3

–84.0

–79.3

–77.8

–

(8% PER for 1024 octet

PSDU)^a

2 Mbps DSSS

5.5 Mbps DSSS

11 Mbps DSSS

RX sensitivity IEEE 802.11g 6 Mbps OFDM

(10% PER for 1024 octet

PSDU)^a

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

RX sensitivity IEEE 802.11n 20 MHz channel spacing for all MCS rates

(10% PER for 4096 octet

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

–

–95.0

–92.7

–90.2

–87.1

–83.5

–78.9

–77.3

–75.7

–

dBm

PSDU)^a,b.Defined for

default parameters: 800 ns

GI and non-STBC.

RX sensitivity IEEE 802.11n 40 MHz channel spacing for all MCS rates

(10% PER for 4096 octet

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

–

–92.8

–89.9

–87.5

–84.0

–80.9

–76.2

–74.7

–73.3

–

dBm

PSDU)^a,c.Defined for

default parameters: 800 ns

GI and non-STBC.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 139

BCM4339 Preliminary Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 40: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

RX sensitivity

20 MHz channel spacing for all MCS rates

IEEE 802.11ac

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

–

–94.3

–91.9

–90.1

–86.9

–83.4

–78.9

–77.3

–75.6

–71.2

–

dBm

(10% PER for 4096 octet

PSDU)^a,d.Defined for

default parameters: 800 ns

GI and non-STBC

RX sensitivity

40 MHz channel spacing for all MCS rates

IEEE 802.11ac

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS9

MCS7

MCS8

MCS7

MCS8

MCS9

MCS7

MCS8

MCS9

–

–91.5

–89.0

–87.2

–84.0

–80.8

–76.3

–74.7

–73.3

–68.9

–67.6

–77.4

–74.7

–74.6

–71.6

–70.1

–71.5

–68.1

–66.0

–

dBm

(10% PER for 4096 octet

PSDU)^a,e.Defined for

default parameters: 800 ns

GI and non-STBC.

RX sensitivity IEEE

20 MHz

40 MHz

80 MHz

802.11ac 20/40/80 MHz

channel spacing with LDPC

(10% PER for 4096 octet

PSDU) at WLAN RF port.

Defined for default

parameters: 800 ns GI,

LDPC coding, and non-

STBC.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 140

BCM4339 Preliminary Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 40: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Blocking level for 3 dB RX 776–794 MHz

CDMA2000

cdmaOne

–

–24

–25

–

dBm

sensitivity degradation

824–849 MHz^g

(without external filtering)^f

824–849 MHz

GSM850

E-GSM

–

–15

–16

–18

–19

–26

–28.5

–45

–50

–45

–

dBm

880–915 MHz

–

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

GSM1800

cdmaOne

WCDMA

Band 7

–

Band 40

Band 38

XGP Band

–

In-band static CW jammer RX PER < 1%, 54 Mbps OFDM,

–80

immunity

1000 octet PSDU for:

(RxSens + 23 dB < Rxlevel < max input

level)

(fc – 8 MHz < fcw < + 8 MHz)

Input in-band IP3^a

Maximum LNA gain

–

–15.5

–

dBm

Minimum LNA gain

–

–1.5

Maximum receive level

@ 2.4 GHz

@ 1, 2 Mbps (8% PER, 1024 octets)

–3.5

–

@ 5.5, 11 Mbps (8% PER, 1024 octets) –9.5

@ 6–54 Mbps (10% PER, 1024 octets) –9.5

@ MCS0–7 rates (10% PER, 4095

octets)

–9.5

–11.5

9

@ MCS8–9 rates (10% PER, 4095

octets)

–

dBm

MHz

LPF 3 dB bandwidth

–

36

Adjacent channel

rejection—DSSS

Desired and interfering signal 30 MHz apart

1 Mbps DSSS

2 Mbps DSSS

–74 dBm

35

–

dB

(Difference between

interfering and desired

signal at 8% PER for 1024

octet PSDU with desired

signal level as specified in

Condition/Notes)

Desired and interfering signal 25 MHz apart

5.5 Mbps DSSS

11 Mbps DSSS

–70 dBm

35

–

dB

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 141

BCM4339 Preliminary Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 40: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Adjacent channel

rejection—OFDM

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–79 dBm

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

–79 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

–61 dBm

–59 dBm

–57 dBm

–

16

15

13

11

8

–

95

3

–

5

dB

(Difference between

interfering and desired

signal (25 MHz apart) at

10% PER for 1024 octet

PSDU with desired signal

level as specified in

4

0

Condition/Notes)

–1

16

13

11

8

Adjacent channel rejection MCS0

MCS0–9 (Difference

between interfering and

desired signal (25 MHz

apart) at 10% PER for 4096

octet PSDU with desired

signal level as specified in

Condition/Notes)

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS9

–

4

0

–1

–2

–4

–6

–

Maximum receiver gain

Gain control step

RSSI accuracy^h

–

Range –95 dBmⁱto –30 dBm

Range above –30 dBm

–5

–8

10

–

8

dB

Return loss

Z_o= 50ꢀ, across the dynamic range

11.5

13

Receiver cascaded noise

figure

At maximum gain

–

4

–

dB

a. Derate by 1.5 dB for –30°C to –10°C and 55°C to 85°C.

b. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.

c. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.

d. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.

e. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.

f. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal

in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any

specific country.

g. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to

third harmonic signals (3 × 824 MHz) falling within band.)

h. The minimum and maximum values shown have a 95% confidence level.

i. –95 dBm with calibration at the time of manufacture, –92 dBm without calibration.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 142

BCM4339 Preliminary Data Sheet

WLAN 2.4 GHz Transmitter Performance Specifications

Note: The specifications in Table 41 include the use of the BCM4339's internal PAs and are specified

at the chip port.

Table 41: WLAN 2.4 GHz Transmitter Performance Specifications

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Frequency range

–

2400

–

2500

MHz

Transmitted power in

cellular and FM bands

(at 18.5 dBm, 100% duty

cycle, 1 Mbps CCK)^a

76–108 MHz

776–794 MHz

869–960 MHz

FM RX

–

–148.5

–126.5

–162.5

–

dBm/Hz

cdmaOne,

GSM850

925–960 MHz

E-GSM

–

–162.5

–149.5

–140.5

–137.5

–

dBm/Hz

1570–1580 MHz GPS

1805–1880 MHz GSM1800

1930–1990 MHz GSM1900,

cdmaOne,

WCDMA

2110–2170 MHz WCDMA

2500–2570 MHz Band 7

2300–2400 MHz Band 40

2570–2620 MHz Band 38

2545–2575 MHz XGP Band

–

–128.5

–104.5

–94.5

–119.5

–109.5

–7.5

–

dBm/Hz

Harmonic level (at 18 dBm 4.8–5.0 GHz

2nd harmonic –

3rd harmonic

EVM Does Not Exceed

dBm/1 MHz

with 100% duty cycle)

7.2–7.5 GHz

–

–17.5

TX power at the chip port 802.11b

–9 dB

–

21.5

–

dBm

for highest power level

setting at 25°C and

VBAT = 3.6V with spectral

mask and EVM

(DSSS/CCK)

OFDM, BPSK

OFDM, QPSK

–8 dB

–

20

19

–

dBm

–13 dB

compliance^{b, c}

OFDM, 16-QAM –19 dB

OFDM, 64-QAM –25 dB

(R = 3/4)

OFDM, 64-QAM –27 dB

(MCS7, HT20)

–

19

–

dBm

OFDM, 256-QAM –30 dB

(MCS8, VHT20)

17

OFDM, 256-QAM –32 dB

(MCS8, VHT40)

17

Phase noise

37.4 MHz Crystal, Integrated from –

10 kHz to 10 MHz

0.45

Degrees

RMS

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 143

BCM4339 Preliminary Data Sheet

WLAN 2.4 GHz Transmitter Performance Specifications

Table 41: WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

TX power control dynamic –

range

10

–

dB

Closed-loop TX power

variation at highest

power level setting

Across full temperature and

voltage range. Applies across

10 dBm to 20 dBm output power

range.

–

±1.5

dB

Carrier suppression

Gain control step

–

15

–

dBc

dB

–

0.25

6

Return loss at

Chip port TX

Z_o= 50ꢀ

–

dB

a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may

also be used within those bands.

b. Derate by 1.5 dB for temperatures less than –10°C or more than 55°C, or voltages less than 3.0V. Derate by

3.0 dB for voltages of less than 2.7V, or voltages of less than 3.0V at temperatures less than –10°C or greater

than 55°C. Derate by 4.5 dB for –40°C to –30°C.

c. TX power for Channel 1 and Channel 11 is specified by nonvolatile memory parameters.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 144

BCM4339 Preliminary Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Note: The specifications in Table 42 are specified at the RF port and include the use of an external

FEM with LNA from Broadcom’s approved-vendor list (AVL), unless otherwise specified. Results with

FEMs that are not on Broadcom’s AVL are not guaranteed.

Table 42: WLAN 5 GHz Receiver Performance Specifications

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Frequency range

–

4900

–

5845

MHz

dBm

RX sensitivity

IEEE 802.11a

(10% PER for 1000 octet

PSDU)^a

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–

–94.5

–93.1

–92.2

–89.6

–86.3

–83

–

–78.3

–76.8

RX sensitivity

20 MHz channel spacing for all MCS rates

IEEE 802.11n

(10% PER for 4096 octet

PSDU)^a

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

–

–94

–

dBm

–

–91.7

–89.2

–86.1

–82.5

–77.9

–76.3

–74.7

Defined for default

parameters: 800 ns GI and

non-STBC.

RX sensitivity

40 MHz channel spacing for all MCS rates

IEEE 802.11n

(10% PER for 4096 octet

PSDU)^a

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

–

–91.8

–88.9

–86.5

–83.0

–79.9

–75.2

–73.7

–72.3

–

dBm

–

Defined for default

parameters: 800 ns GI and

non-STBC.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 145

BCM4339 Preliminary Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 42: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

RX sensitivity

20 MHz channel spacing for all MCS rates

IEEE 802.11ac

(10% PER for 4096 octet

PSDU)^a

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

–

–93.3

–90.3

–87.9

–84.9

–81.4

–76.7

–75.1

–74.6

–70.2

–

dBm

–

Defined for default

parameters: 800 ns GI and

non-STBC.

RX sensitivity

40 MHz channel spacing for all MCS rates

IEEE 802.11ac

(10% PER for 4096 octet

PSDU)^a

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS9

–

–90.5

–87.4

–85.3

–82.1

–79

–

dBm

–

Defined for default

parameters: 800 ns GI and

non-STBC.

–73.9

–72.4

–72.3

–67.9

–66.6

RX sensitivity

80 MHz channel spacing for all MCS rates

IEEE 802.11ac

(10% PER for 4096 octet

PSDU)^a

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS9

–

–87

–

dBm

–

–83.9

–81.9

–78.1

–75

Defined for default

parameters: 800 ns GI and

non-STBC.

–73

–68.5

–64.3

–62.7

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 146

BCM4339 Preliminary Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 42: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

RX sensitivity IEEE

MCS7

MCS8

MCS7

MCS8

MCS9

MCS7

MCS8

MCS9

20 MHz

–

–76.4

–

36

–

dBm

MHz

dB

802.11ac 20/40/80 MHz

channel spacing with

LDPC (10% PER for 4096

octet PSDU) at WLAN RF

port. Defined for default

parameters: 800 ns GI,

LDPC coding and non-

STBC.

20 MHz

–

–73.7

40 MHz

–

–73.6

40 MHz

–

–70.6

40 MHz

–

–69.1

80 MHz

–

–70.5

80 MHz

–

–67.1

80 MHz

–

–65.0

Blocking level for 1 dB RX 776–794 MHz

CDMA2000

cdmaOne

GSM850

E-GSM

–21

–20

–12

–15

–20

–21

–

sensitivity degradation

(without external filtering)^b

824–849 MHz

–

880–915 MHz

–

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

GSM1800

cdmaOne

WCDMA

Band 7

–

Band 40

Band 38

XGP Band

–

Input in-band IP3^a

Maximum LNA gain

–15.5

Minimum LNA gain

–

–1.5

–

Maximum receive level

@ 5.24 GHz

@ 6, 9, 12 Mbps

–9.5

–14.5

9

@ 18, 24, 36, 48, 54 Mbps

–

LPF 3 dB bandwidth

–

Adjacent channel rejection 6 Mbps OFDM

–79 dBm

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

–61 dBm

16

15

13

11

–

(Difference between

interfering and desired

signal (20 MHz apart) at

10% PER for 1000 octet

PSDU with desired signal

level as specified in

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

65 Mbps OFDM

–

dB

–

dB

–

dB

8

–

dB

4

–

dB

Condition/Notes)

0

–

dB

–1

–2

–

dB

–

dB

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 147

BCM4339 Preliminary Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 42: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Alternate adjacent channel 6 Mbps OFDM

–78.5 dBm

–77.5 dBm

–75.5 dBm

–73.5 dBm

–70.5 dBm

–66.5 dBm

–62.5 dBm

–61.5 dBm

–60.5 dBm

32

31

29

27

24

20

16

15

14

–

95

3

–

5

dB

rejection

9 Mbps OFDM

(Difference between

interfering and desired

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

65 Mbps OFDM

–

signal (40 MHz apart) at

10% PER for 1000^coctet

PSDU with desired signal

level as specified in

Condition/Notes)

Maximum receiver gain

Gain control step

–

RSSI accuracy^d

Range –95 dBm^eto –30 dBm

Range above –30 dBm

–5

–8

10

–

8

dB

Return loss

Z_o= 50ꢀ, across the dynamic range

13

Receiver cascaded noise At maximum gain

figure

–

4

6

dB

a. Derate by 1.5 dB for –30°C to –10°C and 55°C to 85°C.

b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal

in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any

specific country.

c. For 65 Mbps, the size is 4096.

d. The minimum and maximum values shown have a 95% confidence level.

e. –95 dBm with calibration at the time of manufacture, –92 dBm without calibration.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 148

BCM4339 Preliminary Data Sheet

WLAN 5 GHz Transmitter Performance Specifications

Note: The specifications in Table 42 include the use of the BCM4339's internal PAs and are specified

at the chip port.

Table 43: WLAN 5 GHz Transmitter Performance Specifications

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Frequency range

–

4900

–

5845

MHz

Transmitted power in

cellular and FM bands (at

18.5 dBm)^a

76–108 MHz

776–794 MHz

869–960 MHz

FM RX

–

–161.5

–

dBm/Hz

cdmaOne,

GSM850

925–960 MHz

E-GSM

–

–161.5

–159.5

–161.5

–

dBm/Hz

1570–1580 MHz GPS

1805–1880 MHz GSM1800

1930–1990 MHz GSM1900,

cdmaOne,

WCDMA

2110–2170 MHz WCDMA

2400–2483 MHz BT/WLAN

2500–2570 MHz Band 7

2300–2400 MHz Band 40

2570–2620 MHz Band 38

2545–2575 MHz XGP band

9.8–11.570 GHz 2nd harmonic

–

–158.5

–156.5

–30.5

–

dBm/Hz

dBm/MHz

Harmonic level

(at 17 dBm)

TX power at the chip port OFDM, QPSK

for highest power level

–13 dB

–

21.5

19

–

dBm

OFDM, 16-QAM –19 dB

setting at 25°C and

VBAT = 3.6V with spectral

mask and EVM

compliance^{b, c}

OFDM, 64-QAM –25 dB

(R = 3/4)

19

OFDM, 64-QAM –27 dB

(MCS7, HT20)

–

19

17

–

dBm

OFDM, 256-QAM –30 dB

(MCS8, VHT80)

OFDM, 256-QAM –32 dB

(MCS9, VHT40

and VHT80)

Phase noise

37.4 MHz crystal, integrated from

10 kHz to 10 MHz

–

0.45

–

Degrees

RMS

TX power control dynamic –

range

10

dB

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 149

BCM4339 Preliminary Data Sheet

General Spurious Emissions Specifications

Table 43: WLAN 5 GHz Transmitter Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum Unit

Closed loop TX power

Across full-temperature and voltage

–

±2.0

dB

variation at highest power range. Applies across 10 to 20 dBm

level setting

output power range.

Carrier suppression

Gain control step

Return loss

–

15

–

dBc

dB

–

0.25

6

Z_o= 50ꢀ

–

dB

a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may

also be used within those bands.

b. Derate by 1.5 dB for temperatures less than –10°C or more than 55°C, or voltages less than 3.0V. Derate by 3.0

dB for voltages of less than 2.7V, or voltages of less than 3.0V at temperatures less than –10°C or greater than

55°C. Derate by 4.5 dB for –40°C to –30°C.

c. TX power for Channel 1 and Channel 11 is specified by non-volatile memory parameters.

General Spurious Emissions Specifications

Table 44: General Spurious Emissions Specifications

Parameter

Condition/Notes

Min. Typ.

Max.

Unit

Frequency range

–

2400

–

2500

MHz

General Spurious Emissions

TX emissions

30 MHz < f < 1 GHz

RBW = 100 kHz

1 GHz < f < 12.75 GHz RBW = 1 MHz

1.8 GHz < f < 1.9 GHz RBW = 1 MHz

5.15 GHz < f < 5.3 GHz RBW = 1 MHz

–

–93

–

dBm

–45.5

–72

–87

RX/standby emissions 30 MHz < f < 1 GHz

RBW = 100 kHz

–107

–65^a

–87

1 GHz < f < 12.75 GHz RBW = 1 MHz

1.8 GHz < f < 1.9 GHz RBW = 1 MHz

5.15 GHz < f < 5.3 GHz RBW = 1 MHz

–

dBm

–100

a. The value presented in this table is the result of LO leakage at 3/2 * f_cfor 2.4 GHz or 2/3 * f_cfor 5 GHz (where

f_cis the carrier frequency). For all other emissions in this range, the value is –96 dBm.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 150

BCM4339 Preliminary Data Sheet

Internal Regulator Electrical Specifications

Section 18: Internal Regulator Electrical

Specifications

Functional operation is not guaranteed outside of the specification limits provided in this section.

Core Buck Switching Regulator

Table 45: Core Buck Switching Regulator (CBUCK) Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

V

Input supply voltage

(DC)

DC voltage range inclusive of

disturbances.

3.0

3.6

PWM mode switching

frequency

CCM, Load > 100 mA VBAT = 3.6V

2.8

4

5.2

MHz

PWM output current

Output current limit

Output voltage range

–

600

mA

V

–

1400

1.35

Programmable, 30 mV steps

Default = 1.35V

1.2

1.5

4

PWM output voltage

DC accuracy

Includes load and line regulation.

Forced PWM mode

–4

–

7

%

PWM ripple voltage, static

Measure with 20 MHz bandwidth limit.

20

mVpp

Static Load. Max. Ripple based on

VBAT = 3.6V, Vout = 1.35V,

Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH,

Cap + Board total-ESR < 20 mꢀ,

C

_out> 1.9 μF, ESL<200pH

PWM mode peak efficiency Peak Efficiency at 200 mA load

78

70

–

86

81

–

%

µs

PFM mode efficiency

10 mA load current

–

Start-up time from

power down

VIO already ON and steady.

Time from REG_ON rising edge to CLDO

reaching 1.2V

850

External inductor

0806 size, ± 30%, 0.11 ± 25% Ohms

–

2.2

4.7

–

µH

µF

2.0^b

10^c

External output capacitor

Ceramic, X5R, 0402,

ESR <30 mꢀ at 4 MHz, ± 20%, 6.3V

0.67^b

External input capacitor

For SR_VDDBATP5V pin,

ceramic, X5R, 0603,

4.7

–

µF

ESR < 30 mꢀ at 4 MHz, ± 20%, 6.3V,

4.7 µF

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 151

BCM4339 Preliminary Data Sheet

3.3V LDO (LDO3P3)

Table 45: Core Buck Switching Regulator (CBUCK) Specifications (Cont.)

Specification

Notes

Min.

Typ.

Max. Units

µs

Input supply voltage

ramp-up time

0 to 4.3V

40

–

a. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative

duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V (for up to 250 seconds),

cumulative duration over the lifetime of the device, are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance,

DC-bias, temperature, and aging.

c. Total capacitance includes those connected at the far end of the active load.

3.3V LDO (LDO3P3)

Table 46: LDO3P3 Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

V

Input supply voltage, V_in

Min. = V_o+ 0.2V = 3.5V dropout voltage

3.0

3.6

requirement must be met under

maximum load for performance

specifications.

Output current

–

0.001

–

450

–

mA

V

Nominal output voltage, V_o

Default = 3.3V

3.3

Dropout voltage

At max load.

–

200

+5

mV

%

Output voltage DC accuracy

Quiescent current

Line regulation

Includes line/load regulation.

No load

–5

–

100

3.5

µA

V_infrom (V_o+ 0.2V) to 4.8V, max load –

mV/V

Load regulation

PSRR

load from 1 mA to 450 mA

_in≥ V_o+ 0.2V,

–

0.3

–

mV/mA

dB

V

20

V_o= 3.3V, C_o= 4.7 µF,

Max. load, 100 Hz to 100 kHz

LDO turn-on time

Chip already powered up.

–

160

4.7

250

10

µs

1.0^b

External output capacitor, C_o

Ceramic, X5R, 0402,

(ESR: 5 mꢀ–240 mꢀ), ± 10%, 10V

µF

External input capacitor

For SR_VDDBATA5V pin (shared with –

Bandgap) Ceramic, X5R, 0402,

4.7

–

µF

(ESR: 30m-200 mꢀ), ± 10%, 10V.

Not needed if sharing VBAT capacitor

4.7 µF with SR_VDDBATP5V.

a. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative

duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V (for up to 250 seconds),

cumulative duration over the lifetime of the device, are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part

tolerance, DC-bias, temperature, and aging.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 152

BCM4339 Preliminary Data Sheet

2.5V LDO (BTLDO2P5)

Table 47: BTLDO2P5 Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

V

Input supply voltage

Min. = 2.5V + 0.2V = 2.7V.

3.0

3.6

Dropout voltage requirement must be

met under maximum load for

performance specifications.

Nominal output voltage

Default = 2.5V.

Range

–

2.5

–

V

Output voltage programmability

2.2

–5

2.8

5

V

Accuracy at any step (including line/

load regulation), load > 0.1 mA.

%

Dropout voltage

Output current

At maximum load.

–

200

70

mV

mA

µA

0.1

–

Quiescent current

No load.

8

16

Maximum load at 70 mA.

Power-down mode.

–

660

1.5

–

700

5

µA

Leakage current

Line regulation

–

µA

V_infrom (V_o+ 0.2V) to 4.8V,

maximum load.

–

3.5

mV/V

Load regulation

PSRR

Load from 1 mA to 70 mA,

V_in= 3.6V.

–

0.3

–

mV/mA

dB

V_in≥ V_o+ 0.2V, V_o= 2.5V, C_o= 2.2 µF, 20

maximum load, 100 Hz to 100 kHz.

LDO turn-on time

In-rush current

Chip already powered up.

–

150

250

µs

V_in= V_o+ 0.15V to 4.8V, C_o= 2.2 µF,

No load.

mA

0.7^b

2.2

4.7

µF

External output capacitor, C_o

External input capacitor

Ceramic, X5R, 0402,

(ESR: 5–240 mꢀ), ±10%, 10V

2.64

–

For SR_VDDBATA5V pin (shared with –

Bandgap) ceramic, X5R, 0402,

(ESR: 30–200 mꢀ), ±10%, 10V.

Not needed if sharing VBAT 4.7 µF

capacitor with SR_VDDBATP5V.

a. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative

duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V (for up to 250 seconds),

cumulative duration over the lifetime of the device, are allowed.

b. The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DC-

bias, temperature, and aging.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 153

BCM4339 Preliminary Data Sheet

CLDO

Table 48: CLDO Specifications

Notes

Specification

Min. Typ. Max. Units

1.35 1.5

Input supply voltage, V_in

Min. = 1.2 + 0.15V = 1.35V dropout voltage 1.3

requirement must be met under maximum

load.

V

Output current

–

0.2

1.1

–

300 mA

1.275 V

Output voltage, V_o

Programmable in 25 mV steps.

Default = 1.2.V

1.2

Dropout voltage

At max. load

–

150 mV

Output voltage DC accuracy

Quiescent current

Includes line/load regulation

No load

–4

–

+4

–

%

24

2.1

–

µA

mA

300 mA load

–

Line regulation

V_infrom (V_o+ 0.15V) to 1.5V, maximum load –

5

mV/V

Load regulation

Leakage current

Load from 1 mA to 300 mA

Power down

–

0.02 0.05 mV/mA

–

1

–

20

3

µA

dB

Bypass mode

–

PSRR

@1 kHz, Vin ≥ 1.35V, C_o= 4.7 µF

20

Start-up time of PMU

VIO up and steady. Time from the REG_ON –

rising edge to the CLDO reaching 1.2V.

–

700 µs

LDO turn-on time

LDO turn-on time when rest of the chip is up –

140 180 µs

1.32^a

External output capacitor, C_o

Total ESR: 5 mꢀ–240 mꢀ

4.7

1

–

µF

External input capacitor

Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from

CBUCK output.

–

2.2

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part

tolerance, DC-bias, temperature, and aging.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 154

BCM4339 Preliminary Data Sheet

LNLDO

Table 49: LNLDO Specifications

Specification

Notes

Min.

Typ.

Max. Units

Input supply voltage, Vin

Min. = 1.2V_o+ 0.15V = 1.35V dropout

1.3

1.35

1.5

V

voltage requirement must be met under

maximum load.

Output current

–

0.1

1.1

–

150

mA

V

Output voltage, V_o

Programmable in 25 mV steps.

Default = 1.2V

1.2

1.275

Dropout voltage

At maximum load

–

150

+4

–

mV

%

Output voltage DC accuracy Includes line/load regulation

–4

–

Quiescent current

No load

44

970

–

µA

Max. load

–

990

5

Line regulation

V_infrom (V_o+ 0.1V) to 1.5V, max load

–

mV/V

Load regulation

Leakage current

Output noise

Load from 1 mA to 150 mA

Power-down

–

0.02

–

0.05

10

mV/mA

µA

@30 kHz, 60–150 mA load C_o= 2.2 µF

@100 kHz, 60–150 mA load C_o= 2.2 µF

–

60

35

nV/rt Hz

PSRR

@ 1kHz, Input > 1.35V, C_o= 2.2 µF, V_o=

1.2V

20

–

dB

LDO turn-on time

LDO turn-on time when rest of chip is up

–

140

2.2

180

4.7

µs

0.5^a

External output capacitor, C_oTotal ESR (trace/capacitor):

µF

5 mꢀ–240 mꢀ

External input capacitor

Only use an external input capacitor at the –

VDD_LDO pin if it is not supplied from

CBUCK output.

1

2.2

µF

Total ESR (trace/capacitor): 30 mꢀ–200 mꢀ

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part

tolerance, DC-bias, temperature, and aging.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 155

BCM4339 Preliminary Data Sheet

System Power Consumption

Section 19: System Power Consumption

Note: Unless otherwise stated, these values apply for the conditions specified in

Table 33: “Recommended Operating Conditions and DC Characteristics,” on page 124.

WLAN Current Consumption

Table 50 shows the typical, total current consumed by the BCM4339. To calculate total-solution current

consumption for designs using external PAs, LNAs, and/or FEMs, add the current consumption of the external

devices to the numbers in Table 50.

All values in Table 50 are with the Bluetooth core in reset (that is, with Bluetooth and FM off).

Table 50: Typical WLAN Current Consumption (BCM4339 Current Only)

VBAT = 3.6V, VDDIO = 1.8V, T_A25°C

Bandwidth

(MHz)

Band

(GHz)

Mode

Vbat, mA

Vio^a, µA

Sleep Modes

OFF^b

SLEEP^c

–

0.005

0.850

0.350

0.550

0.300

5

–

150

IEEE Power Save, DTIM 1^d

IEEE Power Save, DTIM 3^d

IEEE Power Save, DTIM 1^d

IEEE Power Save, DTIM 3^d

Active Modes

2.4

5

Receive^e,fMCS8 (SGI)

CRS^g

Receive^e,fMCS7 (SGI)

CRS^g

Receive^e,fMCS7 (SGI)

CRS^g

Receive^e,fMCS9 (SGI)

CRS^g

20

40

80

2.4

5

50

5

46

66

5

56

5

79.5

67

5

110

103

5

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 156

BCM4339 Preliminary Data Sheet

WLAN Current Consumption

Table 50: Typical WLAN Current Consumption (BCM4339 Current Only) (Cont.)

VBAT = 3.6V, VDDIO = 1.8V, T_A25°C

Bandwidth

(MHz)

Band

(GHz)

Mode

Vbat, mA

Vio^a, µA

Active Modes with External PAs (TX Output Power is –5 dBm at the Chip Port)

Transmit, CCK

20

2.4

88

76

5

Transmit, MCS8, HT20, SGI^{e, h}

Transmit, MCS7, SGI^{e, h}

Transmit, MCS7^{e, h}

Transmit, MCS9, SGI^{e, h}

20

40

80

5

111

125

147

5

Active Modes with Internal PAs (TX Output Power Measured at the Chip Port)

TX CCK 11 Mbps at 21.7 dBm

20

2.4

5

325

240

280

340

270

5

TX OFDM MCS8 (SGI) at 17.2 dBm 20

TX OFDM MCS7 (SGI) at 18.5 dBm 20

TX OFDM MCS7 at 18.7 dBm

40

5

TX OFDM MCS9 (SGI) at 16.2 dBm 40

TX OFDM MCS9 (SGI) at 15.7 dBm 80

5

a. VIO is specified with all pins idle (not switching) and not driving any loads.

b. WL_REG_ON, BT_REG_ON low.

c. Idle, not associated, or inter-beacon.

d. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @1 Mbps. Average current over the specified DTIM

intervals.

e. Measured using packet engine test mode.

f. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.

g. Carrier sense (CCA) when no carrier present.

h. Duty cycle is 100%. Excludes external PA contribution.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 157

BCM4339 Preliminary Data Sheet

Bluetooth and FM Current Consumption

The Bluetooth, BLE, and FM Bluetooth BLE current consumption measurements are shown in Table 51.

Note:

•

The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 51.

For FM measurements, the Bluetooth core is in Sleep mode.

The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

Table 51: Bluetooth BLE and FM Current Consumption

Operating Mode

VBAT (VBAT = 3.6V) Typical VDDIO (VDDIO = 1.8V) Typical Units

Sleep

10

225

235

µA

Standard 1.28s Inquiry Scan

180

320

P and I Scan^b

500 ms Sniff Master

500 ms Sniff Slave

DM1/DH1 Master

DM3/DH3 Master

DM5/DH5 Master

3DH5 Master

170

250

µA

120

250

µA

22.81

28.06

29.01

27.09

7.9

0.034

0.044

0.047

0.100

0.123

0.180

mA

SCO HV3 Master

HV3 + Sniff + Scan^a

11.38

FMRX I²S Audio

8.64

0.022

mA

FMRX Analog Audio only

9.15

8.65

0.022

mA

FMRX I²S Audio + RDS

FMRX Analog Audio + RDS

9.20

175

0.022

235

mA

µA

BLE Scan^b

BLE Scan 10 ms

14.09

0.022

245

mA

µA

mA

µA

BLE Adv – Unconnectable 1.00 sec 69

BLE Adv – Unconnectable 1.28 sec 67

BLE Adv – Unconnectable 2.00 sec 42

235

240

BLE Connected 7.5 ms

BLE Connected 1 sec

BLE Connected 1.28 sec

4.30

0.020

240

53

48

240

a. At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s.

b. No devices present. A 1.28 second interval with a scan window of 11.25 ms.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 158

BCM4339 Preliminary Data Sheet

Interface Timing and AC Characteristics

Section 20: Interface Timing and AC

Characteristics

SDIO/gSPI Timing

SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 43 and Table 52.

Figure 43: SDIO Bus Timing (Default Mode)

f_PP

t_WL

t_WH

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

(max)

(min)

Table 52: SDIO Bus Timing^aParameters (Default Mode)

Parameter

Symbol

Minimum Typical

Maximum Unit

SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)

Frequency – Data Transfer mode

Frequency – Identification mode

Clock low time

fPP

0

–

25

400

–

MHz

kHz

ns

fOD

tWL

tWH

tTLH

tTHL

0

10

–

Clock high time

–

ns

Clock rise time

10

ns

Clock fall time

–

ns

Inputs: CMD, DAT (referenced to CLK)

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 159

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

Table 52: SDIO Bus Timing^aParameters (Default Mode) (Cont.)

Parameter

Symbol

Minimum Typical

Maximum Unit

Input setup time

Input hold time

tISU

tIH

5

–

ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer mode

Output delay time – Identification mode

tODLY

0

–

14

50

ns

a. Timing is based on CL  40pF load on CMD and Data.

b. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 160

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 44 and Table 53.

Figure 44: SDIO Bus Timing (High-Speed Mode)

f_PP

t_WL

t_WH

50% VDD

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

t_OH

Table 53: SDIO Bus Timing^aParameters (High-Speed Mode)

Parameter

Symbol

Minimum Typical

Maximum Unit

SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)

Frequency – Data Transfer Mode

Frequency – Identification Mode

Clock low time

fPP

0

7

–

50

400

–

MHz

kHz

ns

fOD

tWL

tWH

tTLH

tTHL

Clock high time

–

ns

Clock rise time

3

ns

Clock fall time

3

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

Input hold time

tISU

tIH

6

2

–

ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer Mode

Output hold time

tODLY

tOH

–

14

–

ns

pF

2.5

–

Total system capacitance (each line)

CL

40

a. Timing is based on CL  40pF load on CMD and Data.

b. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 161

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

SDIO Bus Timing Specifications in SDR Modes

Clock Timing

Figure 45: SDIO Clock Timing (SDR Modes)

t_CLK

SDIO_CLK

t_CR

t_CF

t_CR

Table 54: SDIO Bus Clock Timing Parameters (SDR Modes)

Parameter

Symbol

Minimum

Maximum

Unit

Comments

–

t_CLK

40

20

10

4.8

–

ns

SDR12 mode

SDR25 mode

SDR50 mode

SDR104 mode

–

t_CR, t_CF

0.2 × t_CLK

t_CR, t_CF< 2.00 ns (max.) @100 MHz,

C_CARD= 10 pF

t

C

_CR, t_CF< 0.96 ns (max.) @208 MHz,

_CARD= 10 pF

Clock duty

cycle

–

30

70

%

–

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 162

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

Device Input Timing

Figure 46: SDIO Bus Input Timing (SDR Modes)

SDIO_CLK

t_IS

t_IH

CMD input

DAT[3:0] input

Table 55: SDIO Bus Input Timing Parameters (SDR Modes)

Symbol

Minimum

Maximum

Unit

Comments

SDR104 Mode

t_IS

t_IH

1.4

0.8

–

ns

C_CARD= 10 pF, VCT = 0.975V

C_CARD= 5 pF, VCT = 0.975V

SDR50 Mode

t_IS

t_IH

3.0

0.8

–

ns

C_CARD= 10 pF, VCT = 0.975V

C_CARD= 5 pF, VCT = 0.975V

SDR25 Mode

t_IS

t_IH

3.0

0.8

–

ns

C_CARD= 10 pF, VCT = 0.975V

C_CARD= 5 pF, VCT = 0.975V

SDR12 Mode

t_IS

t_IH

3.0

0.8

–

ns

C_CARD= 10 pF, VCT = 0.975V

C_CARD= 5 pF, VCT = 0.975V

Broadcom^®

November 17, 2014 • 4339-DS106-R

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BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

Device Output Timing

Figure 47: SDIO Bus Output Timing (SDR Modes up to 100 MHz)

t_CLK

SDIO_CLK

t_ODLY

t_OH

CMD output

DAT[3:0] output

Table 56: SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)

Symbol

Minimum

Maximum

Unit

Comments

t_ODLY

t_OH

–

7.5

14.0

–

ns

t_CLK≥ 10 ns C_L= 30 pF using driver type B for SDR50

t_CLK≥ 20 ns C_L= 40 pF using for SDR12, SDR25

Hold time at the t_ODLY(min) C_L= 15 pF

–

1.5

Figure 48: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)

t_CLK

SDIO_CLK

t_OP

t_ODW

CMD output

DAT[3:0] output

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 164

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

Table 57: SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz)

Symbol

Minimum

Maximum

Unit

Comments

t_OP

0

2

UI

ps

UI

Card output phase

∆t_OP

t_ODW

–350

0.60

+1550

–

Delay variation due to temp change after tuning

t_ODW=2.88 ns @208 MHz

•

∆t_OP= +1550 ps for junction temperature of ∆t_OP= 90 degrees during operation

∆t_OP= –350 ps for junction temperature of ∆t_OP= –20 degrees during operation

∆t_OP= +2600 ps for junction temperature of ∆t_OP= –20 to +125 degrees during operation

Figure 49: ∆t_OPConsideration for Variable Data Window (SDR 104 Mode)

Data valid window

Sampling point after tuning

ȴt_OP

=

Data valid window

1550 ps

ȴt_OP

=

Sampling point after card junction heating

by +90°C from tuning temperature

350 ps

Data valid window

Sampling point after card junction cooling

by 20°C from tuning temperature

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 165

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

SDIO Bus Timing Specifications in DDR50 Mode

Figure 50: SDIO Clock Timing (DDR50 Mode)

t_CLK

SDIO_CLK

t_CR

t_CF

t_CR

Table 58: SDIO Bus Clock Timing Parameters (DDR50 Mode)

Parameter

Symbol

Minimum

Maximum

Unit

Comments

–

t_CLK

20

–

ns

DDR50 mode

t_CR,t_CF

0.2 × tCLK

t_CR, t_CF< 4.00 ns (max) @50 MHz,

C_CARD= 10 pF

Clock duty

cycle

–

45

55

%

–

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 166

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

Data Timing, DDR50 Mode

Figure 51: SDIO Data Timing (DDR50 Mode)

F_PP

SDIO_CLK

t_ISU2x

t_IH2x

t_ISU2x

t_IH2x

DAT[3:0]

input

Invalid

Data

Invalid

Data

Invalid

Data

Invalid

t_ODLY2x(max)

t_ODLY2x

(min)

t_ODLY2x

(min)

Available timing

window for card

output transition

DAT[3:0]

output

Data

In DDR50 mode, DAT[3:0] lines are sampled on both edges of

the clock (not applicable for CMD line)

Available timing

window for host to

sample data from card

Table 59: SDIO Bus Timing Parameters (DDR50 Mode)

Parameter

Input CMD

Symbol

Minimum

Maximum

Unit Comments

Input setup time

Input hold time

t_ISU

t_IH

6

–

ns

C_CARD< 10pF (1 Card)

0.8

Output CMD

Output delay time

Output hold time

t_ODLY

t_OH

–

13.7

–

ns

C_CARD< 30pF (1 Card)

C_CARD< 15pF (1 Card)

1.5

Input DAT

Input setup time

Input hold time

t_ISU2x

t_IH2x

3

–

ns

C_CARD< 10pF (1 Card)

0.8

Output DAT

Output delay time

Output hold time

t_ODLY2x

–

7.0

–

ns

C_CARD< 25pF (1 Card)

C_CARD< 15pF (1 Card)

1.5

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 167

BCM4339 Preliminary Data Sheet

SDIO/gSPI Timing

gSPI Signal Timing

The gSPI host and device always use the rising edge of clock to sample data.

Figure 52: gSPI Timing

Table 60: gSPI Timing Parameters

Parameter

Symbol Minimum

Maximum

Units Note

ns F_max= 48 MHz

Clock period

T1

20.8

–

Clock high/low

Clock rise/fall time^a

T2/T3

T4/T5

(0.45 × T1) – T4 (0.55 × T1) – T4 ns

–

2.5

ns

Measured from 10% to 90% of

VDDIO

Input setup time

Input hold time

T6

T7

5.0

–

Setup time, SIMO valid to

SPI_CLK active edge

–

Hold time, SPI_CLK active edge

to SIMO invalid

Output setup time T8

–

Setup time, SOMI valid before

SPI_CLK rising

Output hold time

T9

–

Hold time, SPI_CLK active edge

to SOMI invalid

CSX to clock^b

Clock to CSX^a

–

7.86

–

ns

CSX fall to 1st rising edge

Last falling edge to CSX high

a. Limit applies when SPI_CLK = F_max. For slower clock speeds, longer rise/fall times are acceptable provided that

the transitions are monotonic and the setup and hold time limits are complied with.

b. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-

word transaction).

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 168

BCM4339 Preliminary Data Sheet

PCI Express Interface Parameters

Table 61: PCI Express Interface Parameters

Parameter

Symbol

Comments

Minimum Typical Maximum Unit

General

Baud rate

BPS

Vref

–

1

5

–

Gbaud

V

Reference clock

amplitude

LVPECL, AC coupled

Receiver

Differential termination ZRX-DIFF-DC

Differential termination 80

100

50

120

60

ꢀ

DC impedance

ZRX-DC

DC common-mode

impedance

40

Powered down

termination (POS)

ZRX-HIGH-IMP-DC- Power-down or RESET 100k

POS high impedance

–

ꢀ

Powered down

termination (NEG)

ZRX-HIGH-IMP-DC- Power-down or RESET 1k

ꢀ

NEG

high impedance

Input voltage

VRX-DIFFp-p

AC coupled, differential 175

p-p

mV

UI

Jitter tolerance

TRX-EYE

Minimum receiver eye 0.4

width

Differential return loss RLRX-DIFF

Differential return loss 10

–

dB

Common-mode return RLRX-CM

loss

Common-mode return

loss

6

Unexpected electrical TRX-IDEL-DET-

An unexpected

–

10

ms

idle enter detect

threshold integration

time

DIFF-ENTERTIME electrical idle must be

recognized no longer

than this time to signal

an unexpected idle

condition.

Signal detect threshold VRX-IDLE-DET-

DIFFp-p

Electrical idle detect

threshold

65

175

mV

Transmitter

Output voltage

VTX-DIFFp-p

VTX-RISE

Differential p-p,

programmable in 16

steps

0.8

–

1200

–

mV

UI

Output voltage rise

time

20% to 80%

0.125

(2.5 GT/s)

0.15

(5 GT/s)

Output voltage fall time VTX-FALL

80% to 20%

0.125

(2.5 GT/s)

–

UI

0.15

(5 GT/s)

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 169

BCM4339 Preliminary Data Sheet

PCI Express Interface Parameters

Table 61: PCI Express Interface Parameters (Cont.)

Parameter

Symbol

Comments

Minimum Typical Maximum Unit

RX detection voltage VTX-RCV-DETECT The amount of voltage –

–

600

100

20

mV

swing

change allowed during

receiver detection.

TX AC peak common- VTX-CM-AC-PP

mode voltage

(5 GT/s)

TX AC common mode

voltage (5 GT/s)

–

0

TX AC peak common- VTX-CM-AC-P

mode voltage

(2.5 GT/s)

TX AC common mode

voltage (2.5 GT/s)

Absolute delta of DC VTX-CM-DC-

Absolute delta of DC

common-model voltage

during L0 and electrical

idle.

100

common-model

ACTIVE-IDLE-

voltage during L0 and DELTA

electrical idle

Absolute delta of DC VTX-CM-DC-LINE- DC offset between D+

0

–

25

mV

common-model

voltage between D+

and D–

DELTA

and D–

Electrical idle

differential peak output p

voltage

VTX-IDLE-DIFF-AC- Peak-to-peak voltage

0

–

20

mV

mA

ꢀ

TX short circuit

current

ITX-SHORT

Current limit when TX

output is shorted to

ground.

90

DC differential TX

termination

ZTX-DIFF-DC

RLTX-DIFF

Low impedance defined 80

during signaling

(parameter is captured

for 5.0 GHz by RLTX-

DIFF)

120

Differential

return loss

Differential

return loss

10 (min) for –

0.05:

–

dB

1.25 GHz

8 (min) for

1.25:

2.5 GHz

Common-mode

return loss

RLTX-CM

TTX-EYE

Common-mode return

loss

6

–

dB

UI

TX eye width

Minimum TX

eye width

0.75

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 170

BCM4339 Preliminary Data Sheet

JTAG Timing

Table 62: JTAG Timing Characteristics

Output

Maximum

Output

Minimum

Signal Name

Period

Setup

Hold

TCK

125 ns

–

TDI

–

20 ns

–

0 ns

–

TMS

–

TDO

–

100 ns

–

0 ns

–

JTAG_TRST

250 ns

–

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 171

BCM4339 Preliminary Data Sheet

Power-Up Sequence and Timing

Section 21: Power-Up Sequence and

Timing

Sequencing of Reset and Regulator Control Signals

The BCM4339 has two signals that allow the host to control power consumption by enabling or disabling the

Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are

provided to indicate proper sequencing of the signals for various operational states (see Figure 53, Figure 54

on page 173, and Figure 55 and Figure 56 on page 174). The timing values indicated are minimum required

values; longer delays are also acceptable.

Description of Control Signals

•

WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON

input to control the internal BCM4339 regulators. When this pin is high, the regulators are enabled and the

WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON

and WL_REG_ON pins are low, the regulators are disabled.

•

BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4339

regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this

pin is low and WL_REG_ON is high, the BT section is in reset.

Note:

•

For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay

between consecutive toggles (where both signals have been driven low). This is to allow time for

the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush

current on the order of 36 mA during the next PMU cold start.

•

The reset requirements for the Bluetooth core are also applicable for the FM core. In other words,

if FM is to be used, then the Bluetooth core must be enabled.

The BCM4339 has an internal power-on reset (POR) circuit. The device will be held in reset for a

maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least

150 ms after VDDC and VDDIO are available before initiating SDIO accesses.

•

VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the

same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 172

BCM4339 Preliminary Data Sheet

Sequencing of Reset and Regulator Control Signals

Control Signal Timing Diagrams

Figure 53: WLAN = ON, Bluetooth = ON

32.678 kHz

Sleep Clock

90% of VH

VBAT*

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high

before VBAT is high.

Figure 54: WLAN = OFF, Bluetooth = OFF

32.678 kHz

Sleep Clock

VBAT*

VDDIO

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 173

BCM4339 Preliminary Data Sheet

Sequencing of Reset and Regulator Control Signals

Figure 55: WLAN = ON, Bluetooth = OFF

32.678 kHz

Sleep Clock

90% of VH

VBAT*

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Figure 56: WLAN = OFF, Bluetooth = ON

32.678 kHz

Sleep Clock

90% of VH

VBAT*

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.

2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 174

BCM4339 Preliminary Data Sheet

Package Information

Section 22: Package Information

Package Thermal Characteristics

Table 63: Package Thermal Characteristics^a

Characteristic

FCFBGA

48.03

17.01

24.52

10.78

18.02

125

WLBGA

32.9

WLCSP

33.45

3.45



_JA(°C/W) (value in still air)

2.56

_JB(°C/W)

0.98

1.00

_JC(°C/W)



_JT(°C/W)

_JB(°C/W)

3.30

3.45



9.85

10.64

125

Maximum Junction Temperature T_j(°C)

Maximum Power Dissipation (W)

125

1.41

1.119

a. No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7

(101.6 mm × 101.6 mm × 1.6 mm) and P = specified power maximum continuous power dissipation.

Junction Temperature Estimation and PSI_JTVersus THETA_JC

Package thermal characterization parameter PSI–J_T(_JT) yields a better estimation of actual junction

temperature (T_J) versus using the junction-to-case thermal resistance parameter Theta–J_C(_JC). The reason

for this is that _JCassumes that all the power is dissipated through the top surface of the package case. In actual

applications, some of the power is dissipated through the bottom and sides of the package. _JTtakes into

account power dissipated through the top, bottom, and sides of the package. The equation for calculating the

device junction temperature is:

T_J= T_T+ P x _JT

Where:

•

T_J= Junction temperature at steady-state condition (°C)

T_T= Package case top center temperature at steady-state condition (°C)

P = Device power dissipation (Watts)



_JT= Package thermal characteristics; no airflow (°C/W)

Environmental Characteristics

For environmental characteristics data, see Table 31: “Environmental Ratings,” on page 123.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 175

BCM4339 Preliminary Data Sheet

Mechanical Information

Section 23: Mechanical Information

Figure 57: 160-Ball FCFBGA Package Mechanical Information

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 176

BCM4339 Preliminary Data Sheet

Mechanical Information

Figure 58: 145-Ball WLBGA Package Mechanical Information

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 177

BCM4339 Preliminary Data Sheet

Mechanical Information

Figure 59: WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up

Note: No top-layer metal is allowed in keep-out areas.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 178

BCM4339 Preliminary Data Sheet

Mechanical Information

Figure 60: 286-Bump WLCSP Package Mechanical Information

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 179

BCM4339 Preliminary Data Sheet

Mechanical Information

Figure 61: WLCSP Keep-out Areas for PCB Layout—Bottom View with Bumps Facing Up

Note: No top-layer metal is allowed in keep-out areas.

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 180

BCM4339 Preliminary Data Sheet

Ordering Information

Section 24: Ordering Information

Operating

Ambient

Temperature

Part Number

Package

Description

BCM4339NKFFBG 160-ball FCFBGA

(8 mm × 8 mm,

Dual-band 2.4 GHz and 5 GHz

WLAN + BT 4.1

–30°C to +85°C

0.4 mm pitch)

BCM4339XKWBG 286-bump WLCSP

(4.87 mm × 5.413 mm,

Dual-band 2.4 GHz and 5 GHz

WLAN + BT 4.1 for FMRX

0.2 mm pitch)

BCM4339XKUBG 145-ball WLBGA

(4.87 mm × 5.413 mm,

0.4 mm pitch)

Dual-band 2.4 GHz and 5 GHz

WLAN + BT 4.1 + FMRX

Broadcom^®

November 17, 2014 • 4339-DS106-R

Page 181

BCM4339 Preliminary Data Sheet

Broadcom^®Corporation reserves the right to make changes without further notice to any products or

data herein to improve reliability, function, or design.

Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,

Broadcom Corporation does not assume any liability arising out of the application or use of this

information, nor the application or use of any product or circuit described herein, neither does it

convey any license under its patent rights nor the rights of others.

®

Broadcom Corporation

Phone: 949-926-5000

Fax: 949-926-5203

5300 California Avenue

E-mail: info@broadcom.com

Web: www.broadcom.com

Irvine, CA 92617

4339-DS106-R

November 17, 2014


型号：	BCM4339XKWBGT
厂家：	CYPRESS
描述：	Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver
文件：	总183页 (文件大小：4237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BCM4339XKWBGT [CYPRESS]

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