CY25701FJXC [CYPRESS]
Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO); 可编程高频晶体振荡器，带有扩频（ SSXO ）
| 型号： | CY25701FJXC |
| 厂家： | 
CYPRESS |
| 描述： | Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) |
| 文件： | 总7页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25701
Programmable High-Frequency Crystal Oscillator
with Spread Spectrum (SSXO)
Benefits
Features
• Crystal Oscillator with Spread Spectrum Clock (SSC)
• Wide operating output (SSCLK) frequency range
• 10–166 MHz
• Provides wide range of spread percentages for
maximum electromagnetic interference (EMI)
reduction, to meet regulatory agency electromagnetic
compliance (EMC) requirements. Reduces devel-
opment and manufacturing costs and time-to-market.
• Eliminates the need for external crystal oscillator.
• Internal PLL to generate up to 166 MHz output.
• Programmable spread spectrum with nominal 31.5 kHz
modulation frequency
• Center spread: ±0.25% to ±2.0%
• Down spread: –0.5% to –4.0%
• Integrated phase-locked loop (PLL)
• Low cycle-to-cycle Jitter
• 3.3V operation
• Output Enable function
• Suitable for most PC, consumer, and networking
applications.
• Application compatibility in standard and low-power
systems.
• In-house programming of samples and prototype
quantities is available using the CY3672 programming
kit and CY3613 socket adapter. Production quantities
are available through Cypress’s value-added distri-
bution partners or by using third-party programmers
from BP Microsystems, HiLo Systems, and others.
• Package available in 4-Lead Plastic JE SMD
Pin Configuration
Logic Block Diagram
CY25701
4-pin Plastic SMD
RFB
PLL
with
MODULATION
CONTROL
1
2
OE
VDD
4
3
CXIN
OUTPUT
DIVIDERS
and
SSCLK
PROGRAMMABLE
CONFIGURATION
VSS
3
SSCLK
MUX
CXOUT
1
OE
4
2
VDD
VSS
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07684 Rev. *B
Revised October 15, 2004
CY25701
Pin Definition
Pin
Name
Description
Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled.
Power supply ground.
1
2
3
4
OE
VSS
SSCLK
VDD
Spread spectrum clock output.
3.3V power supply.
The CY25701 uses a programmable configuration memory
array to synthesize output frequency and spread%.
Functional Description
The CY25701 is a Spread Spectrum Crystal Oscillator (SSXO)
IC used for the purpose of reducing EMI found in today’s
high-speed digital electronic systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the embedded input crystal. By frequency
modulating the clock, the measured EMI at the fundamental
and harmonic frequencies are greatly reduced. This reduction
in radiated energy can significantly reduce the cost of
complying with regulatory agency (EMC) requirements and
improve time-to-market without degrading system perfor-
mance.
The spread% is programmed to either center spread or down
spread with various spread percentages. The range for center
spread is from ±0.25% to ±2.00%. The range for down spread
is from –0.5% to –4.0%. Contact the factory for smaller or
larger spread% amounts if required. Refer to Table 2 for
spread selection values.
The frequency modulated SSCLK output can be programmed
from 10–166 MHz.
The CY25701 is available in a 4-pin plastic SMD package with
operating temperature range of –20 to 70°C.
Table 1. Programming Data Requirement
Pin Function
Pin Name
Pin#
Units
Program Value
Output Frequency
Spread Percent Code
Frequency Modulation
SSCLK
3
MHz
SSCLK
SSCLK
3
%
3
kHz
31.5
ENTER DATA
ENTER DATA
Table 2. Spread Percent Selection
Center Spread
Code
Percentage
Code
A
B
±0.5%
H
C
±0.75%
J
D
±1.0%
K
E
F
±0.25%
±1.5%
L
±2.0%
M
Down Spread
G
Percentage
–0.5%
–1.0%
–1.5%
–2.0%
–3.0%
–4.0%
Output Frequency, SSCLK Output (SSCLK, pin 3)
The modulated frequency at the SSCLK output is produced by
synthesizing the embedded crystal oscillator frequency input.
The range of synthesized clock is from 10–166 MHz.
Programming Description
Field/Factory-Programmable CY25701
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Spread Percentage (SSCLK, pin 3)
The SSCLK spread can be programmed to various spread
percentage values from ±0.25% to ±2.0% for Center Spread
and from –0.5% to –4.0% for Down Spread. Refer to Table 2
for available spread options
Frequency Modulation (SSCLK, pin 3)
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 10 to 166 MHz. Contact the factory
if a higher-modulation frequency is required.
Additional information on the CY25701 can be obtained from
the Cypress web site at www.cypress.com.
Document #: 38-07684 Rev. *B
Page 2 of 7
CY25701
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Absolute Maximum Rating
Supply Voltage (VDD).................................... –0.5V to +7.0V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Operating Conditions
Parameter
Description
Min.
3.00
–20
–
10
30.0
0.05
Typ.
3.30
–
–
–
Max.
3.60
70
Unit
V
°C
VDD
TA
Supply Voltage
Ambient Temperature
CLOAD
FSSCLK
FMOD
TPU
Max. Load Capacitance @ pin 3
SSCLK output frequency, CLOAD = 15 pF
Spread Spectrum Modulation Frequency
15
pF
166
33.0
500
MHz
kHz
ms
31.5
–
Power-up time for VDD to reach minimum specified
voltage (power ramp must be monotonic)
DC Electrical Characteristics
Parameter
Description
Condition
Min.
10
10
0.7VDD
–
–
–
–10
–
–
Typ.
12
12
–
–
–
–
–
5
–
Max. Unit
IOH
IOL
VIH
VIL
IIH
IIL
IOZ
CIN
Output High Current (pin 3)
Output Low Current (pin 3)
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Current (pin 1)
Input Low Current (pin 1)
Output Leakage Current (pin 3) Three-state output, OE = 0
Input Capacitance (pin 1)
Supply Current
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD= 3.3V (sink)
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
Vin = VDD
–
–
mA
mA
V
VDD
0.3VDD
10
V
µA
µA
µA
pF
mA
Vin = VSS
10
10
[1]
Pin 1, or OE
7
30
IVDD
VDD = 3.3V, SSCLK = 10 to 166 MHz,
CLOAD = 0, OE = VDD
AC Electrical Characteristics[1]
Parameter
DC
tR
Description
Output Duty Cycle
Output Rise Time
Output Fall Time
Condition
SSCLK, Measured at VDD/2
20%–80% of VDD, CL = 15pF
20%–80% of VDD, CL = 15pF
SSCLK ≥133 MHz, Measured at VDD/2
25 MHz ≤ SSCLK <133 MHz, Measured at VDD/2
SSCLK < 25 MHz, Measured at VDD/2
Min. Typ.
Max.
55
2.7
2.7
200
Unit
%
45
50
–
–
ns
ns
ps
ps
s
tF
TCCJ1
–
–
[2]
Cycle-to-Cycle Jitter
–
–
SSCLK (Pin 3)
–
–
400
1% of 1/SSCK
350
–
–
TOE1
TOE2
TLOCK
Output Disable Time
(pin1 = OE)
Time from falling edge on OE to stopped outputs
–
150
ns
(Asynchronous)
Output Enable Time
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
Time for SSCLK to reach valid frequency
TA = 25°C, First year
–
150
350
ns
(pin1 = OE)
PLL Lock Time
Aging in Frequency
–
–5
–
–
10
5
ms
ppm
∆f
Notes:
1. Guaranteed by characterization, not 100% tested.
2. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer
to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your
local Cypress Field Application Engineer.
Document #: 38-07684 Rev. *B
Page 3 of 7
CY25701
Application Circuit
Power
VDD
OE
VDD
4
3
1
2
0.1uF
CY25701
VSS
SSCLK
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B
)
t
1B
t
1A
SSCLK
Output Rise/Fall Time
VDD
0V
SSCLK
Tr
Tf
Output Rise time (Tr) = (0.6 x V )/SR1 (or SR3)
DD
Output Fall time (Tf) = (0.6 x V )/SR2 (or SR4)
DD
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Output Enable/Disable Timing
VDD
VIH
OUTPUT
ENABLE
TOE2
VIL
0V
High Impedance
SSCLK
(Asynchronous
)
TOE1
Document #: 38-07684 Rev. *B
Page 4 of 7
CY25701
Informational Graphs [3]
172.5
171.5
170.5
169.5
168.5
167.5
166.5
165.5
164.5
163.5
162.5
161.5
160.5
159.5
169.5
169
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
168.5
168
167.5
167
166.5
Fnominal
166
165.5
Fnominal
165
164.5
164
163.5
163
162.5
0
20
40
60
80
100 120 140
Time (us)
160 180 200
0
20
40
60
80
100
120
140 160 180
200
Time (us)
68.5
68
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
67.5
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
66.5
66
67.5
67
66.5
Fnominal
66
Fnominal
65.5
65
65.5
64.5
64
65
63.5
64.5
0
20
40
60
80
100
120
140 160
180
200
0
20
40
60 80
100 120 140 160 180 200
Time (us)
Time (us)
Ordering Information
Part Number[4,5]
CY25701JXCZZZZ
CY25701JXCZZZZT
CY25701FJXC
Package description
4-Lead Plastic JE SMD – Lead-free
4-Lead Plastic JE SMD, Tape and Reel – Lead-free
4-Lead Plastic JE SMD – Lead-free
Product Flow
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
CY25701FJXCT
4-Lead Plastic JE SMD, Tape and Reel – Lead-free
Notes:
3. The “Informational Graphs” are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on
pages 4 and 5 for device specifications.
4. “ZZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming data
is received from the customer.
5. “FJXC” suffix is used for products programmed in field by Cypress distributors.
Document #: 38-07684 Rev. *B
Page 5 of 7
CY25701
Package Drawing and Dimension
4-Lead JE04A
10.2 0.ꢀ
(10.5 MAX)
4
1.0 0.2
(1.0)
ꢀ.6
5.0
5.6 0.2
(5.8 MAX)
1.0 0.2
(1.0)
1
1.ꢀ
2.1
+0.2
-0.1
2.5
2.4
(2.7 MAX)
4.6
0.1
0.15 0.1
0.51
(0.05 MIN)
5.08 0.1
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: N/A
PKG. WEIGHT: 0.24 gms
5.08
RECOMMENDED SOLDERING PATTERN
51-85204-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07684 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25701
Document History Page
Document Title: CY25701 Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO)
Document Number: 38-07684
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
224108
See ECN
RGL
New data sheet
*A
258974
See ECN
RGL
Corrected the product suffix (lead-free) in the ordering information table
Added note 4
*B
279379
See ECN
RGL
Added ordering part numbers
Document #: 38-07684 Rev. *B
Page 7 of 7
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