CY26126SC [CYPRESS]
Dual Output 125-MHz Clock Generator; 双输出125 - MHz的时钟发生器型号: | CY26126SC |
厂家: | CYPRESS |
描述: | Dual Output 125-MHz Clock Generator |
文件: | 总5页 (文件大小:108K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
5
Advance Information
CY26126
Dual Output 125-MHz
Clock Generator
Features
• Integrated phase-locked loop
• Low skew, low jitter, high accuracy outputs
• 3.3V Operation
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Part Number Outputs
CY26126
Input Frequency Range
25 MHz
Output Frequencies
2
2 copies of 125 MHz (3.3V)
Logic Block Diagram
P Comp
OUTPUT
MULTIPLEXER
AND
DIVIDERS
25 XIN
XOUT
OSC.
Q
125 MHz
125 MHz
VCO
P
PLL
OE
VSS
VDD
Pin Configurations
CY26126
8-pin SOIC
1
2
3
4
XOUT
8
7
6
5
XIN
VDD
CLKB
CLKA
VSS
OE
VSS
Cypress Semiconductor Corporation
Document #: 38-07351 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 14, 2002
Advance Information
CY26126
Pin Summary
Name
XIN
Pin Number
Description
1
Reference Input
3.3V Voltage Supply
Output Enable
VDD
2
3
4
5
6
7
8
OE
VSS
Ground
VSS
Ground
CLKA
CLKB
XOUT[1]
125-MHz Clock Output A
125-MHz Clock Output B
Reference Output
Absolute Maximum Conditions
Parameter
VDD
Description
Min.
–0.5
–65
Max.
7.0
Unit.
V
Supply Voltage
TS
TJ
Storage Temperature[2]
Junction Temperature
Digital Inputs
125
°C
°C
V
125
VSS – 0.3
VSS – 0.3
2
VDD + 0.3
VDD + 0.3
Digital Outputs referred to VDD
Electro-Static Discharge
V
kV
Recommended Operating Conditions
Parameter Description
VDD Operating Voltage
Min.
3.14
0
Typ.
Max.
Unit
V
3.3
3.47
70
TA
Ambient Temperature
°C
CLOAD
Pmax
fREF
Max. Load Capacitance
Max. Output Power Dissipation
Reference Frequency
15
pF
150
mW
MHz
25
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
tPU
0.05
500
ms
DC Electrical Characteristics
Parameter
IOH
Description
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input Capacitance
Input Leakage Current
Supply Current
Conditions
Min.
12
Typ.
24
Max.
Unit
mA
mA
VDD
VDD
pF
VOH = VDD – 0.5, VDD = 3.3V
VOL = 0.5, VDD = 3.3V
IOL
12
24
VIH
CMOS Levels 70% of VDD
CMOS Levels 30% of VDD
0.7
VIL
0.3
7
CIN
IIZ
5
µA
IDD
Sum of Core and Output Current
35
mA
Notes:
1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal).
2. Rated for 10 years.
Document #: 38-07351 Rev. *A
Page 2 of 5
Advance Information
CY26126
AC Electrical Characteristics (VDD = 3.3V)[3]
Parameter
Description
Conditions
Min.
45
Typ.
50
Max.
Unit
%
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
55
t3
t4
Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD
0.8
0.8
1.4
1.4
V/ns
V/ns
Falling Edge Slew
Rate
Output Clock Fall Time, 80% - 20% of VDD
t9
Clock Jitter
Peak to Peak period jitter
200
3
ps
t10
PLL Lock Time
ms
Note:
3. Not 100% tested.
Test Circuit
VDD
CLK out
CLOAD
0.1 µF
0.1 µF
OUTPUTS
VDD
GND
t1
t2
50%
CLK
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
t4
80%
20%
CLK
Figure 2. Rise and Fall Time Definitions
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26126SC
S8
8-Pin SOIC
Commercial
3.3V
Document #: 38-07351 Rev. *A
Page 3 of 5
CY26126
Advance Information
Package Diagram
8-Lead (150-Mil) SOIC S8
51-85066-A
Document #: 38-07351 Rev. *A
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Advance Information
CY26126
Document Title: CY26126 Dual Output 125-MHz Clock Generator
Document Number: 38-07351
Issue
Orig. of
Change
REV.
**
ECN NO.
112233
Date
Description of Change
03/01/02
12/14/02
CKN
RBI
New data sheet
Power up requirements added to Operating Conditions Information
*A
121891
Document #: 38-07351 Rev. *A
Page 5 of 5
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