CY2XL13ZXI01T [CYPRESS]
Clock Generator, 125MHz, CMOS, PDSO8, TSSOP-8;
| 型号： | CY2XL13ZXI01T |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 125MHz, CMOS, PDSO8, TSSOP-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2XL13
Low-Noise LVDS Clock Generator
Low-Noise LVDS Clock Generator
Features
Functional Description
■ Output: One low-voltage differential signal (LVDS) output pair
■ Output frequency: 125 MHz
The CY2XL13 is
a
phase-locked loop (PLL)-based
high-performance clock generator that uses Cypress’s low-noise
voltage control oscillator (VCO) technology to achieve less than
1-ps typical RMS phase jitter. The CY2XL13 uses an external
crystal reference input to generate one LVDS output pair, which
can be asynchronously enabled/disabled with an OE pin. The
device operates at 3.3 V or 2.5 V.
■ Input: 25-MHz external crystal
■ RMS phase jitter:
❐ At 125 MHz (12 kHz to 20 MHz offset): 0.65 ps typical
■ Package: Pb-free 8-pin thin shrunk small outline package
(TSSOP)
■ Supply voltage: 3.3 V or 2.5 V
■ Temperature range: Commercial or industrial
Logic Block Diagram
XIN
CLK
External
Crystal
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
OUTPUT
DIVIDER
CLK#
XOUT
OE
Cypress Semiconductor Corporation
Document Number: 001-63177 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 10, 2013
CY2XL13
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Frequency Table ...............................................................3
Absolute Maximum Conditions .......................................4
Operating Conditions .......................................................4
DC Electrical Characteristics ..........................................5
AC Electrical Characteristics ..........................................6
Crystal Characteristics ....................................................6
Switching Waveforms ......................................................7
Termination Circuits .........................................................8
Application Information ...................................................9
Power Supply Filtering Techniques .............................9
Board Layout and OE Pin ............................................9
Termination for LVDS Output ......................................9
Crystal Interface ..........................................................9
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Drawing and Dimensions ...............................11
Acronyms ........................................................................12
Document Conventions .................................................12
Units of Measure .......................................................12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC® Solutions ......................................................14
Cypress Developer Community .................................14
Technical Support .....................................................14
Document Number: 001-63177 Rev. *A
Page 2 of 14
CY2XL13
Pinout
Figure 1. 8-pin TSSOP pinout
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
OE
Pin Definitions
8-pin TSSOP
Pin
Number
Pin Name
I/O Type
Description
1, 8
VDD
VSS
Power
Power
3.3-V or 2.5-V power supply. All supply current flows through pin 1
Ground
2
3, 4
XOUT, XIN XTAL output Parallel resonant crystal interface
and input
5
OE
CMOS input Output enable: When high, the output is enabled. When low, the output is high impedance.
6, 7
CLK#, CLK LVDS output Differential clock output
Frequency Table
RMS Phase Jitter (Random)
Part Number
Crystal Frequency Output Frequency
25 MHz 125 MHz
Pin 5 Function
Offset Range
Jitter (Typical)
CY2XL13ZXC01
CY2XL13ZXI01
OE
12 kHz to 20 MHz
0.65 ps
Document Number: 001-63177 Rev. *A
Page 3 of 14
CY2XL13
Absolute Maximum Conditions
Parameter
VDD
Description
Supply voltage
Condition
Min
–0.5
–0.5
–65
–
Max
4.4
Unit
V
[1]
VIN
TS
TJ
Input voltage, DC
Relative to VSS
Non operating
VDD + 0.5
150
V
Temperature, Storage
Temperature, Junction
C
C
V
135
ESDHBM
Electrostatic discharge (ESD)
protection (human body model)
JEDEC STD 22-A114-B
At 1/8 in.
2000
–
UL–94
Flammability rating
V–0
–
[2]
JA
Thermal resistance, junction to 0 m/s airflow
100
91
C/W
ambient
1 m/s airflow
2.5 m/s airflow
87
Operating Conditions
Parameter
Description
Min
3.135
2.375
0
Max
3.465
2.625
70
Unit
V
VDD
3.3-V supply voltage
2.5-V supply voltage
V
TA
Ambient temperature, commercial
Ambient temperature, industrial
C
C
ms
–40
85
TPU
Power-up time for all VDD to reach minimum specified voltage (ensure power ramp
is monotonic)
0.05
500
Notes
1. The voltage on any input or I/O pin cannot exceed the V pins during power-up.
DD
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper
(2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metallization. No vias are included in the model.
Document Number: 001-63177 Rev. *A
Page 4 of 14
CY2XL13
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
[3]
IDD
Power supply current with output VDD = 3.465 V, OE = VDD
,
–
–
120
mA
terminated
output terminated
VDD = 2.625 V, OE = VDD
output terminated
,
–
–
–
115
454
mA
mV
[4]
VOD
LVDS differential output voltage VDD = 3.3 V or 2.5 V,
247
R
CLK#
TERM = 100 between CLK and
[4]
VOD
Change in VOD between
complementary output states
VDD = 3.3 V or 2.5 V,
RTERM = 100 between CLK and
CLK#
–
1.125
–
–
–
–
–
50
1.375
50
mV
V
[5]
VOS
VOS
IOZ
LVDS offset output voltage
VDD = 3.3 V or 2.5 V,
R
CLK#
TERM = 100 between CLK and
Change in VOS between
complementary output states
VDD = 3.3 V or 2.5 V,
RTERM = 100 between CLK and
CLK#
mV
A
Output leakage current
Three-state output, unterminated,
measured on one pin while floating
the other pin, OE = VSS
–35
35
VIH
VIL
IIH
Input high voltage, pin 5
Input low voltage, pin 5
Input high current, pin 5
Input low current, pin 5
Input capacitance, pin 5
Pin capacitance, XIN and XOUT
0.7 × VDD
–
–
–
V
–
–
0.3 × VDD
V
Input = VDD
Input = VSS
–
115
–
µA
µA
pF
pF
IIL
–50
–
–
CIN
CINX
15
4.5
–
–
–
Notes
3.
I
includes ~4 mA of current that is dissipated externally in the output termination resistor.
DD
4. Refer to Figure 2 on page 7.
5. Refer to Figure 3 on page 7.
Document Number: 001-63177 Rev. *A
Page 5 of 14
CY2XL13
AC Electrical Characteristics
Parameter [6, 7]
Description
Output frequency
Test Conditions
Min
Typ
Max
Unit
MHz
ns
[8]
FOUT
See note 8
[9]
TR, TF
Output rise or fall time
RMS phase jitter (random)
Duty cycle
20% to 80% of full output swing
Offset = 12 kHz to 20 MHz
–
–
0.5
–
1.0
1.0
55
[8, 10]
TJitter()
ps
[11]
TDC
Measured at zero crossing point
45
–
–
%
[12]
TOHZ
Output disable time
Time from falling edge on OE to
stopped outputs (asynchronous)
–
100
ns
[12]
TOE
Output enable time
Startup time
Time from rising edge on OE to
outputs at a valid frequency
(asynchronous)
–
–
–
–
120
5
ns
TLOCK
Time for CLK to reach valid
frequency measured from the
ms
time VDD = VDD(min)
.
Crystal Characteristics
Parameter
Description
Min
Max
Unit
MO
F[8]
ESR
CS
Mode of oscillation
Frequency
Fundamental
See note 8
50
MHz
Equivalent series resistance
Shunt capacitance
–
–
7
pF
Notes
6. Not 100% tested, guaranteed by design and characterization.
7. Outputs are terminated with 100 between CLK and CLK#. Refer to Figure 8 on page 8.
8. Crystal frequency, output frequency, and typical phase jitter are listed in Frequency Table on page 3.
9. Refer to Figure 4 on page 7.
10. Refer to Figure 7 on page 8.
11. Refer to Figure 5 on page 7.
12. Refer to Figure 6 on page 7.
Document Number: 001-63177 Rev. *A
Page 6 of 14
CY2XL13
Switching Waveforms
Figure 2. Output Voltage Swing
CLK#
VOD1
VOD2
CLK
VOD = VOD1 - VOD2
Figure 3. Output Offset Voltage
CLK
50
VOS
50
CLK#
Figure 4. Output Rise or Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Figure 5. Duty Cycle Timing
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Figure 6. Output Enable and Disable Timing
VIH
OE
VIL
TOHZ
TOE
CLK
High Impedance
CLK#
Document Number: 001-63177 Rev. *A
Page 7 of 14
CY2XL13
Switching Waveforms (continued)
Figure 7. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
Area Under the Masked Phase Noise Plot
RMS Jitter =
Termination Circuits
Figure 8. LVDS Termination
CLK
100
CLK#
Document Number: 001-63177 Rev. *A
Page 8 of 14
CY2XL13
located very close to the receiver. To minimize signal reflections
from the receiver, the differential impedance (Z0) of the trace pair
should be 100 to match the termination resistor.
Application Information
Power Supply Filtering Techniques
As in any high-speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter
performance, use good power-supply isolation practices.
Figure 9 illustrates a typical filtering scheme. Because all the
current flows through pin 1, the resistance and inductance
between this pin and the supply is minimized. A 0.01 or 0.1 µF
ceramic chip capacitor is also located close to this pin to provide
a short and low-impedance AC path to ground. A 1 to 10 µF
ceramic or tantalum capacitor is located in the general vicinity of
this device and may be shared with other devices.
Figure 10. Output Termination
Z0 = 50
CLK
100
IN
Z0 = 50
CLK#
Figure 9. Power Supply Filtering
Crystal Interface
The CY2XL13 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 11 are
determined using an 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are,
therefore, layout dependent.
V
DD
(Pin 8)
3.3V
10µ
V
DD
(Pin 1)
Figure 11. Crystal Input Interface
F
0.01µF
XIN
C1
X1
Device
Board Layout and OE Pin
30 pF
18 pF Parallel
Crystal
If the Output Enable (OE) function on pin 5 is not needed, it may
be connected directly to the VDD plane by a wide trace and
multiple vias. This improves heat dissipation. A resistor between
OE and VDD is not necessary.
XOUT
C2
27 pF
Termination for LVDS Output
The CY2XL13 is designed to drive a standard LVDS load with a
100- termination resistor. Figure 10 shows the standard
termination scheme. The termination resistor should always be
Document Number: 001-63177 Rev. *A
Page 9 of 14
CY2XL13
Ordering Information
Part Number
CY2XL13ZXC01
Package Description
8-pin TSSOP
Product Flow
Commercial, 0 C to 70 C
Commercial, 0 C to 70 C
Industrial, –40 C to 85 C
Industrial, –40 C to 85 C
CY2XL13ZXC01T
CY2XL13ZXI01
8-pin TSSOP – Tape and Reel
8-pin TSSOP
CY2XL13ZXI01T
8-pin TSSOP – Tape and Reel
Ordering Code Definitions
CY 2XL13
Z
X
X
xx
X
X = blank or T
blank = Tube; T = Tape and Reel
Part configuration code: xx = 01
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: Z = 8-pin TSSOP
Base part number
Company ID: CY = Cypress
Document Number: 001-63177 Rev. *A
Page 10 of 14
CY2XL13
Package Drawing and Dimensions
Figure 12. 8-pin TSSOP (4.40 mm Body) Z08.173/ZZ08.173 Package Outline, 51-85093
51-85093 *D
Document Number: 001-63177 Rev. *A
Page 11 of 14
CY2XL13
Acronyms
Document Conventions
Units of Measure
Acronym
Description
Electrostatic Discharge
Field Application Engineer
ESD
FAE
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
HBM
JEDEC
LCC
LVDS
OE
Human Body Model
MHz
A
s
Joint Electron Devices Engineering Council
Leadless Chip Carrier
Low-Voltage Differential Signaling
Output Enable
mA
mm
ns
PCB
PLL
Printed Circuit Board
Phase-Locked Loop
RMS
TSSOP
VCO
XO
Root Mean Square
%
percent
Thin Shrunk Small Outline Package
Voltage Controlled Oscillator
Crystal Oscillator
pF
V
picofarad
volt
W
watt
Document Number: 001-63177 Rev. *A
Page 12 of 14
CY2XL13
Document History Page
Document Title: CY2XL13, Low-Noise LVDS Clock Generator
Document Number: 001-63177
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
2991849
4118896
07/23/2010
09/10/2013
KVM
New data sheet.
*A
CINM
Updated Package Drawing and Dimensions:
spec 51-85093 – Changed revision from *C to *D.
Updated in new template.
Completing Sunset Review.
Document Number: 001-63177 Rev. *A
Page 13 of 14
CY2XL13
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2010-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-63177 Rev. *A
Revised September 10, 2013
Page 14 of 14
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