CY2XP21ZXCT [CYPRESS]
125 MHz LVPECL Clock Generator; 125MHz的LVPECL时钟发生器
| 型号： | CY2XP21ZXCT |
| 厂家： | 
CYPRESS |
| 描述： | 125 MHz LVPECL Clock Generator |
| 文件： | 总7页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY2XP21
125 MHz LVPECL Clock Generator
Features
Functional Description
■
■
■
■
One LVPECL Output Pair
The CY2XP21 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate a
125 MHz clock, which is ideal for 10 Gb Ethernet applications. It
also produces an output frequency that is five times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter. The CY2XP21
has a crystal oscillator interface input and one LVPECL output
pair.
Output Frequency: 112 MHz to 140 MHz
External Crystal Frequency: 22.4 MHz to 28 MHz
Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal
(1.875 MHz to 20 MHz): 0.4 ps (Typical)
■
■
■
Pb-free 8-Pin TSSOP Package
Supply Voltage: 3.3V or 2.5V
Commercial and Industrial Temperature Ranges
Logic Block Diagram
XIN
External
Crystal
CLK
CRYSTAL
OSCILLATOR
LOW -N OISE
PLL
OUTPUT
DIVIDER
CLK#
XOUT
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
NC
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number
Pin Name
VDD
I/O Type
Description
1, 8
2
Power
Power
3.3V or 2.5V power supply
Ground
VSS
3, 4
5
XOUT, XIN
NC
XTAL output and input
Parallel resonant crystal interface
No Connect
6,7
CLK#, CLK
LVPECL output
Differential Clock Output
Cypress Semiconductor Corporation
Document #: 001-52849 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 15, 2009
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PRELIMINARY
CY2XP21
Frequency Table
Inputs
Output Frequency (MHz)
Crystal Frequency (MHz)
PLL Multiplier Value
25
5
5
125
133
26.6
Absolute Maximum Conditions
Parameter
Description
Conditions
Min
–0.5
–0.5
–65
Max
Unit
V
VDD
Supply Voltage
4.4
[1]
VIN
Input Voltage, DC
Relative to VSS
Non operating
VDD + 0.5
150
V
TS
Temperature, Storage
Temperature, Junction
ESD Protection, Human Body Model
Flammability Rating
°C
°C
V
TJ
135
ESDHBM
JEDEC STD 22-A114-B
At 1/8 in.
2000
UL–94
V–0
[2]
ΘJA
Thermal Resistance, Junction to Ambient 0 m/s airflow
100
91
°C/W
1 m/s airflow
2.5 m/s airflow
87
Operating Conditions
Parameter
Description
Min
3.135
2.375
0
Max
3.465
2.625
70
Unit
V
VDD
TA
3.3V Supply Voltage
2.5V Supply Voltage
V
Ambient Temperature, Commercial
Ambient Temperature, Industrial
°C
°C
ms
–40
85
TPU
Power up time for all VDD to reach minimum specified voltage (ensure power ramps
is monotonic)
0.05
500
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
–
Typ
–
Max
150
145
Unit
mA
mA
V
[4]
IDD
Operating Supply Current with
output terminated
VDD = 3.465V, Output terminated
V
DD = 2.625V, Output terminated
–
–
VOH
LVPECL Output High Voltage
LVPECL Output Low Voltage
VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD –1.15
DD – 2.0V
–
VDD –0.75
VDD –1.625
1000
V
VOL
VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD –2.0
DD – 2.0V
–
–
V
mV
mV
V
V
VOD1
VOD2
VOCM
LVPECL Peak-to-Peak Output
Voltage Swing
VDD = 3.3V or 2.5V, RTERM = 50Ω to
DD – 2.0V
600
500
1.2
V
LVPECL Output Voltage Swing VDD = 2.5V, RTERM = 50Ω to VDD
(VOH - VOL 1.5V
–
–
1000
)
LVPECL Output Common Mode VDD = 2.5V, RTERM = 50Ω to VDD
Voltage (VOH + VOL)/2
–
–
–
1.5V
CINX
Pin Capacitance, XIN & XOUT
4.5
pF
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3.
I
includes approximately 24 mA of current that is dissipated externally in the output termination resistors.
DD
Document #: 001-52849 Rev. *A
Page 2 of 7
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PRELIMINARY
CY2XP21
AC Electrical Characteristics[4]
Parameter
FOUT
Description
Output Frequency
Conditions
Min
112
–
Typ
–
Max
Unit
MHz
ps
140
–
TR, TF
TJitter(φ)
TDC
Output Rise or Fall Time
RMS Phase Jitter (Random)
Output Duty Cycle
20% to 80% of full output swing
125 MHz, (1.875–20 MHz)
500
0.4
–
–
–
ps
Measured at zero crossing point
48
–
52
10
%
TLOCK
Startup Time
Time for CLK to reach valid
frequency measured from the time
VDD = VDD(min.)
–
ms
Recommended Crystal Specifications[5]
Parameter
Description
Min
Max
Unit
Mode
F
Mode of Oscillation
Frequency
Fundamental
22.4
–
28
50
7
MHz
Ω
ESR
C0
Equivalent Series Resistance
Shunt Capacitance
–
pF
Parameter Measurements
Figure 2. 3.3V Output Load AC Test Circuit
2V
SCOPE
Z = 50Ω
Z = 50Ω
VDD
CLK
50Ω
LVPECL
CLK#
VSS
50Ω
-1.3V +/- 0.165V
Figure 3. 2.5V Output Load AC Test Circuit
2V
SCOPE
Z = 50Ω
Z = 50Ω
VDD
LVPECL
CLK
50Ω
50Ω
CLK#
VSS
-0.5V +/- 0.125V
Notes
4. INot 100% tested, guaranteed by design and characterization.
5. Characterized using an 18 pF parallel resonant crystal.
Document #: 001-52849 Rev. *A
Page 3 of 7
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PRELIMINARY
CY2XP21
Figure 4. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 5. Output Rise and Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Figure 6. RMS Phase Jitter
Phase noise
Noise
Power
Phase noise mask
Offset Frequency
f2
f1
Area Under the Masked Phase Noise Plot
RMS Jitter =
Figure 7. Output Duty Cycle
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Document #: 001-52849 Rev. *A
Page 4 of 7
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PRELIMINARY
CY2XP21
Application Information
Figure 9. LVPECL Output Termination
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 8 illus-
trates a typical filtering scheme. Since all the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
3.3V
125Ω
125Ω
Z0 = 50Ω
Z0 = 50Ω
CLK
IN
CLK#
84Ω
84Ω
Figure 8. Power Supply Filtering
Crystal Interface
V
DD
(Pin 8)
The CY2XP21 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are deter-
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
thus layout dependent.
3.3V
10µ
V
DD
(Pin 1)
0.1μ
0.01 µF
F
Figure 10. Crystal Input Interface
XIN
Termination for LVPECL Output
C1
30 pF
X1
Device
The CY2XP21 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
to VDD–2.0V. This same termination voltage can also be used for
VDD = 2.5V operation, or it can be terminated to VDD-1.5V. Note
that it is also possible to terminate with 50 ohms to ground (VSS),
but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the desti-
nation device. To avoid reflections, trace characteristic
impedance (Z0) should match the termination impedance.
Figure 9 shows a standard termination scheme.
18 pF Parallel
Crystal
XOUT
C2
27 pF
Board Layout and NC Pin
Pin 5 (NC) does not perform any function on the CY2XP21.
Although not used electrically, it is very useful for heat dissi-
pation. For this reason, users are advised to connect pin 5 to
either a VDD or VSS plane. This helps to lower the thermal resis-
tance of the board / package combination, thus reducing the die
temperature.
Document #: 001-52849 Rev. *A
Page 5 of 7
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PRELIMINARY
CY2XP21
Ordering Information
Part Number
CY2XP21ZXC
Package Type
Product Flow
Commercial, 0°C to 70°C
8-pin TSSOP
CY2XP21ZXCT
CY2XP21ZXI
8-pin TSSOP - Tape and Reel
8-pin TSSOP
Commercial, 0°C to 70°C
Industrial, -40°C to 85°C
Industrial, -40°C to 85°C
CY2XP21ZXIT
8-pin TSSOP - Tape and Reel
Package Drawing and Dimensions
Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
2.90[0.114]
3.10[0.122]
51-85093-*A
Document #: 001-52849 Rev. *A
Page 6 of 7
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PRELIMINARY
CY2XP21
Document History Page
Document Title: CY2XP21 125 MHz LVPECL Clock Generator
Document Number: 001-52849
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
2700242
2718898
04/30/2009 KVM/PYRS New data sheet
06/15/09 WWZ Minor ECN to post data sheet to external web
*A
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-52849 Rev. *A
Revised June 15, 2009
Page 7 of 7
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