CY7C4265A-15ASI [CYPRESS]
8K/16K x 18 Deep Sync FIFOs; 8K / 16K ×18深同步FIFO的
| 型号： | CY7C4265A-15ASI |
| 厂家： | 
CYPRESS |
| 描述： | 8K/16K x 18 Deep Sync FIFOs |
| 文件： | 总23页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4255, CY7C4265, CY7C4265A
8K/16K x 18 Deep Sync FIFOs
Features
Functional Description
The CY7C4255/65/65A are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A
can be cascaded to increase FIFO depth. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs, including
high speed data acquisition, multiprocessor interfaces, and communi-
cations buffering.
■ High Speed, Low Power, First-In First-Out (FIFO) Memories
❐ 8K x 18 (CY7C4255)
❐ 16K x 18 (CY7C4265/4265A)[1]
■ 0.5 Micron CMOS for Optimum Speed and Power
■ High Speed 100 MHz Operation (10 ns read/write cycle times)
■ Low Power — ICC = 45 mA
■ Fully Asynchronous and Simultaneous Read and Write
Operation
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free running Clock (WCLK) and a Write Enable
pin (WEN).When WENis asserted, data is written into the FIFO on the
risingedgeofthe WCLK signal. While WEN is held active, datais contin-
ually written into the FIFO on each cycle. The output port is controlled in
a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN).Inaddition,theCY7C4255/65/65A haveanOutput
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to
100 MHz are achievable.
■ Empty, Full, Half Full, and Programmable Almost Empty and
Almost Full Status Flags
■ TTL compatible
■ Retransmit Function
■ Output Enable (OE) Pins
■ Independent Read and Write Enable Pins
■ Center Power and Ground Pins for Reduced Noise
■ Supports Free-running 50 percent Duty Cycle Clock Inputs
■ Width and Depth Expansion Capability
■ 64-pin TQFP and 64-pin STQFP
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices. Depth expansion is
possible using the Cascade Input (WXI, RXI), Cascade Output
(WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are
connected to the WXI and RXI pins of the next device, and the WXO
and RXO pins of the last device should be connected to the WXI and
RXI pins of the first device. The FL pin of the first device is tied to VSS
■ Pin-compatible Density Upgrade to CY7C42X5 Family
■ Pin-compatible Density Upgrade to IDT72205/15/25/35/45
■ Pb-free Packages Available
and the FL pin of all the remaining devices should be tied to VCC
.
D0–17
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FF
EF
FLAG
LOGIC
RAM
ARRAY
8K x 18
PAE
PAF
SMODE
16K x 18
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
THREE–STATE
READ
WXI
WXO/HF
RXI
OUTPUTREGISTER
CONTROL
EXPANSION
LOGIC
OE
Q0–17
RXO
RCLK
REN
Note
1. CY7C4265 and CY7C4265A are functionally identical
Cypress Semiconductor Corporation
Document #: 38-06004 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 03, 2009
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Pin Configurations
Figure 1. 64-Pin TQFP/STQFP (Top View)
Q
Q
48
47
D
15
D
14
D
13
D
12
1
2
14
13
GND
46
45
3
4
Q
12
Q
V
44
43
42
41
11
D
D
5
6
7
8
11
CC
10
CY7C4255
CY7C4265/65A
Q
10
D
9
Q
9
D
D
8
7
6
GND
40
39
9
10
Q
8
D
D
D
D
D
D
38
37
36
11
12
Q
7
5
Q
6
4
3
13
14
15
Q
5
35
34
GND
2
Q
4
1
D
0
33
V
CC
16
Pin Description
The CY7C4255/65/65A provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full. The Half Full flag shares the WXO
pin. This flag is valid in the standalone and width-expansion
configurations. In the depth expansion, this pin provides the
expansion out (WXO) information that is used to signal the next
FIFO when it is activated.
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags remain valid from one clock
cycle to the next. The Almost Empty/Almost Full flags become
synchronous if the VCC/SMODE is tied to VSS. All configura-
tions are fabricated using an advanced 0.5μ CMOS
technology. Input ESD protection is greater than 2001V, and
latch up is prevented by the use of guard rings.
The Empty and Full flags are synchronous, that is, they change
state relative to either the Read Clock (RCLK) or the Write Clock
Table 1. Selection Guide
Description
7C4255/65-10
7C4255/65/65A-15
7C4255/65-25
7C4255/65-35
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
100
8
10
3
0.5
8
45
50
66.7
10
15
4
40
15
25
6
28.6
20
35
7
1
1
2
10
45
50
15
45
50
20
45
50
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
Table 2. Density and Package
Description
Density
CY7C4255
CY7C4265/65A
8K x 18
16K x18
Package
64-pin TQFP, STQFP
64-pin TQFP, STQFP
Document #: 38-06004 Rev. *E
Page 2 of 23
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CY7C4255, CY7C4265, CY7C4265A
Table 3. Pin Definitions
Signal Name
D0 –17
Description
I/O
Function
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I
O
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
Q0–17
WEN
REN
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to RCLK when VCC/SMODE is tied to VSS
.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to WCLK when VCC/SMODE is tied to VSS
.
LD
Load
I
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT
First Load/
Retransmit
Dual-Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to VSS; all other devices
has FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all
devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode
by strobing RT.
WXI
RXI
RXO
RS
Write Expansion
Input
I
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS
.
Read Expansion
Input
.
Read Expansion
Output
O
I
Cascaded – Connected to RXI of next device.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC
Synchronous Almost Empty/Almost Full flags – tied to VSS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
.
Almost Full Flags
.
Document #: 38-06004 Rev. *E
Page 3 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[2]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................>2001V
(per MIL–STD–883, Method 3015)
Storage Temperature ................................ –65°C to +150°C
Ambient Temperature with Power Applied. –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
Latch Up Current .....................................................>200 mA
Operating Range
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
Ambient
Range
Commercial
Industrial[4]
Temperature[3]
0°C to +70°C
VCC
DC Input Voltage ......................................... −0.5V to VCC+0.5V
5V ± 10%
5V ± 10%
–40°C to +85°C
Electrical Characteristics Over the Operating Range[4]
7C42X5,
7C4265A-15
7C42X5-10
7C42X5-25
7C42X5-35
Unit
Parameter
VOH
VOL
Description
Test Conditions
Min Max Min Max Min Max Min Max
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
2.4
V
V
I
OH = –2.0 mA
Output LOW Voltage
VCC = Min.,
OL = 8.0 mA
0.4
0.4
0.4
0.4
I
[5]
VIH
Input HIGH Voltage
Input LOW Voltage
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
V
V
[5]
VIL
IIX
Input Leakage
Current
VCC = Max.
OE > VIH,
+10
+10
+10
+10 μA
IOZL
IOZH
Output OFF,
High Z Current
–10
+10
–10
+10
–10
+10
–10
+10
μA
VSS < VO < VCC
[6]
ICC1
Active Power Supply
Current
Commercial
45
50
10
15
45
50
10
15
45
50
10
15
45
50
10
15
mA
mA
mA
mA
Industrial
[7]
ICC2
Average Standby
Current
Commercial
Industrial
Capacitance[8, 9]
Parameter
CIN
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max
5
Unit
Input Capacitance
Output Capacitance
pF
pF
V
COUT
7
Notes
2. The Voltage on any input or I/O pin cannot exceed the power pin during power up.
3. is the “Instant On” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. The V and V specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device
T
A
IH
SS
IL
or V
.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are
unloaded. I 1(typical) = (25 mA + (freq – 20 MHz) * (1.0 mA/MHz)).
CC
7. All inputs = V – 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at V . All outputs are unloaded.
CC
SS
8. Tested initially and after any design changes that may affect these parameters.
9. Tested initially and after any process changes that may affect these parameters.
Document #: 38-06004 Rev. *E
Page 4 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Figure 2. AC Test Loads and Waveforms[10, 11]
ALL INPUT PULSES
R1 1.1 KΩ
5V
3.0V
90%
10%
90%
10%
OUTPUT
GND
R2
680Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalentto:
THÉVENIN EQUIVALENT
410Ω
OUTPUT
1.91V
Switching Characteristics Over the Operating Range
7C42X5,
7C4265A-15
7C42X5-10
7C42X5-25
7C42X5-35
Unit
Parameter
Description
Min Max Min Max Min Max Min Max
tS
Clock Cycle Frequency
100
8
66.7
10
40
15
28.6 MHz
20
tA
Data Access Time
2
10
4.5
4.5
3
2
15
6
2
25
10
10
6
2
35
14
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set Up Time
4
tDH
Data Hold Time
0.5
3
1
1
2
tENS
tENH
tRS
Enable Set Up Time
4
6
7
Enable Hold Time
0.5
10
8
1
1
2
Reset Pulse Width[12]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
Output Enable to Output Valid
Output Enable to Output in High Z[13]
Write Clock to Full Flag
Read Clock to Empty Flag
15
10
25
15
35
20
tRSR
tRSF
tPRT
tRTR
tOLZ
tOE
10
15
25
35
30
60
0
35
65
0
45
75
0
55
85
0
3
7
7
3
8
3
12
12
15
15
20
3
15
15
20
20
25
tOHZ
tWFF
tREF
3
3
8
3
3
8
10
10
16
8
tPAFasynch Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC
12
)
)
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
8
12
8
10
16
10
15
20
15
20
25
20
ns
ns
ns
)
tPAEasynch Clock to Programmable Almost-Empty Flag[14]
(Asynchronous mode, VCC/SMODE tied to VCC
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
)
tHF
tXO
Clock to Half-Full Flag
12
6
16
10
20
15
25
20
ns
ns
Clock to Expansion Out
Document #: 38-06004 Rev. *E
Page 5 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Switching Characteristics Over the Operating Range (continued)
7C42X5,
7C4265A-15
7C42X5-10
7C42X5-25
7C42X5-35
Unit
Parameter
Description
Min Max Min Max Min Max Min Max
tXI
Expansion in Pulse Width
4.5
4
6.5
5
10
10
10
14
15
12
ns
ns
ns
tXIS
Expansion in Set-Up Time
tSKEW1
Skew Time between Read Clock and Write Clock
for Full Flag
5
6
tSKEW2
tSKEW3
Skew Time between Read Clock and Write Clock
for Empty Flag
5
6
10
18
12
20
ns
ns
Skew Time between Read Clock and Write Clock 10
for Programmable Almost Empty and Program-
mable Almost Full Flags (Synchronous Mode
only)
15
Notes
10. C = 30 pF for all AC parameters except for t
.
L
OHZ
11. C = 5 pF for t
.
L
OHZ
12. Pulse widths less than minimum values are not enabled.
13. Values guaranteed by design, not currently tested.
14. t
, t
, after program register write is not be valid until 5 ns + t
.
PAFasynch PAEasynch
PAF(E)
Document #: 38-06004 Rev. *E
Page 6 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms
Figure 3. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[15]
t
SKEW1
RCLK
REN
Figure 4. Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
REN
t
t
ENH
ENS
NO OPERATION
t
REF
t
REF
EF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[16]
t
SKEW2
WCLK
WEN
Notes
15. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time
SKEW1
between the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK rising edge.
SKEW1
16. t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time
SKEW2
between the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK rising edge.
SKEW2
Document #: 38-06004 Rev. *E
Page 7 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 5. Reset Timing[17]
t
RS
RS
t
RSR
REN,WEN,
LD
t
t
t
RSF
EF,PAE
RSF
RSF
FF,PAF,
HF
[18]
OE = 1
Q0–Q17
OE = 0
Figure 6. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
D –D
t
DS
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
17
t
ENS
[19]
FRL
t
WEN
t
SKEW2
RCLK
t
REF
EF
REN
[20]
t
A
t
A
Q –Q
D
0
D
1
0
17
t
OLZ
t
OE
OE
Notes
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
19. When t > minimum specification, t (maximum) = t + t
. When t
< minimum specification, t
(maximum) = either 2*t
+ t
or
SKEW2
FRL
CLK
SKEW2
SKEW2
FRL
CLK
SKEW2
t
+ t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
CLK
SKEW2
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06004 Rev. *E
Page 8 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 7. Empty Flag Timing
WCLK
t
t
DS
DS
D0
D1
D –D
0
17
t
t
ENH
ENH
t
t
ENS
ENS
WEN
[19]
FRL
[19]
FRL
t
t
RCLK
t
t
t
REF
t
REF
t
SKEW2
REF
SKEW2
EF
REN
OE
t
A
D0
Q –Q
0
17
Figure 8. Full Flag Timing
NO WRITE
NO WRITE
WCLK
[15]
[15]
t
t
DATA WRITE
t
SKEW1
DS
SKEW1
DATA WRITE
D –D
0
17
t
t
t
WFF
WFF
WFF
FF
WEN
RCLK
REN
t
t
ENH
ENH
t
t
ENS
ENS
LOW
OE
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
17
Document #: 38-06004 Rev. *E
Page 9 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 9. Half-Full Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
HF
HALF FULL + 1
OR MORE
HALF FULL OR LESS
HALF FULLOR LESS
HF
t
HF
RCLK
REN
t
ENS
Figure 10. Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
[21]
t
t
ENH
ENS
t
PAE
N + 1 WORDS
IN FIFO
PAE
n WORDS IN FIFO
t
PAE
RCLK
REN
t
ENS
Note
21. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06004 Rev. *E
Page 10 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 11. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
t
CLKL
CLKH
WCLK
WEN
t
t
t
ENS
ENH
WEN2
PAE
t
ENS
[23]
ENH
Note
22
N + 1 WORDS
INFIFO
Note
24
t
PAE synch
t
t
SKEW3
PAE synch
RCLK
REN
t
ENS
t
t
ENH
ENS
Figure 12. Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
25
Note
WCLK
WEN
t
t
ENH
ENS
t
PAF
FULL– M WORDS
[27]
[26]
INFIFO
PAF
FULL– (M+1) WORDS
[28]
IN FIFO
t
PAF
RCLK
REN
t
ENS
Notes
22. PAE offset − n.
23. t is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
SKEW3
WCLK and the rising RCLK is less than t
, then PAE may not change state until the next RCLK.
SKEW3
24. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW.
25. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265/65A.
26. PAF is offset = m.
27. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265/65A.
28. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265/65A.
Document #: 38-06004 Rev. *E
Page 11 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 13. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Note 29
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENS
ENH
Note
30
WEN2
PAF
t
t
t
PAF
ENS
ENH
FULL– M WORDS
[27]
IN FIFO
[31]
FULL– M + 1 WORDS
IN FIFO
t
PAF synch
t
SKEW3
RCLK
REN
t
ENS
t
t
ENH
ENS
Figure 14. Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
t
DH
DS
PAE OFFSET
D –D
0
17
D
D –
0
PAE OFFSET
PAF OFFSET
11
Notes
29. If a write is performed on this rising edge of the write clock, there are Full − (m − 1) words of the FIFO when PAF goes LOW.
30. PAF offset = m.
31. t
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of
SKEW3
RCLK and the rising edge of WCLK is less than t
, then PAF may not change state until the next WCLK rising edge.
SKEW3
Document #: 38-06004 Rev. *E
Page 12 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 15. Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
A
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Q –Q
0
17
Figure 16. Write Expansion Out Timing
t
CLKH
WCLK
Note 32
t
XO
Note 32
WXO
WEN
t
XO
t
ENS
Figure 17. Read Expansion Out Timing
t
CLKH
WCLK
Note 33
t
XO
RXO
REN
t
XO
t
ENS
Figure 18. Write Expansion In Timing
t
XI
WXI
t
XIS
WCLK
Notes
32. Write to Last Physical Location.
33. Read from Last Physical Location.
Document #: 38-06004 Rev. *E
Page 13 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 19. Read Expansion In Timing
t
XI
RXI
t
XIS
RCLK
Figure 20. Retransmit Timing[34, 35, 36]
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
Notes
34. Clocks are free-running in this case.
35. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at t
.
RTR
36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
to update these flags.
RTR
Document #: 38-06004 Rev. *E
Page 14 of 23
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CY7C4255, CY7C4265, CY7C4265A
read/write operation. When the LD pin is set LOW, and WEN is
LOW, the next offset register in sequence is written.
Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65/65A also includes the control signals WXI, RXI,
WXO, RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 4. Write Offset Register
LD WEN WCLK[37]
Selection
Resetting the FIFO
0
0
Writing to offset registers:
Empty Offset
Full Offset
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. For the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW.
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
FIFO Operation
When the WEN signal is active (LOW), data present on the D0–17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory are presented on the Q0–17 outputs. New data is
presented on each rising edge of RCLK while REN is active LOW
and OE is LOW. REN must set up tENS before RCLK for it to be
a valid read function. WEN must occur tENS before WCLK for it
to be a valid write function.
Flag Operation
The CY7C4255/65/65A devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE is
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register is available to the Q0–17 outputs after
tied to VSS
.
Full Flag
t
OE. If devices are cascaded, the OE function only outputs data
on the FIFO that is read enabled.
The Full Flag (FF) goes LOW when device is Full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK: it is exclusively updated
by each rising edge of WCLK.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs even
after additional reads occur.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, i.e., it is exclusively
updated by each rising edge of RCLK.
Programming
The CY7C4255/65/65A devices contain two 14-bit offset
registers. Data present on D0–13 during a program write deter-
mines the distance from Empty (Full) that the Almost Empty
(Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used (see
Table 4). When the Load LD pin is set LOW and WEN is set
LOW, data on the inputs D0–13 is written into the Empty offset
register on the first LOW-to-HIGH transition of the Write Clock
(WCLK). When the LD pin and WEN are held LOW then data is
written into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see Table 4). Writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then,
by bringing the LD pin HIGH, the FIFO is returned to normal
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/65A features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE are asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See Table 5 on
page 16 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Note
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06004 Rev. *E
Page 15 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read pointer
is incremented until it is equal to the write pointer. Flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are transmitted also.
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
The full depth of the FIFO can be repeatedly retransmitted.
Table 5. Flag Truth Table
Number of Words in FIFO
FF
PAF
HF
PAE
EF
CY7C4255 – 8K x 18
CY7C4265/65A – 16K x 18
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n[38]
1 to n[38]
(n + 1) to 4096
4097 to (8192 – (m + 1))
(8192 – m)[39] to 8191
8192
(n + 1) to 8192
8193 to (16384 – (m + 1))
(16384 – m)[39] to 16383
16384
H
H
H
H
L
L
L
Notes
38. n = Empty Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
39. m = Full Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
Document #: 38-06004 Rev. *E
Page 16 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Width Expansion Configuration
The CY7C4255/65/65A can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion
mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full)
flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from, or writing
data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 21 demon-
strates a 36-word width by using two CY7C4255/65/65As.
Figure 21. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
RESET(RS)
RESET(RS)
DATA IN (D)
36
18
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
7C4255
7C4265
7C4255
7C4265
EMPTY FLAG (EF)
EF
FF
FF
EF
DATA OUT (Q)
18
36
FULL FLAG (FF)
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
Depth Expansion Configuration
(with Programmable Flags)
The CY7C4255/65/65A can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 22 shows
Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
Document #: 38-06004 Rev. *E
Page 17 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Figure 22. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion
Configuration
WXO RXO
7C4255
7C4265
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WXO RXO
7C4255
7C4265
DATA IN(D)
DATA OUT (Q)
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
READ CLOCK(RCLK)
READ ENABLE(REN)
WXO RXO
7C4255
7C4265
RESET(RS)
OUTPUT ENABLE(OE)
LOAD (LD)
FF
EF
FF
EF
PAE
PAE
PAF
PAF
WXI RXI
FIRST LOAD (FL)
Document #: 38-06004 Rev. *E
Page 18 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Figure 23. Typical AC and DC Characteristics
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMALIZED tA vs. SUPPLY
VOLTAGE
1.20
1.60
1.40
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
T = 25°C
V
CC
= 5.0V
5.00
A
4.00
4.50
5.00
5.50
6.00
−55.00
65.00
125.00
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
1.20
1.75
1.50
1.25
1.00
0.75
0.50
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
VIN = 3.0V
TA = 25°C
f = 28 MHz
VIN = 3.0V
CC = 5.0V
f = 28 MHz
V
T
CC = 5.0V
A = 25°C
VIN = 3.0V
V
4.00
4.50
5.00
5.50
6.00
−55.00
5.00
65.00
125.00
20.00 30.00 40.00 50.00
60.00
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
Document #: 38-06004 Rev. *E
Page 19 of 23
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Ordering Information
8Kx18 Deep Sync FIFO
Speed
(ns)
Package
Name
Package
Type
Operating
Range
Ordering Code
10
CY7C4255–10AC
CY7C4255–10AXC
CY7C4255–10ASC
CY7C4255–15AC
CY7C4255–15AXC
51-85046
51-85046
51-85051
51-85046
51-85046
64-Pin Thin Quad Flatpack
Commercial
64-Pin Thin Quad Flatpack (Pb-free)
64-Pin Small Thin Quad Flatpack
64-Pin Thin Quad Flatpack
15
Commercial
64-Pin Thin Quad Flatpack (Pb-free)
16Kx18 Deep Sync FIFO
Speed
Package
Diagram
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4265–10AC
CY7C4265–10ASC
CY7C4265–10ASXC
CY7C4265–10AI
51-85046
51-85051
51-85051
51-85046
51-85046
51-85046
51-85046
51-85051
51-85051
64-Pin Thin Quad Flatpack
Commercial
64-Pin Small Thin Quad Flatpack
64-Pin Small Thin Quad Flatpack (Pb-free)
64-Pin Thin Quad Flatpack
Industrial
CY7C4265–10AXI
CY7C4265–15AC
CY7C4265–15AXC
CY7C4265-15ASC
CY7C4265A–15ASI
64-Pin Thin Quad Flatpack (Pb-free)
64-Pin Thin Quad Flatpack
15
Commercial
64-Pin Thin Quad Flatpack (Pb-free)
64-Pin Small Thin Quad Flatpack
64-Pin Small Thin Quad Flatpack
Industrial
Document #: 38-06004 Rev. *E
Page 20 of 23
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CY7C4255, CY7C4265, CY7C4265A
Package Diagrams
Figure 24. 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm), 51-85051
51-85051 *A
Document #: 38-06004 Rev. *E
Page 21 of 23
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CY7C4255, CY7C4265, CY7C4265A
Package Diagrams (continued)
Figure 25. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm), 51-85046
51-85046-*B
Document #: 38-06004 Rev. *E
Page 22 of 23
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CY7C4255, CY7C4265, CY7C4265A
Document History Page
Document Title: CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs
Document Number: 38-06004
Orig. of
Change
Submission
Date
REV.
ECN NO.
Description of Change
**
106465
122257
252889
385985
SZV
RBI
07/11/01
12/26/02
Change from Spec Number: 38-00468 to 38-06004
*A
*B
*C
Power up requirements added to Maximum Ratings Information
YDT
ESH
See ECN Removed PLCC package and pruned parts from Order Information
See ECN Added Pb-Free logo to top of first page
Added CY7C4265-10ASXC, CY7C4265-10AXI, CY7C4265-15AXC,
CY7C4255-10AXC, CY7C4255-15AXC to ordering information
*D
*E
2623658 VKN/PYRS
12/17/08
Added CY7C4265A part
Updated Ordering information table
2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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Document #: 38-06004 Rev. *E
Revised June 03, 2009
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CY7C4265V-15ASCT
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