CY8C21323-24LFXIT [CYPRESS]
PSoC Programmable System-on-Chip; 的PSoC可编程系统级芯片
| 型号： | CY8C21323-24LFXIT |
| 厂家： | 
CYPRESS |
| 描述： | PSoC Programmable System-on-Chip |
| 文件： | 总36页 (文件大小：943K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C21123, CY8C21223, CY8C21323
PSoC® Programmable System-on-Chip™
■
Additional System Resources:
Features
❐
❐
❐
❐
❐
I2C™ Master, Slave and MultiMaster to 400 kHz
Watchdog and Sleep Timers
■
Powerful Harvard Architecture Processor:
❐
❐
❐
❐
M8C Processor Speeds to 24 MHz
Low Power at High Speed
2.4V to 5.25V Operating Voltage
Operating Voltages down to 1.0V using On-Chip Switch
Mode Pump (SMP)
User Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
❐
Industrial Temperature Range: -40°C to +85°C
Logic Block Diagram
■
Advanced Peripherals (PSoC® Blocks):
❐
Port 1 Port 0
Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC Refs
• Single or Dual 8-Bit 8:1 ADC
PSoC
CORE
❐
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
Full Duplex UART, SPI™ Master or Slave: Connectable to All
GPIO Pins
SystemBus
Global Digital Interconnect
❐
❐
Global Analog Interconnect
Flash
SROM
SRAM
Complex Peripherals by Combining Blocks
CPUCore
(M8C)
Sleep and
Watchdog
■
Flexible On-Chip Memory:
Interrupt
Controller
❐
❐
❐
❐
❐
❐
4K Flash Program Storage 50,000 Erase/Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref .
■
Complete Development Tools:
Digital
PSoC Block
Array
Analog
PSoC Block
Array
❐
❐
❐
❐
❐
Free Development Software (PSoC Designer™)
Full Featured, In-Circuit Emulator and Programmer
Full Speed Emulation
Complex Breakpoint Structure
128 Bytes Trace Memory
■
■
Precision, Programmable Clocking:
❐
Internal ±2.5% 24/48 MHz Oscillator
Sw itch
Mode
Pump
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
❐
Internal Oscillator for Watchdog and Sleep
I2C
Programmable Pin Configurations:
SYSTEM RESOURCES
❐
25 mA Sink, 10 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
❐
Up to Eight Analog Inputs on GPIO
Configurable Interrupt on all GPIO
Cypress Semiconductor Corporation
Document Number: 38-12022 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 29, 2009
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
Digital System
PSoC Functional Overview
The Digital System consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral
configurations include:
The PSoC family consists of many programmable
system-on-chip controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
The PSoC architecture, as shown in Figure 1, consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 General Purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
UART 8 bit with selectable parity (up to four)
SPI master and slave
I2C slave, master, MultiMaster (one available as a System
Resource)
■
■
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to four)
PSoC Core
Pseudo Random Sequence Generators (8 to 32 bit)
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 3.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC Programmable
System-on-Chips, I2C functionality for implementing an I2C
master, slave, MultiMaster, an internal voltage reference that
provides an absolute value of 1.3V to a number of PSoC
subsystems, a switch mode pump (SMP) that generates normal
operating voltages off a single battery cell, and various system
resets supported by the M8C.
Figure 1. Digital System Block Diagram
Port1
Port0
ToSystemBus
DigitalClocks
FromCore
ToAnalog
System
The Digital System consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
DIGITAL SYSTEM
DigitalPSoCBlockArray
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
Row 0
4
DBB00
DBB01
DCB02 DCB03
4
8
8
8
8
GlobalDigital
Interconnect
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Document Number: 38-12022 Rev. *K
Page 2 of 36
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Analog System
Additional System Resources
The Analog System consists of four configurable blocks to allow
creation of complex analog signal flows. Analog peripherals are
very flexible and may be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
System Resources, some of which listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. The merits of each
system resource are.
■
Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
■
Pin-to-pin comparators (one)
Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■
■
TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
■
1.3V reference (as a System Resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
■
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
The number of blocks on the device family is listed in Table 1.
Figure 2. CY8C21x23 Analog System Block Diagram
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Array Input
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or
4 analog blocks. Table 1 lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted.
Configuration
Table 1. PSoC Device Characteristics
ACI0[1:0]
ACI1[1:0]
PSoC Part
Number
ACOL1MUX
CY8C29x66
CY8C27x43
CY8C24x94
up to 4
64
16 12
4
4
2
2
0
0
0
4
4
2
2
2
2
0
12 2K
32
K
Array
up to 2
44
8
4
4
4
4
0
12
48
12
28
8
12 256
16
K
Bytes
56
1
6
6
4
4
3
1K
16
K
ACE00
ASE10
ACE01
ASE11
CY8C24x23A up to 1
24
256
Bytes
4K
8K
4K
8K
[1]
[1]
[2]
CY8C21x34
CY8C21x23
CY8C20x34
up to 1
28
512
Bytes
16
1
256
Bytes
up to 0
28
28
512
Bytes
.
Notes
1. Limited analog functionality
2. Two analog blocks and one CapSense™
Document Number: 38-12022 Rev. *K
Page 3 of 36
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Getting Started
Development Tools
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built in support for third party
assemblers and C compilers.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip™
Technical Reference Manual for CY8C28xxx PSoC devices.
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
Application Notes
System-Level View
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication
interfaces. You define when and how an output device changes
state based upon any or all other system devices. Based upon
the design, PSoC Designer automatically selects one or more
PSoC Programmable System-on-Chip Controllers that match
your system requirements.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Training
Chip-Level View
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 38-12022 Rev. *K
Page 4 of 36
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Code Generation Tools
Designing with PSoC Designer
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user selectable functions.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
The PSoC development process can be summarized in the
following four steps:
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write IO registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Online Help System
Configure Components
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 38-12022 Rev. *K
Page 5 of 36
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Organize and Connect
Document Conventions
You can build signal chains at the chip level by interconnecting
user modules to each other and the IO pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
Acronyms Used
This table lists the acronyms used in this data sheet.
Table 2. Acronyms
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
DAC
DC
digital-to-analog converter
direct current
Generate, Verify, and Debug
EEPROM
electrically erasable programmable read-only
memory
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
FSR
GPIO
ICE
full scale range
general purpose IO
in-circuit emulator
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
IDE
integrated development environment
input/output
IO
ISSP
IPOR
LSb
in-system serial programming
imprecise power on reset
least-significant bit
LVD
low voltage detect
MSb
PC
most-significant bit
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
program counter
PGA
POR
PPOR
PSoC®
PWM
ROM
SC
programmable gain amplifier
power on reset
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
precision power on reset
Programmable System-on-Chip™
pulse width modulator
read only memory
switched capacitor
SMP
SRAM
switch mode pump
static random access memory
Units of Measure
A units of measure table is located in the section
Electrical Specifications on page 15. Table 11 on page 15 lists all
the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Document Number: 38-12022 Rev. *K
Page 6 of 36
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Pin Information
This section describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations. Every port pin (labeled with
a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout
Table 3. Pin Definitions - CY8C21123 8-Pin SOIC
Type
Figure 3. CY8C21123 8-Pin SOIC
Pin
No.
Pin
Name
Description
Digital Analog
1
IO
IO
IO
I
I
P0[5] Analog Column Mux Input
A, I, P0[5]
A, I, P0[3]
I2C SCL, P1[1]
1
2
3
8
7
6
Vdd
P0[4], A, I
P0[2], A, I
2
3
4
5
6
7
8
P0[3] Analog Column Mux Input
P1[1] I2C Serial Clock (SCL), ISSP-SCLK[3]
SOIC
Vss
5
P1[0], I2CSDA
4
Power
Power
Vss
Ground Connection
IO
IO
IO
P1[0] I2C Serial Data (SDA), ISSP-SDATA[3]
I
I
P0[2] Analog Column Mux Input
P0[4] Analog Column Mux Input
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
16-Pin Part Pinout
Table 4. Pin Definitions - CY8C21223 16-Pin SOIC
Type
Figure 4. CY8C21223 16-Pin SOIC
Pin
No.
Pin
Description
Name
Digital Analog
A,I,P0[7]
A, I,P0[5]
A, I,P0[3]
A, I,P0[1]
SMP
Vdd
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
IO
IO
IO
IO
I
I
I
I
P0[7] Analog Column Mux Input
P0[5] Analog Column Mux Input
P0[3] Analog Column Mux Input
P0[1] Analog Column Mux Input
P0[6],A,I
P0[4],A,I
P0[2],A,I
P0[0],A,I
P1[4],EXTCLK
P1[2]
2
3
4
5
SOIC
Vss
I2CSCL,P1[1]
Vss
Power
Power
SMP Switch Mode Pump (SMP) Connection to
required External Components
P1[0],I2CSDA
6
Vss
P1[1] I2C Serial Clock (SCL), ISSP-SCLK[3]
Vss Ground Connection
Ground Connection
7
IO
8
Power
9
IO
IO
IO
IO
IO
IO
IO
P1[0] I2C Serial Data (SDA), ISSP-SDATA[3]
10
11
12
13
14
15
16
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P0[0] Analog Column Mux Input
P0[2] Analog Column Mux Input
P0[4] Analog Column Mux Input
P0[6] Analog Column Mux Input
I
I
I
I
Power
Vdd
Supply Voltage
LEGEND A = Analog, I = Input, and O = Output.
Document Number: 38-12022 Rev. *K
Page 7 of 36
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Table 5. Pin Definitions - CY8C21223 16-Pin COL [3]
Type
Figure 5. CY8C21223 16-Pin COL
Pin
No.
Pin
Description
Name
Digital Analog
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
IO
IO
I
I
P0[3]
P0[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
Analog Column Mux Input
Analog Column Mux Input
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
AI, P0[3]
AI, P0[1]
P0[4], VREF
XRES
P1[4]
1
2
3
4
12
11
) 10
9
COL
Top View
(
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[6]
I2C Serial Clock (SCL), ISSP-SCLK[3]
Ground Connection
I2C Serial Data (SDA), ISSP-SDATA[3]
Power
IO
IO
IO
P1[0]
P1[6]
P1[4]
XRES
10
11
EXTCLK
Input
Active High External Reset with Internal
Pull Down
12
13
14
15
16
IO
I
P0[4]
Vdd
VREF
Power
Supply Voltage
IO
IO
I
I
P0[7]
P0[5]
NC
Analog Column Mux Input
Analog Column Mux Input
No Connect
LEGEND A = Analog, I = Input, and O = Output.
Notes
3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12022 Rev. *K
Page 8 of 36
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CY8C21123, CY8C21223, CY8C21323
20-Pin Part Pinout
Table 6. Pin Definitions - CY8C21323 20-Pin SSOP
Type
Figure 6. CY8C21323 20-Pin SSOP
Pin
No.
Pin
Name
Description
Digital Analog
A,I,P0[7]
A, I,P0[5]
A, I,P0[3]
A, I,P0[1]
Vss
Vdd
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Ground Connection
P0[6],A,I
P0[4],A,I
P0[2],A,I
P0[0],A,I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
SSOP
I2C SCL,P1[7]
I2C SDA,P1[5]
P1[3]
I2C SCL,P1[1]
Vss
Power
Power
Input
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
P1[0],I2C SDA
10
I2C Serial Clock (SCL), ISSP-SCLK[3]
Ground connection
I2C Serial Data (SDA), ISSP-SDATA[3]
10
11
12
13
14
15
IO
IO
IO
IO
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK)
Active High External Reset with Internal
Pull Down
16
17
18
19
20
IO
IO
IO
IO
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Supply Voltage
Power
LEGEND A = Analog, I = Input, and O = Output.
Document Number: 38-12022 Rev. *K
Page 9 of 36
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CY8C21123, CY8C21223, CY8C21323
24-Pin Part Pinout
Table 7. Pin Definitions - CY8C21323 24-Pin QFN[5]
Type
Figure 7. CY8C21323 24-Pin QFN
Pin
No.
Pin
Name
Description
Digital Analog
1
2
IO
I
P0[1]
SMP
Analog Column Mux Input
Power
Power
Switch Mode Pump (SMP) Connection to
required External Components
3
4
5
6
7
8
9
Vss
Ground connection
A, I, P0[1]
SMP
18
17
16
15
14
13
P0[4], A, I
P0[2], A, I
1
2
3
4
5
6
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
NC
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Vss
QFN
(Top View)
P0[0], A, I
NC
XRES
P1[6]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C Serial Clock (SCL), ISSP-SCLK[3]
No Connection
Power
Input
Vss
Ground Connection
I2C Serial Data (SDA), ISSP-SDATA[3]
10
11
12
13
14
IO
IO
IO
IO
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK)
Active High External Reset with Internal
Pull Down
15
16
17
18
19
20
21
22
23
24
NC
No Connection
IO
IO
IO
IO
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Supply Voltage
Power
Power
Vss
Ground Connection
IO
IO
IO
I
I
I
P0[7]
P0[5]
P0[3]
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
LEGEND A = Analog, I = Input, and O = Output.
Note
5. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12022 Rev. *K
Page 10 of 36
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CY8C21123, CY8C21223, CY8C21323
Register Mapping Tables
Register Reference
The PSoC device has a total register address space of
512 bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
This section lists the registers of the CY8C21x23 PSoC device.
For detailed register information, refer the PSoC Programmable
System-on-Chip Technical Reference Manual.
Register Conventions
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
The register conventions specific to this section are listed in the
following table.
Table 8. Register Conventions
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 38-12022 Rev. *K
Page 11 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 9. Register Map Bank 0 Table: User Space
Addr
Addr
Addr
Addr
Name
PRT0DR
Access
Name
Access
Name
ASE10CR0
Access
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
(0,Hex)
00
RW
RW
RW
RW
RW
RW
RW
RW
40
80
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
PRT0IE
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
ASE11CR0
RW
PRT1GS
PRT1DM2
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
I2C_CFG
RW
#
I2C_SCR
I2C_DR
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
RW
RW
#
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RC
W
W
RW
#
PWM_CR
CMP_CR0
CMP_CR1
RES_WDT
#
W
RW
#
RW
DEC_CR0
DEC_CR1
RW
RW
#
ADC0_CR
ADC1_CR
#
#
W
RW
#
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
W
RW
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12022 Rev. *K
Page 12 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 9. Register Map Bank 0 Table: User Space (continued)
Addr
Addr
Addr
Addr
Name
Access
Name
Access
Name
RDI0RI
Access
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
(0,Hex)
30
70
B0
RW
RW
RW
RW
RW
RW
RW
F0
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RDI0SYN
RDI0IS
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 10. Register Map Bank 1 Table: Configuration Space
Addr
Addr
Addr
(1,Hex)
Addr
Name
PRT0DM0
Access
Name
Access
Name
Access
Name
Access
(1,Hex)
(1,Hex)
(1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
00
RW
RW
RW
RW
RW
RW
RW
RW
40
ASE10CR0
80
RW
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
ASE11CR0
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12022 Rev. *K
Page 13 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 10. Register Map Bank 1 Table: Configuration Space (continued)
Addr
(1,Hex)
Addr
(1,Hex)
Addr
(1,Hex)
Addr
(1,Hex)
Name
Access
Name
Access
Name
Access
Name
Access
1C
5C
9C
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
DBB00FN
RW
RW
RW
CLK_CR0
RW
RW
RW
RW
RW
DBB00IN
CLK_CR1
DBB00OU
ABF_CR0
AMD_CR0
CMP_GO_EN
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
ADC0_TR
ADC1_TR
RW
RW
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
CLK_CR3
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
FLS_PR1
RW
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12022 Rev. *K
Page 14 of 36
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CY8C21123, CY8C21223, CY8C21323
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For up to date electrical specifications,
check if you have the latest data sheet by visiting the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 85oC and T ≤ 100oC, except where noted.
A
J
Refer to Table 25 on page 25 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 11. Voltage versus IMO Frequency
Figure 10. Voltage versus CPU Frequency
5.25
4.75
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
O
V
p
a
e
l
R
i
r
d
a
e
t
g
i
n
i
o
g
n
3.60
3.00
2.40
SLIMO
Mode=1
SLIMO SLIMO
Mode=1 Mode=1
SLIMO
Mode=0
3.00
2.40
93kHz
12MHz
CPUFrequency
24MHz
93kHz
6MHz
IMOFrequency
3MHz
12MHz
24MHz
The following table lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
oC
dB
fF
degree Celsius
decibels
μW
mA
ms
mV
nA
ns
microwatts
milli-ampere
milli-second
milli-volts
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
kilohertz
nV
W
kilohm
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
pA
pF
pp
picoampere
picofarad
peak-to-peak
parts per million
picosecond
ppm
ps
sps
s
samples per second
sigma: one standard deviation
volts
microvolts root-mean-square
V
Document Number: 38-12022 Rev. *K
Page 15 of 36
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CY8C21123, CY8C21223, CY8C21323
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 12. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
Typ
Max
Units
Notes
TSTG
-55
–
+100
°C
Higher storage temperatures
reduce data retention time.
Recommended storage temper-
ature is +25°C ± 25°C. Extended
duration storage temperatures
above 65°C degrade reliability.
TA
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
–
–
–
–
–
–
–
+85
+6.0
°C
V
Vdd
VIO
VIOZ
IMIO
ESD
LU
Vss - 0.5
Vss - 0.5
-25
Vdd + 0.5
Vdd + 0.5
+50
V
DC Voltage Applied to Tristate
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch up Current
V
mA
V
2000
–
–
Human Body Model ESD
200
mA
Operating Temperature
Table 13. Operating Temperature
Symbol
Description
Min
-40
-40
Typ
–
Max
+85
Units
°C
Notes
TA
TJ
Ambient Temperature
Junction Temperature
–
+100
°C
The temperature rise from
ambient to junction is package
specific. SeeTable 37 on page
34. The user must limit the power
consumption to comply with this
requirement.
Document Number: 38-12022 Rev. *K
Page 16 of 36
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
DC Electrical Characteristics
DC Chip-Level Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 14. DC Chip-Level Specifications
Symbol
Description
Supply Voltage
Min
Typ
Max
Units
Notes
Vdd
2.40
–
5.25
V
See DC POR and LVD specifica-
tions, Table 21 on page 21.
IDD
Supply Current, IMO = 24 MHz
Supply Current, IMO = 6 MHz
Supply Current, IMO = 6 MHz
–
–
–
3
4
mA Conditions are Vdd = 5.0V, 25oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 0.366 kHz.
IDD3
1.2
1.1
2
mA Conditions are Vdd = 3.3V, 25oC,
CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
IDD27
1.5
mA Conditions are Vdd = 2.55V,
25oC, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
ISB27
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active. Mid temperature range.
–
–
2.6
2.8
4
5
μA Vdd = 2.55V, 0°C to 40°C
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
μA Vdd = 3.3V, -40°C ≤ TA ≤ 85°C
VREF
Reference Voltage (Bandgap)
1.28
1.16
1.30
1.30
1.32
V
V
V
Trimmed for appropriate Vdd.
Vdd = 3.0V to 5.25V
VREF27 Reference Voltage (Bandgap)
AGND Analog Ground
1.330
Trimmed for appropriate Vdd.
Vdd = 2.4V to 3.0V
VREF - 0.003 VREF VREF+ 0.003
Document Number: 38-12022 Rev. *K
Page 17 of 36
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CY8C21123, CY8C21223, CY8C21323
DC General Purpose IO Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 15. 5V and 3.3V DC GPIO Specifications
Symbol
RPU
Description
Min
4
Typ
5.6
5.6
–
Max
Units
kΩ
Notes
Pull up Resistor
8
8
–
RPD
Pull down Resistor
High Output Level
4
kΩ
VOH
Vdd -
1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
0.8
V
IOL=25mA, Vdd=4.75to5.25V (8total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
150 mA maximum combined IOL
budget.
VIL
VIH
VH
IIL
Input Low Level
–
2.1
–
–
–
V
V
Vdd = 3.0 to 5.25
Vdd = 3.0 to 5.25
Input High Level
Input Hysteresis
60
1
–
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
nA Gross tested to 1 μA
CIN
–
3.5
10
pF Package and pin dependent.
Temp = 25°C
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF Package and pin dependent.
Temp = 25°C
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C
≤ TA ≤ 85°C. Typical parameters apply to 2.7V at 25°C and are for design guidance only.
Table 16. 2.7V DC GPIO Specifications
Symbol
RPU
Description
Min
4
Typ
5.6
5.6
–
Max
Units
kΩ
kΩ
Notes
Pull up Resistor
8
8
–
RPD
Pull down Resistor
High Output Level
4
VOH
Vdd -
0.4
V
IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to
3.0V (16 mA maximum, 50 mA Typ
combined IOH budget).
VOL
Low Output Level
–
–
0.75
V
IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA
maximum combined IOL budget).
VIL
VIH
VH
IIL
Input Low Level
–
2.0
–
–
–
0.75
–
V
V
Vdd = 2.4 to 3.0
Vdd = 2.4 to 3.0
Input High Level
Input Hysteresis
60
1
–
mV
nA
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
–
Gross tested to 1 μA
Package and pin dependent.
Temp = 25°C
CIN
–
3.5
10
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
Document Number: 38-12022 Rev. *K
Page 18 of 36
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CY8C21123, CY8C21223, CY8C21323
DC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 17. 5V DC Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
μV/oC
Notes
VOSOA
Input Offset Voltage (absolute value)
TCVOSOA Average Input Offset Voltage Drift
–
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
200
4.5
–
pA
Gross tested to 1 μA
–
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.0
–
Vdd - 1
V
GOLOA
ISOA
Open Loop Gain
80
–
–
–
dB
Amplifier Supply Current
10
30
μA
Table 18. 3.3V DC Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
μV/oC
Notes
VOSOA
Input Offset Voltage (absolute value)
TCVOSOA Average Input Offset Voltage Drift
–
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
200
4.5
–
pA
Gross tested to 1 μA
–
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
GOLOA
ISOA
Common Mode Voltage Range
Open Loop Gain
0
80
–
–
–
Vdd - 1
V
–
dB
μA
Amplifier Supply Current
10
30
Table 19. 2.7V DC Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
μV/oC
Notes
VOSOA
Input Offset Voltage (absolute value)
TCVOSOA Average Input Offset Voltage Drift
–
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
200
4.5
–
pA
Gross tested to 1 μA
–
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
GOLOA
ISOA
Common Mode Voltage Range
Open Loop Gain
0
80
–
–
–
Vdd - 1
V
–
dB
μA
Amplifier Supply Current
10
30
Document Number: 38-12022 Rev. *K
Page 19 of 36
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DC Switch Mode Pump Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 20. DC Switch Mode Pump (SMP) Specifications
Symbol
VPUMP5V
Description
Min
Typ
Max Units
Notes
5V Output Voltage from Pump
4.75
5.0
5.25
3.60
2.80
V
V
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set
to 5.0V.
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set
to 3.25V.
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set
to 2.55V.
Configuration of footnote.[6]
VPUMP3V
VPUMP2V
IPUMP
3.3V Output Voltage from Pump
2.6V Output Voltage from Pump
3.00
2.45
3.25
2.55
Available Output Current
VBAT = 1.8V, VPUMP = 5.0V
5
8
8
–
–
–
–
–
–
mA SMP trip voltage is set to 5.0V.
mA SMP trip voltage is set to 3.25V.
mA SMP trip voltage is set to 2.55V.
V
V
BAT = 1.5V, VPUMP = 3.25V
BAT = 1.3V, VPUMP = 2.55V
VBAT5V
Input Voltage Range from Battery
Input Voltage Range from Battery
Input Voltage Range from Battery
1.8
1.0
1.0
1.2
–
–
–
–
–
5
5.0
3.3
2.8
–
V
V
V
V
Configuration of footnote.[6] SMP trip
voltage is set to 5.0V.
Configuration of footnote.[6] SMP trip
voltage is set to 3.25V.
Configuration of footnote.[6] SMP trip
voltage is set to 2.55V.
VBAT3V
VBAT2V
VBATSTART
ΔVPUMP_Line
Minimum Input Voltage from Battery to
Start Pump
Configuration of footnote.[6] 0°C ≤ TA ≤
100. 1.25V at TA = -40oC.
Line Regulation (over Vi range)
–
%VO Configuration of footnote.[6] VO is the
“Vdd Value for PUMP Trip” specified by
the VM[2:0] setting in the DC POR and
LVD Specification, Table 21 on page 21.
ΔVPUMP_Load Load Regulation
–
5
–
%VO Configuration of footnote.[6] VO is the
“Vdd Value for PUMP Trip” specified by
the VM[2:0] setting in the DC POR and
LVD Specification, Table 21 on page 21.
ΔVPUMP_Ripple Output Voltage Ripple (depends on
–
100
50
–
–
–
mVpp Configuration of footnote.[6] Load is
5 mA.
cap/load)
E3
E2
Efficiency
Efficiency
35
35
%
Configuration of footnote.[6] Load is
5 mA. SMP trip voltage is set to 3.25V.
80
%
For I load = 1mA, VPUMP = 2.55V,
V
BAT = 1.3V, 10 uH inductor, 1 uF
capacitor, and Schottky diode.
FPUMP
Switching Frequency
Switching Duty Cycle
–
–
1.3
50
–
–
MHz
%
DCPUMP
Note
6.
L = 2 mH inductor, C = 10 mF capacitor, D = Schottky diode. See Figure 12 on page 21.
1 1 1
Document Number: 38-12022 Rev. *K
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Figure 12. Basic Switch Mode Pump Circuit
D1
Vdd
VPUMP
L1
C1
SMP
V ss
+
VBAT
PSoC
Battery
DC POR and LVD Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 21. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Vdd must be greater than or equal to
2.5V during startup, reset from the
XRES pin, or reset from Watchdog.
VPPOR0
VPPOR1
VPPOR2
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
–
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62[9]
3.09
V
V
V
V
V
V
V
V
3.16
3.32[10]
4.74
4.83
4.92
5.12
Notes
7. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
9. Always greater than 50 mV above VLVD0.
10. Always greater than 50 mV above VLVD3.
Document Number: 38-12022 Rev. *K
Page 21 of 36
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DC Programming Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 22. DC Programming Specifications
Symbol
Description
Min
2.70
–
Typ
–
Max
–
Units
V
Notes
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
VILP
Supply Current During Programming or Verify
5
25
mA
V
Input Low Voltage During Programming or
Verify
–
–
0.8
VIHP
IILP
Input High Voltage During Programming or
Verify
2.2
–
–
–
–
–
–
–
0.2
V
mA
mA
V
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
–
Driving internal pull down
resistor
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
–
1.5
Driving internal pull down
resistor
VOLV
VOHV
Output Low Voltage During Programming or
Verify
Vss + 0.75
Vdd
Output High Voltage During Programming or
Verify
Vdd - 1.0
50,000
V
FlashENPB Flash Endurance (per block)
–
–
Erase/write cycles per
block
0
0
0
FlashENT
FlashDR
Flash Endurance (total)[11]
Flash Data Retention
1,800,000
–
–
–
Erase/write cycles
0
10
–
–
Years
Note
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no
single block ever sees more than 50,000 cycles).For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the
result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more
information.
Document Number: 38-12022 Rev. *K
Page 22 of 36
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AC Electrical Characteristics
AC Chip-Level Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 23. 5V and 3.3V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
24.6[12,13,14]
FIMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
MHz Trimmed for 5V or 3.3V
operation using factory trim
values. See Figure 11 on
page 15.
SLIMO mode = 0.
6.35[12,13,14]
FIMO6
Internal Main Oscillator Frequency for 6 MHz
CPU Frequency (5V Nominal)
5.75
0.93
6
MHz Trimmed for 3.3V operation
using factory trim values. See
Figure 11 on page 15. SLIMO
mode = 1.
24.6[12,13]
FCPU1
24
MHz 24 MHz only for
SLIMO mode = 0.
,
14]
12.3[13
FCPU2
FBLK5
CPU Frequency (3.3V Nominal)
0.93
0
12
48
MHz
Digital PSoC Block Frequency0(5V Nominal)
MHz Refer to the AC Digital Block
Specifications.
49.2[12,13,15]
24.6[13,15]
FBLK33
Digital PSoC Block Frequency (3.3V Nominal)
0
24
MHz
F32K1
Internal Low Speed Oscillator Frequency
32 kHz RMS Period Jitter
15
–
32
100
1400
–
64
200
–
kHz
ns
Jitter32k
Jitter32k
TXRST
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
–
ns
10
40
–
–
μs
DC24M
Step24M
Fout48M
50
60
–
%
24 MHz Trim Step Size
50
kHz
49.2[12,14]
48 MHz Output Frequency
46.8
48.0
MHz Trimmed. Using factory trim
values.
Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO)
–
–
300
–
ps
FMAX
Maximum frequency of signal on row input or
row output.
12.3
–
MHz
TRAMP
Supply Ramp Time
0
–
μs
Notes
12. 4.75V < Vdd < 5.25V.
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. 3.0V < Vdd < 3.6V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
15. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12022 Rev. *K
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Table 24. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
12.7[16,17,18]
FIMO12
Internal Main Oscillator Frequency for 12 MHz 11.5
120
MHz Trimmed for 2.7V operation using
factory trim values. See Figure 11
on page 15. SLIMO mode = 1.
6.35[16,17,18]
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.5
6
MHz Trimmed for 2.7V operation using
factory trim values. See Figure 11
on page 15. SLIMO mode = 1.
3.15[16,17]
FCPU1
FBLK27
CPU Frequency (2.7V Nominal)
0.093
0
3
MHz 24 MHz only for SLIMO mode = 0.
12.5[16,17,18]
Digital PSoC Block Frequency (2.7V Nominal)
12
MHz Refer to the AC Digital Block
Specifications.
F32K1
Internal Low Speed Oscillator Frequency
8
–
32
150
1400
–
96
200
–
kHz
ns
Jitter32k 32 kHz RMS Period Jitter
Jitter32k 32 kHz Peak-to-Peak Period Jitter
–
ns
TXRST
FMAX
External Reset Pulse Width
10
–
–
μs
Maximum frequency of signal on row input or
row output
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Figure 13. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 14. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
Notes
16. 2.4V < Vdd < 3.0V.
17. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
18. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.
Document Number: 38-12022 Rev. *K
Page 24 of 36
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AC General Purpose IO Specifications
Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 25. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
12
18
18
–
Units
Notes
GPIO Operating Frequency
MHz Normal Strong Mode
TRiseF
TFallF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
2
–
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
TRiseS
TFallS
10
10
27
22
–
Table 26. 2.7V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
3
Units
Notes
GPIO Operating Frequency
MHz Normal Strong Mode
TRiseF
TFallF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
6
–
50
ns
ns
ns
ns
Vdd = 2.4 to 3.0V, 10% - 90%
6
–
50
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
TRiseS
TFallS
18
18
40
40
120
120
Figure 15. GPIO Timing Diagram
90%
GPIO
Pin
10%
TRiseF
TRi seS
TFallF
TFallS
AC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 27. 5V and 3.3V AC Amplifier Specifications
Symbol
TCOMP1
TCOMP2
Description
Min
Typ
Typ
Max
100
300
Units
ns
Comparator Mode Response Time, 50 mVpp Signal Centered on Ref
Comparator Mode Response Time, 2.5V Input, 0.5V Overdrive
ns
Table 28. 2.7V AC Amplifier Specifications
Symbol
TCOMP1
TCOMP2
Description
Min
Max
600
300
Units
ns
Comparator Mode Response Time, 50 mVpp Signal Centered on Ref
Comparator Mode Response Time, 1.5V Input, 0.5V Overdrive
ns
Document Number: 38-12022 Rev. *K
Page 25 of 36
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AC Digital Block Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 29. 5V and 3.3V AC Digital Block Specifications
Function
All
Functions
Description
Maximum Block Clocking Frequency (> 4.75V)
Maximum Block Clocking Frequency (< 4.75V)
Capture Pulse Width
Min
Typ
Max Units
Notes
49.2
24.6
–
MHz 4.75V < Vdd < 5.25V
MHz 3.0V < Vdd < 4.75V
Timer
50[19]
–
–
–
–
–
–
ns
Maximum Frequency, No Capture
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
–
49.2
24.6
–
MHz 4.75V < Vdd < 5.25V
MHz
Counter
50
–
ns
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
49.2
24.6
MHz 4.75V < Vdd < 5.25V
MHz
–
Dead Band
Asynchronous Restart Mode
Synchronous Restart Mode
20
50
50
–
–
–
–
–
–
–
–
ns
ns
Disable Mode
–
ns
Maximum Frequency
49.2
49.2
MHz 4.75V < Vdd < 5.25V
MHz 4.75V < Vdd < 5.25V
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
24.6
8.2
MHz
SPIM
SPIS
MHz Maximum data rate at 4.1 MHz due
to 2 x over clocking
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmissions 50
Transmitter
Receiver
Maximum Input Clock Frequency
–
24.6
MHz Maximum data rate at 3.08 MHz due
to 8 x over clocking
Maximum Input Clock Frequency
–
–
24.6
MHz Maximum data rate at 3.08 MHz due
to 8 x over clocking
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. *K
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Table 30. 2.7V AC Digital Block Specifications
Function
All
Description
Min
Typ
Max Units
Notes
Maximum Block Clocking Frequency
12.7
MHz 2.4V < Vdd < 3.0V
Functions
Timer
Capture Pulse Width
100[20]
–
–
–
–
–
–
ns
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
100
–
12.7
–
MHz
ns
Counter
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
12.7
12.7
MHz
MHz
–
Dead Band
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
100
100
–
–
–
–
–
–
–
–
ns
ns
–
ns
Maximum Frequency
12.7
12.7
MHz
MHz
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
12.7
6.35
MHz
SPIM
SPIS
MHz Maximum data rate at 3.17 MHz
due to 2 x over clocking
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmis-
sions
100
Transmitter
Receiver
Maximum Input Clock Frequency
–
–
–
–
12.7
12.7
MHz Maximum data rate at 1.59 MHz
due to 8 x over clocking
Maximum Input Clock Frequency
MHz Maximum data rate at 1.59 MHz
due to 8 x over clocking
Note
20. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. *K
Page 27 of 36
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CY8C21123, CY8C21223, CY8C21323
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C
and are for design guidance only.
Table 31. 5V AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
20.6
150
Typ
–
Max
24.6
5300
–
Units
MHz
ns
Notes
FOSCEXT Frequency
–
–
–
High Period
Low Period
–
–
ns
Power Up IMO to Switch
–
–
μs
Table 32. 3.3V AC External Clock Specifications
Symbol Description
Min
Typ
Max
Units
Notes
FOSCEXT Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz Maximum CPU frequency is 12 MHz
at 3.3V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
FOSCEXT Frequency with CPU Clock divide by 2 or
greater
0.186
–
24.6
MHz If the frequency of the external clock
isgreaterthan12MHz, theCPUclock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
41.7
41.7
150
–
–
–
5300
ns
ns
μs
–
–
Table 33. 2.7V AC External Clock Specifications
Symbol Description
Min
Typ
Max
Units
Notes
FOSCEXT Frequency with CPU Clock divide by 1
0.093
–
6.060
MHz Maximum CPU frequency is 3 MHz at
2.7V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
FOSCEXT Frequency with CPU Clock divide by 2 or
greater
0.186
–
12.12
MHz If the frequency of the external clock
is greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
83.4
83.4
150
–
–
–
5300
ns
ns
μs
–
–
Document Number: 38-12022 Rev. *K
Page 28 of 36
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CY8C21123, CY8C21223, CY8C21323
AC Programming Specifications
Table 34 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 34. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
Description
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
Rise Time of SCLK
Fall Time of SCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB
TWRITE
TDSCLK3
TDSCLK2
Flash Erase Time (Block)
–
15
30
–
–
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
–
50
70
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
–
–
ns
AC I2C Specifications
Table 35 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 35. AC Characteristics of the I2C SDA and SCL Pins for Vcc ≥ 3.0V
Standard Mode
Fast Mode
Symbol
Description
Units
Min
Max
Min
Max
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
2500
4.0
4.7
–
–
–
–
–
1.3
0.6
0.6
0
100[20]
0.6
–
–
–
–
μs
μs
μs
μs
ns0
μs
μs
ns
TSUSTAI2C Setup Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Setup Time0
0
0
–
–
TSUSTOI2C Setup Time for STOP Condition
–
–
–
–
–
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
1.3
0
50
Note
20. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This automatically becomes
SU;DAT
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SU;DAT
Document Number: 38-12022 Rev. *K
Page 29 of 36
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CY8C21123, CY8C21223, CY8C21323
Table 36. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode Not Supported)
Standard Mode
Fast Mode
Min Max
Symbol
Description
Units
Min
Max
FSCLI2C
SCL Clock Frequency
0
100
–
–
kHz
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
4.0
–
–
–
μs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
ns
TSUSTAI2C Setup Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Setup Time
250
4.0
4.7
–
TSUSTOI2C Setup Time for STOP Condition
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
TLOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Document Number: 38-12022 Rev. *K
Page 30 of 36
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CY8C21123, CY8C21223, CY8C21323
Packaging Information
This section illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each
package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 17. 8-Pin (150-Mil) SOIC
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066 *C
Document Number: 38-12022 Rev. *K
Page 31 of 36
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CY8C21123, CY8C21223, CY8C21323
Figure 18. 16-Pin (150-Mil) SOIC
51-85022 *B
Figure 19. 16-Pin COL
001-09116 *D
Document Number: 38-12022 Rev. *K
Page 32 of 36
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CY8C21123, CY8C21223, CY8C21323
Figure 20. 20-Pin (210-MIL) SSOP
51-85077 *C
Figure 21. 24-Pin (4x4) QFN
SIDE VIEW
TOP VIEW
BOTTOM VIEW
0.05
C
3.90
4.10
1.00 MAX.
0.80 MAX.
0.23±0.05
0.05 MAX.
0.20 REF.
3.70
3.80
2.49
PIN1 ID
0.20 R.
Ø0.50
N
N
1
2
1
2
0.45
SOLDERABLE
EXPOSED
PAD
2.45
2.55
2.49
0.30-0.50
0.42±0.18
(4X)
0°-12°
0.50
C
2.45
2.55
SEATING
PLANE
NOTES:
1.
HATCH IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.042g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LF24A
LY24A
STANDARD
LEAD FREE
51-85203 *A
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Document Number: 38-12022 Rev. *K
Page 33 of 36
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CY8C21123, CY8C21223, CY8C21323
Thermal Impedances
Table 37. Thermal Impedances per Package
[21]
Package
Typical θJA
8 SOIC
186°C/W
125°C/W
46°C/W
117°C/W
40°C/W
16 SOIC
16 COL
20 SSOP
24 QFN[22]
Solder Reflow Peak Temperature
Table 38 lists the minimum solder reflow peak temperature to achieve good solderability.
Table 38. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[23]
Maximum Peak Temperature
260°C
8 SOIC
240°C
240°C
240°C
240°C
240°C
16 SOIC
16 COL
20 SSOP
24 QFN
260°C
260°C
260°C
260°C
Notes
21. T = T + POWER x θJA
J
A
22. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5°C with Sn-Pb or 245+/-5°C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12022 Rev. *K
Page 34 of 36
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CY8C21123, CY8C21223, CY8C21323
Ordering Information
The following table lists the CY8C21x23 PSoC device’s key package features and ordering codes.
Table 39. CY8C21x23 PSoC Device Key Features and Ordering Information
8-Pin (150-Mil) SOIC
CY8C21123-24SXI
CY8C21123-24SXIT
4K
4K
4K
4K
4K
4K
4K
4K
4K
256
256
256
256
256
256
256
256
256
No
No
-40°C to
+85°C
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
4
4
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
No
No
8-Pin (150-Mil) SOIC
(Tape and Reel)
-40°C to
+85°C
6
16-Pin (150-Mil) SOIC CY8C21223-24SXI
Yes
Yes
Yes
No
-40°C to
+85°C
12
12
12
16
16
16
16
No
16-Pin (150-Mil) SOIC CY8C21223-24SXIT
(Tape and Reel)
-40°C to
+85°C
No
16-Pin (3x3) COL
CY8C21223-24LGXI
-40°C to
+85°C
No
20-Pin (210-Mil) SSOP CY8C21323-24PVXI
-40°C to
+85°C
Yes
Yes
Yes
Yes
20-Pin (210-Mil) SSOP CY8C21323-24PVXIT
(Tape and Reel)
No
-40°C to
+85°C
24-Pin (4x4) QFN
CY8C21323-24LFXI
Yes
Yes
-40°C to
+85°C
24-Pin (4x4) QFN
(Tape and Reel)
CY8C21323-24LFXIT
-40°C to
+85°C
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12022 Rev. *K
Page 35 of 36
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CY8C21123, CY8C21223, CY8C21323
Document History Page
Document Title: CY8C21123, CY8C21223, CY8C21323 PSoC® Programmable System-on-Chip™
Document Number:38-12022
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
133248
208900
212081
227321
235973
NWJ
NWJ
NWJ
CMS Team
SFV
See ECN
See ECN
See ECN
See ECN
See ECN
New silicon and document (Revision **).
Add new part, new package and update all ordering codes to Pb-free.
Expand and prepare Preliminary version.
Update specs., data, format.
Updated Overview and Electrical Spec. chapters, along with 24-pin pinout.
Added CMP_GO_EN register (1,64h) to mapping table.
*A
*B
*C
*D
*E
290991
HMT
See ECN
Update data sheet standards per SFV memo. Fix device table. Add part numbers
to pinouts and fine tune. Change 20-pin SSOP to CY8C21323. Add Reflow Temp.
table. Update diagrams and specs.
*F
*G
301636
324073
HMT
HMT
See ECN
See ECN
DC Chip-Level Specification changes. Update links to new CY.com Portal.
Obtained clearer 16 SOIC package. Update Thermal Impedances and Solder
Reflow tables. Re-add pinout ISSP notation. Fix ADC type-o. Fix TMP register
names. Update Electrical Specifications. Add CY logo. Update CY copyright.
Make data sheet Final.
*H
*I
2588457 KET/HMI/
AESA
2618175 OGNE/PYRS 12/09/08
10/22/2008 New package information on page 9. Converted data sheet to new template.
Added 16-Pin OFN package diagram.
Added Note in Ordering Information Section. Changed title from PSoC
Mixed-Signal Array to PSoC Programmable System-on-Chip. Updated ‘Devel-
opment Tools’ and ‘Designing with PSoC Designer’ sections on pages 5 and 6
*J
*K
2682782 MAXK/AESA 04/03/2009 Corrected 16 COL pinout.
2699713 MAXK 04/29/09 Minor ECN to correct paragraph style of 16 COL Pinout. No change in content.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12022 Rev. *K
Revised April 29, 2009
Page 36 of 36
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
2
2
herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights
2
2
to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
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