CYBLE-212019-00 [CYPRESS]
Telecom Circuit,;型号: | CYBLE-212019-00 |
厂家: | CYPRESS |
描述: | Telecom Circuit, 电信 电信集成电路 |
文件: | 总39页 (文件大小:972K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CYBLE-212019-00
CYBLE-212023-10
EZ-BLE™ PRoC™ Module
EZ-BLE™ PRoC™ Module
■ Low power mode support
General Description
❐ Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on
The CYBLE-2120XX-X0 is a Bluetooth Low Energy (BLE)
wireless module solution. The CYBLE-2120XX-X0 is a turnkey
solution and includes onboard crystal oscillators, trace antenna,
passive components, and the Cypress PRoC™ BLE. Refer to
the CYBL10XX7X datasheet for additional details on the
capabilities of the PRoC BLE device used on this module.
❐ Hibernate: 150 nA with SRAM retention
❐ Stop: 60 nA with GPIO (P2.2) or XRES wakeup
Functional Capabilities
■ Up to 22 capacitive sensors for buttons or sliders with
best-in-class signal-to-noise ration (SNR) and liquid tolerance
The CYBLE-2120XX-X0 supports a number of peripheral
functions (ADC, timers, counters, PWM) and serial
communication protocols (I2C, UART, SPI) through its
programmable architecture. The CYBLE-212019-00 includes a
royalty-free BLE stack compatible with Bluetooth 4.1 and
provides up to 23 GPIOs in a 14.52 × 19.20 × 2.00 mm package.
■ 12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■ Two serial communication blocks (SCBs) supporting I2C
(master/slave), SPI (master/slave), or UART
■ Four dedicated 16-bit timer, counter, or PWM blocks
(TCPWMs)
The CYBLE-2120XX-X0 is available in a fully certified and
qualified version (CYBLE-212019-00), and an uncertified
version (CYBLE-212023-10). The CYBLE-212023-10 does not
include an RF shield and is not certified by Bluetooth SIG or
regulatory agencies. The CYBLE-2120XX-X0 is drop-in
compatible with the CYBLE-0120XX-00 EZ-BLE PRoC Module.
■ LCD drive supported on all GPIOs (common or segment)
■ Programmable low voltage detect (LVD) from 1.8 V to 4.5 V
■ I2S master interface
The CYBLE-2120XX-X0 is a complete solution targeted at
applications requiring cost optimized BLE wireless connectivity.
■ Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or
Broadcaster roles
Module Description
■ Switches between Central and Peripheral roles on-the-go
■ Module size: 14.52 mm × 19.20 mm × 2.00 mm (with shield)
■ Castelated solder pad connections for ease-of-use
■ 256-KB flash memory, 32-KB SRAM memory
■ Standard Bluetooth Low Energy profiles and services for
interoperability
■ Custom profile and service for specific use cases
■ Up to 23 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output
Benefits
■ Bluetooth 4.1 single-mode module (CYBLE-212019-00 only)
❐ QDID: 81503
❐ Declaration ID: D030315
The CYBLE-2120XX-X0 module is provided as a turnkey
solution, including all necessary hardware required to use BLE
communication standards.
■ Certified to FCC, IC, MIC, KC, and CE regulations
■ Industrial temperature range: –40 °C to +85 °C
■ Proven hardware design ready to use
■ Cost optimized for applications without space constraint
■ Reprogrammable architecture
■ 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
■ Fully certified module eliminates the time needed for design,
development and certification processes
■ Watchdog timer with dedicated internal low-speed oscillator
(ILO)
■ Bluetooth SIG qualified with QDID and Declaration ID
■ Flexible communication protocol support
■ Two-pin SWD for programming
Power Consumption
■ PSoC Creator™ provides an easy-to-use integrated design
environment (IDE) to configure, develop, program, and test a
BLE application
■ TX output power: –18 dbm to +3 dbm
■ Received signal strength indicator (RSSI) with 1-dB resolution
■ TX current consumption of 15.6 mA (radio only, 0 dbm)
■ RX current consumption of 16.4 mA (radio only)
Cypress Semiconductor Corporation
Document Number: 002-09764 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 22, 2017
CYBLE-212019-00
CYBLE-212023-10
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
■ Overview: EZ-BLE Module Portfolio, Module Roadmap
■ EZ-BLE PRoC Product Overview
■ Knowledge Base Articles
❐ KBA10896 - Pin Mapping Differences Between the
EZ-BLE™ PRoC™ Evaluation Board
(CYBLE-212019-EVAL) and the BLE Pioneer Kit
(CY8CKIT-042-BLE) - KBA10896
❐ KBA210638 - RF Regulatory Certifications for
CYBLE-012011-00 and CYBLE-212019-00 EZ-BLE™
PRoC® Modules - KBA210638
■ PRoC BLE Silicon Datasheet
■ Application notes: Cypress offers a number of BLE application
notes covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started with
EZ-BLE modules are:
❐ KBA97095 - EZ-BLE™ Module Placement
❐ KBA213976 -FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
❐ KBA210802 - Queries on BLE Qualification and Declaration
Processes
❐ AN96841 - Getting Started with EZ-BLE Module
❐ AN94020 - Getting Started with PRoC BLE
❐ AN97060 - PSoC® 4 BLE and PRoC™ BLE - Over-The-Air
(OTA) Device Firmware Upgrade (DFU) Guide
❐ AN91162 - Creating a BLE Custom Profile
❐ AN91184 - PSoC 4 BLE - Designing BLE Applications
■ Development Kits:
❐ AN92584 - Designing for Low Power and Estimating Battery
❐ CYBLE-212019-EVAL, CYBLE-2120XX-X0 Evaluation
Life for BLE Applications
Board
❐ AN85951 - PSoC® 4 CapSense® Design Guide
❐ CY8CKIT-042-BLE, Bluetooth® Low Energy (BLE) Pioneer
❐ AN95089 - PSoC® 4/PRoC™ BLE Crystal Oscillator Selec-
Kit
❐ CY8CKIT-002, PSoC® MiniProg3 Program and Debug Kit
tion and Tuning Techniques
❐ AN91445 - Antenna Design and RF Layout Guidelines
■ Technical Reference Manual (TRM):
❐ PRoC® BLE Technical Reference Manual
■ Test and Debug Tools:
❐ CYSmart, Bluetooth® LE Test and Debug Tool (Windows)
❐ CYSmart Mobile, Bluetooth® LE Test and Debug Tool
(Android/iOS Mobile App)
Two Easy-To-Use Design Environments to Get You Started Quickly
®
PSoC Creator™ Integrated Design Environment (IDE)
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and
debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC
peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,
production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and
configure to suit a broad array of application requirements.
Blutooth Low Energy Component
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you
quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and
provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)
hardware via the stack.
EZ-Serial™ BLE Firmware Platform
The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed
in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control
signals through the module’s GPIOs, making it easy to add BLE functionality quickly to existing designs.
Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for
User Manuals and instructions for getting started as well as detailed reference materials.
EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you
can download each EZ-BLE module’s firmware images on the EZ-Serial webpage.
hardware via the stack.
Technical Support
■ Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.
■ Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.
■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-09764 Rev. *G
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CYBLE-212023-10
Contents
Overview............................................................................ 4
Module Description...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 7
Digital and Analog Capablities and Connections.......... 9
Power Supply Connections and Recommended External
Components.................................................................... 10
Connection Options................................................... 10
External Component Recommendation .................... 10
Critical Components List ........................................... 13
Antenna Design......................................................... 13
Electrical Specification .................................................. 14
GPIO ......................................................................... 16
XRES......................................................................... 17
Digital Peripherals ..................................................... 20
Serial Communication ............................................... 22
Memory ..................................................................... 23
System Resources .................................................... 23
Environmental Specifications ....................................... 29
Environmental Compliance ....................................... 29
RF Certification.......................................................... 29
Safety Certification .................................................... 29
Environmental Conditions ......................................... 29
ESD and EMI Protection ........................................... 29
Regulatory Information.................................................. 30
FCC........................................................................... 30
Industry Canada (IC) Certification............................. 31
European R&TTE Declaration of Conformity ............ 31
MIC Japan................................................................. 32
KC Korea................................................................... 32
Packaging........................................................................ 33
Ordering Information...................................................... 35
Part Numbering Convention...................................... 35
Acronyms........................................................................ 36
Document Conventions ................................................. 36
Units of Measure ....................................................... 36
Document History Page................................................. 37
Sales, Solutions, and Legal Information ...................... 39
Worldwide Sales and Design Support....................... 39
Products.................................................................... 39
PSoC® Solutions ...................................................... 39
Cypress Developer Community................................. 39
Technical Support ..................................................... 39
Document Number: 002-09764 Rev. *G
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CYBLE-212019-00
CYBLE-212023-10
Overview
Module Description
The CYBLE-2120XX-X0 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs
should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item
Specification
Length (X) 14.52 ± 0.15 mm
Width (Y) 19.20 ± 0.15 mm
Length (X) 11.00 ± 0.15 mm
Width (Y) 5.00 ± 0.15 mm
Module dimensions
Antenna location dimensions
PCB thickness
Shield height
Height (H) 0.80 ± 0.10 mm
Height (H) 1.20 ± 0.10 mm
1.20-mm typical (shield) - CYBLE-212019-00
0.75-mm typical (crystal) - CYBLE-212023-10
Maximum component height
Height (H)
2.00-mm typical - CYBLE-212019-00
1.55-mm typical - CYBLE-212023-10
Total module thickness (bottom of module to highest component) Height (H)
See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-2120XX-X0.
Document Number: 002-09764 Rev. *G
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CYBLE-212019-00
CYBLE-212023-10
Figure 1. Module Mechanical Drawing
Top View (View from Top)
Side View
Bottom View (Seen from Bottom)
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Table 3.
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CYBLE-212019-00
CYBLE-212023-10
Pad Connection Interface
As shown in the bottom view of Figure 1 on page 5, the CYBLE-2120XX-X0 connects to the host board via solder pads on the backside
of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-2120XX-X0 module.
Table 2. Solder Pad Connection Description
Name Connections Connection Type
SP 31 Solder Pads
Pad Length Dimension
Pad Width Dimension
Pad Pitch
1.02 mm
0.71 mm
1.27 mm
Figure 2. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner.
This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module placement
best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional
keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The
recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm).
Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-2120XX-X0 Antenna
Host PCB Keep Out Area Around Trace Antenna
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CYBLE-212019-00
CYBLE-212023-10
Recommended Host PCB Layout
Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-212019-00. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad
on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. Host Layout Pattern for CYBLE-2120XX-X0
Figure 5. Module Pad Location from Origin
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
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Table 3 provides the center location for each solder pad on the CYBLE-2120XX-X0. All dimensions are referenced to the center of
the solder pad. Refer to Figure 6 for the location of each module solder pad.
Table 3. Module Solder Pad Location
Figure 6. Solder Pad Reference Location
Solder Pad
(Center of Pad)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
1
(0.39, 4.88)
(0.39, 6.15)
(15.35, 192.13)
(15.35, 242.13)
(15.35, 292.13)
(15.35, 342.13)
(15.35, 392.13)
(15.35, 442.13)
(15.35, 492.13)
(15.35, 542.13)
(15.35, 592.13)
(15.35, 642.13)
(15.35, 692.13)
(80.31, 740.94)
(130.31, 740.94)
(180.31, 740.94)
(230.31, 740.94)
(280.31, 740.94)
(330.31, 740.94)
(380.31, 740.94)
(430.31, 740.94)
(480.31, 740.94)
(530.31, 740.94)
(556.69, 642.12)
(556.69, 592.12)
(556.69, 542.12)
(556.69, 492.12)
(556.69, 442.12)
(556.69, 392.12)
(556.69, 342.12)
(556.69, 292.12)
(556.69, 242.12)
(556.69, 192.12)
2
3
(0.39, 7.42)
4
(0.39, 8.69)
5
(0.39, 9.96)
6
(0.39, 11.23)
(0.39, 12.50)
(0.39, 13.77)
(0.39, 15.04)
(0.39, 16.31)
(0.39, 17.58)
(2.04, 18.82)
(3.31, 18.82)
(4.58, 18.82)
(5.85, 18.82)
(7.12, 18.82)
(8.39, 18.82)
(9.66, 18.82)
(10.93, 18.82)
(12.20, 18.82)
(13.47, 18.82)
(14.14, 16.31)
(14.14, 15.04)
(14.14, 13.77)
(14.14, 12.50)
(14.14, 11.23)
(14.14, 9.96)
(14.14, 8.69)
(14.14, 7.42)
(14.14, 6.15)
(14.14, 4.88)
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Top View (Seen on Host PCB)
Document Number: 002-09764 Rev. *G
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CYBLE-212019-00
CYBLE-212023-10
Digital and Analog Capabilities and Connections
Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on
CYBLE-2120XX-X0, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each
connection is configurable for a single option shown with a ✓.
Table 4. Solder Pad Connection Definitions
SolderPad Device
Number Port Pin
Cap-
Sense
WCO ECO
Out Out
UART
SPI
I2C
TCPWM[2,3]
LCD
SWD
GPIO
1
XRES
External Reset Hardware Connection Input
✓(TCPWM0_P) ✓(CMOD
2
P4.0[4] ✓(SCB1_RTS) ✓(SCB1_MOSI)
)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
3
P3.7 ✓(SCB1_CTS)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(Sensor)
✓
✓
✓
4
P3.6 ✓(SCB1_RTS)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
5
P3.5
✓(SCB1_TX)
✓(SCB1_RX)
✓(SCB1_SCL)
6
P3.4
✓(SCB1_SDA) ✓(TCPWM)
✓(TCPWM)
7
P3.3 ✓(SCB0_CTS)
8
P3.2 ✓(SCB0_RTS)
✓(TCPWM)
9
P2.6
VREF
P2.4
P2.3
P2.2
P2.0
VDD
✓(TCPWM)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reference Voltage Input (Optional)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓
✓
✓
✓
✓
✓
✓
✓
✓(SCB0_SS3)
✓(SCB0_SS1)
Digital Power Supply Input (1.8 to 5.5V)
P1.7 ✓(SCB0_CTS) ✓(SCB0_SCLK
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
P1.6
P1.5
P1.4
P1.0
P0.4
P0.5
✓(SCB0_RTS) ✓(SCB0_SS0)
✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL)
✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM)
✓(TCPWM)
✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM)
✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
P0.7 ✓(SCB0_CTS) ✓(SCB0_SCLK
✓(SWDCLK)
✓(SWDIO)
P0.6 ✓(SCB0_RTS) ✓(SCB0_SS0)
GND[5]
GND[5]
GND[5]
GND[5]
VDDR
Ground Connection
Ground Connection
Ground Connection
Ground Connection
Radio Power Supply (1.9V to 5.5V)
P5.0
✓(SCB1_RX) ✓(SCB1_SS0) ✓(SCB1_SDA) ✓(TCPWM3_P) ✓(Sensor)
✓(SCB1_TX) ✓(SCB1_SCLK ✓(SCB1_SCL) ✓(TCPWM3_N) ✓(Sensor)
✓
✓
✓
✓
P5.1
✓
Notes
2. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions.
3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive
or negative polarity. TCPWM connections on ports 4 and 5 are direct and can only be used with the specified TCPWM block and polarity specified above.
4. When using the capacitive sensing functionality, Pad 2 (P4.0) must be connected to a C
capacitor is 2.2 nF and should be placed as close to the module as possible.
capacitor (located off of Cypress BLE Module). The value of this
MOD
5. The main board needs to connect all GND connections (Pad 25/26/27/28) on the module to the common ground of the system.
2
2
6. If the I S feature is used in the design, the I S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator.
Document Number: 002-09764 Rev. *G
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Power Supply Connections and Recommended External Components
Power Connections
External Component Recommendation
The CYBLE-2120XX-X0 contains two power supply connec-
tions, VDD and VDDR. The VDD connection supplies power for
both digital and analog device operation. The VDDR connection
supplies power for the device radio.
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts
a supply range of 1.9 V to 5.5 V. These specifications can be
found in Table 9. The maximum power supply ripple for both
power connections on the module is 100 mV, as shown in
Table 7.
Figure 7 details the recommended host schematic options for a
single supply scenario. The use of one or two ferrite beads will
depend on the specific application and configuration of the
CYBLE-2120XX-X0.
Figure 8 details the recommended host schematic for an
independent supply scenario.
The power supply ramp rate of VDD must be equal to or greater
than that of VDDR.
The recommended ferrite bead value is 330 , 100 MHz. (Murata
BLM21PG331SN1D).
Connection Options
Two connection options are available for any application:
1. Single supply: Connect VDD and VDDR to the same supply.
2. Independent supply: Power VDD and VDDR separately.
Figure 7. Recommended Host Schematic Options for a Single Supply Option
Single Ferrite Bead Option (Seen from Bottom)
Two Ferrite Bead Option (Seen from Bottom)
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Figure 8. Recommended Host Schematic for an Independent Supply Option
Two Ferrite Bead Option (Seen from Bottom)
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The CYBLE-2120XX-X0 schematic is shown in Figure 9.
Figure 9. CYBLE-2120XX-X0 Schematic Diagram
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Critical Components List
Table 5 details the critical components used in the CYBLE-2120XX-X0 module.
Table 5. Critical Component List
Component
Reference Designator
Description
Silicon
Crystal
Crystal
U1
Y1
Y2
56-pin QFN Programmable Radio-on-Chip (PRoC) with BLE
24.000 MHz, 12PF
32.768 kHz, 12.5PF
Antenna Design
Table 6 details trace antenna used in the CYBLE-2120XX-X0 module. For more information, see Table 8.
Table 6. Trace Antenna Specifications
Item
Description
Frequency Range
Peak Gain
2400–2500 MHz
0.5-dBi typical
Average Gain
Return Loss
–0.5-dBi typical
10-dB minimum
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Electrical Specification
Table 7 details the absolute maximum electrical characteristics for the Cypress BLE module.
Table 7. CYBLE-2120XX-X0 Absolute Maximum Ratings
Parameter
VDDD_ABS
Description
Min
–0.5
–0.5
Typ
–
Max
6
Units
Details/Conditions
Analog, digital, or radio supply relative to VSS
V
V
Absolute maximum
(VSSD = VSSA
)
VCCD_ABS
Direct digital core voltage input relative to VSSD
–
1.95
Absolute maximum
3.0-V supply
Maximum power supply ripple for VDD and VDDR
input voltage
VDD_RIPPLE
–
–
100
mV Ripple frequency of 100 kHz
to 750 kHz
VGPIO_ABS
IGPIO_ABS
GPIO voltage
–0.5
–25
–
–
VDD +0.5
25
V
Absolute maximum
Maximum current per GPIO
mA Absolute maximum
GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS
Absolute maximum current
injected per pin
IGPIO_injection
LU
–0.5
–
0.5
mA
Pin current for latch up
–200
200
mA
–
Table 8 details the RF characteristics for the Cypress BLE module.
Table 8. CYBLE-2120XX-X0 RF Performance Characteristics
Parameter
RFO
Description
RF output power on ANT
Min
Typ
Max
Units
Details/Conditions
Configurable via register
settings
–18
0
3
dBm
Guaranteed by design
simulation
RXS
RF receive sensitivity on ANT
–
–87
–
dBm
FR
Module frequency range
Peak gain
2400
–
2480
MHz
dBi
dBi
dB
–
–
–
–
GP
–
–
–
0.5
–
–
–
GAvg
RL
Average gain
–0.5
–10.5
Return loss
Table 9 through Table 48 list the module level electrical characteristics for the CYBLE-2120XX-X0. All specifications are valid for
–40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 9. CYBLE-2120XX-X0 DC Specifications
Parameter
VDD1
Description
Power supply input voltage
Min
Typ
Max
Units
Details/Conditions
1.8
–
5.5
V
With regulator enabled
Internally unregulated
supply
VDD2
Power supply input voltage unregulated
1.71
1.8
1.89
V
VDDR1
VDDR2
Radio supply voltage (radio on)
Radio supply voltage (radio off)
1.9
–
–
5.5
5.5
V
V
–
–
1.71
Active Mode, VDD = 1.71 V to 5.5 V
T = 25 °C,
IDD3
IDD4
IDD5
IDD6
IDD7
Execute from flash; CPU at 3 MHz
–
–
–
–
–
1.7
–
–
–
–
–
–
mA
VDD = 3.3 V
Execute from flash; CPU at 3 MHz
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 12 MHz
mA T = –40 °C to 85 °C
T = 25 °C,
mA
2.5
–
VDD = 3.3 V
mA T = –40 °C to 85 °C
T = 25 °C,
mA
4
VDD = 3.3 V
Document Number: 002-09764 Rev. *G
Page 14 of 39
CYBLE-212019-00
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Table 9. CYBLE-2120XX-X0 DC Specifications (continued)
Parameter
IDD8
Description
Min
Typ
Max
Units
Details/Conditions
Execute from flash; CPU at 12 MHz
–
–
–
mA T = –40 °C to 85 °C
T = 25 °C,
mA
IDD9
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 48 MHz
Execute from flash; CPU at 48 MHz
–
–
–
–
7.1
–
–
–
–
–
V
DD = 3.3 V
IDD10
IDD11
IDD12
mA T = –40 °C to 85 °C
T = 25 °C,
mA
13.4
–
VDD = 3.3 V
mA T = –40 °C to 85 °C
Sleep Mode, VDD = 1.8 V to 5.5 V
IDD13 IMO on
Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V
IDD14 ECO on
Deep-Sleep Mode, VDD = 1.8 V to 3.6 V
T = 25 °C, VDD = 3.3 V,
mA
–
–
–
–
–
–
SYSCLK = 3 MHz
T = 25 °C, VDD = 3.3 V,
mA
SYSCLK = 3 MHz
T = 25 °C,
A
IDD15
IDD16
IDD17
IDD18
WDT with WCO on
WDT with WCO on
WDT with WCO on
WDT with WCO on
–
–
–
–
1.5
–
–
–
–
–
VDD = 3.3 V
A T = –40 °C to 85 °C
T = 25 °C,
–
A
VDD = 5 V
–
A T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed)
IDD19
IDD20
WDT with WCO on
WDT with WCO on
–
–
–
–
–
–
A T = 25 °C
A T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 V to 3.6 V
T = 25 °C,
nA
IDD27
IDD28
GPIO and reset active
–
–
150
–
–
–
VDD = 3.3 V
GPIO and reset active
nA T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 V to 5.5 V
T = 25 °C,
nA
IDD29
GPIO and reset active
–
–
–
–
–
–
VDD = 5 V
IDD30
GPIO and reset active
nA T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 V to 3.6 V
T = 25 °C,
nA
IDD33
Stop-mode current (VDD
)
–
20
–
V
DD = 3.3 V
T = 25 °C,
DDR = 3.3 V
IDD34
IDD35
IDD36
Stop-mode current (VDDR
)
)
–
–
–
40
–
–-
–
nA
V
Stop-mode current (VDD
)
nA T = –40 °C to 85 °C
T = –40 °C to 85 °C,
nA
Stop-mode current (VDDR
–
–
VDDR = 1.9 V to 3.6 V
Stop Mode, VDD = 3.6 V to 5.5 V
IDD37 Stop-mode current (VDD
T = 25 °C,
nA
)
–
–
–
–
–
–
V
DD = 5 V
T = 25 °C,
DDR = 5 V
IDD38
IDD39
IDD40
Stop-mode current (VDDR
)
)
nA
V
Stop-mode current (VDD
)
–
–
–
–
–
–
nA T = –40 °C to 85 °C
nA T = –40 °C to 85 °C
Stop-mode current (VDDR
Document Number: 002-09764 Rev. *G
Page 15 of 39
CYBLE-212019-00
CYBLE-212023-10
Table 10. AC Specifications
Parameter
Description
Min
DC
–
Typ
–
Max
48
–
Units
Details/Conditions
FCPU
CPU frequency
MHz 1.71 V VDD 5.5 V
TSLEEP
Wakeup from Sleep mode
0
s
s
Guaranteed by characterization
24-MHz IMO. Guaranteed by
characterization
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
THIBERNATE
TSTOP
Wakeup from Hibernate mode
Wakeup from Stop mode
–
–
–
–
2
2
ms
ms
Guaranteed by characterization
XRES wakeup
GPIO
Table 11. GPIO DC Specifications
Parameter
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage HIGH threshold
LVTTL input, VDD < 2.7 V
LVTTL input, VDD 2.7 V
Input voltage LOW threshold
LVTTL input, VDD < 2.7 V
LVTTL input, VDD 2.7 V
Output voltage HIGH level
Output voltage HIGH level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Pull-up resistor
0.7 × VDD
–
CMOS input
[7]
VIH
0.7 × VDD
–
–
V
–
2.0
–
–
V
–
–
–
0.3× VDD
V
CMOS input
VIL
–
–
0.3× VDD
V
–
–
–
0.8
–
V
–
VDD –0.6
–
V
IOH = 4 mA at 3.3-V VDD
VOH
VDD –0.5
–
–
V
IOH = 1 mA at 1.8-V VDD
–
–
0.6
0.6
0.4
8.5
8.5
2
V
IOL = 8 mA at 3.3-V VDD
VOL
–
–
V
IOL = 4 mA at 1.8-V VDD
–
–
V
IOL = 3 mA at 3.3-V VDD
RPULLUP
RPULLDOWN
IIL
3.5
5.6
5.6
–
k
k
nA
nA
pF
mV
1
–
Pull-down resistor
3.5
–
Input leakage current (absolute value)
Input leakage on CTBm input pins
Input capacitance
–
25 °C, VDD = 3.3 V
IIL_CTBM
CIN
VHYSTTL
VHYSCMOS
–
–
4
–
–
25
–
7
–
Input hysteresis LVTTL
40
–
–
VDD > 2.7 V
–
Input hysteresis CMOS
0.05 × VDD
–
Current through protection diode to
IDIODE
–
–
–
–
100
200
A
–
–
VDD/VSS
Maximum total source or sink chip
current
ITOT_GPIO
mA
Note
7.
V
must not exceed V + 0.2 V.
IH DD
Document Number: 002-09764 Rev. *G
Page 16 of 39
CYBLE-212019-00
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Table 12. GPIO AC Specifications
Parameter Description
TRISEF
Min
2
Typ
–
Max
12
Units
ns
Details/Conditions
Rise time in Fast-Strong mode
Fall time in Fast-Strong mode
Rise time in Slow-Strong mode
Fall time in Slow-Strong mode
3.3-V VDDD, CLOAD = 25 pF
TFALLF
TRISES
TFALLS
2
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
3.3-V VDDD, CLOAD = 25 pF
3.3-V VDDD, CLOAD = 25 pF
10
10
–
60
ns
–
60
ns
GPIO FOUT; 3.3 V VDD 5.5 V
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
FGPIOIN
–
–
–
–
–
–
–
–
–
–
33
16.7
7
MHz 90/10%, 25-pF load, 60/40 duty cycle
MHz 90/10%, 25-pF load, 60/40 duty cycle
MHz 90/10%, 25-pF load, 60/40 duty cycle
MHz 90/10%, 25-pF load, 60/40 duty cycle
MHz 90/10% VIO
Fast-Strong mode
GPIO FOUT; 1.7 VVDD 3.3 V
Fast-Strong mode
GPIO FOUT; 3.3 V VDD 5.5 V
Slow-Strong mode
GPIO FOUT; 1.7 V VDD 3.3 V
Slow-Strong mode
3.5
48
GPIO input operating frequency
1.71 V VDD 5.5 V
Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Parameter
Description
Min
–
Typ
–
Max
10
Units
Details/Conditions
Input leakage (absolute value).
VIH > VDD
IIL
VOL
A 25°C, VDD = 0 V, VIH = 3.0 V
Output voltage LOW level
–
–
0.4
V
IOL = 20 mA, VDD > 2.9 V
Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Parameter
TRISE_OVFS
TFALL_OVFS
TRISESS
Description
Min
1.5
1.5
10
Typ
–
Max
12
Units
ns
Details/Conditions
Output rise time in Fast-Strong mode
Output fall time in Fast-Strong mode
Output rise time in Slow-Strong mode
Output fall time in Slow-Strong mode
25-pF load, 10%–90%, VDD = 3.3 V
25-pF load, 10%–90%, VDD = 3.3 V
25-pF load, 10%-90%, VDD = 3.3 V
25-pF load, 10%-90%, VDD = 3.3 V
–
12
ns
–
60
ns
TFALLSS
10
–
60
ns
GPIO FOUT; 3.3 V VDD 5.5 V
FGPIOUT1
FGPIOUT2
–
–
–
–
24
16
MHz 90/10%, 25-pF load, 60/40 duty cycle
MHz 90/10%, 25-pF load, 60/40 duty cycle
Fast-Strong mode
GPIO FOUT; 1.71 V VDD 3.3 V
Fast-Strong mode
XRES
Table 15. XRES DC Specifications
Parameter Description
VIH
Min
Typ
–
Max
Units
V
Details/Conditions
CMOS input
CMOS input
Input voltage HIGH threshold
Input voltage LOW threshold
Pull-up resistor
0.7 × VDDD
–
VIL
–
3.5
–
–
0.3 × VDDD
V
RPULLUP
CIN
5.6
3
8.5
–
k
pF
–
–
–
Input capacitance
VHYSXRES
Input voltage hysteresis
Current through protection diode to
–
100
–
mV
IDIODE
–
–
100
A
–
VDD/VSS
Table 16. XRES AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRESETWIDTH Reset pulse width
1
–
–
s
–
Document Number: 002-09764 Rev. *G
Page 17 of 39
CYBLE-212019-00
CYBLE-212023-10
Temperature Sensor
Table 17. Temperature Sensor Specifications
Parameter
TSENSACC
Description
Min
Typ
Max
Units
Details/Conditions
Temperature-sensor accuracy
–5
±1
5
°C
–40 °C to +85 °C
SAR ADC
Table 18. SAR ADC DC Specifications
Parameter Description
A_RES
Min
–
Typ
Max
Units
Details/Conditions
Resolution
–
–
12
8
bits
A_CHNIS_S
A-CHNKS_D
A-MONO
Number of channels - single-ended
–
8 full-speed[8]
Diff inputs use
Number of channels - differential
Monotonicity
–
–
–
–
–
–
4
–
neighboring I/O[8]
Yes
With external
reference
A_GAINERR
Gain error
±0.1
%
Measured with 1-V
VREF
A_OFFSET
Input offset voltage
–
–
2
mV
A_ISAR
A_VINS
A_VIND
A_INRES
A_INCAP
Current consumption
–
VSS
VSS
–
–
–
–
–
–
1
mA
V
Input voltage range - single-ended
Input voltage range - differential
Input resistance
VDDA
VDDA
2.2
V
k
pF
Input capacitance
–
10
Percentage of Vbg
(1.024 V)
VREFSAR
Trimmed internal reference to SAR
–1
–
1
%
Table 19. SAR ADC AC Specifications
Parameter Description
A_PSRR
Min
Typ
Max
Units
Details/Conditions
Measured at 1-V
reference
Power-supply rejection ratio
70
–
–
dB
A_CMRR
A_SAMP
Common-mode rejection ratio
Sample rate
66
–
–
–
–
1
dB
Msps
SAR operating speed without external ref.
bypass
Fsarintref
–
–
100
Ksps 12-bit resolution
A_SNR
A_BW
Signal-to-noise ratio (SNR)
65
–
–
–
–
dB
FIN = 10 kHz
Input bandwidth without aliasing
A_SAMP/2
kHz
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
1 Msps
A_INL
A_INL
A_INL
A_dnl
–1.7
–1.5
–1.5
–1
–
–
–
–
–
2
LSB
LSB
LSB
V
V
V
REF = 1 V to VDD
REF = 1.71 V to VDD
REF = 1 V to VDD
Integral nonlinearity. VDDD = 1.71 V to 3.6 V,
1 Msps
1.7
1.7
2.2
2
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
500 ksps
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 1 Msps
LSB VREF = 1 V to VDD
Differential nonlinearity. VDD = 1.71 V to
3.6 V, 1 Msps
A_DNL
–1
LSB VREF = 1.71 V to VDD
Note
8. A maximum of eight single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other funcitonality (e.g. CapSense). If
the AMUX Buses are being used for other functions, then the maximum number of single-ended ADC channels is six. Similarly, if the AMUX Buses are being
used for other functionality, then the maximum number of differential ADC channels is three.
Document Number: 002-09764 Rev. *G
Page 18 of 39
CYBLE-212019-00
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Table 19. SAR ADC AC Specifications (continued)
Parameter
A_DNL
Description
Min
–1
–
Typ
–
Max
2.2
Units
Details/Conditions
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 500 ksps
LSB VREF = 1 V to VDD
A_THD
Total harmonic distortion
–
–65
dB
FIN = 10 kHz
CSD
CSD Block Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VCSD
Voltage range of operation
DNL for 8-bit resolution
INL for 8-bit resolution
DNL for 7-bit resolution
INL for 7-bit resolution
1.71
–1
–
–
–
–
–
5.5
1
V
–
–
–
–
–
IDAC1
IDAC1
IDAC2
IDAC2
LSB
LSB
LSB
LSB
–3
3
–1
1
–3
3
Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
SNR
Ratio of counts of finger to noise
5
–
–
Ratio
Output current of IDAC1 (8 bits) in High
range
IDAC1_CRT1
IDAC1_CRT2
IDAC2_CRT1
IDAC2_CRT2
–
–
–
–
612
306
305
153
–
–
–
–
–
–
–
–
A
A
A
A
Output current of IDAC1 (8 bits) in Low
range
Output current of IDAC2 (7 bits) in High
range
Output current of IDAC2 (7 bits) in Low
range
Document Number: 002-09764 Rev. *G
Page 19 of 39
CYBLE-212019-00
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Digital Peripherals
Timer
Table 20. Timer DC Specifications
Parameter
ITIM1
ITIM2
ITIM3
Description
Min
–
Typ
–
Max
42
Units
Details/Conditions
16-bit timer
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
A
A
A
–
–
130
535
16-bit timer
16-bit timer
–
–
Table 21. Timer AC Specifications
Parameter Description
TTIMFREQ
Min
FCLK
Typ
–
Max
48
Units
MHz
Details/Conditions
Operating frequency
TCAPWINT
Capture pulse width (internal)
Capture pulse width (external)
Timer resolution
2 × TCLK
2 × TCLK
TCLK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
TCAPWEXT
TTIMRES
TTENWIDINT
TTENWIDEXT
TTIMRESWINT
TTIMRESEXT
Enable pulse width (internal)
Enable pulse width (external)
Reset pulse width (internal)
Reset pulse width (external)
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
Counter
Table 22. Counter DC Specifications
Parameter Description
ICTR1
ICTR2
ICTR3
Min
–
Typ
–
Max
42
Units
A
A
Details/Conditions
16-bit counter
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
–
–
130
535
16-bit counter
–
–
A
16-bit counter
Table 23. Counter AC Specifications
Parameter
TCTRFREQ
Description
Min
Typ
–
Max
48
–
Units
MHz
ns
Details/Conditions
Operating frequency
FCLK
–
–
–
–
–
–
–
–
TCTRPWINT
TCTRPWEXT
TCTRES
Capture pulse width (internal)
Capture pulse width (external)
Counter Resolution
2 × TCLK
2 × TCLK
TCLK
–
–
–
ns
–
–
ns
TCENWIDINT
TCENWIDEXT
TCTRRESWINT
Enable pulse width (internal)
Enable pulse width (external)
Reset pulse width (internal)
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
–
–
ns
–
–
ns
–
–
ns
TCTRRESWEXT Reset pulse width (external)
–
–
ns
Document Number: 002-09764 Rev. *G
Page 20 of 39
CYBLE-212019-00
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Pulse Width Modulation (PWM)
Table 24. PWM DC Specifications
Parameter
IPWM1
IPWM2
IPWM3
Description
Min
–
Typ
–
Max
42
Units
Details/Conditions
16-bit PWM
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
A
A
A
–
–
130
535
16-bit PWM
–
–
16-bit PWM
Table 25. PWM AC Specifications
Parameter Description
TPWMFREQ
TPWMPWINT
TPWMEXT
Min
Typ
Max
48
–
Units
MHz
ns
Details/Conditions
Operating frequency
FCLK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Pulse width (internal)
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
Pulse width (external)
–
ns
TPWMKILLINT
TPWMKILLEXT
TPWMEINT
Kill pulse width (internal)
Kill pulse width (external)
Enable pulse width (internal)
Enable pulse width (external)
Reset pulse width (internal)
Reset pulse width (external)
–
ns
–
ns
–
ns
TPWMENEXT
TPWMRESWINT
TPWMRESWEXT
–
ns
–
ns
–
ns
LCD Direct Drive
Table 26. LCD Direct Drive DC Specifications
Parameter
ILCDLOW
Description
Min
Typ
Max
Units
Details/Conditions
16 × 4 small segment
display at 50 Hz
Operating current in low-power mode
–
17.5
–
A
LCD capacitance per segment/common
driver
CLCDCAP
LCDOFFSET
ILCDOP1
–
–
–
500
20
2
5000
pF
mV
mA
–
Long-term segment offset
–
–
–
32 × 4 segments. 50 Hz at
25 °C
LCD system operating current, VBIAS = 5 V
32 × 4 segments
50 Hz at 25 °C
ILCDOP2
LCD system operating current, VBIAS = 3.3 V
–
2
–
mA
Table 27. LCD Direct Drive AC Specifications
Parameter Description
FLCD
Min
Typ
Max
Units
Details/Conditions
LCD frame rate
10
50
150
Hz
–
Document Number: 002-09764 Rev. *G
Page 21 of 39
CYBLE-212019-00
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Serial Communication
Table 28. Fixed I2C DC Specifications
Parameter
II2C1
Description
Min
–
Typ
–
Max
50
Units
A
A
A
A
Details/Conditions
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
I2C enabled in Deep-Sleep mode
–
–
–
–
II2C2
II2C3
II2C4
–
–
155
390
1.4
–
–
–
–
Table 29. Fixed I2C AC Specifications
Parameter Description
FI2C1
Min
Typ
Max
Units
Details/Conditions
Bit rate
–
–
400
kHz
Table 30. Fixed UART DC Specifications
Parameter
IUART1
IUART2
Description
Min
–
Typ
–
Max
55
Units
A
A
Details/Conditions
Block current consumption at 100 kbps
Block current consumption at 1000 kbps
–
–
–
–
312
Table 31. Fixed UART AC Specifications
Parameter Description
FUART
Min
Typ
Max
Units
Details/Conditions
Bit rate
–
–
1
Mbps
–
Table 32. Fixed SPI DC Specifications
Parameter
ISPI1
ISPI2
ISPI3
Description
Min
–
Typ
–
Max
360
560
600
Units
A
A
Details/Conditions
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
–
–
–
–
–
–
–
A
Table 33. Fixed SPI AC Specifications
Parameter Description
FSPI
Min
Typ
Max
Units
Details/Conditions
SPI operating frequency (master; 6x over sampling)
–
–
8
MHz
–
Table 34. Fixed SPI Master Mode AC Specifications
Parameter
Description
Min
Typ Max Units
Details/Conditions
TDMO
MOSI valid after SCLK driving edge
–
–
–
–
18
ns
ns
ns
–
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
TDSI
20
0
–
Full clock, late MISO sampling
Referred to Slave capturing edge
THMO
Previous MOSI data hold time
–
Table 35. Fixed SPI Slave Mode AC Specifications
Parameter
TDMI
Description
Min
Typ
–
Max
Units
ns
Details/Conditions
MOSI valid before SCLK capturing edge
MISO valid after SCLK driving edge
40
–
–
TDSO
–
42 + 3 × TCPU
ns
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V
TDSO_ext
–
–
50
ns
THSO
Previous MISO data hold time
0
–
–
–
–
ns
ns
TSSELSCK
SSEL valid to first SCK valid edge
100
Document Number: 002-09764 Rev. *G
Page 22 of 39
CYBLE-212019-00
CYBLE-212023-10
Memory
Table 36. Flash DC Specifications
Parameter
VPE
Description
Min
1.71
2
Typ
–
Max
5.5
–
Units
Details/Conditions
–
Erase and program voltage
V
TWS48
TWS32
TWS16
Number of Wait states at 32–48 MHz
Number of Wait states at 16–32 MHz
Number of Wait states for 0–16 MHz
–
CPU execution from flash
CPU execution from flash
CPU execution from flash
1
–
–
0
–
–
Table 37. Flash AC Specifications
Parameter
Description
Min
Typ
–
Max
20
13
7
Units
Details/Conditions
[9]
TROWWRITE
Row (block) write time (erase and program)
Row erase time
–
–
ms Row (block) = 256 bytes
[9]
TROWERASE
–
ms
ms
–
–
–
–
–
–
–
[9]
TROWPROGRAM
Row program time after erase
Bulk erase time (256 KB)
–
–
[9]
TBULKERASE
–
–
35
25
–
ms
[9]
TDEVPROG
Total device program time
–
–
seconds
cycles
years
years
FEND
FRET
FRET2
Flash endurance
100 K
20
10
–
Flash retention. TA 55 °C, 100 K P/E cycles
Flash retention. TA 85 °C, 10 K P/E cycles
–
–
–
–
System Resources
Power-on-Reset (POR)
Table 38. POR DC Specifications
Parameter
Description
Min
0.80
0.75
15
Typ
–
Max
1.45
1.40
200
Units
V
Details/Conditions
VRISEIPOR
VFALLIPOR
VIPORHYST
Rising trip voltage
–
–
–
Falling trip voltage
Hysteresis
–
V
–
mV
Table 39. POR AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Precision power-on reset (PPOR) response
time in Active and Sleep modes
TPPOR_TR
–
–
1
s
–
Table 40. Brown-Out Detect
Parameter
Description
Min
1.64
1.4
Typ
–
Max
–
Units
Details/Conditions
VFALLPPOR
VFALLDPSLP
BOD trip voltage in Active and Sleep modes
BOD trip voltage in Deep Sleep
V
V
–
–
–
–
Table 41. Hibernate Reset
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VHBRTRIP
BOD trip voltage in Hibernate
1.1
–
–
V
–
Note
9. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-09764 Rev. *G
Page 23 of 39
CYBLE-212019-00
CYBLE-212023-10
Voltage Monitors (LVD)
Table 42. Voltage Monitor DC Specifications
Parameter
VLVI1
Description
Min
1.71
1.76
1.85
1.95
2.05
2.15
2.24
2.34
2.44
2.54
2.63
2.73
2.83
2.93
3.12
4.39
–
Typ
1.75
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.20
4.50
–
Max
1.79
1.85
1.95
2.05
2.15
2.26
2.36
2.46
2.56
2.67
2.77
2.87
2.97
3.08
3.28
4.61
100
Units
V
Details/Conditions
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
Block current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VLVI2
V
VLVI3
V
VLVI4
V
VLVI5
V
VLVI6
V
VLVI7
V
VLVI8
V
VLVI9
V
VLVI10
VLVI11
VLVI12
VLVI13
VLVI14
VLVI15
VLVI16
LVI_IDD
V
V
V
V
V
V
V
A
Table 43. Voltage Monitor AC Specifications
Parameter
TMONTRIP
Description
Min
Typ
Max
Units
Details/Conditions
Voltage monitor trip time
–
–
1
s
–
SWD Interface
Table 44. SWD Interface Specifications
Parameter
F_SWDCLK1
F_SWDCLK2
Description
3.3 V VDD 5.5 V
1.71 V VDD 3.3 V
Min
Typ
–
Max
Units
MHz
MHz
ns
Details/Conditions
–
14
SWDCLK 1/3 CPU clock frequency
–
–
7
SWDCLK 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
0.25 × T
–
–
–
–
–
–
0.25 × T
–
–
0.5 × T
–
ns
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
–
1
–
ns
–
ns
Document Number: 002-09764 Rev. *G
Page 24 of 39
CYBLE-212019-00
CYBLE-212023-10
Internal Main Oscillator
Table 45. IMO DC Specifications
Parameter
IIMO1
Description
Min
–
Typ
–
Max
1000
325
225
180
150
Units
A
A
A
A
Details/Conditions
IMO operating current at 48 MHz
IMO operating current at 24 MHz
IMO operating current at 12 MHz
IMO operating current at 6 MHz
IMO operating current at 3 MHz
–
–
–
–
–
IIMO2
IIMO3
IIMO4
IIMO5
–
–
–
–
–
–
–
–
A
Table 46. IMO AC Specifications
Parameter Description
FIMOTOL3
FIMOTOL3
Min
–
Typ
–
Max
±2
–
Units
%
Details/Conditions
Frequency variation from 3 to 48 MHz
IMO startup time
With API-called calibration
–
–
12
s
Internal Low-Speed Oscillator
Table 47. ILO DC Specifications
Parameter
IILO2
Description
ILO operating current at 32 kHz
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
A
–
Table 48. ILO AC Specifications
Parameter Description
TSTARTILO1
FILOTRIM1
Min
–
Typ
–
Max
2
Units
ms
Details/Conditions
ILO startup time
–
–
32-kHz trimmed frequency
15
32
50
kHz
Table 49. Recommended ECO Trim Value
Parameter Description
24-MHz trim value
Value
0x0000BCBC
Details/Conditions
Recommended trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
ECOTRIM
(firmware configuration)
BLE Subsystem
Table 50. BLE Subsystem
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
RF Receiver Specification
RXS, IDLE
RX sensitivity with idle transmitter
–
–
–89
–91
–
–
dBm
dBm
–
RX sensitivity with idle transmitter
excluding Balun loss
Guaranteed by design
simulation
RF-PHY Specification
(RCV-LE/CA/01/C)
RXS, DIRTY
RXS, HIGHGAIN
PRXMAX
RX sensitivity with dirty transmitter
–
–
–87
–91
–1
–70
–
dBm
dBm
dBm
RX sensitivity in high-gain mode with idle
transmitter
–
RF-PHY Specification
(RCV-LE/CA/06/C)
Maximum input power
–10
–
Cochannel interference,
Wanted signal at –67 dBm and Interferer
at FRX
RF-PHY Specification
(RCV-LE/CA/03/C)
CI1
–
9
21
dB
Document Number: 002-09764 Rev. *G
Page 25 of 39
CYBLE-212019-00
CYBLE-212023-10
Table 50. BLE Subsystem (continued)
Parameter Description
Min
Typ
Max
Units
Details/Conditions
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±1 MHz
RF-PHY Specification
(RCV-LE/CA/03/C)
CI2
CI3
CI4
CI5
CI3
–
3
15
dB
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±2 MHz
RF-PHY Specification
(RCV-LE/CA/03/C)
–
–
–29
–39
–20
–30
–27
–27
–27
–27
–
–
–
dB
dB
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±3 MHz
RF-PHY Specification
(RCV-LE/CA/03/C)
Adjacent channel interference
Wanted Signal at –67 dBm and Interferer
RF-PHY Specification
(RCV-LE/CA/03/C)
–
–
dB
at Image frequency (FIMAGE
)
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at Image frequency (FIMAGE ± 1 MHz)
RF-PHY Specification
(RCV-LE/CA/03/C)
–
–
dB
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 30–2000 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB1
OBB2
OBB3
OBB4
IMD
–30
–35
–35
–30
–50
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2003–2399 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
–
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2484–2997 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
–
Out-of-band blocking,
Wanted signal a –67 dBm and Interferer
at F = 3000–12750 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
–
Inter modulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset channel
RF-PHY Specification
(RCV-LE/CA/05/C)
–
100-kHz measurement
bandwidth
ETSI EN300 328 V1.8.1
Receiver spurious emission
30 MHz to 1.0 GHz
RXSE1
RXSE2
–
–57
–47
1-MHz measurement
bandwidth
ETSI EN300 328 V1.8.1
Receiver spurious emission
1.0 GHz to 12.75 GHz
–
–
RF Transmitter Specifications
TXP, ACC
RF power accuracy
–
–
–
±1
20
0
–
–
–
dB
dB
–
–
–
TXP, RANGE
TXP, 0dBm
RF power control range
Output power, 0-dB Gain setting (PA7)
dBm
Output power, maximum power setting
(PA10)
TXP, MAX
TXP, MIN
F2AVG
–
3
–
–
dBm
dBm
kHz
kHz
–
–
Output power, minimum power setting
(PA1)
–
–18
–
Average frequency deviation for
10101010 pattern
RF-PHY Specification
(TRM-LE/CA/05/C)
185
225
–
Average frequency deviation for
11110000 pattern
RF-PHY Specification
(TRM-LE/CA/05/C)
F1AVG
250
275
Document Number: 002-09764 Rev. *G
Page 26 of 39
CYBLE-212019-00
CYBLE-212023-10
Table 50. BLE Subsystem (continued)
Parameter Description
Min
Typ
Max
Units
Details/Conditions
RF-PHY Specification
(TRM-LE/CA/05/C)
EO
Eye opening = F2AVG/F1AVG
Frequency accuracy
0.8
–
–
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, ACC
FTX, MAXDR
FTX, INITDR
FTX, DR
IBSE1
–150
–50
–20
–20
–
–
–
–
–
–
–
–
–
150
50
kHz
kHz
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
Maximum frequency drift
Initial frequency drift
RF-PHY Specification
(TRM-LE/CA/06/C)
20
kHz/
50 s
RF-PHY Specification
(TRM-LE/CA/06/C)
Maximum drift rate
20
In-band spurious emission at 2-MHz
offset
RF-PHY Specification
(TRM-LE/CA/03/C)
–20
-30
dBm
dBm
dBm
dBm
In-band spurious emission at 3-MHz
offset
RF-PHY Specification
(TRM-LE/CA/03/C)
IBSE2
–
Transmitter spurious emissions
(average), <1.0 GHz
TXSE1
–
-55.5
-41.5
FCC-15.247
FCC-15.247
Transmitter spurious emissions
(average), >1.0 GHz
TXSE2
–
RF Current Specifications
IRX
Receive current in normal mode
–
–
–
–
–
–
18.7
16.4
21.5
20
–
–
–
–
–
–
mA
mA
mA
mA
mA
mA
–
IRX_RF
Radio receive current in normal mode
Receive current in high-gain mode
TX current at 3-dBm setting (PA10)
TX current at 0-dBm setting (PA7)
Radio TX current at 0 dBm setting (PA7)
Measured at VDDR
IRX, HIGHGAIN
ITX, 3dBm
ITX, 0dBm
ITX_RF, 0dBm
–
–
16.5
15.6
–
Measured at VDDR
Radio TX current at 0 dBm excluding
Balun loss
Guaranteed by design
simulation
ITX_RF, 0dBm
–
14.2
–
mA
ITX,-3dBm
ITX,-6dBm
ITX,-12dBm
ITX,-18dBm
TX current at –3-dBm setting (PA4)
TX current at –6-dBm setting (PA3)
TX current at –12-dBm setting (PA2)
TX current at –18-dBm setting (PA1)
–
–
–
–
15.5
14.5
13.2
12.5
–
–
–
–
mA
mA
mA
mA
–
–
–
–
TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
Average current at 1-second BLE
connection interval
Iavg_1sec, 0dBm
Iavg_4sec, 0dBm
–
–
17.1
6.1
–
–
A
A
For empty PDU exchange
TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
Average current at 4-second BLE
connection interval
For empty PDU exchange
General RF Specifications
FREQ
CHBW
DR
RF operating frequency
2400
–
2
2482
MHz
MHz
kbps
–
–
–
Channel spacing
On-air data rate
–
–
–
–
1000
Document Number: 002-09764 Rev. *G
Page 27 of 39
CYBLE-212019-00
CYBLE-212023-10
Table 50. BLE Subsystem (continued)
Parameter Description
IDLE2TX
Min
–
Typ
120
75
Max
140
120
Units
s
Details/Conditions
BLE.IDLE to BLE. TX transition time
BLE.IDLE to BLE. RX transition time
–
–
IDLE2RX
–
s
RSSI Specifications
RSSI, ACC
RSSI accuracy
–
–
–
±5
1
–
–
–
dB
dB
s
–
–
–
RSSI, RES
RSSI resolution
RSSI sample period
RSSI, PER
6
Document Number: 002-09764 Rev. *G
Page 28 of 39
CYBLE-212019-00
CYBLE-212023-10
Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-212019-00 module will be certified under the following RF certification standards at production release.
■ FCC: WAP2011
■ CE
■ IC: 7922A-2011
■ MIC: 203-JN0509
■ KC: MSIP-CRM-Cyp-2011
Safety Certification
The CYBLE-2120XX-X0 module complies with the following regulations:
■ Underwriters Laboratories, Inc. (UL) - Filing E331901
■ CSA
■ TUV
Environmental Conditions
Table 51 describes the operating and storage conditions for the Cypress BLE module.
Table 51. Environmental Conditions for CYBLE-2120XX-X0
Description
Minimum Specification
Maximum Specification
85 °C
Operating temperature
–40 °C
Operating humidity (relative, non-condensation)
Thermal ramp rate
5%
85%
–
–40 °C
–
3 °C/minute
85 °C
Storage temperature
Storage temperature and humidity
85 ° C at 85%
15 kV Air
2.2 kV Contact
ESD: Module integrated into system Components[10]
–
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Note
10. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 002-09764 Rev. *G
Page 29 of 39
CYBLE-212019-00
CYBLE-212023-10
Regulatory Information
FCC
FCC NOTICE:
The device CYBLE-212019-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter
approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device
may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.
CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, ê may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna.
■ Increase the separation between the equipment and receiver.
■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
■ Consult the dealer or an experienced radio/TV technician for help
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible
label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP2011.
In any case the end product must be labeled exterior with “Contains FCC ID: WAP2011”.
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these
fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the
following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.
RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved
antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas
in Table 6 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal
instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-212019-00 with the trace antenna is far below the FCC radio frequency exposure limits.
Nevertheless, use CYBLE-212019-00 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-09764 Rev. *G
Page 30 of 39
CYBLE-212019-00
CYBLE-212023-10
Industry Canada (IC) Certification
CYBLE-212019-00 is licensed to meet the regulatory requirements of Industry Canada (IC),
License: IC: 7922A-2011
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure
compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from
www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 6 on page 13, having a maximum gain of 0.5 dBi. Antennas
not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna
impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna
or transmitter.
IC NOTICE:
The device CYBLE-212019-00 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the
requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This
device may not cause harmful interference, and (2) This device must accept any interference received, including interference that
may cause undesired operation.
IC RADIATION EXPOSURE STATEMENT FOR CANADA
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)
this device may not cause interference, and (2) this device must accept any interference, including interference that may cause
undesired operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter
tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label
on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC
Notice above. The IC identifier is 7922A-2011. In any case, the end product must be labeled in its exterior with "Contains IC:
7922A-2011"
European R&TTE Declaration of Conformity
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-212023-10 complies with the essential requirements and
other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the
Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-212019-00 in the specified reference design can be used in the following countries: Austria, Belgium,
Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-
bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
Document Number: 002-09764 Rev. *G
Page 31 of 39
CYBLE-212019-00
CYBLE-212023-10
MIC Japan
CYBLE-212019-00 is certified as a module with type certification number 203-JN0509. End products that integrate CYBLE-212023-10
do not need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-212019-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-2011.
Document Number: 002-09764 Rev. *G
Page 32 of 39
CYBLE-212019-00
CYBLE-212023-10
Packaging
Table 52. Solder Reflow Peak Temperature
Maximum Time at Peak
Module Part Number
Package
Maximum Peak Temperature
No. of Cycles
Temperature
CYBLE-2120XX-X0
31-pad SMT
260 °C
30 seconds
2
Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Module Part Number
Package
MSL
CYBLE-2120XX-X0
31-pad SMT
MSL 3
The CYBLE-2120XX-X0 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-212019-00.
Figure 10. CYBLE-2120XX-X0 Tape Dimensions
Figure 11 details the orientation of the CYBLE-2120XX-X0 in the tape as well as the direction for unreeling.
Figure 11. Component Orientation in Tape and Unreeling Direction
Document Number: 002-09764 Rev. *G
Page 33 of 39
CYBLE-212019-00
CYBLE-212023-10
Figure 12 details reel dimensions used for the CYBLE-212019-00.
Figure 12. Reel Dimensions
The CYBLE-2120XX-X0 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The
center-of-mass for the CYBLE-2120XX-X0 is detailed in Figure 13.
Figure 13. CYBLE-2120XX-X0 Center of Mass (Seen from Top)
Document Number: 002-09764 Rev. *G
Page 34 of 39
CYBLE-212019-00
CYBLE-212023-10
Ordering Information
Table 54 lists the CYBLE-2120XX-X0 part numbers and features.
Table 54. Ordering Information
CPU Flash
12-Bit
SAR
ADC
Part Number
Speed Size CapSense SCB TCPWM
(MHz) (KB)
I2S LCD Package
Packing
Certified
CYBLE-212019-00
CYBLE-212023-10
48
48
256
256
Yes
Yes
2
2
4
4
1 Msps Yes Yes 31-SMT Tape and Reel
1 Msps Yes Yes 31-SMT Tape and Reel
Yes
No
Table 55 lists the CYBLE-2120XX-X0 reel shipment quantities.
Table 55. Tape and Reel Package Quantity and Minimum Order Amount
Description
Minimum Reel Quantity Maximum Reel Quantity
Comments
Ships in 500 unit reel quantities.
Reel Quantity
500
500
500
500
–
Minimum Order Quantity (MOQ)
Order Increment (OI)
–
The CYBLE-212019-00 is offered in tape and reel packaging. The CYBLE-212019-00 ships with a maximum of 500 units/reel.
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
U.S. Cypress Headquarters Address
U.S. Cypress Headquarter Contact Info
Cypress website address
198 Champion Court, San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Document Number: 002-09764 Rev. *G
Page 35 of 39
CYBLE-212019-00
CYBLE-212023-10
Acronyms
Document Conventions
Table 56. Acronyms Used in this Document
Units of Measure
Acronym
Description
Bluetooth Low Energy
Table 57. Units of Measure
BLE
Symbol
Unit of Measure
degree Celsius
kilovolt
Bluetooth
SIG
°C
Bluetooth Special Interest Group
kV
CE
European Conformity
mA
mm
mV
A
m
MHz
GHz
V
milliamperes
millimeters
millivolt
CSA
EMI
ESD
FCC
GPIO
IC
Canadian Standards Association
electromagnetic interference
electrostatic discharge
microamperes
micrometers
megahertz
gigahertz
Federal Communications Commission
general-purpose input/output
Industry Canada
IDE
KC
integrated design environment
Korea Certification
volt
Ministry of Internal Affairs and Communications
(Japan)
MIC
PCB
RX
printed circuit board
receive
QDID
qualification design ID
surface-mount technology; a method for producing
electronic circuitry in which the components are
placed directly onto the surface of PCBs
SMT
TCPWM
TUV
timer, counter, pulse width modulator (PWM)
Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)
TX
transmit
Document Number: 002-09764 Rev. *G
Page 36 of 39
CYBLE-212019-00
CYBLE-212023-10
Document History Page
Document Title: CYBLE-212019-00/CYBLE-212023-10, EZ-BLE™ PRoC™ Module
Document Number: 002-09764
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
5086199
5148398
DSO
01/14/2016 Preliminary datasheet for CYBLE-212019-00 module.
*A
DSO
02/22/2016 Update More Information section to add KBA210638 (Certification Test Reports)
to reference list.
Update More Information section to add KBA10896 to reference list.
Updated orientation of module drawings in Figure 1, Figure 2, Figure 3, Figure 4,
Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, and Figure 13 to match orien-
tation in PSoC Creator.
Update Table 4 to add additional information with respect to the functional capabil-
ities for each solder pad.
*B
*C
5137880
5418947
MINS
DSO
04/20/2016 Updated Document Title to read as “CYBLE-212019-00/CYBLE-212023-10,
EZ-BLE™ PRoC™ Module”.
Added CYBLE-212023-10 related information in all instances across the
document.
Updated to new template.
08/30/2016 Changed status from Preliminary to Final.
Updated General Description:
Updated Module Description:
Added Bluetooth Declaration ID and QDID under “Bluetooth 4.1 single-mode
module”.
Updated Power Consumption:
Replaced “Stop: 60 nA with XRES wakeup” with “Stop: 60 nA with GPIO (P2.2)
or XRES wakeup” under “Low power mode support”.
Updated More Information:
Added additional Knowledge Base Article references.
Updated Electrical Specification:
Updated System Resources:
Updated Internal Low-Speed Oscillator:
Updated Table 49 (Updated details in “Value” column corresponding to ECOTRIM
parameter).
Updated Ordering Information:
No change in part numbers.
Added Table 55 (To specify minimum and maximum reel quantities ship for orders
of the CYBLE-2120XX-X0 module).
Updated to new template.
*D
5529621
DSO
11/15/2016 Updated More Information:
Added EZ-Serial™ BLE Firmware Platform section.
Updated Overview:
Updated Figure 1 to specify that Bottom View is “Seen from Bottom”.
Updated Recommended Host PCB Layout:
Updated Figure 4, Figure 5, and Figure 6 captions to specify that these as “Seen
on Host PCB”.
Updated Power Supply Connections and Recommended External Components:
Updated Figure 7 and Figure 8 to specify that these are “Seen from Bottom”.
Updated Digital and Analog Capabilities and Connections:
Updated Table 4:
Updated TCPWM column to add TCPWM capability on Port 2 pins.
Added Footnote 3.
*E
*F
5553544
5731446
DSO
12/14/2016 Updated Electrical Specification:
Updated SAR ADC:
Updated Table 18 to add Note 8 to specify under what conditions the maximum
number of ADC channels can be achieved.
GNKK
05/09/2017 Updated the Cypress logo.
Document Number: 002-09764 Rev. *G
Page 37 of 39
CYBLE-212019-00
CYBLE-212023-10
Document History Page
Document Title: CYBLE-212019-00/CYBLE-212023-10, EZ-BLE™ PRoC™ Module
Document Number: 002-09764
*G
6002363
DSO
12/22/2017 Updated reel dimensions in Figure 10 and Figure 12.
Document Number: 002-09764 Rev. *G
Page 38 of 39
CYBLE-212019-00
CYBLE-212023-10
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
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© Cypress Semiconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-09764 Rev. *G
Revised December 22, 2017
Page 39 of 39
相关型号:
CYBUS3384PC
Bus Driver, 2-Func, 5-Bit, True Output, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
CYPRESS
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