CYD18S36V18-250BBXC_技术文档

FullFlex

FullFlex™ Synchronous

SDR Dual-Port SRAM

— Selectable LVTTL (3.3V), Extended HSTL

(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on

each port

Features

• True dual-ported memory allows simultaneous access

to the shared array from each port

— Burst counters for sequential memory access

— Mailbox with interrupt flags for message passing

— Dual Chip Enables for easy depth expansion

• SynchronouspipelinedoperationwithSingleDataRate

(SDR) operation on each port

— SDR interface at 250 MHz

Functional Description

— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)

• Selectable pipelined or flow-through mode

• 1.5V or 1.8V core power supply

The FullFlex™ Dual-Port SRAM families consist of 4-Mbit,

9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static

RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two

ports are provided, allowing the array to be accessed simulta-

neously. Simultaneous access to a location triggers determin-

istic access control. For FullFlex72 these ports can operate

independently with 72-bit bus widths and each port can be

independently configured for two pipelined stages. Each port

can also be configured to operate in pipelined or flow-through

mode.

• Commercial and Industrial temperature

• IEEE 1149.1 JTAG boundary scan

• Available in 484-ball PBGA Packages and 256-ball

FBGA packages

• FullFlex72 family

— 36-Mbit: 512K x 72 (CYD36S72V18)

— 18-Mbit: 256K x 72 (CYD18S72V18)

— 9-Mbit: 128K x 72 (CYD09S72V18)

— 4-Mbit: 64K x 72 (CYD04S72V18)

• FullFlex36 family

Advanced features include built-in deterministic access

control to manage address collisions during simultaneous

access to the same memory location, Variable Impedance

Matching (VIM) to improve data transmission by matching the

output driver impedance to the line impedance, and echo

clocks to improve data transfer.

— 36-Mbit: 1M x 36 (CYD36S36V18)

— 18-Mbit: 512K x 36 (CYD18S36V18)

— 9-Mbit: 256K x 36 (CYD09S36V18)

— 4-Mbit: 128K x 36 (CYD04S36V18)

• FullFlex18 family

To reduce the static power consumption, chip enables can be

used to power down the internal circuitry. The number of

cycles of latency before a change in CE0 or CE1 will enable

or disable the databus matches the number of cycles of read

latency selected for the device. In order for a valid write or read

to occur, both chip enable inputs on a port must be active.

— 36-Mbit: 2M x 18 (CYD36S18V18)

— 18-Mbit: 1M x 18 (CYD18S18V18)

— 9-Mbit: 512K x 18 (CYD09S18V18)

— 4-Mbit: 256K x 18 (CYD04S18V18)

Each port contains an optional burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally.

Additional features of this device include a mask register and

• Built-in deterministic access control to manage

address collisions

a mirror register to control counter increments and

wrap-around. The counter-interrupt (CNTINT) flags notify the

host that the counter will reach maximum count value on the

next clock cycle. The host can read the burst-counter internal

address, mask register address, and busy address on the

address lines. The host can also load the counter with the

address stored in the mirror register by utilizing the retransmit

functionality. Mailbox interrupt flags can be used for message

passing, and JTAG boundary scan and asynchronous Master

Reset (MRST) are also available. The logic block diagram in

Figure 1 displays these features.

— Deterministic flag output upon collision detection

— Collision detection on back-to-back clock cycles

— First Busy Address readback

• Advanced features for improved high-speed data

transfer and flexibility

— Variable Impedance Matching (VIM)

— Echo clocks

The FullFlex72 is offered in a 484-ball plastic BGA package.

The FullFlex36 and FullFlex18 are offered in both 484-ball and

256-ball fine pitch BGA packages.

Cypress Semiconductor Corporation

Document #: 38-06082 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 21, 2006

FullFlex

FTSEL

CQEN

FTSEL

L

R

CQEN

L

R

CONFIG Block

PORTSTD[1:0]

L

R

DQ [71:0]

R

DQ[71:0]

L

BE [7:0]

R

L

CE0

R

CE0

L

IO

CE1

R

L

OE

R

Control

OE

L

R/W

R

R/W

L

CQ1

CQ0

L

CQ1

CQ0

R

L

CQ0

R

Dual Ported Array

BUSY

Collision Detection Logic

BUSY

L

R

A [20:0]

L

R

CNT/MSK

L

R

ADS

L

R

CNTEN

R

L

Address &

Counter Logic

Address &

Counter Logic

CNTRST

RET

R

L

R

RET

L

CNTINT

L

CNTINT

R

C

L

R

WRP

L

WRP

R

TRST

TMS

TDI

Mailboxes

INT

R

L

JTAG

TDO

TCK

ZQ0

L

R

ZQ1

L

R

RESET

LOGIC

MRST

READY

L

R

LowSPD

R

L

Figure 1. FullFlex72 18-Mbit (CYD18S72V18) Block Diagram^{[1, 2, 3]}

Notes:

1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and the CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18,

and the CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and the CYD04S18V18 devices have 18 address bits. The

CYD09S72V18 and the CYD04S36V18 devices have 17 address bits. The CYD04S72V18 has 16 address bits.

2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.

3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte

enables.

Document #: 38-06082 Rev. *G

Page 2 of 51

FullFlex

FullFlex72 SDR 484-ball BGA Pinout (Top View)

20 21 22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

DNU DQ61 DQ59 DQ57 DQ54 DQ51 DQ48 DQ45 DQ42 DQ39 DQ36 DQ36 DQ39 DQ42 DQ45 DQ48 DQ51 DQ54 DQ57 DQ59 DQ61 DNU

A

B

C

L

R

DQ63 DQ62 DQ60 DQ58 DQ55 DQ52 DQ49 DQ46 DQ43 DQ40 DQ37 DQ37 DQ40 DQ43 DQ46 DQ49 DQ52 DQ55 DQ58 DQ60 DQ62 DQ63

L

R

DQ65 DQ64 VSS VSS DQ56 DQ53 DQ50 DQ47 DQ44 DQ41 DQ38 DQ38 DQ41 DQ44 DQ47 DQ50 DQ53 DQ56 VSS VSS DQ64 DQ65

L

R

DQ67 DQ66 VSS VSS VSS CQ1L CQ1L

LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS VSS VSS DQ66 DQ67

[4]

VSS

L

SPDL STD0

L

NTL STD1

L

R

D

E

F

DQ69 DQ68 VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU VSS VDDI DQ68 DQ69

OL OL OL OL OL OL OR OR OR OR OR

L

R

DQ71 DQ70 CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DQ70 DQ71

OL OL OL OL OL RE RE RE RE OR OR OR OR OR

L

R

A0L A1L RETL BE4L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE4R RETR A1R A0R

OL OL OR OR

G

H

J

L

R

A2L A3L WRP BE5L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE5R WRP A3R A2R

OL OL OR OR

L

R

A4L A5L READ BE6L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE6R READ A5R A4R

YL OL OL OR OR YR

A6L A7L ZQ1L BE7L VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI BE7R ZQ1R A7R A6R

[4]

K

L

RE

OR

A8L A9L

CL

OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R

RE RE

A10L A11L VSS BE3L VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE3R VSS A11R A10R

RE RE

M

N

A12L A13L ADSL BE2L VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE2R ADSR A13R A12R

OL RE RE

A14L A15L CNT/ BE1L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT/ A15R A14R

MSKL

OL

OR

MSK

R

P

R

T

A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R

[7]

[6]

[7]

NL

OL

OR

NR

A18L DNU CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR DNU A18R

[5]

STL

OL

L

R

OR

STR

DQ35 DQ34 R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DQ34 DQ35

U

V

L

NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR

R

DQ33 DQ32 FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DQ32 DQ33

LL OL OL OL OL OL OR OR OR OR OR OR LR

L

R

DQ31 DQ30 VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS TDI TDO DQ30 DQ31

[4]

L

STD1 NTR

R

STD0 SPDR

R

W

Y

DQ29 DQ28 VSS VSS DQ20 DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DQ20 TMS TCK DQ28 DQ29

L

R

DQ27 DQ26 DQ24 DQ22 DQ19 DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DQ19 DQ22 DQ24 DQ26 DQ27

AA

L

R

DNU DQ25 DQ23 DQ21 DQ18 DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DQ18 DQ21 DQ23 DQ25 DNU

AB

L

R

Notes:

4. Leaving this pin DNU disables VIM.

5. Leave this ball unconnected for CYD18S72V18, CYD09S72V18 and CYD04S72V18.

6. Leave this ball unconnected for CYD09S72V18 and CYD04S72V18.

7. Leave this ball unconnected for CYD04S72V18.

Document #: 38-06082 Rev. *G

Page 3 of 51

FullFlex

FullFlex36 SDR 484-ball BGA Pinout (Top View)^[8]

20 21 22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

DNU DNU DNU DNU DNU DQ33 DQ30 DQ27 DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 DQ27 DQ30 DQ33 DNU DNU DNU DNU DNU

A

B

C

L

R

DNU DNU DNU DNU DNU DQ34 DQ31 DQ28 DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 DQ28 DQ31 DQ34 DNU DNU DNU DNU DNU

L

R

DNU DNU VSS VSS DNU DQ35 DQ32 DQ29 DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 DQ29 DQ32 DQ35 DNU VSS VSS DNU DNU

L

R

DNU DNU VSS VSS VSS CQ1L CQ1L

LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS VSS VSS DNU DNU

[4]

VSS

SPDL STD0

L

NTL STD1

L

D

E

F

DNU DNU VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU VSS VDDI DNU DNU

OL OL OR OR OR OR OL OL OL OL OR

DNU DNU CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DNU DNU

OL OL OR OR OR RE RE RE RE OL OL OL OR OR

A0L A1L RETL BE2L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R A0R

OL OL OR OR

G

H

J

L

R

A2L A3L WRP BE3L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R WRP A3R A2R

OL OL OR OR

L

R

A4L A5L READ DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU READ A5R A4R

YL OL OL OR OR YR

A6L A7L ZQ1L DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI DNU ZQ1R A7R A6R

[4]

K

L

RE

OR

A8L A9L

CL

OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R

RE RE

A10L A11L VSS DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU VSS A11R A10R

RE RE

M

N

A12L A13L ADSL DNU VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU ADSR A13R A12R

OL RE RE

A14L A15L CNT/ BE1L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT/ A15R A14R

MSKL

OL

OR

MSK

R

P

R

T

A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R

NL OL OL OR OR NR

A18L A19L CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R

STL OL OL OR OR STR

L

R

DNU DNU R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DNU DNU

NL OL OL OR OR OR RE RE RE RE OL OL OL OR OR NR

U

V

DNU DNU FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DNU DNU

LL OL OR OR OR OR OL OL OL OL OR OR LR

DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS TDI TDO DNU DNU

[4]

STD1 NTR

R

STD0 SPDR

R

W

Y

DNU DNU VSS VSS DNU DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DNU TMS TCK DNU DNU

L

R

DNU DNU DNU DNU DNU DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DNU DNU DNU DNU DNU

AA

AB

L

R

DNU DNU DNU DNU DNU DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DNU DNU DNU DNU DNU

L

R

Note:

8. Use this pinout only for device CYD36S36V18 of the FullFlex36 family.

Document #: 38-06082 Rev. *G

Page 4 of 51

FullFlex

FullFlex18 SDR 484-ball BGA Pinout (Top View)^[9]

20 21 22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

DNU DNU DNU DNU DNU DNU DNU DNU DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 DNU DNU DNU DNU DNU DNU DNU DNU

A

B

C

L

R

DNU DNU DNU DNU DNU DNU DNU DNU DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 DNU DNU DNU DNU DNU DNU DNU DNU

L

R

DNU DNU VSS VSS DNU DNU DNU DNU DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 DNU DNU DNU DNU VSS VSS DNU DNU

L

R

DNU DNU VSS VSS VSS CQ1L CQ1L

LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS VSS VSS DNU DNU

[4]

VSS

SPDL STD0

L

NTL STD1

L

D

E

F

DNU DNU VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU VSS VDDI DNU DNU

OL OL OR OR OR OR OL OL OL OL OR

DNU DNU CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DNU DNU

OL OL OR OR OR RE RE RE RE OL OL OL OR OR

A0L A1L RETL BE1L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE1R RETR A1R A0R

OL OL OR OR

G

H

J

L

R

A2L A3L WRP DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU WRP A3R A2R

OL OL OR OR

L

R

A4L A5L READ DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU READ A5R A4R

YL OL OL OR OR YR

A6L A7L ZQ1L DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI DNU ZQ1R A7R A6R

[4]

K

L

RE

OR

A8L A9L

CL

OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R

RE RE

A10L A11L VSS DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU VSS A11R A10R

RE RE

M

N

A12L A13L ADSL DNU VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU ADSR A13R A12R

OL RE RE

A14L A15L CNT/ DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU CNT/ A15R A14R

MSKL

OL

OR

MSK

R

P

R

T

A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R

NL OL OL OR OR NR

A18L A19L CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R

STL OL OL OR OR STR

L

R

A20L DNU R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DNU A20R

NL OL OL OR OR OR RE RE RE RE OL OL OL OR OR NR

U

V

DNU DNU FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DNU DNU

LL OL OR OR OR OR OL OL OL OL OR OR LR

DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS TDI TDO DNU DNU

[4]

STD1 NTR

R

STD0 SPDR

R

W

Y

DNU DNU VSS VSS DNU DNU DNU DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU DNU DNU DNU TMS TCK DNU DNU

DNU DNU DNU DNU DNU DNU DNU DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU DNU DNU DNU DNU DNU DNU DNU

DNU DNU DNU DNU DNU DNU DNU DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU DNU DNU DNU DNU DNU DNU DNU

AA

AB

Note:

9. Use this pinout only for device CYD36S18V18 of the FullFlex18 family.

Document #: 38-06082 Rev. *G

Page 5 of 51

FullFlex

FullFlex36 SDR 256-Ball BGA (Top View)

10 11

1

2

3

4

5

6

7

8

9

12

13

14

15

16

DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R

A

B

C

D

E

F

DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R

[4]

DQ34L DQ35L

RETL

WRPL

CE0L

INTL

CQ1L

DNU

TRST

MRST ZQ0R

CQ1R

INTR

RETR DQ35R DQ34R

A0L

A2L

A1L

A3L

VREFL FTSELL LOWSP

DL

VSS

VTTL

VTTL VSS

LOWSP FTSELR VREFR WRPR

DR

A1R

A3R

A0R

A2R

CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R

CE0R

A4L

A5L

CNTINTL BE3L VDDIOL

[4]

VSS

VSS VDDIOR BE3R CNTINTR A5R

A4R

A6L

A7L

BUSYL

BE2L

ZQ0L

VSS VDDIOR BE2R

BUSYR

CR

A7R

A9R

A6R

G

H

J

A8L

A9L

CL

VTTL VCORE

VSS

VCORE VTTL

A8R

A10L

A12L

A14L

A11L

A13L

A15L

VSS

PORTST VCORE

D1L

VCORE PORTST

D1R

VSS

A11R

A13R

A15R

A10R

A12R

A14R

A16R

OEL

BE1L VDDIOL

VSS VDDIOR BE1R

OER

ADSR

K

L

ADSL

BE0L VDDIOL

VSS VDDIOR BE0R

[11]

A16L A17L

[10]

R/WL

CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R

M

N

P

R

T

[4]

[10]

A18L

DNU

CNT/MS VREFL PORTST READYL ZQ1L

VTTL

TMS

VTTL ZQ1R

READY PORTST VREFR CNT/MS DNU A18R

KL

D0L

R

D0R

KR

DQ16L DQ17L CNTENL CNTRST CQ0L

L

CQ0L

DQ5L

DQ4L

TCK

TDO

DQ1R

DQ0R

TDI

CQ0R

CQ0R CNTRST CNTENR DQ17R DQ16R

R

DQ15L DQ13L DQ11L

DQ9L

DQ7L

DQ3L

DQ2L

DQ1L

DQ0L

DQ3R

DQ2R

DQ5R

DQ4R

DQ7R

DQ9R

DQ11R DQ13R DQ15R

DQ14L DQ12L DQ10L

DQ8L

DQ6L

DQ6R

DQ8R

DQ10R DQ12R DQ14R

Notes:

10. Leave this ball unconnected for CYD09S36V18 and CYD04S36V18.

11. Leave this ball unconnected for CYD04S36V18.

Document #: 38-06082 Rev. *G

Page 6 of 51

FullFlex

FullFlex18 SDR 256-Ball BGA (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DNU

DQ17L DQ16L DQ13L DQ12L

DQ9L

DQ9R DQ12R DQ13R DQ16R DQ17R

DNU

A

B

C

D

E

F

DNU

A0L

DNU

A1L

DNU

INTL

DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R

[4]

DNU

INTR

DNU

A1R

A3R

DNU

A0R

RETL

CQ1L

DNU

TRST

MRST ZQ0R

CQ1R

RETR

WRPL VREFL FTSELL LOWSP

DL

VSS

VTTL

VTTL VSS

LOWSP FTSELR VREFR WRPR

DR

A2L

A3L

CE0L

CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R

CE0R

A2R

A4L

A5L

CNTINTL DNU VDDIOL

[4]

VSS

VSS VDDIOR DNU CNTINTR A5R

A4R

A6L

A7L

BUSYL

DNU

ZQ0L

VSS VDDIOR DNU

BUSYR

CR

A7R

A9R

A6R

G

H

J

A8L

A9L

CL

VTTL VCORE

VSS

VCORE VTTL

A8R

A10L

A12L

A14L

A16L

A11L

A13L

A15L

A17L

VSS PORTST VCORE

D1L

VCORE PORTST

D1R

VSS

A11R

A13R

A15R

A17R

A10R

A12R

A14R

A16R

OEL

BE1L VDDIOL

VSS VDDIOR BE1R

OER

ADSR

K

L

ADSL

BE0L VDDIOL

VSS VDDIOR BE0R

R/WL

CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR

M

N

P

R

T

[13]

[12]

[4]

[12]

[13]

A18L

A19L

CNT/MS VREFL PORTST READYL ZQ1L

KL

VTTL

TMS

VTTL ZQ1R

READY PORTST VREFR CNT/MS A19R

A18R

D0L

R

D0R

KR

DNU

DNU CNTENL CNTRST CQ0L

L

CQ0L

DQ5L

DQ4L

TCK

TDO

DQ1R

DQ0R

TDI

CQ0R

CQ0R CNTRST CNTENR DNU

R

DNU

DQ6L

DQ2L

DQ3L

DQ1L

DQ0L

DQ2R

DQ3R

DQ5R

DQ4R

DQ6R

DNU

DQ8L

DQ7L

DQ7R

DQ8R

DNU

Notes:

12. Leave this ball unconnected for CYD09S18V18 and CYD04S18V18.

13. Leave this ball unconnected for CYD04S18V18.

Document #: 38-06082 Rev. *G

Page 7 of 51

FullFlex

Table 1. Selection Guide

–250

250

–200

200

–167

167

4.0

Unit

MHz

ns

[15]

f_MAX

Max. Access Time (Clock to Data)

2.64

3.3

Typical Operating Current I_CC

930^[14]

210^[14]

800^[14]

210^[14]

700^[14]

210^[14]

mA

Typical Standby Current for I_SB3(Both Ports CMOS Level)

Pin Definitions

Left Port

A[20:0]_L

Right Port

A[20:0]_R

Description

Address Inputs.^[1]

DQ[71:0]_L

BE[7:0]_L

DQ[71:0]_R

BE[7:0]_R

Data Bus Input/Output.^[2]

Byte Select Inputs.^[3]Asserting these signals enables Read and Write operations to

the corresponding bytes of the memory array.

BUSY_L

BUSY_R

Port Busy Output. When there is an address match and both chip enables are active

for both ports, an external BUSY signal is asserted on the fifth clock cycles from when

the collision occurs.

C_L

C_R

Clock Signal. Maximum clock input rate is f_MAX

.

CE0_L

CE1_L

CQEN_L

CQ0_L

CE0_R

CE1_R

CQEN_R

CQ0_R

Active LOW Chip Enable Input.

Active HIGH Chip Enable Input.

Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.

Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal

Output for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for

FullFlex18 devices.

CQ0_L

CQ0_R

Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Inverted

Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock

Signal Output for DQ[8:0] for FullFlex18 devices.

CQ1_L

CQ1_R

Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal

Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9]

for FullFlex18 devices.

CQ1_L

CQ1_R

Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Inverted

Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock

Signal Output for DQ[17:9] forFullFlex18 devices.

ZQ[1:0]_L

ZQ[1:0]_R

VIM Output Impedance Matching Input. To use, connect a calibrating resistor

between ZQ and ground. The resistor must be five times larger than the intended line

impedance driven by the dual-port. Assert HIGH or leave DNU to disable Variable

Impedance Matching.

OE_L

INT_L

OE_R

INT_R

Output Enable Input. This asynchronous signal must be asserted LOW to enable the

DQ data pins during Read operations.

Mailbox Interrupt Flag Output. The mailbox permits communications between ports.

The upper two memory locations can be used for message passing. INT_Lis asserted

LOW when the right port writes to the mailbox location of the left port, and vice versa.

An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.

LowSPD_L

LowSPD_R

Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation

at less than 100 MHz, assert this pin LOW.

[16]

PORTSTD[1:0]_L

PORTSTD[1:0]_R

Port Clock/Address/Control/Data/Echo Clock/I/O Standard Select Input. Assert

these pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS,

and HIGH/HIGH for 1.8V LVCMOS, respectively. These pins must be driven by VTTL

referenced levels.

Notes:

14. For 18-Mbit x72 commercial configuration only, please refer to the electrical characteristics section for complete information.

15. SDR mode with two pipelined stages.

16. PORTSTD[1:0] and PORTSTD[1:0] have internal pull-down resistors.

L

R

Document #: 38-06082 Rev. *G

Page 8 of 51

FullFlex

Pin Definitions (continued)

Left Port

R/W_L

Right Port

Description

R/W_R

Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the

dual-port memory array.

READY_L

READY_R

Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable

Impedance Matching circuits have completed calibration. This is a wired OR capable

output.

CNT/MSK_L

ADS_L

CNT/MSK_R

ADS_R

Port Counter/Mask Select Input. Counter control input.

Port Counter Address Load Strobe Input. Counter control input.

Port Counter Enable Input. Counter control input.

Port Counter Reset Input. Counter control input.

CNTEN_L

CNTRST_L

CNTINT_L

CNTEN_R

CNTRST_R

CNTINT_R

Port Counter Interrupt Output. This pin is asserted LOW one cycle before the

unmasked portion of the counter is incremented to all “1s”.

WRP_L

RET_L

WRP_R

RET_R

Port Counter Wrap Input. When the burst counter reaches the maximum count, on

the next counter increment WRP can be set LOW to load the unmasked counter bits

to 0 or set HIGH to load the counter with the value stored in the mirror register.

Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for

repeated access to the same segment of memory.

VREF_L

VREF_R

VDDIO_R

FTSEL_R

Port External HSTL I/O Reference Input. This pin is left DNU when HSTL is not used.

Port Data I/O Power Supply.

VDDIO_L

FTSEL_L

Port Flow-through Mode Select Input. Assert this pin LOW to select Flow-through

mode. Assert this pin HIGH to select Pipelined mode.

MRST

Master Reset Input. MRST is an asynchronous input signal and affects both ports.

Asserting MRST LOW performs all of the reset functions as described in the text. A

MRST operation is required at power-up. This pin must be driven by a VDDIO_Lrefer-

enced signal.

TMS

TDI

JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.

State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V

LVCMOS.

JTAG Test Data Input. Data on the TDI input will be shifted serially into selected

registers. Operation for LVTTL or 2.5V LVCMOS.

TRST

TCK

JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.

JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.

TDO

JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is

normally three-stated except when captured data is shifted out of the JTAG TAP.

Operation for LVTTL or 2.5V LVCMOS.

VSS

VCORE

VTTL

Ground Inputs.

Device Core Power Supply.

LVTTL Power Supply.

Selectable I/O Standard

Table 2. Port Standard Selection

The FullFlex device families also offer the option of choosing

one of four port standards for the device. Each port can

independently select standards from single-ended HSTL class

I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The

selection of the standard is determined by the PORTSTD pins

for each port. These pins should be connected to either an

LVTTL or 2.5V LVCMOS power suppy. This will determine the

input clock, address, control, data, and Echo clock standard

for each port as shown in Table 2. Please note that only 1.8V

LVCMOS and HSTL are supported for 4-Mbit, 9-Mbit, 18-Mbit

devices running at 250 MHz, and for 36-Mbit devices running

at 200 MHz.

PORTSTD1

VSS

PORTSTD0

VSS

I/O Standard

LVTTL

VSS

VTTL

HSTL

VTTL

VSS

2.5V LVCMOS

1.8V LVCMOS

VTTL

Clocking

Separate clocks synchronize the operations on each port.

Each port has one clock input C. In this mode, all the transac-

tions on the address, control, and data will be on the C rising

Document #: 38-06082 Rev. *G

Page 9 of 51

FullFlex

edge. All transactions on the address, control, data input,

output, and byte enables will occur on the C rising edge.

clock is associated with half the data bits. The output clock will

match the corresponding ports I/O configuration.

To enable Echo clock outputs, tie CQEN HIGH. To disable

Echo clock outputs, tie CQEN LOW.

Table 3. Data Pin Assignment

BE Pin Name

BE[7]

Data Pin Name

DQ[71:63]

DQ[62:54]

DQ[53:45]

DQ[44:36]

DQ[35:27]

DQ[26:18]

DQ[17:9]

Input Clock

Data Out

BE[6]

BE[5]

Echo Clock

BE[4]

Echo Clock

BE[3]

Figure 2. SDR Echo Clock Delay

BE[2]

Deterministic Access Control

BE[1]

Deterministic Access Control is provided for ease of design.

The circuitry detects when both ports are accessing the same

location and provides an external BUSY flag to the port on

which data may be corrupted. The collision detection logic

saves the address in conflict (Busy Address) to a readable

register. In the case of multiple collisions, the first Busy

address will be written to the Busy Address register.

BE[0]

DQ[8:0]

Selectable Pipelined/Flow-through Mode

To meet data rate and throughput requirements, the FullFlex

families offer selectable pipelined or flow-through mode. Echo

clocks are not supported in flow-through mode and the DLL

must be disabled.

If both ports are accessing the same location at the same time

and only one port is doing a write, if t_CCSis met, then the data

being written to and read from the address is valid data. For

example, if the right port is reading and the left port is writing

and the left ports clock meets t_CCS, then the data being read

from the address by the right port will be the old data. In the

same case, if the right ports clock meets t_CCS, then the data

being read out of the address from the right port will be the new

data. In the above case, if t_CCSis violated by the either ports

clock with respect to the other port and the right port gets the

external BUSY flag, the data from the right port is corrupted.

Table 4 shows the t_CCStiming that must be met to guarantee

the data.

Flow-through mode is selected by the FTSEL pin. Strapping

this pin HIGH selects pipelined mode. Strapping this pin LOW

selects flow-through mode.

DLL

The FullFlex familes of devices have an on-chip DLL. Enabling

the DLL reduces the clock to data valid (t_CD) time allowing

more set-up time for the receiving device. For operation below

100 MHz, the DLL must be disabled. This is selectable by

strapping LowSPD low.

Whenever the operating frequency is altered beyond the Clock

Input Cycle to Cycle Jitter spec, the DLL is required to be reset

followed by 1024 clocks before any valid operation.

Table 5 shows that, in the case of the left port writing and the

right port reading, when an external BUSY flag is asserted on

the right port, the data read out of the device will not be

guaranteed.

LowSPD pins can be used to reset the DLL(s) for a single port

independent of all other circuitry. MRST can be used to reset

all DLLs on the chip, for information on DLL lock and reset

time, please see the Master Reset section below.

The value in the busy address register can be read back to the

address lines. The required input control signals for this

function are shown in Table 8. The value in the busy address

register will be read out to the address lines t_CAafter the same

amount of latency as a data read operation. After an initial

address match, the BUSY flag is asserted and the address

under contention is saved in the busy address register. All

following address matches cause the BUSY flag to be

generated, however, none of the addresses are saved into the

busy address register. Once a busy readback is performed,

the address of the first match that happens at least two clocks

cycles after the busy readback is saved into the busy address

register.

Echo Clocking

As the speed of data increases, on-board delays caused by

parasitics make providing accurate clock trees extremely

difficult. To counter this problem, the FullFlex families incor-

porate Echo Clocks. Echo Clocks are enabled on a per port

basis. The dual-port receives input clocks that are used to

clock in the address and control signals for a read operation.

The dual-port retransmits the input clocks relative to the data

output. The buffered clocks are provided on the CQ1/CQ1 and

CQ0/CQ0 outputs. Each port has a pair of Echo clocks. Each

Table 4. t_CCSTiming for All Operating Modes

Port A—Early Arriving Port Port B—Late Arriving Port

t_CCS

Mode

Active Edge

Mode

Active Edge

Unit

C Rise to Opposite C Rise Set-up Time for Non-corrupt Data

SDR

C

SDR

C

t_CYC(min)– 0.5

ns

Document #: 38-06082 Rev. *G

Page 10 of 51

FullFlex

Table 5. Deterministic Access Control Logic

Left Port Right Port Left Clock Right Clock

BUSY_L

BUSY_R

Description

Read

Write

Read

X

0

H

L

H

L

No Collision

>t_CCS

0

Read OLD Data

Read NEW Data

Read OLD Data

>t_CCS

0

<t_CCS

Data Not Guaranteed

Read NEW Data

0

<t_CCS

H

L

Data Not Guaranteed

Read NEW Data

Read

Write

>t_CCS

0

>t_CCS

0

H

L

Read OLD Data

<t_CCS

Read NEW Data

Data Not Guaranteed

Read OLD Data

0

<t_CCS

H

L

Data Not Guaranteed

Array Data Corrupted

Array Stores Right Port Data

Array Stores Left Port Data

Write

0

>–t_CCS& <t_CCS

L

>t_CCS

0

L

H

L

>t_CCS

H

Table 7. Variable Impedance Matching Operation

RQ Connection Output Configuration

Variable Impedance Matching (VIM)

Each port contains a Variable Impedance Matching circuit to

set the impedance of the I/O driver to match the impedance of

the on-board traces. The impedance is set for all outputs

except JTAG and is done on a per port basis. To take

advantage of the VIM feature, connect a calibrating resistor

(RQ) that is five times the value of the intended line impedance

from the ZQ pin to VSS. The output impedance is then

adjusted to account for drifts in supply voltage and temper-

ature every 1024 clock cycles. If a port’s clock is suspended,

the VIM circuit will retain its last setting until the clock is

restarted. On restart, it will then resume periodic adjustment.

In the case of a significant change in device temperature or

supply voltage, recalibration will happen every 1024 clock

cycles. A Master Reset will initialize the VIM circuitry. Table 6

shows the VIM parameters and Table 7 describes the VIM

operation modes.

100Ω - 275Ω to VSS Output Driver Impedance = RQ/5 ±

15% at Vout = VDDIO/2

ZQ to VDDIO

VIM Disabled. Rout < 20Ω at Vout =

VDDIO/2

Address Counter and Mask Register Operations^[1]

Each port of the FullFlex family contains a programmable burst

address counter. The burst counter contains four registers: a

counter register, a mask register, a mirror register, and a busy

address register.

The counter register contains the address used to access the

RAM array. It is changed only by the master reset (MRST),

Counter Reset, Counter Load, Retransmit, and Counter

Increment operations.

In order to disable VIM, the ZQ pin must be connected to

VDDIO of the relative supply for the I/Os before a Master

Reset.

The mask register value affects the Counter Increment and

Counter Reset operations by preventing the corresponding

bits of the counter register from changing. It also affects the

counter interrupt output (CNTINT). The mask register is only

changed by Mask Reset, Mask Load, and MRST. The Mask

Load operation loads the value of the address bus into the

mask register. The mask register defines the counting range

of the counter register. The mask register is divided into two or

three consecutive regions. Zero or more “0s” define the

masked region and one or more “1s” define the unmasked

portion of the counter register. The counter register may only

be divided into up to three regions. The region containing the

least significant bits must be no more than two “0s”. Bits one

and zero may be “10” respectively, masking the least signif-

icant counter bit and causing the counter to increment by two

instead of one. If bits one and zero are “00”, the two least

significant bits are masked and the counter will increment by

four instead of one. For example, in the case of a 256Kx72

Table 6. Variable Impedance Matching Parameters

Parameter

RQ Value

Min. Max.

Unit

Ω

Tolerance

± 2%

100

20

275

55

Output Impedance

Reset Time

Ω

± 15%

N/A

N/A 1024 Cycles

Update Time

N/A

Document #: 38-06082 Rev. *G

Page 11 of 51

FullFlex

configuration, a mask register value of 003FC divides the

mask register into three regions. With bit 0 being the least

significant bit and bit 17 being the most significant bit, the two

least significant bits are masked, the next eight bits are

unmasked, and the remaining bits are masked.

1FFFFE, 07FFFF, and 003FFC are permitted values but

02FFFF, 003FFA, and 07FFE4 are not.

Counter Readback Operation

The internal value of the counter register can be read out on

the address lines. The address will be valid t_CAafter the

selected number of latency cycles configured by FTSEL. The

data bus (DQ) is tri-stated on the cycle that the address is

presented on the address lines. Figure 3 shows a block

diagram of this logic.

The mirror register is used to reload the counter register on

retransmit operations (see “retransmit” below) and wrap

functions (see “counter increment” below). The last value

loaded into the counter register is stored in the mirror register.

The mirror register is only changed by master reset (MRST),

Counter Reset, and Counter Load.

Mask Readback Operation

Table 8 summarizes the operations of these registers and the

required input control signals. All signals except MRST are

synchronized to the ports clock.

The internal value of the mask register can be read out on the

address lines. The address will be valid t_CAafter the selected

number of latency cycles configured by FTSEL. The data bus

(DQ) is tri-stated on the cycle that the address is presented on

the address lines. Figure 3 shows a block diagram of the

operation.

Counter Load Operation^[1]

The address counter and mirror registers are both loaded with

the address value presented on the address lines. This value

ranges from 0 to 1FFFFF.

Counter Reset Operation

Mask Load Operation^[1]

All unmasked bits of the counter and mirror registers are reset

to “0”. All masked bits remain unchanged. A mask reset

followed by a counter reset will reset the counter and mirror

registers to 00000.

The mask register is loaded with the address value presented

on the address bus. This value ranges from 0 to 1FFFFF

though not all values permit correct increment operations.

Permitted values are in the form of 2ⁿ–1, 2ⁿ–2, or 2ⁿ–4. The

counter register can only be segmented in up to three regions.

From the most significant bit to the least significant bit,

permitted values have zero or more “0s”, one or more “1s”, and

the least significant two bits can be “11”, “10”, or “00”. Thus

Mask Reset Operation

The mask register is reset to all “1s”, which unmasks every bit

of the burst counter.

Document #: 38-06082 Rev. *G

Page 12 of 51

FullFlex

Table 8. Burst Counter and Mask Register Control Operation (Any Port) ^{[17, 18]}

C

MRST CNTRST CNT/MSK CNTEN ADS RET

Operation

Description

X

L

X

Master Reset Reset address counter to all 0s, mask register

to all 1s, and busy address to all 0’s.

H

L

H

X

Counter Reset Reset counter and mirror unmasked portion to

all 0s.

H

L

X

L

X

L

X

Mask Reset

Reset mask register to all 1s.

H

Counter Load Load burst counter and mirror with external

address value presented on address lines.

H

L

X

Mask Load

Load mask register with value presented on the

address lines.

H

L

H

L

Retransmit

Load counter with value in the mirror register

Internally increment address counter value.

H

Counter

Increment

H

L

H

L

H

L

Counter Hold Constantly hold the address value for multiple

clock cycles.

Counter

Readback

Read out counter internal value on address

lines.

L

Mask

Read out mask register value on address lines.

Readback

L

H

Busy Address Read out first busy address after last busy

Readback

address readback

H

L

H

L

X

L

Reserved

L

H

L

H

L

H

L

Notes:

17. “X” = “Don’t Care”, “H” = HIGH, “L” = LOW.

18. Counter operation and mask register operation is independent of chip enables.

Document #: 38-06082 Rev. *G

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FullFlex

Increment Operation^[1]

Retransmit

Once the address counter is initially loaded with an external

address, the counter can internally increment the address

value and address the entire memory array. Only the

unmasked bits of the counter register are incremented. In

order for a counter bit to change, the corresponding bit in the

mask register must be “1”. If the two least significant bits of the

mask register are “11”, the burst counter will increment by one.

If the two least significant bits are “10”, the burst counter will

increment by two, and if they are “00”, the burst counter will

increment by four. If all unmasked counter bits are incre-

mented to “1” and WRP is deasserted, the next increment will

wrap the counter back to the initially loaded value. The cycle

before the increment that results in all unmasked counter bits

to become “1s”, a counter interrupt flag (CNTINT) is asserted

if the counter is incremented again. This increment will cause

the counter to reach its maximum value and the next increment

will return the counter register to its initial value that was stored

in the mirror register if WRP is deasserted. If WRP is asserted,

the unmasked portion of the counter is filled with “0” instead.

The example shown in Figure 4 shows an example of the

CYDD36S18V18 device with the mask register loaded with a

mask value of 00007F unmasking the seven least significant

bits. Setting the mask register to this value allows the counter

to access the entire memory space. The address counter is

then loaded with an initial value of 000005 assuming WRP is

deasserted. The masked bits, the seventh address through the

twenty-first address, do not increment in an increment

operation. The counter address will start at address 000005

and will increment its internal address value until it reaches the

mask register value of 00007F. The counter wraps around the

memory block to location 000005 at the next count. CNTINT

is issued when the counter reaches the maximum –1 count.

Retransmit allows repeated access to the same block of

memory without the need to reload the initial address. An

internal mirror register stores the address counter value last

loaded. While RET is asserted low, the counter will continue to

wrap back to the value in the mirror register independent of the

state of WRP.

Counter Interrupt

The counter interrupt (CNTINT) is asserted LOW one clock

cycle before an increment operation that results in the

unmasked portion of the counter register being all “1s”. It is

deasserted by counter reset, counter load, mask reset, mask

load, and MRST.

Counting by Two

When the two least significant bits of the mask register are

“10,” the counter increments by two.

Counting by Four

When the two least significant bits of the mask register are

“00”, the counter increments by four.

Mailbox Interrupts

The upper two memory locations can be used for message

passing and permit communications between ports. Table 9

shows the interrupt operation for both ports. The highest

memory location is the mailbox for the right port and the

maximum address – 1 is the mailbox for the left port.

When one port Writes to the other port’s mailbox, the INT flag

of the port that the mailbox belongs to is asserted LOW. The

INT flag remains asserted until the mailbox location is read by

the other port. When a port reads its mailbox, the INT flag is

deasserted high after one cycle of latency with respect to the

input clock of the port to which the mailbox belongs and is

independent of OE.

Hold Operation

The value of all three registers can be constantly maintained

unchanged for an unlimited number of clock cycles. Such

operation is useful in applications where wait states are

needed, or when address is available a few cycles ahead of

data in a shared bus interface.

Table 9 shows that in order to set the INT_Rflag, a Write

operation by the left port to address 1FFFFF will assert INT_R

LOW. A valid Read of the 1FFFFF location by the right port will

reset INT_RHIGH after one cycle of latency with respect to the

right port’s clock. At least one byte enable has to be activated

to set or reset the mailbox interrupt.

Document #: 38-06082 Rev. *G

Page 14 of 51

FullFlex

CNT/MSK

CNTEN

A

Decode

Logic

CNTRST

RET

MRST

A

C

Mask

Register

Counter/

Address

Register

Address

Decode

RAM

Array

Load/Increment

20

From

Address

Lines

Mirror

Counter

To Readback

and Address

Decode

1

0

1

0

From

Increment

Logic

Mask

Register

20

Wrap

20

From

Mask

Bit 0

and 1

From

Counter

+1

+2

+4

Wrap

Detect

Wrap

To

1

0

20

1

0

Counter

Figure 3. Counter, Mask, and Mirror Logic Block Diagram^[1]

Document #: 38-06082 Rev. *G

Page 15 of 51

FullFlex

CNTINT

H

Example:

Load

Counter-Mask

0

0s

1

0

Register = 00007F

2²⁰2¹⁹

2⁶2⁵2⁴2³2²2¹2⁰

Unmasked Address

2⁷

Masked Address

Mask

Register

LSB

Load

Address

Counter = 000005

H

L

X

Xs

0

1

0

1

X

2²⁰2¹⁹

2⁶2⁵2⁴2³2²2¹2⁰

Address

Counter

LSB

2⁷

Max

Address

Value

X

1

1 1

1

2²⁰2¹⁹

2⁶2⁵2⁴2³2²2¹2⁰

Max + 1

Address

Value

H

X

0

1

0

1

X

2²⁰2¹⁹

2⁶2⁵2⁴2³2²2¹2⁰

Figure 4. Programmable Counter-Mask Register Operation with WRP deasserted^{[1, 22]}

Table 9. Interrupt Operation Example^{[1, 17, 19, 20, 21]}

Left Port

A_0L–20L

Right Port

A_0R–20R

Function

Set Right INT_RFlag

Reset Right INT_RFlag

Set Left INT_LFlag

R/W_L

CE_L

L

INT_L

X

R/W_R

CE_R

X

INT_R

L

X

H

Max. Address

X

H

L

X

L

Max. Address

Max. Address–1

X

H

X

L

X

Reset Left INT_LFlag

L

Max. Address–1

H

X

Master Reset

OR capable output with a strong pull-up and weak pull-down.

Up to four outputs may be connected together. For faster

pull-down of the signal, connect a 250 Ohm resistor to VSS. If

the DLL and VIM circuits are disabled for a port, the port will

be operational within five clock cycles. However, the READY

will be asserted within 160 clock cycles.

The FullFlex family of Dual-Ports undergo a complete reset

when MRST is asserted. MRST must be driven by VDDIO_L

referenced levels. The MRST can be asserted asynchronously

to the clocks and must remain asserted for at least t_RS. Once

asserted MRST deasserts READY, initializes the internal burst

counters, internal mirror registers, and internal Busy

Addresses to zero, and initializes the internal mask register to

all “1s”. All mailbox interrupts (INT), Busy Address Outputs

(BUSY), and burst counter interrupts (CNTINT) are

deasserted upon master reset. Additionally, MRST must not

be released until all power supplies including VREF are fully

ramped, all port clocks and mode select inputs (LOWSPD, ZQ,

CQEN, DDRON, FTSEL, and PORTSTD) are valid and stable.

This begins calibration of the DLL and VIM circuits. READY

will be asserted within 1024 clock cycles. READY is a wired

IEEE 1149.1 Serial Boundary Scan (JTAG)

The FullFlex families incorporate an IEEE 1149.1 serial

boundary scan test access port (TAP). The TAP operates

using JEDEC-standard 3.3V or 2.5V I/O logic levels depending

on the VTTL power supply. It is composed of four input

connections and one output connection required by the test

logic defined by the standard.

Notes:

19. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and

0

1

can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge.

20. OE is “Don’t Care” for mailbox operation.

21. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.

22. The “X” in this diagram represents the counter’s upper bits.

Document #: 38-06082 Rev. *G

Page 16 of 51

FullFlex

Table 10.JTAG IDCODE Register Definitions

Table 11.Scan Registers Sizes

Part Number

CYD36S72V18

CYD36S36V18

CYD36S18V18

CYD18S72V18

CYD18S36V18

CYD18S18V18

CYD09S72V18

CYD09S36V18

CYD09S18V18

CYD04S72V18

CYD04S36V18

CYD04S18V18

Configuration

512Kx72

1024Kx36

2048Kx36

256Kx72

512Kx36

1024Kx18

128Kx72

256Kx36

512Kx18

64Kx72

Value

0C026069h (x2)

0C023069h

0C024069h

0C025069h

0C026069h

0C027069h

0C028069h

0C029069h

0C02A069h

0C02B069h

0C02C069h

0C02D069h

Register Name

Instruction

Bit Size

4

1

Bypass

Identification

Boundary Scan

32

n^[23]

128Kx36

256Kx18

Table 12.Instruction Identification Codes

Instruction Code

EXTEST

Description

0000

1111

1011

0111

Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.

Places the BYR between TDI and TDO.

BYPASS

IDCODE

HIGHZ

Loads the IDR with the vendor ID code and places the register between TDI and TDO.

Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers

to a High-Z state.

CLAMP

0100

Controls boundary to 1/0. Places BYR between TDI and TDO.

SAMPLE/PRELOAD 1000

Captures the input/output ring contents. Places BSR between TDI and TDO.

RESERVED

All other codes Other combinations are reserved. Do not use other than the above.

Note:

23. Details of the boundary scan length can be found in the BSDL file for the device.

Document #: 38-06082 Rev. *G

Page 17 of 51

FullFlex

Maximum Ratings

Operating Range

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Range

Ambient Temperature

VCORE

Commercial

0°C to +70°C

1.8V ± 100 mV

1.5V ± 80 mV

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Industrial

–40°C to +85°C

1.8V ± 100 mV

1.5V ± 80 mV

Supply Voltage to Ground Potential.............. –0.5V to + 4.1V

Power Supply Requirements

DC Voltage Applied to

Outputs in High-Z State.......................–0.5V to V_DDIO+ 0.5V

Min.

Typ.

Max.

3.6V

2.7V

1.9V

3.6V

2.7V

0.95V

DC Input Voltage.................................–0.5V to V_DDIO+ 0.5V

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage...........................................> 2200V

(JEDEC JESD8-6, JESD8-B)

LVTTL VDDIO

2.5V LVCMOS VDDIO

HSTL VDDIO

3.0V

2.3V

1.4V

1.7V

3.0V

2.3V

0.68V

3.3V

2.5V

1.5V

1.8V

3.3V

2.5V

0.75V

1.8V LVCMOS VDDIO

3.3V VTTL

Latch-up Current.....................................................> 200 mA

2.5V VTTL

HSTL VREF

Electrical Characteristics Over the Operating Range

All Speed Bins^[24]

Typ.

Unit

Parameter

Description

Configuration

Min.

Max.

V_OH

Output HIGH Voltage

(V_DDIO= Min., I_OH= –8 mA)

LVTTL

2.4^[25]

V

(V_DDIO= Min., I_OH= –4 mA)

(V_DDIO= Min., I_OH= –6 mA)

(V_DDIO= Min., I_OH= –4 mA)

HSTL (DC)^[26]

HSTL (AC)^[26]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

VDDIO – 0.4^[25]

VDDIO – 0.5^[25]

1.7^[25]

V

VDDIO – 0.45^[25]

V_OL

Output HIGH Voltage

0.4^[25]

(V_DDIO= Min., I_OL= 8 mA)

(V_DDIO= Min., I_OL= 4 mA)

(V_DDIO= Min., I_OL= 6 mA)

(V_DDIO= Min., I_OL= 4 mA)

Input HIGH Voltage

HSTL(DC)^[26]

HSTL (AC)^[26]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

HSTL(DC)^[26]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

0.4^[25]

0.5^[25]

0.7^[25]

V

0.45^[25]

V_IH

2

VREF + 0.1

1.7

VDDIO + 0.3

1.26

V_IL

Input LOW Voltage

–0.3

0.8

HSTL(DC)^[26]

2.5V LVCMOS

1.8V LVCMOS

–0.3

VREF – 0.1

0.7

0.36

Notes:

24. LVTTL and 2.5V LVCMOS are not available for 4-Mbit, 9-Mbit, 18-Mbit devices running at 250 MHz and 36-Mbit devices running at 200 MHz.

25. These parameters are met with VIM disabled.

26. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed. AC VIH/VIL in HSTL mode

are measured with 1V/ns input edge rates

Document #: 38-06082 Rev. *G

Page 18 of 51

FullFlex

Electrical Characteristics Over the Operating Range (continued)

All Speed Bins^[24]

Typ.

Unit

Parameter

Description

Configuration

Min.

Max.

Output HIGH Voltage

(V_DDIO= Min., I_OH= –24 mA)

LVTTL

2.7^[25]

V

READY

V_OH

(V_DDIO= Min., I_OH= –12 mA)

(V_DDIO= Min., I_OH= –15 mA)

(V_DDIO= Min., I_OH= –12 mA)

HSTL(DC)^[26]

HSTL (AC)^[26]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

VDDIO – 0.4^[25]

VDDIO – 0.5^[25]

2.0^[25]

V

VDDIO – 0.45^[25]

Output HIGH Voltage

0.4^[25]

V

READY

V_OL

(V_DDIO= Min., I_O= 0.12 mA)

(V_DDIO= Min., I_OL= 0.12 mA)

(V_DDIO= Min., I_OL= 0.15 mA)

(V_DDIO= Min., I_OL= 0.08 mA)

Output Leakage Current

HSTL(DC)^[26]

HSTL (AC)^[26]

2.5V LVCMOS

1.8V LVCMOS

0.4^[25]

0.5^[25]

0.7^[25]

0.45^[25]

10

V

I_OZ

I_IX1

–10

µA

Input Leakage Current Except

TDI, TMS, MRST

10

I_IX2

I_IX3

Input Leakage Current TDI,

TMS, MRST

–300

–10

10

µA

Input Leakage Current

PORTSTD, DDRON

300

Document #: 38-06082 Rev. *G

Page 19 of 51

FullFlex

Electrical Characteristics Over the Operating Range

–250^[24]

–200^[24]

–167

–133

Parameter

Description

Configuration Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I_CC

Operating Current

(V_CORE= Max.,I_OUT= 0 mA)

Outputs Disabled

512Kx72 Com. N/A

Ind. N/A

N/A 1440 1800 1280 1620 1120 1430 mA

N/A N/A N/A 1330 1730 1170 1550 mA

N/A 1180 1500 1050 1350 930 1220 mA

N/A N/A N/A 1110 1470 980 1330 mA

N/A 1130 1430 1000 1290 890 1160 mA

N/A N/A N/A 1060 1410 940 1280 mA

980 700

820 1030 730

1024Kx36 Com. N/A

Ind. N/A

2048Kx18 Com. N/A

Ind. N/A

256Kx72 Com. 930 1140 800

880

930

720

780

690

750

700

740

570

600

580

610

650

680

520

530

550

N/A

mA

Ind. N/A

512Kx36 Com. 750

Ind. N/A

N/A

920

N/A

880

N/A

930

N/A

740

N/A

770

N/A

880

N/A

690

N/A

720

N/A

640

670

610

640

660

540

550

570

620

630

510

520

530

540

800

860

770

830

790

830

640

670

660

690

740

770

590

600

610

620

570

590

540

570

560

580

470

490

480

500

540

550

450

460

470

1024Kx18 Com. 710

Ind. N/A

128Kx72 Com. 770

Ind. N/A

256Kx36 Com. 630

Ind. N/A

512Kx18 Com. 660

Ind. N/A

64Kx72 Com. 740

Ind. N/A

128Kx36 Com. 610

Ind. N/A

256Kx18 Com. 630

Ind. N/A

Document #: 38-06082 Rev. *G

Page 20 of 51

FullFlex

Electrical Characteristics Over the Operating Range (continued)

–250^[24]

–200^[24]

–167

–133

Parameter

Description

Standby Current

(Both Ports TTL Level)

Configuration Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I_SB1

512Kx72 Com. N/A

Ind. N/A

N/A 1000 1250 920 1160 830 1060 mA

N/A N/A 970 1260 880 1170 mA

910 1140 820 1050 740 960 mA

N/A N/A 880 1160 790 1080 mA

890 1110 810 1030 730 940 mA

860 1140 780 1050 mA

N/A

700

N/A

640

N/A

620

N/A

560

N/A

500

N/A

520

N/A

520

N/A

450

N/A

470

N/A

CE_Land CE_R≥ V_IH, f = f_MAX

1024Kx36 Com. N/A

Ind. N/A

2048Kx18 Com. N/A

Ind. N/A

N/A

500

530

460

480

450

470

400

420

380

390

410

380

390

360

370

N/A

630

680

570

630

560

610

490

540

440

470

460

480

450

480

400

410

420

256Kx72 Com. 570

Ind. N/A

460

490

410

440

410

430

360

380

340

360

350

370

340

350

320

330

320

330

580

630

530

580

520

570

450

490

400

430

410

440

400

430

360

370

380

N/A

mA

512Kx36 Com. 520

Ind. N/A

1024Kx18 Com. 500

Ind. N/A

128Kx72 Com. 460

Ind. N/A

256Kx36 Com. 430

Ind. N/A

512Kx18 Com. 450

Ind. N/A

64Kx72 Com. 440

Ind. N/A

128Kx36 Com. 410

Ind. N/A

256Kx18 Com. 420

Ind. N/A

Document #: 38-06082 Rev. *G

Page 21 of 51

FullFlex

Electrical Characteristics Over the Operating Range (continued)

–250^[24]

–200^[24]

–167

–133

Parameter

Description

Standby Current

(One Port TTL or CMOS

Level)

Configuration Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I_SB2

512Kx72 Com. N/A

Ind. N/A

N/A 1300 1570 1160 1410 1020 1260 mA

N/A N/A N/A 1210 1520 1070 1370 mA

N/A 1090 1330 980 1210 870 1100 mA

N/A N/A N/A 1030 1330 920 1210 mA

N/A 1040 1270 930 1160 830 1050 mA

980 1270 880 1160 mA

1024Kx36 Com. N/A

Ind. N/A

CE_L| CE_R≥ V_IH, f = f_MAX

2048Kx18 Com. N/A

Ind. N/A

N/A

890

N/A

760

N/A

730

N/A

730

N/A

610

N/A

620

N/A

680

N/A

560

N/A

570

N/A

650

680

550

570

520

550

520

550

460

480

460

480

500

510

440

450

440

450

N/A

790

840

670

730

640

690

630

670

530

560

530

560

580

610

480

500

490

500

256Kx72 Com. 760

Ind. N/A

580

610

490

520

470

490

460

480

400

430

410

430

440

450

380

390

400

710

760

610

670

580

640

560

610

470

500

480

510

550

420

440

430

450

N/A

mA

512Kx36 Com. 630

Ind. N/A

1024Kx18 Com. 600

Ind. N/A

128Kx72 Com. 620

Ind. N/A

256Kx36 Com. 540

Ind. N/A

512Kx18 Com. 550

Ind. N/A

64Kx72 Com. 590

Ind. N/A

128Kx36 Com. 510

Ind. N/A

256Kx18 Com. 520

Ind. N/A

Document #: 38-06082 Rev. *G

Page 22 of 51

FullFlex

Electrical Characteristics Over the Operating Range

All Speed Bins^[24]

Parameter

I_SB3

Description

Standby Current

(Both Ports CMOS Level)

Configuration

Com.

Typ.

410

460

410

460

410

460

210

230

210

230

210

230

150

170

150

170

150

170

130

140

130

140

130

140

Max.

590

700

590

700

590

700

300

350

300

350

300

350

200

220

200

220

200

220

150

170

150

170

150

170

Unit

mA

512Kx72

1024Kx36

2048Kx18

256Kx72

512Kx36

1024Kx18

128Kx72

256Kx36

512Kx18

64Kx72

Ind.

Com.

Ind.

CE_Land CE_R≥ V_CORE– 0.2V, f = 0

Com.

Ind.

Com.

Ind.

Com.

Ind.

Com.

Ind.

Com.

Ind.

Com.

Ind.

Com.

Ind.

Com.

Ind.

128Kx36

256Kx18

Com.

Ind.

Com.

Ind.

Table 13.Capacitance

Signals

Packages

CYDD36S72V18

CYDD18S72V18

CYDD09S72V18

CYDD04S72V18

CYDD18S36V18

CYDD09S36V18

CYDD04S36V18

CYDD18S18V18

CYDD09S18V18

CYDD04S18V18

CYDD36S18V18

CYDD36S36V18

OE

12 pF

10 pF

12 pF

18 pF

10 pF

20 pF

16 pF

20 pF

30 pF

16 pF

BE, DQ

All other signals

Document #: 38-06082 Rev. *G

Page 23 of 51

FullFlex

AC Test Load and Waveforms

V T H = 1 .5 V fo r L V T T L

V T H = 5 0 % V D D IO fo r 2 . 5 V C M O S

V T H = 5 0 % V D D IO fo r 1 . 8 V C M O S

V

= N C

R E F

V

R E F

5 0 O h m

O u tp u t

T e s t P o in t

R = 2 5 0 O h m

V T H

R E A D Y

Z Q

D e v ic e u n d e r

te s t

C

= 1 0 p F

R Q = 2 5 0 O h m

Figure 5. Output Test Load for LVTTL/CMOS

V T H

=

5 0 % V D D I O

5 0 O h m

V

=

E F

0 . 7 5 V

R

V

R

E F

5 0 O h m

O u t p u t

R E A D Y Z Q

R = 2 5 0 O h m

T e s t P o i n t

V T H

C = 1 0 p F f o r S D R

D e v i c e u n d e r

t e s t

R Q = 2 5 0 O h m

Figure 6. Output Test Load for HSTL

Figure 7. HSTL Input Waveform

Document #: 38-06082 Rev. *G

Page 24 of 51

FullFlex

Switching Characteristics Over the Operating Range

Table 14.SDR Mode, Signals effected by DLL

DLL ON (LOWSPD=1)^[29]

DLL OFF

(LOWSPD=0)^[29]

–250^[24]

Min. Max.

–200^[24]

Min. Max.

–167

Min. Max.

–133

Uni

t

Parameter

Description

Min. Max.

Min.

Max.

[33]

t_CD2

C Rise to DQ Valid

for Pipelined Mode

2.64^[28,

3.30^[28,

4.00^[28,

4.50^[28,

6.00^[28,ns

32]

1.00 2.64^[32]1.00 3.30^[32]1.00 4.00^[32]1.00 4.50^[32]1.00

1.00 2.64^[28,1.00 3.30^[28,1.00 4.00^[28,1.00 4.50^[28,1.00

6.00^[32ns

[33]

t_CCQ

C Rise to CQ Rise

[27, 33]

t_CKHZ2

C Rise to DQ

Output High Z in

Pipelined Mode

6.00^[28,ns

32]

[27, 33]

t_CKLZ2

C Rise to DQ

1.00

ns

Output Low Z in

Pipelined Mode

Table 15.SDR Mode

–250^[24]

–200^[24]

–167

–133

Parameter

Description

Min.

Max.

Min.

100

Max.

Min.

100

Max.

Min.

Max. Unit

f_MAX

Maximum Operating

100

250

200

167

100

133 MHz

(PIPELINED) Frequency for Pipelined

Mode

f_MAX

(FLOW-

Maximum Operating

Frequency for Flow-through

100

77

66.7

55.6 MHz

THROUGH) Mode

t_CYC

C Clock Cycle Time for

4.00^[32]

10.00

5.00^[32]10.00 6.00^[32]10.00 7.00^[32]

10.00

ns

(PIPELINED) Pipelined Mode

t_CYC

C Clock Cycle Time for

10.00^[32]

13.00^[32]

15.00^[32]

18.00^[32]

(FLOW-

THROUGH)

Flow-through Mode

t_CKD

t_SD

C Clock Duty Time

45

1.20^[28,32]

55

45

1.50^[28,32]

55

45

1.70^[28,32]

55

45

1.80^[28,32]

55

%

Data Input HSTL

Set-up Time 1.8V LVCMOS

to C Rise

ns

2.5V LVCMOS 1.45^[28,32]

3.3V LVTTL

1.75^[28,32]

0.5

1.95^[28,32]

0.5

2.05^[28,32]

0.5

ns

[30, 31]

t_HD

Data Input Hold Time after C

Rise

0.5

t_SAC

Address & HSTL

1.20^[28,30,

1.50^[28,30,

1.70^[28,30,

1.80^[28,30,

32]

Control

1.8V LVCMOS

Input Setup

Time to C

Rise

2.5V LVCMOS 1.45^[28,30,

3.3V LVTTL

1.75^[28,30,

1.95^[28,30,

2.05^[28,30,

32]

[30]

t_HAC

Address & Control Input

Hold Time after C Rise

0.50

0.60

0.70

ns

t_OE

Output Enable to Data Valid

3.40^[28,32]

4.40^[28,

5.00^[28

5.50^[28,ns

32]

,32]

32]

[27]

t_OLZ

OE to Low Z

1.00

ns

Notes:

27. Parameters specified with the load capacitance in Figure 5 and Figure 6.

28. For the x18 devices, add 200 ps to this parameter in the table above.

29. Test conditions assume a signal transition time of 2 V/ns.

30. add 100ps to this timing for 36M devices.

31. add 200ps to this timing for 36M x72 devices

32. Add 15% to this parameter if a VCORE of 1.5V is used.

33. This parameter assumes input clock cycle to cycle jitter of +/- 0ps.

Document #: 38-06082 Rev. *G

Page 25 of 51

FullFlex

Table 15.SDR Mode

–250^[24]

–200^[24]

–167

Min.

1.00

–133

Parameter

Description

Min.

1.00

Max.

3.40^[28,32]

Min.

1.00

Max.

4.40^[28,

Max.

Min.

Max. Unit

[27]

t_OHZ

OE to High Z

5.00^[28

1.00

5.50^[28,ns

32]

,32]

32]

t_CD1

C Rise to DQ Valid for

Flow-through Mode

(LowSPD = 1)

7.20^[28,32]

9.00^[28,

11.00

13.00

ns

32]

[28,32]

t_CA1

t_CA2

CRisetoAddressReadback

Valid for Flow-through Mode

7.20^[32]

4.00^[32]

9.00^[32]

5.00^[32]

11.00

13.00

ns

[32]

CRisetoAddressReadback

Valid for Pipelined Mode

6.00^[32

7.50^[32]ns

]

[33]

t_DC

t_JIT

DQ Output Hold after C Rise

1.00

ns

Clock Input Cycle to Cycle

Jitter

+/- 200

0.60^[28]

0.70^[28]

+/- 200

0.70^[28]

0.80^[28]

+/- 200

+/- 200 ps

0.80^[28

0.90^[28]ns

[33]

t_CQHQV

Echo Clock HSTL

(CQ)Highto 1.8V LVCMOS

]

Output Valid

2.5V LVCMOS

0.90^[28

1.00^[28]ns

]

3.3V LVTTL

t_CQHQX

Echo Clock HSTL

(CQ)Highto 1.8V LVCMOS

–0.60

–0.75

1.00

–0.70

–0.85

1.00

–0.80

–0.95

1.00

–0.90

–1.05

1.00

ns

Output Hold

2.5V LVCMOS

3.3V LVTTL

7.20^[28,32]

9.00^[28,

11.00

13.00

ns

[27]

t_CKHZ1

C Rise to DQ Output High Z

in Flow-through Mode

32]

[28,32]

[27]

t_CKLZ1

t_AC

t_CKHZA1

C Rise to DQ Output Low Z

in Flow-through Mode

Address Output Hold after C

Rise

[27]

C Rise to Address Output

High Z for Flow-through

Mode

7.20^[32]

4.00^[32]

9.00^[32]

5.00^[32]

11.00

13.00

[32]

t_CKHZA2

C Rise to Address Output

High Z for Pipelined Mode

1.00

0.50

1.00

0.50

1.00

0.50

1.00

6.00^[32

1.00

0.50

1.00

7.50^[32]ns

ns

]

[27]

t_CKLZA

t_SCINT

t_RCINT

t_SINT

C Rise to Address Output

Low Z

C Rise to CNTINT Low

C Rise to CNTINT High

C Rise to INT Low

2.64^[32]

6.00^[32]

2.64^[32]

3.30^[32]

7.00^[32]

3.30^[32]

4.00^[32

4.50^[32]ns

8.50^[32]ns

4.50^[32]ns

]

4.00^[32

]

8.00^[32

]

t_RINT

C Rise to INT High

8.00^[32

]

t_BSY

C Rise to BUSY Valid

4.00^[32

]

Table 16.Master Reset Timing

–250^[24]

–200^[24]

Min. Max.

–167

–133

Parameter

t_PUP

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

ms

Power-Up Time

1

5

1

5

1

5

1

5

t_RS

Master Reset Pulse Width

cycles

Document #: 38-06082 Rev. *G

Page 26 of 51

FullFlex

Table 16.Master Reset Timing

–250^[24]

–200^[24]

–167

–133

Min. Max.

Parameter

t_RSR

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

cycles

ns

Master Reset Recovery Time

Master Reset to Outputs Inactive/Hi Z

Master Reset Release to Port Ready

C Rise to Port Ready

5

t_RSF

12

15

18

22.50

[34]

t_RDY

1024

8^[32]

1024

9.5^[32]

1024

11^[32]

1024 cycles

[35]

t_CORDY

13^[32]

ns

Table 17.JTAG Timing

–250^[24]

–200^[24]

–167

–133

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

MHz

ns

f_JTAG

t_TCYC

t_TH

JTAG TAP Controller Frequency

TCK Cycle Time

20

50

20

10

50

20

10

50

20

10

50

20

10

TCK High Time

ns

t_TL

TCK Low Time

ns

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOV

t_TDOX

t_JXZ

TMS Set-up to TCK Rise

TMS Hold to TCK Rise

TDI Set-up to TCK Rise

TDI Hold to TCK Rise

TCK Low to TDO Valid

TCK Low to TDO Invalid

TCK Low to TDO High Z

TCK Low to TDO Active

ns

10

ns

0

ns

15

ns

t_JZX

ns

t_JZX

ns

Notes:

34. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250-Ω resistor to VSS.

35. Add this propagation delay after t

for all Master Reset Operations.

RDY

Switching Waveforms

JTAG Timing

t_TH

t_TL

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOX

t_TDOV

Document #: 38-06082 Rev. *G

Page 27 of 51

FullFlex

Switching Waveforms (continued)

Master Reset^[34]

~

V

CORE

t

RS

PUP

~

MRST

C

t

RDY

CORDY

~

READY

t

RSF

All Address

& Data

t

RSR

All Other

Inputs

~

READ Cycle for Pipelined Mode

t

CYC

C

CE

OE

t

HAC

SAC

R/W

A

n

n+1

x

n+2

n

n+3

n+4

n+5

n+6

2 Pipelined stages

DQ

n+4

x-1

n+1

n+2

n+3

DQ

t

DC

t

CD2

Document #: 38-06082 Rev. *G

Page 28 of 51

FullFlex

Switching Waveforms (continued)

WRITE Cycle for Pipelined and Flow-through Modes

t

CYC

C

CE

R/W

A

n+6

A

n

n+1

n+2

n+3

n+4

n+5

2 Pipelined stages

DQ

n+6

n

n+1

n+2

n+3

n+4

n+5

DQ

t_SDt_HD

READ with Address Counter Advance for Pipelined Mode

t

CYC

C

A

n

Internal

Address

A

n+1

A

n

n+2

n+3

ADS

CNTEN

DQ

n+1

x-1

x

n

DQ

n+2

n+3

Document #: 38-06082 Rev. *G

Page 29 of 51

FullFlex

Switching Waveforms (continued)

READ with Address Counter Advance for Flow-through Mode

tCYC

C

t^SACtHAC

A

An

ADS

CNTEN

DQ

tSAC tHAC

tCD1

DQx

DQn

DQn + 1

DQn + 2

DQn + 3

DQn + 4

tDC

READ EXTERNAL ADDRESS

READ WITH COUNTER

COUNTER HOLD

READ WITH COUNTER

Document #: 38-06082 Rev. *G

Page 30 of 51

FullFlex

Switching Waveforms (continued)

Port-to-Port WRITE–READ for Pipelined Mode

t

CYC

Left Port

C

L

A

A_L

n

R/W_L

DQ_L

DQ

n

Right Port

t

CCS

C

R

t

CYC

A_R

A

n

R/W_R

DQ_R

t

SAC HAC

DQ

n

t

DC

CD2

Chip Enable READ for Pipelined Mode

t

CYC

C

CE0

CE1

R/W

A

t

SAC HAC

A

n+6

n

n+1

n+2

n+3

n+4

n+5

DQ

n+3

n

t

DC

t

CD2

CKLZ2

Document #: 38-06082 Rev. *G

Page 31 of 51

FullFlex

Switching Waveforms (continued)

OE Controlled WRITE for Pipelined Mode

t

CYC

C

A

n+3

x+1

x+2

x+3

n

n+1

n+2

R/W

OE

t_OHZ

DQ

x+1

DQ

n+3

DQ

x-1

x

n

n+1

n+2

OE Controlled WRITE for Flow-through Mode

t

CYC

C

A

n+3

x+1

x+2

x+3

n

n+1

n+2

R/W

OE

t_OHZ

DQ

x+2

DQ

n+3

DQ

x

x+1

n

n+1

n+2

Document #: 38-06082 Rev. *G

Page 32 of 51

FullFlex

Switching Waveforms (continued)

Byte-Enable READ for Pipelined Mode

t_CYC

C

A

n

n+1

n+2

n+3

A

R/W

BE7

BE6

BE5

BE4

BE3

BE2

BE1

BE0

t_CKLZ2

t_CKHZ2

DQ_n+1(63:71)

DQ

63:71

DQ_n+1(54:62)

DQ

54:62

DQ_n+2(45:53)

45:53

36:44

DQ_n+2(36:44)

DQ_n+1(27:35)

DQ

27:35

DQ_n+2(18:26)

18:26

DQ_n+3(9:17)

DQ

9:17

0:8

DQ_n+3(0:8)

Document #: 38-06082 Rev. *G

Page 33 of 51

FullFlex

Switching Waveforms (continued)

Port-to-Port WRITE-to-READ for Flow-through Mode

C^L

R/W L

tSAC

tHAC

NO MATCH

AL

MATCH

tSD

tHD

VALID

DQL

tCCS

CR

tCD1

R/W R

tHAC

tSAC

NO MATCH

AR

MATCH

tCD1

DQR

VALID

tDC

Busy Address Readback for Pipelined and Flow-through Modes, DDRON = CNT/MSK = RET = LOW^[36]

t

CYC

~

C

Internal

Address

A_match+2

A_match+3

A_match+4

BUSY

~

CNTEN

ADS

~

External

Address

A_match

Pipelined

t_AC

t_CA2

External

Address

~

A_match

Flow-through

t_AC

t_CA1

Note:

36. A

is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy

match

Address Readback.”

Document #: 38-06082 Rev. *G

Page 34 of 51

FullFlex

Switching Waveforms (continued)

Read Cycle for Flow-through Mode

tCYC

C

CE0

CE1

tSAC

t^HAC

BEn

R/W

tSAC

tHAC

A

An

An + 1

An + 2

An + 3

tCKHZ1

tCD1

tDC

DQ

DQn

DQn + 1

DQn + 2

tDC

tCKLZ1

tOLZ

tOHZ

OE

tOE

READ-to-WRITE for Pipelined Mode (OE = V_IL)^[37,38,39]

t_CYC

t_CL

C

t_CH

A

x

A

n

A

R/W

DQ

n+1

n+2

t_SACt_HAC

t

CKLZ2

DQ

x

DQ

x-2

t_CD2

x-1

DQ

n+2

DQ

n+1

n

t_DC

t_CKHZ2

t_SDt_HD

Notes:

37. When OE = V , the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data.

IL

38. Two dummy writes should be issued to accomplish bus turnaround. The 3rd instruction is the first valid write.

39. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption.

Document #: 38-06082 Rev. *G

Page 35 of 51

FullFlex

Switching Waveforms (continued)

READ-to-WRITE for Pipelined Mode (OE Controlled)^[40,41]

t_CYC

C

A

n+3

x

x+1

x+2

n

n+1

n+2

A

t_SACt_HAC

R/W

OE

DQ

t_OHZ

t_SDt_HD

DQ

x

DQ

n+3

x-2

x-1

n

n+1

n+2

Notes:

40. OE should be deasserted and t

allowed to elapse before the first write operation is issued.

OHZ

41. Any write scheduled to complete after OE is deasserted will be preempted.

Document #: 38-06082 Rev. *G

Page 36 of 51

FullFlex

Switching Waveforms (continued)

Read-to-Write-to-Read for Flow-through Mode (OE = LOW)

tCYC

C

tSAC tHAC

CE0

CE1

BEn

tSAC

tHAC

R/W

A

An

An + 1

An + 2

An + 3

An + 4

tSD

tHD

DQIN

DQn + 2

tCD1

DQn

tDC

DQOUT

DQn + 1

DQn + 3

tCKHZ1

tCKLZ1

tDC

READ

NOP

W RITE

READ

Document #: 38-06082 Rev. *G

Page 37 of 51

FullFlex

Switching Waveforms (continued)

Read-to-Write-to-Read for Flow-through Mode (OE Controlled)

tCYC

C

tHAC

tSAC

CE0

CE¹

BEn

tHAC

tSAC

R/W

A

An

An + 1

An + 2

tHD

An + 3

An + 4

An + 5

tSD

DQIN

DQn + 2

DQn + 3

tOE

tCD1

tDC

tCD1

DQOUT

DQn

DQn + 4

tDC

tCKLZ1

tOHZ

OE

READ

W RITE

READ

Document #: 38-06082 Rev. *G

Page 38 of 51

FullFlex

Switching Waveforms (continued)

BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-through Modes, Clock Timing Violates t_CCS. (Flag Both

Ports)

Port A

C

A

R/W

BUSY

C

t_BSY

< t_CCS

Port B

A

R/W

t_BSY

BUSY

BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-through Modes, Clock Timing Meets t_CCS. (Flag Losing

Port)

Losing Port

C

A

R/W

t_ccs

t_BSY

BUSY

t_BSY

Winning Port

C

A

Match

R/W

BUSY

Document #: 38-06082 Rev. *G

Page 39 of 51

FullFlex

Switching Waveforms (continued)

Read with Echo Clock for Pipelined Mode (CQEN = HIGH)

C

t

HAC

SAC

R/W

A

n

n+1

n+2

n+3

n+4

n+5

n+6

CQ0

CQ1

t

CCQ

CQ1

DQ

t

CQHQX

CQHQV

DQ

n+4

DQ

x

n

n+1

n+2

n+3

x-1

Document #: 38-06082 Rev. *G

Page 40 of 51

FullFlex

Switching Waveforms (continued)

Mailbox Interrupt Output

t_CYC

C

L

A_MAX

A_L

R/W_L

DQ_L

INT_R

t_SINT

t_RINT

C

R

A_MAX

A_R

R/W_R

DQ_MAX

DQ_R

Document #: 38-06082 Rev. *G

Page 41 of 51

FullFlex

Ordering Information

512K

×

72 (36 Mbit) 1.8V/1.5V Synchronous CYD36S72V18 Dual-Port SRAM

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYD36S72V18-200BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYD36S72V18-200BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

167 CYD36S72V18-167BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYD36S72V18-167BGC

CYD36S72V18-167BGXI

CYD36S72V18-167BGI

BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial

BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial

133 CYD36S72V18-133BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYD36S72V18-133BGC

CYD36S72V18-133BGXI

CYD36S72V18-133BGI

BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial

BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial

256K

×

72 (18 Mbit) 1.8V/1.5V Synchronous CYD18S72V18 Dual-Port SRAM

Speed

(MHz)

Package

Operating

Range

Ordering Code

Name

BY484

BG484

BY484

BG484

BY484

BG484

BY484

BG484

BY484

BG484

Package Type

250 CYD18S72V18-250BGXC

CYD18S72V18-250BGC

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial

484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial

200 CYD18S72V18-200BGXC

CYD18S72V18-200BGC

CYD18S72V18-200BGXI

CYD18S72V18-200BGI

167 CYD18S72V18-167BGXC

CYD18S72V18-167BGC

CYD18S72V18-167BGXI

CYD18S72V18-167BGI

128K

×

72 (9 Mbit) 1.8V/1.5V Synchronous CYD09S72V18 Dual-Port SRAM

Speed

(MHz)

Package

Operating

Range

Ordering Code

Name

BY484

BG484

BY484

BG484

BY484

BG484

BY484

BG484

BY484

BG484

Package Type

250 CYD09S72V18-250BGXC

CYD09S72V18-250BGC