CYD18S72V-133BBI_技术文档

CYD04S72V

CYD09S72V

CYD18S72V

FLEx72™ 3.3V 64K/128K/256K x 72

Synchronous Dual-Port RAM

Features

Functional Description

• True dual-ported memory cells that allow simultaneous

The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit

pipelined, synchronous, true dual-port static RAMs that are

high-speed, low-power 3.3V CMOS. Two ports are provided,

permitting independent, simultaneous access to any location

in memory. The result of writing to the same location by more

than one port at the same time is undefined. Registers on

control, address, and data lines allow for minimal set-up and

hold time.

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal write pulse width is

independent of the duration of the R/W input signal. The

internal write pulse is self-timed to allow the shortest possible

cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

access of the same memory location

• Synchronous pipelined operation

• Family of 4-Mbit, 9-Mbit, and 18-Mbit devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

• 3.3V low power

— Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

• Mailbox function for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 484-ball FBGA (1-mm pitch)

• Pb-Free packaging available

• Counter wrap around control

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

The CYD18S72V device have limited features. Please see

“Address Counter and Mask Register Operations^[17]” on

page 6“ for details.

• Dual Chip Enables on both ports for easy depth

Seamless Migration to Next-Generation Dual-Port Family

expansion

Cypress offers a migration path for all devices to the

next-generation devices in the Dual-Port family with a

compatible footprint. Please contact Cypress Sales for more

details.

• Seamless Migration to Next Generation Dual-Port

Family

Table 1. Product Selection Guide

4-Mbit

9-Mbit

18-Mbit

Density

(64K x 72)

CYD04S72V

167

(128K x 72)

(256K x 72)

Part Number

Max. Speed (MHz)

CYD09S72V

CYD18S72V

167

4.0

270

133

5.0

410

Max. Access Time—Clock to Data (ns)

Typical operating current (mA)

Package

4.0

225

484-ball FBGA

23 mm x 23 mm

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-06069 Rev. *I

Revised May 2, 2006

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Logic Block Diagram^[1]

FTSEL

L

FTSEL

R

CONFIG Block

PORTST[1:0]

L

PORTST[1:0]

R

DQ [71:0]

R

DQ[71:0]

L

BE [7:0]

R

BE [7:0]

L

CE0

R

L

IO

Control

IO

Control

CE1

R

OE

R

OE

L

R/W

R

L

Dual-Ported Array

Arbitration Logic

BUSY

L

R

A [17:0]

L

R

CNT/MSK

ADS

R

L

CNTEN

R

L

Address &

Counter Logic

Address &

Counter Logic

CNTRST

L

R

RET

L

RET

R

CNTINT

L

CNTINT

R

C

L

C

R

WRP

L

WRP

R

TRST

TMS

TDI

Mailboxes

INT

R

L

JTAG

TDO

TCK

MRST

READY

RESET

LOGIC

READY

L

R

LowSPD

R

LowSPD

L

Note:

1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.

Document #: 38-06069 Rev. *I

Page 2 of 25

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Pin Configuration

484-ball BGA

Top View

CYD04S72V/CYD09S72V/CYD18S72V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

NC DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R NC

A

DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R

B

C

DQ65L DQ64L VSS

DQ67L DQ66L VSS

VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS

VSS DQ64R DQ65R

VSS DQ66R DQ67R

[2, 5]

VSS

VSS NC

NC

VSS LOWSP PORTS NC

BUSYL CNTINT PORTS NC NC

NC

VSS

[2,4]

[2, 5]

DL

TD0L

L

TD1L

[2, 4]

[2,4]

[10]

D

DQ69L DQ68L VDDIO VSS

L

VSS VDDIO VDDIO VDDIO VDDIOLVDDIOL VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO NC

VSS VDDIO DQ68R DQ69R

R

L

R

E

F

[8]

[9]

[8]

DQ71L DQ70L CE1L CE0L VDDIO VDDIO VDDIO VDDIO VDDIOL VCORE VCOREVCORE VCORE VDDIO VDDIO VDDIO VDDIO VDDIO CE0R CE1R DQ70R DQ71R

[9]

L

R

[2,

A0L

A2L

A4L

A6L

A8L

A1L RETL

BE4L VDDIO VDDIO VREFL VSS

VSS

VSS VREFR VDDIO VDDIO BE4R RETR

A1R

A0R

A2R

A4R

A6R

A8R

3]

[2, 4]

3]

L

R

G

H

J

[2

[

A3L WRPL BE5L VDDIO VDDIO VSS

VSS

VSS VDDIO VDDIO BE5R WRPR A3R

,3]

2,3]

L

R

A5L READY BE6L VDDIO VDDIO VSS

VSS VDDIO VDDIO BE6R READY A5R

[2, 5]

L

R

[2,5]

A7L NC

BE7L VTTL VCORE VSS

OEL VTTL VCORE VSS

VSS VCORE VDDIO BE7R NC

R

A7R

A9R

K

L

A9L

CL

VSS VCORE VTTL OER

CR

A10L A11L

VSS BE3L VTTL VCORE VSS

[9]

VSS VCORE VTTL BE3R VSS A11R A10R

M

N

P

A12L A13L ADSL

BE2L VDDIO VCORE VSS

L

VSS VCORE VTTL BE2R ADSR A13R A12R

[9]

A14L A15L CNT/M BE1L VDDIO VDDIO VSS

VSS VDDIO VDDIO BE1R CNT/M A15R A14R

[8]

SKL

L

R

SKR

A16L A17L CNTEN BE0L VDDIO VDDIO VSS

VSS VDDIO VDDIO BE0R CNTEN A17R A16R

[6]

[7]

[6]

L

R

[9]

R

T

A18L

[2,5]

NC CNTRS INTL VDDIO VDDIO VREFL VSS

VSS

VSS VREFR VDDIO VDDIO INTR CNTRS NC

A18R

[2,5]

[8]

[2, 4]

[8]

TL

L

R

TR

[2,

DQ35L DQ34L R/WL REVL VDDIO VDDIO VDDIO VDDIO VDDIOL VCORE VCOREVCORE VCORE VDDIO VDDIO VDDIO VDDIO VDDIO REVR R/WR DQ34R DQ35R

[2,4]

4]

L

R

U

V

[2,

DQ33L DQ32L FTSELL VDDIO NC VDDIO VDDIO VDDIO VDDIOL VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL DQ32R DQ33R

[2,3]

5]

[2,3]

L

R

[2, 5]

[2,

[2, 5]

DQ31L DQ30L VSS MRST VSS NC

NC

REVL PORTS CNTINT BUSYR NC

PORTS LOWSP VSS NC

[2,4]

NC

VSS

TDI

TDO DQ30R DQ31R

TCK DQ28R DQ29R

4]

[2, 5]

[2,4]

TD1R

R

TD0R DR

[2, 4]

[10]

W

Y

DQ29L DQ28L VSS

VSS DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DQ20R TMS

DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R

NC DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R NC

AA

AB

Notes:

2. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.

3. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.

4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.

5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.

6. Leave this ball unconnected for a 64K x 72 configuration.

7. Leave this ball unconnected for 128K x 72 and 64K x72 configurations.

8. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO.

9. These balls are not applicable for CYD18S72V device. They need to be tied to VSS.

10. These balls are not applicable for CYD18S72V device. They need to be no connected.

Document #: 38-06069 Rev. *I

Page 3 of 25

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Pin Definitions

Left Port

Right Port

Description

A_0L–A_17L

A_0R–A_17R

Address Inputs.

BE_0L–BE_7L

BE_0R–BE_7R

Byte Enable Inputs. Asserting these signals enables Read and Write operations

to the corresponding bytes of the memory array.

[2,5]

BUSY_L

BUSY_R

Port Busy Output. When the collision is detected, a BUSY is asserted.

C_L

C_R

Input Clock Signal.

[9]

CE0_L

CE0_R

Active Low Chip Enable Input.

[8]

CE1_L

CE1_R

Active High Chip Enable Input.

DQ_0L–DQ_71L

OE_L

DQ_0R–DQ_71R

OE_R

Data Bus Input/Output.

Output Enable Input. This asynchronous signal must be asserted LOW to enable

the DQ data pins during Read operations.

INT_L

INT_R

Mailbox Interrupt Flag Output. The mailbox permits communications between

ports. The upper two memory locations can be used for message passing. INT_Lis

asserted LOW when the right port writes to the mailbox location of the left port, and

vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of

its mailbox.

[2,4]

LowSPD_L

LowSPD_R

Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD

disables the port DLL.

[2,4]

PORTSTD[1:0]_L

R/W_L

PORTSTD[1:0]_R

R/W_R

Port Address/Control/Data I/O Standard Select Input.

Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from

the dual-port memory array.

[2,5]

READY_L

READY_R

Port Ready Output. This signal will be asserted when a port is ready for normal

operation.

[8]

CNT/MSK_L

CNT/MSK_R

Port Counter/Mask Select Input. Counter control input.

Port Counter Address Load Strobe Input. Counter control input.

Port Counter Enable Input. Counter control input.

Port Counter Reset Input. Counter control input.

[9]

ADS_L

ADS_R

[9]

CNTEN_L

CNTEN_R

[8]

CNTRST_L

CNTRST_R

[10]

CNTINT_L

CNTINT_R

Port Counter Interrupt Output. This pin is asserted LOW when the unmasked

portion of the counter is incremented to all “1s”.

[2,3]

WRP_L

WRP_R

Port Counter Wrap Input. After the burst counter reaches the maximum count, if

WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be

loaded with the value stored in the mirror register.

Port Counter Retransmit Input. Counter control input.

[2,3]

RET_L

RET_R

[2,3]

FTSEL_L

FTSEL_R

Flow-Through Select. Use this pin to select Flow-Through mode. When is

de-asserted, the device is in pipelined mode.

[2,4]

VREF_L

VREF_R

Port External High-Speed IO Reference Input.

VDDIO_L

VDDIO_R

Port IO Power Supply.

REV^[2,4]

Reserved pins for future features.

L

R

MRST

TRST^[2,5]

Master Reset Input. MRST is an asynchronous input signal and affects both ports.

A master reset operation is required at power-up.

JTAG Reset Input.

Document #: 38-06069 Rev. *I

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Pin Definitions (continued)

Left Port

Right Port

Description

TMS

TDI

JTAG Test Mode Select Input. It controls the advance of JTAG TAP state

machine. State machine transitions occur on the rising edge of TCK.

JTAG Test Data Input. Data on the TDI input will be shifted serially into selected

registers.

TCK

TDO

JTAG Test Clock Input.

JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO

is normally three-stated except when captured data is shifted out of the JTAG TAP.

V_SS

Ground Inputs.

[11]

V_CORE

V_TTL

Core Power Supply.

LVTTL Power Supply.

Master Reset

write operation by the left port to address 3FFFF will assert

INT_RLOW. At least one byte has to be active for a write to

The FLEx72 family devices undergo a complete reset by

taking the MRST input LOW. MRST input can switch

asynchronously to the clocks. MRST initializes the internal

burst counters to zero, and the counter mask registers to all

ones (completely unmasked). MRST also forces the mailbox

interrupt (INT) flags and the Counter Interrupt (CNTINT) flags

HIGH. MRST must be performed on the FLEx72 family

devices after power-up.

generate an interrupt. A valid Read of the 3FFFF location by

the right port will reset INT_RHIGH. At least one byte has to be

active in order for a read to reset the interrupt. When one port

writes to the other port’s mailbox, the INT of the port that the

mailbox belongs to is asserted LOW.

The INT is reset when the owner (port) of the mailbox reads

the contents of the mailbox. The interrupt flag is set in

a flow-thru mode (i.e., it follows the clock edge of the writing

port). Also, the flag is reset in a flow-thru mode (i.e., it follows

the clock edge of the reading port)

Each port can read the other port’s mailbox without resetting

the interrupt. And each port can write to its own mailbox

without setting the interrupt. If an application does not require

message passing, INT pins should be left open.

Mailbox Interrupts

The upper two memory locations may be used for message

passing and permit communications between ports. Table 2

shows the interrupt operation for both ports using 18 Mbit

device as an example. The highest memory location, 3FFFF

is the mailbox for the right port and 3FFFE is the mailbox for

the left port. Table 2.shows that in order to set the INT_Rflag, a

Table 2. Interrupt Operation Example ^{[1, 12, 13, 14]}

Left Port

Right Port

Function

R/W_L

CE_L

A_0L–17L

INT_L

R/W_R

CE_R

A_0R–17R

INT_R

Set Right INT_RFlag

L

3FFFF

X

L

Reset Right INT_RFlag

Set Left INT_LFlag

X

H

X

L

X

L

H

L

3FFFF

3FFFE

X

H

X

Reset Left INT_LFlag

3FFFE

H

X

Notes:

11. This family of Dual-Ports does not use V

, and these pins are internally NC. The next generation Dual-Port family, the FLEx72-E™, will use V

of 1.5V

CORE

or 1.8V. Please contact local Cypress FAE for more information.

12. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK

0

1

and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.

13. OE is “Don’t Care” for mailbox operation.

14. At least one of BE0 or BE7 must be LOW.

Document #: 38-06069 Rev. *I

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Table 3. Address Counter and Counter Mask Register Control Operation (Any Port) ^[15,16]

CLK MRST CNT/MSK CNTRST ADS CNTEN

Operation

Description

X

L

X

Master Reset

Reset address counter to all 0s and mask register

to all 1s

H

L

X

L

X

L

Counter Reset

Counter Load

Reset counter unmasked portion to all 0s

H

Load counter with external address value presented

on address lines

H

L

H

L

Counter Readback Read out counter internal value on address lines

Counter Increment Internally increment address counter value

H

Counter Hold

Constantly hold the address value for multiple clock

cycles

H

L

X

L

X

L

Mask Reset

Mask Load

Reset mask register to all 1s

H

Load mask register with value presented on the

address lines

H

L

H

L

H

X

Mask Readback

Reserved

Read out mask register value on address lines

H

Operation undefined

Address Counter and Mask Register Operations^[17]

asynchronous. All the other control signals in Table 3

(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the

port’s CLK. All these counter and mask operations are

independent of the port’s chip enable inputs (CE0 and CE1).

This section describes the features only apply to 4 Mbit and 9

Mbit devices, not to 18 Mbit device. Each port have a program-

mable burst address counter. The burst counter contains three

registers: a counter register, a mask register, and a mirror

register.

The counter register contains the address used to access the

RAM array. It is changed only by the Counter Load, Increment,

Counter Reset, and by master reset (MRST) operations.

The mask register value affects the Increment and Counter

Reset operations by preventing the corresponding bits of the

counter register from changing. It also affects the counter

interrupt output (CNTINT). The mask register is changed only

by the Mask Load and Mask Reset operations, and by the

MRST. The mask register defines the counting range of the

counter register. It divides the counter register into two

regions: zero or more “0s” in the most significant bits define

the masked region, one or more “1s” in the least significant bits

define the unmasked region. Bit 0 may also be “0,” masking

the least significant counter bit and causing the counter to

increment by two instead of one.

The mirror register is used to reload the counter register on

increment operations (see “retransmit,” below). It always

contains the value last loaded into the counter register, and is

changed only by the Counter Load, and Counter Reset opera-

tions, and by the MRST.

Counter enable (CNTEN) inputs are provided to stall the

operation of the address input and utilize the internal address

generated by the internal counter for fast, interleaved memory

applications. A port’s burst counter is loaded when the port’s

address strobe (ADS) and CNTEN signals are LOW. When the

port’s CNTEN is asserted and the ADS is deasserted, the

address counter will increment on each LOW to HIGH

transition of that port’s clock signal. This will Read/Write one

word from/into each successive address location until CNTEN

is deasserted. The counter can address the entire memory

array, and will loop back to the start. Counter reset (CNTRST)

is used to reset the unmasked portion of the burst counter to

0s. A counter-mask register is used to control the counter

wrap.

Counter Reset Operation

All unmasked bits of the counter and mirror registers are reset

to “0.” All masked bits remain unchanged. A Mask Reset

followed by a Counter Reset will reset the counter and mirror

registers to 00000, as will master reset (MRST).

Counter Load Operation

The address counter and mirror registers are both loaded with

Table 3 summarizes the operation of these registers and the

the address value presented at the address lines.

required input control signals. The MRST control signal is

Notes:

15. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.

16. Counter operation and mask register operation is independent of chip enables.

17. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF.

The CYD18S72V has 18 address bits and a maximum address value of 3FFFF.

Document #: 38-06069 Rev. *I

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Counter Increment Operation

valid t_CA2after the next rising edge of the port’s clock. If

address readback occurs while the port is enabled (CE0 LOW

and CE1 HIGH), the data lines (DQs) will be three-stated.

Figure 1 shows a block diagram of the operation.

Once the address counter register is initially loaded with an

external address, the counter can internally increment the

address value, potentially addressing the entire memory array.

Only the unmasked bits of the counter register are incre-

mented. The corresponding bit in the mask register must be

a “1” for a counter bit to change. The counter register is incre-

mented by 1 if the least significant bit is unmasked, and by 2

if it is masked. If all unmasked bits are “1,” the next increment

will wrap the counter back to the initially loaded value. If an

Increment results in all the unmasked bits of the counter being

“1s,” a counter interrupt flag (CNTINT) is asserted. The next

Increment will return the counter register to its initial value,

which was stored in the mirror register. The counter address

can instead be forced to loop to 00000 by externally

connecting CNTINT to CNTRST.^[18]An increment that results

in one or more of the unmasked bits of the counter being “0”

will de-assert the counter interrupt flag. The example in

Figure 2 shows the counter mask register loaded with a mask

value of 0003Fh unmasking the first 6 bits with bit “0” as the

LSB and bit “16” as the MSB. The maximum value the mask

register can be loaded with is 1FFFFh. Setting the mask

register to this value allows the counter to access the entire

memory space. The address counter is then loaded with an

initial value of 8h. The base address bits (in this case, the 6th

address through the 16th address) are loaded with an address

value but do not increment once the counter is configured for

increment operation. The counter address will start at address

8h. The counter will increment its internal address value till it

reaches the mask register value of 3Fh. The counter wraps

around the memory block to location 8h at the next count.

CNTINT is issued when the counter reaches its maximum

value.

Retransmit

Retransmit is a feature that allows the Read of a block of

memory more than once without the need to reload the initial

address. This eliminates the need for external logic to store

and route data. It also reduces the complexity of the system

design and saves board space. An internal “mirror register” is

used to store the initially loaded address counter value. When

the counter unmasked portion reaches its maximum value set

by the mask register, it wraps back to the initial value stored in

this “mirror register.” If the counter is continuously configured

in increment mode, it increments again to its maximum value

and wraps back to the value initially stored into the “mirror

register.” Thus, the repeated access of the same data is

allowed without the need for any external logic.

Mask Reset Operation

The mask register is reset to all “1s,” which unmasks every bit

of the counter. Master reset (MRST) also resets the mask

register to all “1s.”

Mask Load Operation

The mask register is loaded with the address value presented

at the address lines. Not all values permit correct increment

operations. Permitted values are of the form 2ⁿ–1 or 2ⁿ–2.

From the most significant bit to the least significant bit,

permitted values have zero or more “0s,” one or more “1s,” or

one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values,

but 1F0FF, 003FC, and 00000 are not.

Counter Hold Operation

Mask Readback Operation

The value of all three registers can be constantly maintained

unchanged for an unlimited number of clock cycles. Such

operation is useful in applications where wait states are

needed, or when address is available a few cycles ahead of

data in a shared bus interface.

The internal value of the mask register can be read out on the

address lines. Readback is pipelined; the address will be valid

t_CM2after the next rising edge of the port’s clock. If mask

readback occurs while the port is enabled (CE0 LOW and CE1

HIGH), the data lines (DQs) will be three-stated. Figure 1

shows a block diagram of the operation.

Counter Interrupt

Counting by Two

The counter interrupt (CNTINT) is asserted LOW when an

increment operation results in the unmasked portion of the

counter register being all “1s.” It is deasserted HIGH when an

Increment operation results in any other value. It is also

de-asserted by Counter Reset, Counter Load, Mask Reset

and Mask Load operations, and by MRST.

When the least significant bit of the mask register is “0,” the

counter increments by two. This may be used to connect the

x72 devices as a 144-bit single port SRAM in which the

counter of one port counts even addresses and the counter of

the other port counts odd addresses. This even-odd address

scheme stores one half of the 144-bit data in even memory

locations, and the other half in odd memory locations.

Counter Readback Operation

The internal value of the counter register can be read out on

the address lines. Readback is pipelined; the address will be

Note:

18. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.

Document #: 38-06069 Rev. *I

Page 7 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

CNT/MSK

CNTEN

ADS

Decode

Logic

CNTRST

MRST

Bidirectional

Address

Lines

Mask

Register

Counter/

Address

Register

Address

Decode

RAM

Array

CLK

Load/Increment

17

From

Address

Lines

Mirror

Counter

To Readback

and Address

Decode

1

0

1

0

From

Increment

Logic

Mask

17

Wrap

Register

17

Bit 0

From

Mask

From

Counter

+1

+2

Wrap

To

1

0

Detect

17

1

0

Counter

Figure 1. Counter, Mask, and Mirror Logic Block Diagram^[1]

Document #: 38-06069 Rev. *I

Page 8 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

CNTINT

H

Example:

Load

Counter-Mask

Register = 3F

0

0s

0

1

2¹⁶2¹⁵

2⁶2⁵2⁴2³2²2¹2⁰

Unmasked Address

Mask

Register

bit-0

Masked Address

Load

Address

Counter = 8

H

L

X

Xs

X

0

1

0

2¹⁶2¹⁵

2⁶2⁵2⁴2³2²2¹2⁰

Address

Counter

bit-0

Max

Address

Register

X

1

1 1

1

2¹⁶2¹⁵

2⁶2⁵2⁴2³2²2¹2⁰

Max + 1

Address

Register

H

X

0

1

0

2¹⁶2¹⁵

2⁶2⁵2⁴2³2²2¹2⁰

Figure 2. Programmable Counter-Mask Register Operation^{[1, 19]}

IEEE 1149.1 Serial Boundary Scan (JTAG)^[20]

Boundary Scan Hierarchy for FLEx72 Family

Internally, the CYD04S72V and CYD09S72V have two DIEs

while CYD18S72V have four DIEs. Each DIE contains all the

circuitry required to support boundary scan testing. The

circuitry includes the TAP, TAP controller, instruction register,

and data registers. The circuity and operation of the DIE

boundary scan are described in detail below. The scan chain

of each DIE is connected serially to form the scan chain of the

FLEx72 family as shown in Figure 3. TMS and TCK are

connected in parallel to each DIE to drive all 4 TAP controllers

in unison. In many cases, each DIE will be supplied with the

same instruction. In other cases, it might be useful to supply

different instructions to each DIE. One example would be

testing the device ID of one DIE while bypassing the others.

Each pin of FLEx72 family is typically connected to multiple

DIEs. For connectivity testing with the EXTEST instruction, it

is desirable to check the internal connections between DIEs

as well as the external connections to the package. This can

be accomplished by merging the netlist of the devices with the

netlist of the user’s circuit board. To facilitate boundary scan

testing of the devices, Cypress provides the BSDL file for each

DIE, the internal netlist of the device, and a description of the

device scan chain. The user can use these materials to easily

integrate the devices into the board’s boundary scan

environment. Further information can be found in the Cypress

application note Using JTAG Boundary Scan For System In a

Package (SIP) Dual-Port SRAMs.

The FLEx72 incorporates an IEEE 1149.1 serial boundary

scan test access port (TAP). The TAP controller functions in a

manner that does not conflict with the operation of other

devices using 1149.1-compliant TAPs. The TAP operates

using JEDEC-standard 3.3V I/O logic levels. It is composed of

three input connections and one output connection required by

the test logic defined by the standard.

Performing a TAP Reset

A reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This reset does not affect the operation of the

FLEx72 family and may be performed while the device is

operating. An MRST must be performed on the FLEx72 after

power-up.

Performing a Pause/Restart

When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the

scan chain will output the next bit in the chain twice. For

example, if the value expected from the chain is 1010101, the

device will output a 11010101. This extra bit will cause some

testers to report an erroneous failure for the FLEx72 in a scan

test. Therefore the tester should be configured to never enter

the PAUSE-DR state.

Notes:

19. The “X” in this diagram represents the counter upper bits.

20. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.

Document #: 38-06069 Rev. *I

Page 9 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

18 Mbit

4 Mbit/9 Mbit

TDO

D4

TDO

D2

TDI

TDO

D3

TDO

D1

TDO

D1

TDI

Figure 3. Scan Chain

Table 4. Identification Register Definitions

Instruction Field

Revision Number(31:28)

Cypress Device(27:12)

Value

0h

C002h

Description

Reserved for version number

Defines Cypress DIE number for CYD18S72V and

CYD09S72V

C001h

034h

1

Defines Cypress DIE number for CYD04S72V

Allows unique identification of FLEx72 family device vendor

Indicates the presence of an ID register

Cypress JDEC ID(11:1)

ID Register Presence (0)

Table 5. Scan Registers Sizes

Register Name

Instruction

Bit Size

4

Bypass

1

Identification

Boundary Scan

32

n^[21]

Table 6. Instruction Identification Codes

Instruction

EXTEST

BYPASS

IDCODE

HIGHZ

Code

Description

0000

1111

1011

0111

0100

Captures the Input/Output ring contents. Places the BSR between the TDI and TDO

Places the BYR between TDI and TDO

Loads the IDR with the vendor ID code and places the register between TDI and TDO

Places BYR between TDI and TDO. Forces all FLEx72 output drivers to a High-Z state

Controls boundary to 1/0. Places BYR between TDI and TDO

CLAMP

SAMPLE/PRELOAD 1000

Captures the input/output ring contents. Places BSR between TDI and TDO

Resets the non-boundary scan logic. Places BYR between TDI and TDO

NBSRST

1100

RESERVED

All other codes Other combinations are reserved. Do not use other than the above

Note:

21. See details in the device BSDL files.

Document #: 38-06069 Rev. *I

Page 10 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Maximum Ratings^[22]

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage...........................................> 2000V

(JEDEC JESD22-A114-2000B)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-up Current.....................................................> 200 mA

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Operating Range

Power Applied............................................–55°C to + 125°C

Ambient

Supply Voltage to Ground Potential.............. –0.5V to + 4.6V

[11]

Range

Temperature

V_DD

V_CORE

DC Voltage Applied to

Commercial 0°C to +70°C 3.3V ± 165 mV 1.8V ± 100 mV

Industrial –40°C to +85°C 3.3V ± 165 mV 1.8V ± 100mV

Outputs in High-Z State..........................–0.5V to V_DD+ 0.5V

DC Input Voltage...............................–0.5V to V_DD+ 0.5V^[23]

Electrical Characteristics Over the Operating Range

–167

–133

–100

Typ

Parameter

Description

Part No.

Min. Typ Max Min. Typ Max Min.

Max Unit

V_OH

Output HIGH Voltage (V_DD= Min., I_OH

=

2.4

2.0

2.4

2.0

V

–4.0 mA)

V_OL

Output LOW Voltage (V_DD= Min., I_OL= +4.0

mA)

Input HIGH Voltage

Input LOW Voltage

Output Leakage Current

Input Leakage Current Except TDI, TMS,

MRST

0.4

V

V_IH

V_IL

I_OZ

I_IX1

2.0

V

µA

0.8

10

0.8

10

0.8

10

–10

I_IX2

I_CC

Input Leakage Current TDI, TMS, MRST

–0.1

1.0 –0.1

225 300

406 580

1.0

225 300

350 500

410 580

–0.1

1.0

mA

Operating Current

CYD04S72V

CYD09S72V

CYD18S72V

CYD04S72V

CYD09S72V

(V_DD= Max.,I_OUT= 0 mA),

Outputs Disabled

315

450 mA

mA

I_SB1

I_SB2

I_SB3

I_SB4

I_SB5

Standby Current

90

115

90

115

(Both Ports TTL Level)

CE_Land CE_R≥ V_IH, f = f_MAX

105 150

Standby Current

CYD04S72V

CYD09S72V

160 210

266 380

160 210

266 380

mA

(One Port TTL Level)

CE_L| CE_R≥ V_IH, f = f_MAX

Standby Current (Both

Ports CMOS Level) CE_L

and CE_R≥ V_DD– 0.2V, f = 0

CYD04S72V

CYD09S72V

55

75

55

75

Standby Current

CYD04S72V

CYD09S72V

160 210

224 320

160 210

224 320

(One Port CMOS Level)

CE_L| CE_R≥ V_IH, f = f_MAX

Operating Current (VDDIO CYD18S72V

= Max, Iout = 0 mA, f = 0)

Outputs Disabled

Core Operating Current for (V_DD= Max.,

I_OUT= 0 mA), Outputs Disabled

75

0

mA

[11]

I_CORE

0

Notes:

22. The voltage on any input or I/O pin can not exceed the power pin during power-up.

23. Pulse width < 20 ns.

Document #: 38-06069 Rev. *I

Page 11 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Capacitance^[24]

Part#

Parameter

Description

Input Capacitance

Output Capacitance

Input Capacitance

Output Capacitance

Test Conditions

T_A= 25°C, f = 1 MHz,

V_DD= 3.3V

Max

20

Unit

pF

CYD04S72V C_IN

CYD09S72V

C_OUT

CYD18S72V C_IN

C_OUT

10^[25]

40

20

AC Test Load and Waveforms

3.3V

Z₀= 50Ω

R = 50Ω

OUTPUT

R1 = 590Ω

OUTPUT

C = 10 pF

C = 5 pF

R2 = 435Ω

V_TH= 1.5V

(a) Normal Load (Load 1)

(b) Three-state Delay (Load 2)

3.0V

90%

10%

90%

10%

ALL INPUT PULSES

Vss

< 2 ns

Switching Characteristics Over the Operating Range

–167

–133

–100

CYD04S72V

CYD09S72V

CYD18S72V

Parameter

f_MAX2

t_CYC2

Description

Maximum Operating Frequency

Clock Cycle Time

Clock HIGH Time

Clock LOW Time

Min.

Max

167

Min.

Max

133

Min.

Max

133

Min.

Max

100

Unit

MHz

ns

6.0

2.7

7.5

3.0

7.5

3.4

10

4.5

t_CH2

t_CL2

[26]

t_R

t_F

Clock Rise Time

Clock Fall Time

2.0

3.0

[26]

t_SA

t_HA

t_SB

t_HB

t_SC

t_HC

t_SW

t_HW

t_SD

t_HD

Address Set-up Time

Address Hold Time

Byte Select Set-up Time

Byte Select Hold Time

Chip Enable Set-up Time

Chip Enable Hold Time

R/W Set-up Time

2.3

0.6

2.3

0.6

2.3

0.6

2.3

0.6

2.3

0.6

2.3

2.5

0.6

2.5

0.6

2.5

0.6

2.5

0.6

2.5

0.6

2.5

2.2

1.0

2.2

1.0

NA

2.2

1.0

2.2

1.0

NA

2.7

1.0

2.7

1.0

NA

2.7

1.0

2.7

1.0

NA

R/W Hold Time

Input Data Set-up Time

Input Data Hold Time

ADS Set-up Time

t_SAD

Notes:

24. C

also references C

I/O.

OUT

25. Except INT and CNTINT which are 20 pF.

26. Except JTAG signal (t and t < 10 ns max).

R

F

Document #: 38-06069 Rev. *I

Page 12 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Characteristics Over the Operating Range (continued)

–167

–133

CYD04S72V

–100

CYD04S72V

CYD09S72V

CYD18S72V

Parameter

t_HAD

t_SCN

Description

ADS Hold Time

CNTEN Set-up Time

CNTEN Hold Time

CNTRST Set-up Time

CNTRST Hold Time

CNT/MSK Set-up Time

CNT/MSK Hold Time

Output Enable to Data Valid

OE to Low Z

Min.

0.6

2.3

0.6

2.3

0.6

2.3

0.6

Max

Min.

0.6

2.5

0.6

2.5

0.6

2.5

0.6

Max

Min.

Max

Min.

NA

Max

Unit

ns

NA

t_HCN

t_SRST

t_HRST

t_SCM

t_HCM

t_OE

4.0

4.4

5.5

[27, 28]

t_OLZ

t_OHZ

0

[27, 28]

OE to High Z

Clock to Data Valid

Clock to Counter Address Valid

4.0

4.4

5.5

5.0

NA

5.5

5.2

NA

t_CD2

t_CA2

t_CM2

Clock to Mask Register

Readback Valid

t_DC

Data Output Hold After Clock

HIGH

Clock HIGH to Output High Z

Clock HIGH to Output Low Z

Clock to INT Set Time

Clock to INT Reset Time

Clock to CNTINT Set Time

Clock to CNTINT Reset time

1.0

ns

[27, 28]

t_CKHZ

t_CKLZ

t_SINT

t_RINT

t_SCINT

t_RCINT

0

4.0

6.7

5.0

0

4.4

7.5

5.7

0

4.7

7.5

NA

0

5.0

10

NA

ns

[27, 28]

1.0

0.5

1.0

0.5

1.0

0.5

NA

1.0

0.5

NA

Port to Port Delays

t_CCS

Clock to Clock Skew

5.2

6.0

5.7

8.0

ns

Master Reset Timing

t_RS

t_RSS

t_RSR

t_RSF

Master Reset Pulse Width

Master Reset Set-up Time

Master Reset Recovery Time

Master Reset to Outputs Inactive

5.0

6.0

5.0

6.0

5.0

6.0

5.0

8.5

5.0

cycles

ns

cycles

ns

10.0

NA

10.0

NA

t_RSCNTINT

Master Reset to Counter

ns

Interrupt Flag Reset Time

Notes:

27. This parameter is guaranteed by design, but is not production tested.

28. Test conditions used are Load 2.

Document #: 38-06069 Rev. *I

Page 13 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

JTAG Timing Characteristics

CYD04S72V

CYD09S72V

CYD18S72V

–167/–133/–100

Parameter

Description

Maximum JTAG TAP Controller Frequency

Min.

Max

10

Unit

MHz

ns

f_JTAG

t_TCYC

t_TH

TCK Clock Cycle Time

TCK Clock HIGH Time

TCK Clock LOW Time

100

40

10

t_TL

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOV

t_TDOX

TMS Set-up to TCK Clock Rise

TMS Hold After TCK Clock Rise

TDI Set-up to TCK Clock Rise

TDI Hold After TCK Clock Rise

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

30

ns

0

Switching Waveforms

t_TH

t_TL

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOX

t_TDOV

Document #: 38-06069 Rev. *I

Page 14 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Waveforms (continued)

Master Reset

MRST

t_RS

t_RSF

ALL

ADDRESS/

DATA

t_RSS

INACTIVE

LINES

t_RSR

ALL

OTHER

INPUTS

ACTIVE

TMS

CNTINT

INT

TDO

Read Cycle^{[12, 29, 30, 31, 32]}

t_CYC2

t_CH2

t_CL2

CLK

CE

t_SC

t_HC

t_SC

t_HC

t_SB

t_HB

BE0–BE7

R/W

t_SW

t_SA

t_HW

t_HA

ADDRESS

A_n

A_n+1

A_n+2

A_n+3

t_DC

1 Latency

t_CD2

DATA_OUT

Q_n

Q_n+1

Q_n+2

t_OHZ

t_CKLZ

t_OLZ

OE

t

OE

Notes:

29. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.

30. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.

31. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.

IH

32. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.

IL

IH

Numbers are for reference only.

Document #: 38-06069 Rev. *I

Page 15 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Waveforms (continued)

Bank Select Read^{[33, 34]}

t_CYC2

t_CH2

t_CL2

CLK

t_HA

t_SA

A₃

A₄

ADDRESS_(B1)

A₅

A₀

A₁

A₂

t_HC

t_SC

CE_(B1)

t_CD2

t_CKHZ

t_HC

t_CKHZ

t_SC

Q₀

Q₃

Q₁

DATA_OUT(B1)

ADDRESS_(B2)

t_HA

t_SA

t_DC

A₂

t_DC

A₃

t_CKLZ

A₄

A₅

A₀

A₁

t_HC

t_SC

CE_(B2)

t_CD2

t_CKHZ

t_CD2

t_SC

t_HC

DATA_OUT(B2)

Q₄

Q₂

t_CKLZ

Read-to-Write-to-Read (OE = LOW)^{[32, 35, 36, 37, 38]}

t_CYC2

t_CH2

t_CL2

CLK

CE

t_SC

t_HC

t_SW

t_HW

R/W

t_SW

t_HW

A_n

A_n+1

A_n+2

t_SDt_HD

D_n+2

A_n+3

ADDRESS

DATA_IN

t_SA

t_HA

t_CD2

t_DC

t_CKHZ

Q_n

DATA_OUT

WRITE

NO OPERATION

READ

Notes:

33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx72 device from this data sheet. ADDRESS

(B1)

= ADDRESS

.

(B2)

34. ADS = CNTEN = BE0 – BE7 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.

35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.

36. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

37. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.

0

1

38. CE = BE0 – BE7 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be

completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.

Document #: 38-06069 Rev. *I

Page 16 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Waveforms (continued)

Read-to-Write-to-Read (OE Controlled)^{[32, 35, 37, 38]}

t_CYC2

t_CH2

t_CL2

CLK

CE

t_SC

t_HC

t_HW

t_SW

R/W t_SW

t_HW

A_n

A_n+1

A_n+2

A_n+3

A_n+4

A_n+5

ADDRESS

t_SA

t_HA

t_SDt_HD

D_n+2

DATA_IN

D_n+3

t_CD2

DATA_OUT

Q_n

Q_n+4

t_OHZ

OE

READ

WRITE

READ

Read with Address Counter Advance^[37]

t_CYC2

t_CH2

t_CL2

CLK

t_SA

t_HA

ADDRESS

A_n

t_SAD

t_HAD

ADS

t_SAD

t_HAD

CNTEN

t_SCN

t_HCN

t_SCN

t_HCN

t_CD2

Q_x–1

Q_x

t_DC

Q_n

Q_n+1

COUNTER HOLD

Q_n+2

DATA_OUT

Q_n+3

READ

READ WITH COUNTER

EXTERNAL

ADDRESS

Document #: 38-06069 Rev. *I

Page 17 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Waveforms (continued)

Write with Address Counter Advance ^[38]

t_CYC2

t_CH2

t_CL2

CLK

t_SA

t_HA

A_n

ADDRESS

INTERNAL

ADDRESS

A_n

A_n+1

A_n+2

A_n+3

A_n+4

t_SAD

t_HAD

ADS

CNTEN

DATA_IN

t_SCN

t_HCN

D_n

D_n+1

D_n+2

D_n+3

D_n+4

t_SD

t_HD

WRITE EXTERNAL

WRITE WITH WRITE COUNTER

COUNTER HOLD

WRITE WITH COUNTER

ADDRESS

Document #: 38-06069 Rev. *I

Page 18 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Waveforms (continued)

Counter Reset ^{[39, 40]}

t_CYC2

t_CH2t_CL2

CLK

t_HA

A_m

t_SA

A_p

A_n

ADDRESS

INTERNAL

A_x

A_p

A_n

1

0

A_m

ADDRESS

t_HW

t_SW

R/W

ADS

CNTEN

CNTRST

t_HRST

t_SRST

t_HD

D₀

t_SD

DATA_IN

t_CD2

[52]

DATA_OUT

Q₀

Q_n

Q₁

t_CKLZ

READ

ADDRESS 0

READ

ADDRESS 1

READ

COUNTER

RESET

WRITE

ADDRESS 0

READ

ADDRESS A_m

ADDRESS A_n

Notes:

39. CE = BE0 – BE7 = LOW; CE = MRST = CNT/MSK = HIGH.

0

1

40. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.

Document #: 38-06069 Rev. *I

Page 19 of 25

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CYD04S72V

CYD09S72V

CYD18S72V

Switching Waveforms (continued)

Readback State of Address Counter or Mask Register^{[41, 42, 43, 44]}

t_CYC2

t_CH2t_CL2

CLK

t_CA2or t_CM2

t_SA

t_HA

EXTERNAL

A_n*

A_n

ADDRESS

A₀–A₁₇

INTERNAL

ADDRESS

A_n+4

A_n+1

A_n+2

A_n+3

A_n

t_SAD

t_HAD

ADS

CNTEN

t_SCN

t_HCN

t_CD2

t_CKHZ

Q_n

t_CKLZ

DATA_OUT

Q_n+1

Q_x-1

Q_n+2

Q_x-2

Q

n+3

LOAD

READBACK

COUNTER

INTERNAL

ADDRESS

INCREMENT

EXTERNAL

ADDRESS

Notes:

41. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.

0

1

42. Address in output mode. Host must not be driving address bus after t

in next clock cycle.

CKLZ

43. Address in input mode. Host can drive address bus after t

.

CKHZ

44. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.

Document #: 38-06069 Rev. *I

Page 20 of 25

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CYD09S72V

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Switching Waveforms (continued)

Left_Port (L_Port) Write to Right_Port (R_Port) Read^{[45, 46, 47]}

t_CYC2

t_CH2

t_CL2

CLK_L

t_HA

t_SA

L_PORT

A_n

ADDRESS

t_SW

t_HW

R/W_L

t_CKHZ

t_SD

t_HD

t_CKLZ

L_PORT

DATA_IN

D_n

t_CCS

t_CYC2

t_CL2

CLK_R

t_CH2

t_SA

t_HA

R_PORT

A_n

ADDRESS

R/W_R

t_CD2

R_PORT

DATA_OUT

Q_n

t_DC

Notes:

45. CE = OE = ADS = CNTEN = BE0 – BE7 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.

0

1

46. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t

is violated, indeterminate data will be Read out.

CCS

CYC2

47. If t

< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t

+ t

) after the rising edge of R_Port's clock. If

CCS

CD2

t

> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t

+ t

) after the rising edge of R_Port's clock.

CCS

CYC2

CD2

Document #: 38-06069 Rev. *I

Page 21 of 25

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Switching Waveforms (continued)

Counter Interrupt and Retransmit^{[48, 49, 50, 51, 52]}

t_CYC2

t_CH2

t_CL2

CLK

t_SCM

t_HCM

CNT/MSK

ADS

CNTEN

COUNTER

INTERNAL

ADDRESS

1FFFE

t_SCINT

1FFFC

Last_Loaded

1FFFD

1FFFF

t_RCINT

Last_Loaded +1

CNTINT

Mailbox Interrupt Timing^{[53, 54, 55, 56, 57]}

t_CYC2

t_CH2

t_CL2

CLK_L

t_SAt_HA

3FFFF

L_PORT

A_n+1

A_n

A_n+2

A_n+3

ADDRESS

t_SINT

t_RINT

INT_R

t_CYC2

t_CL2

t_CH2

CLK_R

t_SAt_HA

A_m

R_PORT

A_m+1

3FFFF

A_m+3

A_m+4

ADDRESS

Notes:

48. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.

0

1

49. CNTINT is always driven.

50. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.

51. The mask register assumed to have the value of 1FFFFh.

52. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.

53. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.

0

1

54. Address “1FFFF” is the mailbox location for R_Port.

55. L_Port is configured for Write operation, and R_Port is configured for Read operation.

56. At least one byte enable (B0 – B3) is required to be active during interrupt operations.

57. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.

Document #: 38-06069 Rev. *I

Page 22 of 25

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Table 7. Read/Write and Enable Operation (Any Port) ^{[1, 15, 58, 59, 60]}

Inputs

Outputs

DQ₀– DQ₇₁

High-Z

OE

CLK

CE₀

CE₁

R/W

X

Operation

Deselected

X

H

X

L

X

L

H

X

L

High-Z

D_IN

Deselected

Write

H

X

D_OUT

High-Z

Read

H

X

Outputs Disabled

Ordering Information

256K

× 72 (18-Mbit) 3.3V Synchronous CYD18S72V Dual-Port SRAM

Speed

(MHz)

Ordering Code

Package Name

Package Type

Operating Range

133

100

CYD18S72V-133BBC

BB484

484-ball Grid Array

Commercial

23 mm x 23 mm with 1.0-mm pitch (FBGA)

CYD18S72V-133BBXC

CYD18S72V-133BBI

CYD18S72V-100BBC

CYD18S72V-100BBXC

CYD18S72V-100BBI

CYD18S72V-100BBXI

BB484

484-ball Pb-Free Ball Grid Array

Commercial

Industrial

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Grid Array

Commercial

Industrial

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Pb-Free Ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Pb-Free Ball Grid Array

Industrial

23 mm x 23 mm with 1.0-mm pitch (FBGA)

128K

× 72 (9-Mbit) 3.3V Synchronous CYD09S72V Dual-Port SRAM

167

CYD09S72V-167BBC

CYD09S72V-133BBC

CYD09S72V-133BBI

BB484

484-ball Grid Array

Commercial

Industrial

23 mm x 23 mm with 1.0-mm pitch (FBGA)

133

484-ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

64K x 72 (4-Mbit) 3.3 Synchronous CYD04S72V Dual-Port SRAM

167

CYD04S72V-167BBC

CYD04S72V-133BBC

CYD04S72V-133BBI

BB484

484-ball Grid Array

Commercial

Industrial

23 mm x 23 mm with 1.0-mm pitch (FBGA)

133

484-ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

484-ball Grid Array

23 mm x 23 mm with 1.0-mm pitch (FBGA)

Notes:

58. OE is an asynchronous input signal.

59. When CE changes state, deselection and Read happen after one cycle of latency.

60. CE = OE = LOW; CE = R/W = HIGH.

0

1

Document #: 38-06069 Rev. *I

Page 23 of 25

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Package Diagram

484-ball FBGA (23 mm x 23 mm x 1.6 mm) BB484

"/44/- 6)%7

4/0 6)%7

ꢁꢂꢁꢉ - #

!ꢃ #/2.%2

ꢁꢂꢀꢉ - # ! "

!ꢃ #/2.%2

ꢁꢂꢇꢁ¼ꢁꢂꢃꢁꢄꢅꢈꢅ8ꢆ

ꢀꢃ ꢃꢊ ꢃꢋ ꢃꢉ ꢃꢌ

ꢃꢃ

ꢃꢃ ꢃꢌ ꢃꢉ ꢃꢋ ꢃꢊ

ꢊ ꢃꢁ ꢃꢀ ꢃꢅ ꢃꢇ ꢃꢈ

ꢀꢃ

ꢀꢁ ꢀꢀ

ꢃ

ꢀ

ꢌ

ꢅ

ꢉ

ꢇ

ꢋ

ꢈ

ꢀꢀ ꢀꢁ ꢃꢈ ꢃꢇ ꢃꢅ ꢃꢀ ꢃꢁ

ꢊ

ꢈ

ꢋ

ꢇ

ꢉ

ꢅ

ꢌ

ꢀ

ꢃ

!

"

!

"

#

$

%

$

%

&

'

(

*

'

(

*

+

,

-

.

0

-

.

0

2

4

5

6

5

6

7

9

7

9

!!

!"

!!

!"

ꢃꢂꢁꢁ

!

ꢃꢁꢂꢉꢁ

ꢀꢃꢂꢁꢁ

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ꢀꢌꢂꢁꢁ¼ꢁꢂꢃꢁ

ꢁꢂꢃꢁꢄꢅ8ꢆ

3%!4).' 0,!.%

#

51-85124-*E

2%&%2%.#% *%$%# -/ꢍꢃꢊꢀ

0ACKAGE 7EIGHT ꢍ ꢃꢂꢌ GRAMS

FLEx72 and FLEx72-E are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in

this document are the trademarks of their respective holders.

Document #: 38-06069 Rev. *I

Page 24 of 25

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: FLEx72™ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM

Document Number: 38-06069

Orig. of

REV.

**

ECN NO. Issue Date Change Description of Change

125859

06/17/03

SPN

New Data Sheet

*A

128707

08/01/03

SPN

Added -133 speed bin

Updated spec values for I_CC,t_{HA, HB, HW, HD}

t

Added new parameter I_CC1

Added bank select read and read to write to read (OE=low) timing diagrams

*B

128997

09/18/03

SPN

Updated spec values for t_{OE, OHZ, CH2, CL2, HA, HB, HW, HD, CC, SB5, SA,}

t_{SB, SW, SD, CD2}

Updated read to write (OE=low) timing diagram

t

I

t

Updated Master Reset values for t_RS,t_{RSR, RSF}

t

Updated pinout

Updated V_COREvoltage range

*C

*D

129936

233830

09/30/03

See ECN

SPN

Updated package diagram

Updated t_CD2value on first page

Removed Preliminary status

WWZ

Added 4 Mbit and 9 Mbit x72 devices into the data sheet with updated pinout,

pin description table, power table, and timing table

Changed title

Added Preliminary status to reflect the addition of 4 Mbit and 9 Mbit devices

Removed FLEx72-E from the document

Added counter related functions for 4 Mbit and 9 Mbit

Removed standard JTAG description

Updated block diagram

Updated pinout with FTSEL and one more PORTSTD pins per port

Updated tRSF of CYD18S72V value

*E

*F

288892

327355

See ECN

WWZ

AEQ

Change pinout D15 from REV[2,4] to VSS to reflect SC pin removal

Changed pinout K3 from NC to NC[2,5]

Changed pinout K20 from NC to NC[2,5]

Changed pinout D15 from VSS to NC

Changed pinout D8 and M3 from REVL[2,4] to VSS

Changed pinout M20 and W15 from REVR[2,4] to VSS

*G

*H

345735

360316

See ECN

PCX

YDT

VREF Pin Definition Updated

Added Pb-Free Part Ordering Informations

Added note for V_CORE

Changed notes for PORTSTD to VSS

Changed ICC, ISB1, ISB2 and ISB4 number for CYD09S72V per PE request

*I

460454

See ECN

YDT

Changed CYDxxS72AV to CYDxxS72V (rev. A not implemented)

Document #: 38-06069 Rev. *I

Page 25 of 25

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型号：	CYD18S72V-133BBI
厂家：	CYPRESS
描述：	FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM FLEx72⑩ 3.3V 64K / 128K / 256K X 72同步双端口RAM 存储内存集成电路静态存储器时钟
文件：	总25页 (文件大小：696K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYD18S72V-133BBI [CYPRESS]

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